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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-27 22:13:56 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-27 22:13:56 -0400
commit936813a8807c5684c6a97f1081b31027403d4a93 (patch)
treebc3a1343ea1548195ab4e5dd11b1830f8b9cc52b /include/asm-arm
parent73a0e405dce7d720808536b708f7c738b413b1a2 (diff)
parent6a93096195305f6f2a39544a034e77e2e74d5799 (diff)
Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6: [MTD] NAND: Select chip before checking write protect status [MTD] CORE mtdchar.c: fix off-by-one error in lseek() [MTD] NAND: Fix typo in mtd/nand/ts7250.c [JFFS2][XATTR] coexistence between xattr and write buffering support. [JFFS2][XATTR] Fix wrong copyright [JFFS2][XATTR] Re-define xd->refcnt as atomic_t [JFFS2][XATTR] Fix memory leak with jffs2_xattr_ref [JFFS2][XATTR] rid unnecessary writing of delete marker. [JFFS2][XATTR] Fix ACL bug when updating null xattr by null ACL. [JFFS2][XATTR] using 'delete marker' for xdatum/xref deletion [MTD] Fix off-by-one error in physmap.c [MTD] Remove unused 'nr_banks' variable from ixp2000 map driver [MTD NAND] s3c2412 support in s3c2410.c [MTD] Initialize 'writesize' [MTD] NAND: ndfc fix address offset thinko [MTD] NAND: S3C2410 convert prinks to dev_*()s [MTD] NAND: Missing fixups
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-s3c2410/regs-nand.h48
1 files changed, 47 insertions, 1 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/arch-s3c2410/regs-nand.h
index 7cff235e667a..c1470c695c33 100644
--- a/include/asm-arm/arch-s3c2410/regs-nand.h
+++ b/include/asm-arm/arch-s3c2410/regs-nand.h
@@ -39,10 +39,19 @@
39#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28) 39#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
40#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) 40#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
41#define S3C2440_NFMECC1 S3C2410_NFREG(0x30) 41#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
42#define S3C2440_NFSECC S3C2410_NFREG(0x34) 42#define S3C2440_NFSECC S3C24E10_NFREG(0x34)
43#define S3C2440_NFSBLK S3C2410_NFREG(0x38) 43#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
44#define S3C2440_NFEBLK S3C2410_NFREG(0x3C) 44#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
45 45
46#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
47#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
48#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
49#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
50#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
51#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
52#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
53#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
54
46#define S3C2410_NFCONF_EN (1<<15) 55#define S3C2410_NFCONF_EN (1<<15)
47#define S3C2410_NFCONF_512BYTE (1<<14) 56#define S3C2410_NFCONF_512BYTE (1<<14)
48#define S3C2410_NFCONF_4STEP (1<<13) 57#define S3C2410_NFCONF_4STEP (1<<13)
@@ -77,5 +86,42 @@
77#define S3C2440_NFSTAT_RnB_CHANGE (1<<2) 86#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
78#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3) 87#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
79 88
89#define S3C2412_NFCONF_NANDBOOT (1<<31)
90#define S3C2412_NFCONF_ECCCLKCON (1<<30)
91#define S3C2412_NFCONF_ECC_MLC (1<<24)
92#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
93
94#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
95#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
96#define S3C2412_NFCONT_SOFTLOCK (1<<16)
97#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
98#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
99#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
100#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
101#define S3C2412_NFCONT_nFCE1 (1<<2)
102#define S3C2412_NFCONT_nFCE0 (1<<1)
103
104#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
105#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
106#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
107#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
108#define S3C2412_NFSTAT_nFCE1 (1<<3)
109#define S3C2412_NFSTAT_nFCE0 (1<<2)
110#define S3C2412_NFSTAT_Res1 (1<<1)
111#define S3C2412_NFSTAT_READY (1<<0)
112
113#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
114#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
115#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
116#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
117#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
118#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
119#define S3C2412_NFECCERR_NONE (0)
120#define S3C2412_NFECCERR_1BIT (1)
121#define S3C2412_NFECCERR_MULTIBIT (2)
122#define S3C2412_NFECCERR_ECCAREA (3)
123
124
125
80#endif /* __ASM_ARM_REGS_NAND */ 126#endif /* __ASM_ARM_REGS_NAND */
81 127