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authorPaul Walmsley <paul@pwsan.com>2008-03-18 04:04:51 -0400
committerTony Lindgren <tony@atomide.com>2008-04-14 13:29:37 -0400
commit445959821f82846913fe09fee0573e0238415e8c (patch)
tree38d0ec8fd827017e21961a42a58a9bcaaede7c6e /include/asm-arm
parentc595713da76bc7cedddf5135072ea6037cc0befb (diff)
ARM: OMAP2: Change 24xx to use new register access
This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-omap/clock.h5
-rw-r--r--include/asm-arm/arch-omap/entry-macro.S2
-rw-r--r--include/asm-arm/arch-omap/io.h70
-rw-r--r--include/asm-arm/arch-omap/omap24xx.h96
4 files changed, 152 insertions, 21 deletions
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index fa6881049903..fc7b80643852 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -88,4 +88,9 @@ extern int clk_get_usecount(struct clk *clk);
88#define CLOCK_IN_OMAP242X (1 << 25) 88#define CLOCK_IN_OMAP242X (1 << 25)
89#define CLOCK_IN_OMAP243X (1 << 26) 89#define CLOCK_IN_OMAP243X (1 << 26)
90 90
91/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
92#define CORE_CLK_SRC_32K 0
93#define CORE_CLK_SRC_DPLL 1
94#define CORE_CLK_SRC_DPLL_X2 2
95
91#endif 96#endif
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index f6967c8df323..74cd57221c8e 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -68,7 +68,7 @@
68 .endm 68 .endm
69 69
70 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 70 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
71 ldr \base, =VA_IC_BASE 71 ldr \base, =OMAP2_VA_IC_BASE
72 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ 72 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
73 cmp \irqnr, #0x0 73 cmp \irqnr, #0x0
74 bne 2222f 74 bne 2222f
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 289082d07f14..160578e1f557 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -80,6 +80,13 @@
80#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ 80#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */
81#define OMAP243X_GPMC_VIRT 0xFE000000 81#define OMAP243X_GPMC_VIRT 0xFE000000
82#define OMAP243X_GPMC_SIZE SZ_1M 82#define OMAP243X_GPMC_SIZE SZ_1M
83#define OMAP243X_SDRC_PHYS OMAP243X_SDRC_BASE
84#define OMAP243X_SDRC_VIRT 0xFD000000
85#define OMAP243X_SDRC_SIZE SZ_1M
86#define OMAP243X_SMS_PHYS OMAP243X_SMS_BASE
87#define OMAP243X_SMS_VIRT 0xFC000000
88#define OMAP243X_SMS_SIZE SZ_1M
89
83#endif 90#endif
84 91
85#define IO_OFFSET 0x90000000 92#define IO_OFFSET 0x90000000
@@ -88,16 +95,73 @@
88#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ 95#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
89 96
90/* DSP */ 97/* DSP */
91#define DSP_MEM_24XX_PHYS OMAP24XX_DSP_MEM_BASE /* 0x58000000 */ 98#define DSP_MEM_24XX_PHYS OMAP2420_DSP_MEM_BASE /* 0x58000000 */
92#define DSP_MEM_24XX_VIRT 0xe0000000 99#define DSP_MEM_24XX_VIRT 0xe0000000
93#define DSP_MEM_24XX_SIZE 0x28000 100#define DSP_MEM_24XX_SIZE 0x28000
94#define DSP_IPI_24XX_PHYS OMAP24XX_DSP_IPI_BASE /* 0x59000000 */ 101#define DSP_IPI_24XX_PHYS OMAP2420_DSP_IPI_BASE /* 0x59000000 */
95#define DSP_IPI_24XX_VIRT 0xe1000000 102#define DSP_IPI_24XX_VIRT 0xe1000000
96#define DSP_IPI_24XX_SIZE SZ_4K 103#define DSP_IPI_24XX_SIZE SZ_4K
97#define DSP_MMU_24XX_PHYS OMAP24XX_DSP_MMU_BASE /* 0x5a000000 */ 104#define DSP_MMU_24XX_PHYS OMAP2420_DSP_MMU_BASE /* 0x5a000000 */
98#define DSP_MMU_24XX_VIRT 0xe2000000 105#define DSP_MMU_24XX_VIRT 0xe2000000
99#define DSP_MMU_24XX_SIZE SZ_4K 106#define DSP_MMU_24XX_SIZE SZ_4K
100 107
108#elif defined(CONFIG_ARCH_OMAP3)
109
110/* We map both L3 and L4 on OMAP3 */
111#define L3_34XX_PHYS L3_34XX_BASE /* 0x68000000 */
112#define L3_34XX_VIRT 0xf8000000
113#define L3_34XX_SIZE SZ_1M /* 44kB of 128MB used, want 1MB sect */
114
115#define L4_34XX_PHYS L4_34XX_BASE /* 0x48000000 */
116#define L4_34XX_VIRT 0xd8000000
117#define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
118
119/*
120 * Need to look at the Size 4M for L4.
121 * VPOM3430 was not working for Int controller
122 */
123
124#define L4_WK_34XX_PHYS L4_WK_34XX_BASE /* 0x48300000 */
125#define L4_WK_34XX_VIRT 0xd8300000
126#define L4_WK_34XX_SIZE SZ_1M
127
128#define L4_PER_34XX_PHYS L4_PER_34XX_BASE /* 0x49000000 */
129#define L4_PER_34XX_VIRT 0xd9000000
130#define L4_PER_34XX_SIZE SZ_1M
131
132#define L4_EMU_34XX_PHYS L4_EMU_34XX_BASE /* 0x54000000 */
133#define L4_EMU_34XX_VIRT 0xe4000000
134#define L4_EMU_34XX_SIZE SZ_64M
135
136#define OMAP34XX_GPMC_PHYS OMAP34XX_GPMC_BASE /* 0x6E000000 */
137#define OMAP34XX_GPMC_VIRT 0xFE000000
138#define OMAP34XX_GPMC_SIZE SZ_1M
139
140#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
141#define OMAP343X_SMS_VIRT 0xFC000000
142#define OMAP343X_SMS_SIZE SZ_1M
143
144#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
145#define OMAP343X_SDRC_VIRT 0xFD000000
146#define OMAP343X_SDRC_SIZE SZ_1M
147
148
149#define IO_OFFSET 0x90000000
150#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
151#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
152#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
153
154/* DSP */
155#define DSP_MEM_34XX_PHYS OMAP34XX_DSP_MEM_BASE /* 0x58000000 */
156#define DSP_MEM_34XX_VIRT 0xe0000000
157#define DSP_MEM_34XX_SIZE 0x28000
158#define DSP_IPI_34XX_PHYS OMAP34XX_DSP_IPI_BASE /* 0x59000000 */
159#define DSP_IPI_34XX_VIRT 0xe1000000
160#define DSP_IPI_34XX_SIZE SZ_4K
161#define DSP_MMU_34XX_PHYS OMAP34XX_DSP_MMU_BASE /* 0x5a000000 */
162#define DSP_MMU_34XX_VIRT 0xe2000000
163#define DSP_MMU_34XX_SIZE SZ_4K
164
101#endif 165#endif
102 166
103#ifndef __ASSEMBLER__ 167#ifndef __ASSEMBLER__
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 14c0f9496579..b9fcaae287c8 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -1,3 +1,28 @@
1/*
2 * include/asm-arm/arch-omap/omap24xx.h
3 *
4 * This file contains the processor specific definitions
5 * of the TI OMAP24XX.
6 *
7 * Copyright (C) 2007 Texas Instruments.
8 * Copyright (C) 2007 Nokia Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
1#ifndef __ASM_ARCH_OMAP24XX_H 26#ifndef __ASM_ARCH_OMAP24XX_H
2#define __ASM_ARCH_OMAP24XX_H 27#define __ASM_ARCH_OMAP24XX_H
3 28
@@ -13,33 +38,70 @@
13 38
14/* interrupt controller */ 39/* interrupt controller */
15#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000) 40#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
16#define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
17#define OMAP24XX_IVA_INTC_BASE 0x40000000 41#define OMAP24XX_IVA_INTC_BASE 0x40000000
18#define IRQ_SIR_IRQ 0x0040 42#define IRQ_SIR_IRQ 0x0040
19 43
20#ifdef CONFIG_ARCH_OMAP2420 44#define OMAP2420_CTRL_BASE L4_24XX_BASE
21#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) 45#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
22#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000) 46#define OMAP2420_PRCM_BASE (L4_24XX_BASE + 0x8000)
23#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000) 47#define OMAP2420_CM_BASE (L4_24XX_BASE + 0x8000)
24#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) 48#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
25#endif 49#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
50#define OMAP2420_SMS_BASE 0x68008000
26 51
27#ifdef CONFIG_ARCH_OMAP2430 52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
28#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) 53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
29#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000) 54#define OMAP2430_CM_BASE (L4_WK_243X_BASE + 0x6000)
30#define OMAP24XX_SDRC_BASE (0x6D000000) 55#define OMAP2430_PRM_BASE OMAP2430_CM_BASE
31#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) 56
57#define OMAP243X_SMS_BASE 0x6C000000
58#define OMAP243X_SDRC_BASE 0x6D000000
32#define OMAP243X_GPMC_BASE 0x6E000000 59#define OMAP243X_GPMC_BASE 0x6E000000
33#endif 60#define OMAP243X_SCM_BASE (L4_WK_243X_BASE + 0x2000)
61#define OMAP243X_CTRL_BASE OMAP243X_SCM_BASE
62#define OMAP243X_HS_BASE (L4_24XX_BASE + 0x000ac000)
34 63
35/* DSP SS */ 64/* DSP SS */
36#define OMAP24XX_DSP_BASE 0x58000000 65#define OMAP2420_DSP_BASE 0x58000000
37#define OMAP24XX_DSP_MEM_BASE (OMAP24XX_DSP_BASE + 0x0) 66#define OMAP2420_DSP_MEM_BASE (OMAP2420_DSP_BASE + 0x0)
38#define OMAP24XX_DSP_IPI_BASE (OMAP24XX_DSP_BASE + 0x1000000) 67#define OMAP2420_DSP_IPI_BASE (OMAP2420_DSP_BASE + 0x1000000)
39#define OMAP24XX_DSP_MMU_BASE (OMAP24XX_DSP_BASE + 0x2000000) 68#define OMAP2420_DSP_MMU_BASE (OMAP2420_DSP_BASE + 0x2000000)
69
70#define OMAP243X_DSP_BASE 0x5C000000
71#define OMAP243X_DSP_MEM_BASE (OMAP243X_DSP_BASE + 0x0)
72#define OMAP243X_DSP_MMU_BASE (OMAP243X_DSP_BASE + 0x1000000)
40 73
41/* Mailbox */ 74/* Mailbox */
42#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000) 75#define OMAP24XX_MAILBOX_BASE (L4_24XX_BASE + 0x94000)
43 76
77/* Camera */
78#define OMAP24XX_CAMERA_BASE (L4_24XX_BASE + 0x52000)
79
80/* Security */
81#define OMAP24XX_SEC_BASE (L4_24XX_BASE + 0xA0000)
82#define OMAP24XX_SEC_RNG_BASE (OMAP24XX_SEC_BASE + 0x0000)
83#define OMAP24XX_SEC_DES_BASE (OMAP24XX_SEC_BASE + 0x2000)
84#define OMAP24XX_SEC_SHA1MD5_BASE (OMAP24XX_SEC_BASE + 0x4000)
85#define OMAP24XX_SEC_AES_BASE (OMAP24XX_SEC_BASE + 0x6000)
86#define OMAP24XX_SEC_PKA_BASE (OMAP24XX_SEC_BASE + 0x8000)
87
88#if defined(CONFIG_ARCH_OMAP2420)
89
90#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE
91#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE
92#define OMAP2_CM_BASE OMAP2420_CM_BASE
93#define OMAP2_PRM_BASE OMAP2420_PRM_BASE
94#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
95
96#elif defined(CONFIG_ARCH_OMAP2430)
97
98#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE
99#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE
100#define OMAP2_CM_BASE OMAP2430_CM_BASE
101#define OMAP2_PRM_BASE OMAP2430_PRM_BASE
102#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
103
104#endif
105
44#endif /* __ASM_ARCH_OMAP24XX_H */ 106#endif /* __ASM_ARCH_OMAP24XX_H */
45 107