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authorLennert Buytenhek <buytenh@wantstofly.org>2006-04-01 18:07:39 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-04-01 18:07:39 -0500
commit23759dc6430428897a36c4d493f611eca55c9481 (patch)
treec62050927599b36ed223753c35fd737e3c0c6762 /include/asm-arm
parentd3f4c571b6e596f9d39c596426269006a309d3b8 (diff)
[ARM] 3439/2: xsc3: add I/O coherency support
Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-ixp23xx/memory.h17
-rw-r--r--include/asm-arm/dma-mapping.h22
-rw-r--r--include/asm-arm/memory.h8
-rw-r--r--include/asm-arm/pgtable-hwdef.h1
-rw-r--r--include/asm-arm/pgtable.h1
5 files changed, 42 insertions, 7 deletions
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h
index bebcf0aa0d72..6e19f46d54d1 100644
--- a/include/asm-arm/arch-ixp23xx/memory.h
+++ b/include/asm-arm/arch-ixp23xx/memory.h
@@ -28,6 +28,7 @@
28 * to an address that the kernel can use. 28 * to an address that the kernel can use.
29 */ 29 */
30#ifndef __ASSEMBLY__ 30#ifndef __ASSEMBLY__
31#include <asm/mach-types.h>
31 32
32#define __virt_to_bus(v) \ 33#define __virt_to_bus(v) \
33 ({ unsigned int ret; \ 34 ({ unsigned int ret; \
@@ -40,6 +41,22 @@
40 data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ 41 data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \
41 __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) 42 __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
42 43
44/*
45 * Coherency support. Only supported on A2 CPUs or on A1
46 * systems that have the cache coherency workaround.
47 */
48static inline int __ixp23xx_arch_is_coherent(void)
49{
50 extern unsigned int processor_id;
51
52 if (((processor_id & 15) >= 2) || machine_is_roadrunner())
53 return 1;
54
55 return 0;
56}
57
58#define arch_is_coherent() __ixp23xx_arch_is_coherent()
59
43#endif 60#endif
44 61
45 62
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
index e3e8541ee63b..63ca7412a462 100644
--- a/include/asm-arm/dma-mapping.h
+++ b/include/asm-arm/dma-mapping.h
@@ -47,7 +47,7 @@ static inline int dma_get_cache_alignment(void)
47 47
48static inline int dma_is_consistent(dma_addr_t handle) 48static inline int dma_is_consistent(dma_addr_t handle)
49{ 49{
50 return 0; 50 return !!arch_is_coherent();
51} 51}
52 52
53/* 53/*
@@ -145,7 +145,9 @@ static inline dma_addr_t
145dma_map_single(struct device *dev, void *cpu_addr, size_t size, 145dma_map_single(struct device *dev, void *cpu_addr, size_t size,
146 enum dma_data_direction dir) 146 enum dma_data_direction dir)
147{ 147{
148 consistent_sync(cpu_addr, size, dir); 148 if (!arch_is_coherent())
149 consistent_sync(cpu_addr, size, dir);
150
149 return virt_to_dma(dev, (unsigned long)cpu_addr); 151 return virt_to_dma(dev, (unsigned long)cpu_addr);
150} 152}
151#else 153#else
@@ -255,7 +257,9 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
255 257
256 sg->dma_address = page_to_dma(dev, sg->page) + sg->offset; 258 sg->dma_address = page_to_dma(dev, sg->page) + sg->offset;
257 virt = page_address(sg->page) + sg->offset; 259 virt = page_address(sg->page) + sg->offset;
258 consistent_sync(virt, sg->length, dir); 260
261 if (!arch_is_coherent())
262 consistent_sync(virt, sg->length, dir);
259 } 263 }
260 264
261 return nents; 265 return nents;
@@ -310,14 +314,16 @@ static inline void
310dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, 314dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
311 enum dma_data_direction dir) 315 enum dma_data_direction dir)
312{ 316{
313 consistent_sync((void *)dma_to_virt(dev, handle), size, dir); 317 if (!arch_is_coherent())
318 consistent_sync((void *)dma_to_virt(dev, handle), size, dir);
314} 319}
315 320
316static inline void 321static inline void
317dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, 322dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
318 enum dma_data_direction dir) 323 enum dma_data_direction dir)
319{ 324{
320 consistent_sync((void *)dma_to_virt(dev, handle), size, dir); 325 if (!arch_is_coherent())
326 consistent_sync((void *)dma_to_virt(dev, handle), size, dir);
321} 327}
322#else 328#else
323extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); 329extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction);
@@ -347,7 +353,8 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
347 353
348 for (i = 0; i < nents; i++, sg++) { 354 for (i = 0; i < nents; i++, sg++) {
349 char *virt = page_address(sg->page) + sg->offset; 355 char *virt = page_address(sg->page) + sg->offset;
350 consistent_sync(virt, sg->length, dir); 356 if (!arch_is_coherent())
357 consistent_sync(virt, sg->length, dir);
351 } 358 }
352} 359}
353 360
@@ -359,7 +366,8 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
359 366
360 for (i = 0; i < nents; i++, sg++) { 367 for (i = 0; i < nents; i++, sg++) {
361 char *virt = page_address(sg->page) + sg->offset; 368 char *virt = page_address(sg->page) + sg->offset;
362 consistent_sync(virt, sg->length, dir); 369 if (!arch_is_coherent())
370 consistent_sync(virt, sg->length, dir);
363 } 371 }
364} 372}
365#else 373#else
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index afa5c3ea077c..2b3cf69b3ed9 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -234,6 +234,14 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
234#define virt_to_dma(dev, addr) (__arch_virt_to_dma(dev, addr)) 234#define virt_to_dma(dev, addr) (__arch_virt_to_dma(dev, addr))
235#endif 235#endif
236 236
237/*
238 * Optional coherency support. Currently used only by selected
239 * Intel XSC3-based systems.
240 */
241#ifndef arch_is_coherent
242#define arch_is_coherent() 0
243#endif
244
237#endif 245#endif
238 246
239#include <asm-generic/memory_model.h> 247#include <asm-generic/memory_model.h>
diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h
index 1d033495cc75..1bc1f997bda2 100644
--- a/include/asm-arm/pgtable-hwdef.h
+++ b/include/asm-arm/pgtable-hwdef.h
@@ -73,6 +73,7 @@
73#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) 73#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
74#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ 74#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
75#define PTE_EXT_APX (1 << 9) /* v6 */ 75#define PTE_EXT_APX (1 << 9) /* v6 */
76#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */
76#define PTE_EXT_SHARED (1 << 10) /* v6 */ 77#define PTE_EXT_SHARED (1 << 10) /* v6 */
77#define PTE_EXT_NG (1 << 11) /* v6 */ 78#define PTE_EXT_NG (1 << 11) /* v6 */
78 79
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index e595ae24efe2..e85c08d78dda 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -156,6 +156,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
156#define L_PTE_WRITE (1 << 5) 156#define L_PTE_WRITE (1 << 5)
157#define L_PTE_EXEC (1 << 6) 157#define L_PTE_EXEC (1 << 6)
158#define L_PTE_DIRTY (1 << 7) 158#define L_PTE_DIRTY (1 << 7)
159#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */
159#define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */ 160#define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */
160#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ 161#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */
161 162