diff options
author | Ben Dooks <ben-linux@fluff.org> | 2007-02-17 09:05:17 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-17 10:00:33 -0500 |
commit | 15e4db7b8054ac171de946b9511655446dd29b8f (patch) | |
tree | c1946c73a44e87cae5595a02299014c11b5e336a /include/asm-arm | |
parent | 64f33beafbaae55d116e933e8eae6b068fba617f (diff) |
[ARM] 4219/1: S3C2443: DMA source definitions
Defines for the S3C2443 DMA source selection,
and update the maximum channels to 6 if the S3C2443
is selected.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-s3c2410/dma.h | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h index 58ffa7ba3c88..c6e8d8f64938 100644 --- a/include/asm-arm/arch-s3c2410/dma.h +++ b/include/asm-arm/arch-s3c2410/dma.h | |||
@@ -51,13 +51,19 @@ enum dma_ch { | |||
51 | DMACH_UART0_SRC2, /* s3c2412 second uart sources */ | 51 | DMACH_UART0_SRC2, /* s3c2412 second uart sources */ |
52 | DMACH_UART1_SRC2, | 52 | DMACH_UART1_SRC2, |
53 | DMACH_UART2_SRC2, | 53 | DMACH_UART2_SRC2, |
54 | DMACH_UART3, /* s3c2443 has extra uart */ | ||
55 | DMACH_UART3_SRC2, | ||
54 | DMACH_MAX, /* the end entry */ | 56 | DMACH_MAX, /* the end entry */ |
55 | }; | 57 | }; |
56 | 58 | ||
57 | #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ | 59 | #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ |
58 | 60 | ||
59 | /* we have 4 dma channels */ | 61 | /* we have 4 dma channels */ |
60 | #define S3C2410_DMA_CHANNELS (4) | 62 | #ifndef CONFIG_CPU_S3C2443 |
63 | #define S3C2410_DMA_CHANNELS (4) | ||
64 | #else | ||
65 | #define S3C2410_DMA_CHANNELS (6) | ||
66 | #endif | ||
61 | 67 | ||
62 | /* types */ | 68 | /* types */ |
63 | 69 | ||
@@ -321,6 +327,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); | |||
321 | #define S3C2410_DMA_DCDST (0x1C) | 327 | #define S3C2410_DMA_DCDST (0x1C) |
322 | #define S3C2410_DMA_DMASKTRIG (0x20) | 328 | #define S3C2410_DMA_DMASKTRIG (0x20) |
323 | #define S3C2412_DMA_DMAREQSEL (0x24) | 329 | #define S3C2412_DMA_DMAREQSEL (0x24) |
330 | #define S3C2443_DMA_DMAREQSEL (0x24) | ||
324 | 331 | ||
325 | #define S3C2410_DISRCC_INC (1<<0) | 332 | #define S3C2410_DISRCC_INC (1<<0) |
326 | #define S3C2410_DISRCC_APB (1<<1) | 333 | #define S3C2410_DISRCC_APB (1<<1) |
@@ -415,4 +422,31 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn); | |||
415 | #define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) | 422 | #define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) |
416 | 423 | ||
417 | #endif | 424 | #endif |
425 | |||
426 | #define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) | ||
427 | |||
428 | #define S3C2443_DMAREQSEL_HW (1) | ||
429 | |||
430 | #define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) | ||
431 | #define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) | ||
432 | #define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) | ||
433 | #define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) | ||
434 | #define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) | ||
435 | #define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) | ||
436 | #define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) | ||
437 | #define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) | ||
438 | #define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) | ||
439 | #define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) | ||
440 | #define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) | ||
441 | #define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) | ||
442 | #define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) | ||
443 | #define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) | ||
444 | #define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) | ||
445 | #define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) | ||
446 | #define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) | ||
447 | #define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) | ||
448 | #define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) | ||
449 | #define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) | ||
450 | #define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) | ||
451 | |||
418 | #endif /* __ASM_ARCH_DMA_H */ | 452 | #endif /* __ASM_ARCH_DMA_H */ |