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authorCatalin Marinas <catalin.marinas@arm.com>2007-09-25 10:22:24 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 09:41:28 -0500
commit25ebee020bd34d1f4c5678538204f0b10bf9f6d5 (patch)
treeb9b04ddf0b9916922a3cba47a7f64f44cd0b28ff /include/asm-arm/vfpmacros.h
parentc98929c07a01c9ec2e1e5253456acc7168da8b66 (diff)
[ARM] 4583/1: ARMv7: Add VFPv3 support
This patch adds the support for VFPv3 (the kernel currently supports VFPv2). The main difference is 32 double registers (compared to 16). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/vfpmacros.h')
-rw-r--r--include/asm-arm/vfpmacros.h18
1 files changed, 16 insertions, 2 deletions
diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h
index 27fe028b4e72..cccb3892e73c 100644
--- a/include/asm-arm/vfpmacros.h
+++ b/include/asm-arm/vfpmacros.h
@@ -15,19 +15,33 @@
15 .endm 15 .endm
16 16
17 @ read all the working registers back into the VFP 17 @ read all the working registers back into the VFP
18 .macro VFPFLDMIA, base 18 .macro VFPFLDMIA, base, tmp
19#if __LINUX_ARM_ARCH__ < 6 19#if __LINUX_ARM_ARCH__ < 6
20 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} 20 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
21#else 21#else
22 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} 22 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
23#endif 23#endif
24#ifdef CONFIG_VFPv3
25 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
26 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
27 cmp \tmp, #2 @ 32 x 64bit registers?
28 ldceql p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
29 addne \base, \base, #32*4 @ step over unused register space
30#endif
24 .endm 31 .endm
25 32
26 @ write all the working registers out of the VFP 33 @ write all the working registers out of the VFP
27 .macro VFPFSTMIA, base 34 .macro VFPFSTMIA, base, tmp
28#if __LINUX_ARM_ARCH__ < 6 35#if __LINUX_ARM_ARCH__ < 6
29 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} 36 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
30#else 37#else
31 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15} 38 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
32#endif 39#endif
40#ifdef CONFIG_VFPv3
41 VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
42 and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
43 cmp \tmp, #2 @ 32 x 64bit registers?
44 stceql p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
45 addne \base, \base, #32*4 @ step over unused register space
46#endif
33 .endm 47 .endm