diff options
| author | Ben Dooks <ben@simtec.co.uk> | 2009-03-03 19:49:26 -0500 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-03-05 07:00:59 -0500 |
| commit | 8150bc886be5ce3cc301a2baca1fcf2cf7bd7f39 (patch) | |
| tree | ed9e73c106d8680fa5256988a01abfa577420717 /include/asm-arm/plat-s3c24xx | |
| parent | c59765042f53a79a7a65585042ff463b69cb248c (diff) | |
S3C24XX: Move and update IIS headers
Move the IIS headers to their correct place.
Signed-off-by: Ben Dooks <ben@simtec.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'include/asm-arm/plat-s3c24xx')
| -rw-r--r-- | include/asm-arm/plat-s3c24xx/regs-iis.h | 77 | ||||
| -rw-r--r-- | include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h | 72 |
2 files changed, 0 insertions, 149 deletions
diff --git a/include/asm-arm/plat-s3c24xx/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h deleted file mode 100644 index a6f1d5df13b4..000000000000 --- a/include/asm-arm/plat-s3c24xx/regs-iis.h +++ /dev/null | |||
| @@ -1,77 +0,0 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/regs-iis.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2410 IIS register definition | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_IIS_H | ||
| 14 | #define __ASM_ARCH_REGS_IIS_H | ||
| 15 | |||
| 16 | #define S3C2410_IISCON (0x00) | ||
| 17 | |||
| 18 | #define S3C2410_IISCON_LRINDEX (1<<8) | ||
| 19 | #define S3C2410_IISCON_TXFIFORDY (1<<7) | ||
| 20 | #define S3C2410_IISCON_RXFIFORDY (1<<6) | ||
| 21 | #define S3C2410_IISCON_TXDMAEN (1<<5) | ||
| 22 | #define S3C2410_IISCON_RXDMAEN (1<<4) | ||
| 23 | #define S3C2410_IISCON_TXIDLE (1<<3) | ||
| 24 | #define S3C2410_IISCON_RXIDLE (1<<2) | ||
| 25 | #define S3C2410_IISCON_PSCEN (1<<1) | ||
| 26 | #define S3C2410_IISCON_IISEN (1<<0) | ||
| 27 | |||
| 28 | #define S3C2410_IISMOD (0x04) | ||
| 29 | |||
| 30 | #define S3C2440_IISMOD_MPLL (1<<9) | ||
| 31 | #define S3C2410_IISMOD_SLAVE (1<<8) | ||
| 32 | #define S3C2410_IISMOD_NOXFER (0<<6) | ||
| 33 | #define S3C2410_IISMOD_RXMODE (1<<6) | ||
| 34 | #define S3C2410_IISMOD_TXMODE (2<<6) | ||
| 35 | #define S3C2410_IISMOD_TXRXMODE (3<<6) | ||
| 36 | #define S3C2410_IISMOD_LR_LLOW (0<<5) | ||
| 37 | #define S3C2410_IISMOD_LR_RLOW (1<<5) | ||
| 38 | #define S3C2410_IISMOD_IIS (0<<4) | ||
| 39 | #define S3C2410_IISMOD_MSB (1<<4) | ||
| 40 | #define S3C2410_IISMOD_8BIT (0<<3) | ||
| 41 | #define S3C2410_IISMOD_16BIT (1<<3) | ||
| 42 | #define S3C2410_IISMOD_BITMASK (1<<3) | ||
| 43 | #define S3C2410_IISMOD_256FS (0<<2) | ||
| 44 | #define S3C2410_IISMOD_384FS (1<<2) | ||
| 45 | #define S3C2410_IISMOD_16FS (0<<0) | ||
| 46 | #define S3C2410_IISMOD_32FS (1<<0) | ||
| 47 | #define S3C2410_IISMOD_48FS (2<<0) | ||
| 48 | #define S3C2410_IISMOD_FS_MASK (3<<0) | ||
| 49 | |||
| 50 | #define S3C2410_IISPSR (0x08) | ||
| 51 | #define S3C2410_IISPSR_INTMASK (31<<5) | ||
| 52 | #define S3C2410_IISPSR_INTSHIFT (5) | ||
| 53 | #define S3C2410_IISPSR_EXTMASK (31<<0) | ||
| 54 | #define S3C2410_IISPSR_EXTSHFIT (0) | ||
| 55 | |||
| 56 | #define S3C2410_IISFCON (0x0c) | ||
| 57 | |||
| 58 | #define S3C2410_IISFCON_TXDMA (1<<15) | ||
| 59 | #define S3C2410_IISFCON_RXDMA (1<<14) | ||
| 60 | #define S3C2410_IISFCON_TXENABLE (1<<13) | ||
| 61 | #define S3C2410_IISFCON_RXENABLE (1<<12) | ||
| 62 | #define S3C2410_IISFCON_TXMASK (0x3f << 6) | ||
| 63 | #define S3C2410_IISFCON_TXSHIFT (6) | ||
| 64 | #define S3C2410_IISFCON_RXMASK (0x3f) | ||
| 65 | #define S3C2410_IISFCON_RXSHIFT (0) | ||
| 66 | |||
| 67 | #define S3C2400_IISFCON_TXDMA (1<<11) | ||
| 68 | #define S3C2400_IISFCON_RXDMA (1<<10) | ||
| 69 | #define S3C2400_IISFCON_TXENABLE (1<<9) | ||
| 70 | #define S3C2400_IISFCON_RXENABLE (1<<8) | ||
| 71 | #define S3C2400_IISFCON_TXMASK (0x07 << 4) | ||
| 72 | #define S3C2400_IISFCON_TXSHIFT (4) | ||
| 73 | #define S3C2400_IISFCON_RXMASK (0x07) | ||
| 74 | #define S3C2400_IISFCON_RXSHIFT (0) | ||
| 75 | |||
| 76 | #define S3C2410_IISFIFO (0x10) | ||
| 77 | #endif /* __ASM_ARCH_REGS_IIS_H */ | ||
diff --git a/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h b/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h deleted file mode 100644 index 25d4058bcfed..000000000000 --- a/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h +++ /dev/null | |||
| @@ -1,72 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/plat-s3c24xx/regs-s3c2412-iis.h | ||
| 2 | * | ||
| 3 | * Copyright 2007 Simtec Electronics <linux@simtec.co.uk> | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * S3C2412 IIS register definition | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_S3C2412_IIS_H | ||
| 14 | #define __ASM_ARCH_REGS_S3C2412_IIS_H | ||
| 15 | |||
| 16 | #define S3C2412_IISCON (0x00) | ||
| 17 | #define S3C2412_IISMOD (0x04) | ||
| 18 | #define S3C2412_IISFIC (0x08) | ||
| 19 | #define S3C2412_IISPSR (0x0C) | ||
| 20 | #define S3C2412_IISTXD (0x10) | ||
| 21 | #define S3C2412_IISRXD (0x14) | ||
| 22 | |||
| 23 | #define S3C2412_IISCON_LRINDEX (1 << 11) | ||
| 24 | #define S3C2412_IISCON_TXFIFO_EMPTY (1 << 10) | ||
| 25 | #define S3C2412_IISCON_RXFIFO_EMPTY (1 << 9) | ||
| 26 | #define S3C2412_IISCON_TXFIFO_FULL (1 << 8) | ||
| 27 | #define S3C2412_IISCON_RXFIFO_FULL (1 << 7) | ||
| 28 | #define S3C2412_IISCON_TXDMA_PAUSE (1 << 6) | ||
| 29 | #define S3C2412_IISCON_RXDMA_PAUSE (1 << 5) | ||
| 30 | #define S3C2412_IISCON_TXCH_PAUSE (1 << 4) | ||
| 31 | #define S3C2412_IISCON_RXCH_PAUSE (1 << 3) | ||
| 32 | #define S3C2412_IISCON_TXDMA_ACTIVE (1 << 2) | ||
| 33 | #define S3C2412_IISCON_RXDMA_ACTIVE (1 << 1) | ||
| 34 | #define S3C2412_IISCON_IIS_ACTIVE (1 << 0) | ||
| 35 | |||
| 36 | #define S3C2412_IISMOD_MASTER_INTERNAL (0 << 10) | ||
| 37 | #define S3C2412_IISMOD_MASTER_EXTERNAL (1 << 10) | ||
| 38 | #define S3C2412_IISMOD_SLAVE (2 << 10) | ||
| 39 | #define S3C2412_IISMOD_MASTER_MASK (3 << 10) | ||
| 40 | #define S3C2412_IISMOD_MODE_TXONLY (0 << 8) | ||
| 41 | #define S3C2412_IISMOD_MODE_RXONLY (1 << 8) | ||
| 42 | #define S3C2412_IISMOD_MODE_TXRX (2 << 8) | ||
| 43 | #define S3C2412_IISMOD_MODE_MASK (3 << 8) | ||
| 44 | #define S3C2412_IISMOD_LR_LLOW (0 << 7) | ||
| 45 | #define S3C2412_IISMOD_LR_RLOW (1 << 7) | ||
| 46 | #define S3C2412_IISMOD_SDF_IIS (0 << 5) | ||
| 47 | #define S3C2412_IISMOD_SDF_MSB (0 << 5) | ||
| 48 | #define S3C2412_IISMOD_SDF_LSB (0 << 5) | ||
| 49 | #define S3C2412_IISMOD_SDF_MASK (3 << 5) | ||
| 50 | #define S3C2412_IISMOD_RCLK_256FS (0 << 3) | ||
| 51 | #define S3C2412_IISMOD_RCLK_512FS (1 << 3) | ||
| 52 | #define S3C2412_IISMOD_RCLK_384FS (2 << 3) | ||
| 53 | #define S3C2412_IISMOD_RCLK_768FS (3 << 3) | ||
| 54 | #define S3C2412_IISMOD_RCLK_MASK (3 << 3) | ||
| 55 | #define S3C2412_IISMOD_BCLK_32FS (0 << 1) | ||
| 56 | #define S3C2412_IISMOD_BCLK_48FS (1 << 1) | ||
| 57 | #define S3C2412_IISMOD_BCLK_16FS (2 << 1) | ||
| 58 | #define S3C2412_IISMOD_BCLK_24FS (3 << 1) | ||
| 59 | #define S3C2412_IISMOD_BCLK_MASK (3 << 1) | ||
| 60 | #define S3C2412_IISMOD_8BIT (1 << 0) | ||
| 61 | |||
| 62 | #define S3C2412_IISPSR_PSREN (1 << 15) | ||
| 63 | |||
| 64 | #define S3C2412_IISFIC_TXFLUSH (1 << 15) | ||
| 65 | #define S3C2412_IISFIC_RXFLUSH (1 << 7) | ||
| 66 | #define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf) | ||
| 67 | #define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf) | ||
| 68 | |||
| 69 | |||
| 70 | |||
| 71 | #endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */ | ||
| 72 | |||