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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/pgtable.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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1/*
2 * linux/include/asm-arm/pgtable.h
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASMARM_PGTABLE_H
11#define _ASMARM_PGTABLE_H
12
13#include <asm-generic/4level-fixup.h>
14
15#include <asm/memory.h>
16#include <asm/proc-fns.h>
17#include <asm/arch/vmalloc.h>
18
19/*
20 * Hardware-wise, we have a two level page table structure, where the first
21 * level has 4096 entries, and the second level has 256 entries. Each entry
22 * is one 32-bit word. Most of the bits in the second level entry are used
23 * by hardware, and there aren't any "accessed" and "dirty" bits.
24 *
25 * Linux on the other hand has a three level page table structure, which can
26 * be wrapped to fit a two level page table structure easily - using the PGD
27 * and PTE only. However, Linux also expects one "PTE" table per page, and
28 * at least a "dirty" bit.
29 *
30 * Therefore, we tweak the implementation slightly - we tell Linux that we
31 * have 2048 entries in the first level, each of which is 8 bytes (iow, two
32 * hardware pointers to the second level.) The second level contains two
33 * hardware PTE tables arranged contiguously, followed by Linux versions
34 * which contain the state information Linux needs. We, therefore, end up
35 * with 512 entries in the "PTE" level.
36 *
37 * This leads to the page tables having the following layout:
38 *
39 * pgd pte
40 * | |
41 * +--------+ +0
42 * | |-----> +------------+ +0
43 * +- - - - + +4 | h/w pt 0 |
44 * | |-----> +------------+ +1024
45 * +--------+ +8 | h/w pt 1 |
46 * | | +------------+ +2048
47 * +- - - - + | Linux pt 0 |
48 * | | +------------+ +3072
49 * +--------+ | Linux pt 1 |
50 * | | +------------+ +4096
51 *
52 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
53 * PTE_xxx for definitions of bits appearing in the "h/w pt".
54 *
55 * PMD_xxx definitions refer to bits in the first level page table.
56 *
57 * The "dirty" bit is emulated by only granting hardware write permission
58 * iff the page is marked "writable" and "dirty" in the Linux PTE. This
59 * means that a write to a clean page will cause a permission fault, and
60 * the Linux MM layer will mark the page dirty via handle_pte_fault().
61 * For the hardware to notice the permission change, the TLB entry must
62 * be flushed, and ptep_establish() does that for us.
63 *
64 * The "accessed" or "young" bit is emulated by a similar method; we only
65 * allow accesses to the page if the "young" bit is set. Accesses to the
66 * page will cause a fault, and handle_pte_fault() will set the young bit
67 * for us as long as the page is marked present in the corresponding Linux
68 * PTE entry. Again, ptep_establish() will ensure that the TLB is up to
69 * date.
70 *
71 * However, when the "young" bit is cleared, we deny access to the page
72 * by clearing the hardware PTE. Currently Linux does not flush the TLB
73 * for us in this case, which means the TLB will retain the transation
74 * until either the TLB entry is evicted under pressure, or a context
75 * switch which changes the user space mapping occurs.
76 */
77#define PTRS_PER_PTE 512
78#define PTRS_PER_PMD 1
79#define PTRS_PER_PGD 2048
80
81/*
82 * PMD_SHIFT determines the size of the area a second-level page table can map
83 * PGDIR_SHIFT determines what a third-level page table entry can map
84 */
85#define PMD_SHIFT 21
86#define PGDIR_SHIFT 21
87
88#define LIBRARY_TEXT_START 0x0c000000
89
90#ifndef __ASSEMBLY__
91extern void __pte_error(const char *file, int line, unsigned long val);
92extern void __pmd_error(const char *file, int line, unsigned long val);
93extern void __pgd_error(const char *file, int line, unsigned long val);
94
95#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
96#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
97#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
98#endif /* !__ASSEMBLY__ */
99
100#define PMD_SIZE (1UL << PMD_SHIFT)
101#define PMD_MASK (~(PMD_SIZE-1))
102#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
103#define PGDIR_MASK (~(PGDIR_SIZE-1))
104
105#define FIRST_USER_PGD_NR 1
106#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
107
108/*
109 * ARMv6 supersection address mask and size definitions.
110 */
111#define SUPERSECTION_SHIFT 24
112#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
113#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
114
115/*
116 * Hardware page table definitions.
117 *
118 * + Level 1 descriptor (PMD)
119 * - common
120 */
121#define PMD_TYPE_MASK (3 << 0)
122#define PMD_TYPE_FAULT (0 << 0)
123#define PMD_TYPE_TABLE (1 << 0)
124#define PMD_TYPE_SECT (2 << 0)
125#define PMD_BIT4 (1 << 4)
126#define PMD_DOMAIN(x) ((x) << 5)
127#define PMD_PROTECTION (1 << 9) /* v5 */
128/*
129 * - section
130 */
131#define PMD_SECT_BUFFERABLE (1 << 2)
132#define PMD_SECT_CACHEABLE (1 << 3)
133#define PMD_SECT_AP_WRITE (1 << 10)
134#define PMD_SECT_AP_READ (1 << 11)
135#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
136#define PMD_SECT_APX (1 << 15) /* v6 */
137#define PMD_SECT_S (1 << 16) /* v6 */
138#define PMD_SECT_nG (1 << 17) /* v6 */
139#define PMD_SECT_SUPER (1 << 18) /* v6 */
140
141#define PMD_SECT_UNCACHED (0)
142#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
143#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
144#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
145#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
146#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
147
148/*
149 * - coarse table (not used)
150 */
151
152/*
153 * + Level 2 descriptor (PTE)
154 * - common
155 */
156#define PTE_TYPE_MASK (3 << 0)
157#define PTE_TYPE_FAULT (0 << 0)
158#define PTE_TYPE_LARGE (1 << 0)
159#define PTE_TYPE_SMALL (2 << 0)
160#define PTE_TYPE_EXT (3 << 0) /* v5 */
161#define PTE_BUFFERABLE (1 << 2)
162#define PTE_CACHEABLE (1 << 3)
163
164/*
165 * - extended small page/tiny page
166 */
167#define PTE_EXT_AP_MASK (3 << 4)
168#define PTE_EXT_AP_UNO_SRO (0 << 4)
169#define PTE_EXT_AP_UNO_SRW (1 << 4)
170#define PTE_EXT_AP_URO_SRW (2 << 4)
171#define PTE_EXT_AP_URW_SRW (3 << 4)
172#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
173
174/*
175 * - small page
176 */
177#define PTE_SMALL_AP_MASK (0xff << 4)
178#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
179#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
180#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
181#define PTE_SMALL_AP_URW_SRW (0xff << 4)
182
183/*
184 * "Linux" PTE definitions.
185 *
186 * We keep two sets of PTEs - the hardware and the linux version.
187 * This allows greater flexibility in the way we map the Linux bits
188 * onto the hardware tables, and allows us to have YOUNG and DIRTY
189 * bits.
190 *
191 * The PTE table pointer refers to the hardware entries; the "Linux"
192 * entries are stored 1024 bytes below.
193 */
194#define L_PTE_PRESENT (1 << 0)
195#define L_PTE_FILE (1 << 1) /* only when !PRESENT */
196#define L_PTE_YOUNG (1 << 1)
197#define L_PTE_BUFFERABLE (1 << 2) /* matches PTE */
198#define L_PTE_CACHEABLE (1 << 3) /* matches PTE */
199#define L_PTE_USER (1 << 4)
200#define L_PTE_WRITE (1 << 5)
201#define L_PTE_EXEC (1 << 6)
202#define L_PTE_DIRTY (1 << 7)
203
204#ifndef __ASSEMBLY__
205
206#include <asm/domain.h>
207
208#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
209#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
210
211/*
212 * The following macros handle the cache and bufferable bits...
213 */
214#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE
215#define _L_PTE_READ L_PTE_USER | L_PTE_EXEC
216
217extern pgprot_t pgprot_kernel;
218
219#define PAGE_NONE __pgprot(_L_PTE_DEFAULT)
220#define PAGE_COPY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
221#define PAGE_SHARED __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE)
222#define PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
223#define PAGE_KERNEL pgprot_kernel
224
225#endif /* __ASSEMBLY__ */
226
227/*
228 * The table below defines the page protection levels that we insert into our
229 * Linux page table version. These get translated into the best that the
230 * architecture can perform. Note that on most ARM hardware:
231 * 1) We cannot do execute protection
232 * 2) If we could do execute protection, then read is implied
233 * 3) write implies read permissions
234 */
235#define __P000 PAGE_NONE
236#define __P001 PAGE_READONLY
237#define __P010 PAGE_COPY
238#define __P011 PAGE_COPY
239#define __P100 PAGE_READONLY
240#define __P101 PAGE_READONLY
241#define __P110 PAGE_COPY
242#define __P111 PAGE_COPY
243
244#define __S000 PAGE_NONE
245#define __S001 PAGE_READONLY
246#define __S010 PAGE_SHARED
247#define __S011 PAGE_SHARED
248#define __S100 PAGE_READONLY
249#define __S101 PAGE_READONLY
250#define __S110 PAGE_SHARED
251#define __S111 PAGE_SHARED
252
253#ifndef __ASSEMBLY__
254/*
255 * ZERO_PAGE is a global shared page that is always zero: used
256 * for zero-mapped memory areas etc..
257 */
258extern struct page *empty_zero_page;
259#define ZERO_PAGE(vaddr) (empty_zero_page)
260
261#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
262#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
263
264#define pte_none(pte) (!pte_val(pte))
265#define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0))
266#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
267#define pte_offset_kernel(dir,addr) (pmd_page_kernel(*(dir)) + __pte_index(addr))
268#define pte_offset_map(dir,addr) (pmd_page_kernel(*(dir)) + __pte_index(addr))
269#define pte_offset_map_nested(dir,addr) (pmd_page_kernel(*(dir)) + __pte_index(addr))
270#define pte_unmap(pte) do { } while (0)
271#define pte_unmap_nested(pte) do { } while (0)
272
273#define set_pte(ptep, pte) cpu_set_pte(ptep,pte)
274#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
275
276/*
277 * The following only work if pte_present() is true.
278 * Undefined behaviour if not..
279 */
280#define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT)
281#define pte_read(pte) (pte_val(pte) & L_PTE_USER)
282#define pte_write(pte) (pte_val(pte) & L_PTE_WRITE)
283#define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC)
284#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY)
285#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG)
286
287/*
288 * The following only works if pte_present() is not true.
289 */
290#define pte_file(pte) (pte_val(pte) & L_PTE_FILE)
291#define pte_to_pgoff(x) (pte_val(x) >> 2)
292#define pgoff_to_pte(x) __pte(((x) << 2) | L_PTE_FILE)
293
294#define PTE_FILE_MAX_BITS 30
295
296#define PTE_BIT_FUNC(fn,op) \
297static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
298
299/*PTE_BIT_FUNC(rdprotect, &= ~L_PTE_USER);*/
300/*PTE_BIT_FUNC(mkread, |= L_PTE_USER);*/
301PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
302PTE_BIT_FUNC(mkwrite, |= L_PTE_WRITE);
303PTE_BIT_FUNC(exprotect, &= ~L_PTE_EXEC);
304PTE_BIT_FUNC(mkexec, |= L_PTE_EXEC);
305PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY);
306PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY);
307PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG);
308PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG);
309
310/*
311 * Mark the prot value as uncacheable and unbufferable.
312 */
313#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
314#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~L_PTE_CACHEABLE)
315
316#define pmd_none(pmd) (!pmd_val(pmd))
317#define pmd_present(pmd) (pmd_val(pmd))
318#define pmd_bad(pmd) (pmd_val(pmd) & 2)
319
320#define copy_pmd(pmdpd,pmdps) \
321 do { \
322 pmdpd[0] = pmdps[0]; \
323 pmdpd[1] = pmdps[1]; \
324 flush_pmd_entry(pmdpd); \
325 } while (0)
326
327#define pmd_clear(pmdp) \
328 do { \
329 pmdp[0] = __pmd(0); \
330 pmdp[1] = __pmd(0); \
331 clean_pmd_entry(pmdp); \
332 } while (0)
333
334static inline pte_t *pmd_page_kernel(pmd_t pmd)
335{
336 unsigned long ptr;
337
338 ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
339 ptr += PTRS_PER_PTE * sizeof(void *);
340
341 return __va(ptr);
342}
343
344#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
345
346/*
347 * Permanent address of a page. We never have highmem, so this is trivial.
348 */
349#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
350
351/*
352 * Conversion functions: convert a page and protection to a page entry,
353 * and a page entry and page directory to the page they refer to.
354 */
355#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
356
357/*
358 * The "pgd_xxx()" functions here are trivial for a folded two-level
359 * setup: the pgd is never bad, and a pmd always exists (as it's folded
360 * into the pgd entry)
361 */
362#define pgd_none(pgd) (0)
363#define pgd_bad(pgd) (0)
364#define pgd_present(pgd) (1)
365#define pgd_clear(pgdp) do { } while (0)
366#define set_pgd(pgd,pgdp) do { } while (0)
367
368#define page_pte_prot(page,prot) mk_pte(page, prot)
369#define page_pte(page) mk_pte(page, __pgprot(0))
370
371/* to find an entry in a page-table-directory */
372#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
373
374#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
375
376/* to find an entry in a kernel page-table-directory */
377#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
378
379/* Find an entry in the second-level page table.. */
380#define pmd_offset(dir, addr) ((pmd_t *)(dir))
381
382/* Find an entry in the third-level page table.. */
383#define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
384
385static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
386{
387 const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER;
388 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
389 return pte;
390}
391
392extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
393
394/* Encode and decode a swap entry.
395 *
396 * We support up to 32GB of swap on 4k machines
397 */
398#define __swp_type(x) (((x).val >> 2) & 0x7f)
399#define __swp_offset(x) ((x).val >> 9)
400#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
401#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
402#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
403
404/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
405/* FIXME: this is not correct */
406#define kern_addr_valid(addr) (1)
407
408#include <asm-generic/pgtable.h>
409
410/*
411 * We provide our own arch_get_unmapped_area to cope with VIPT caches.
412 */
413#define HAVE_ARCH_UNMAPPED_AREA
414
415/*
416 * remap a physical address `phys' of size `size' with page protection `prot'
417 * into virtual address `from'
418 */
419#define io_remap_page_range(vma,from,phys,size,prot) \
420 remap_pfn_range(vma, from, (phys) >> PAGE_SHIFT, size, prot)
421
422#define io_remap_pfn_range(vma,from,pfn,size,prot) \
423 remap_pfn_range(vma, from, pfn, size, prot)
424
425#define MK_IOSPACE_PFN(space, pfn) (pfn)
426#define GET_IOSPACE(pfn) 0
427#define GET_PFN(pfn) (pfn)
428
429#define pgtable_cache_init() do { } while (0)
430
431#endif /* !__ASSEMBLY__ */
432
433#endif /* _ASMARM_PGTABLE_H */