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authorJeff Garzik <jgarzik@pobox.com>2005-11-09 01:20:26 -0500
committerJeff Garzik <jgarzik@pobox.com>2005-11-09 01:20:26 -0500
commitc7c6e9494cc9a4a5b1a2ca870ed4531ad2b98a83 (patch)
tree1185ddc2c4cea1c4da09d6b83893f91aefe7cd3d /include/asm-arm/arch-realview/entry-macro.S
parent8cedcfd43a0b00741fff43d6a4c1a8b7748db3b0 (diff)
parent8e8b77dd4846b73f2e0756cf59123ee709246d11 (diff)
Merge branch 'upstream'
Diffstat (limited to 'include/asm-arm/arch-realview/entry-macro.S')
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 2712ba77bb3a..4df469bf42e2 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -47,3 +47,17 @@
47 cmpcs \irqnr, \irqnr 47 cmpcs \irqnr, \irqnr
48 48
49 .endm 49 .endm
50
51 /* We assume that irqstat (the raw value of the IRQ acknowledge
52 * register) is preserved from the macro above.
53 * If there is an IPI, we immediately signal end of interrupt on the
54 * controller, since this requires the original irqstat value which
55 * we won't easily be able to recreate later.
56 */
57
58 .macro test_for_ipi, irqnr, irqstat, base, tmp
59 bic \irqnr, \irqstat, #0x1c00
60 cmp \irqnr, #16
61 strcc \irqstat, [\base, #GIC_CPU_EOI]
62 cmpcs \irqnr, \irqnr
63 .endm