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authorJeff Garzik <jgarzik@pobox.com>2005-08-29 16:12:36 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-08-29 16:12:36 -0400
commit2fca877b68b2b4fc5b94277858a1bedd46017cde (patch)
treefd02725406299ba2f26354463b3c261721e9eb6b /include/asm-arm/arch-pxa/pxa-regs.h
parentff40c6d3d1437ecdf295b8e39adcb06c3d6021ef (diff)
parent02b3e4e2d71b6058ec11cc01c72ac651eb3ded2b (diff)
/spare/repo/libata-dev branch 'v2.6.13'
Diffstat (limited to 'include/asm-arm/arch-pxa/pxa-regs.h')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index b5e54a9e9fa7..51f0fe0ac165 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1505,6 +1505,7 @@
1505#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ 1505#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1506#define PSSR_RDH (1 << 5) /* Read Disable Hold */ 1506#define PSSR_RDH (1 << 5) /* Read Disable Hold */
1507#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ 1507#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1508#define PSSR_STS (1 << 3) /* Standby Mode Status */
1508#define PSSR_VFS (1 << 2) /* VDD Fault Status */ 1509#define PSSR_VFS (1 << 2) /* VDD Fault Status */
1509#define PSSR_BFS (1 << 1) /* Battery Fault Status */ 1510#define PSSR_BFS (1 << 1) /* Battery Fault Status */
1510#define PSSR_SSS (1 << 0) /* Software Sleep Status */ 1511#define PSSR_SSS (1 << 0) /* Software Sleep Status */
@@ -1965,6 +1966,7 @@
1965#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ 1966#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
1966#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ 1967#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
1967 1968
1969#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
1968#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ 1970#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
1969#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ 1971#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
1970#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ 1972#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */