[ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories

Now that Linux includes support for the Atmel AT91SAM9260 and
AT91SAM9261 processors in addition to the original Atmel AT91RM9200
(with support for more AT91 processors pending), the "mach-at91rm9200"
and "arch-at91rm9200" directories should be renamed to indicate their
more generic nature.

The following git commands should be run BEFORE applying this patch:
  git-mv arch/arm/mach-at91rm9200 arch/arm/mach-at91
  git-mv include/asm-arm/arch-at91rm9200 include/asm-arm/arch-at91

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 39 insertions, 0 deletions

diff --git a/include/asm-arm/arch-at91/at91_rstc.h b/include/asm-arm/arch-at91/at91_rstc.h
new file mode 100644
index 000000000000..0b7afbc015a2
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_rstc.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-at91/at91_rstc.h
+ *
+ * Reset Controller (RSTC) - System peripherals regsters.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_RSTC_H
+#define AT91_RSTC_H
+
+#define AT91_RSTC_CR            (AT91_RSTC + 0x00)      /* Reset Controller Control Register */
+#define         AT91_RSTC_PROCRST       (1 << 0)                /* Processor Reset */
+#define         AT91_RSTC_PERRST        (1 << 2)                /* Peripheral Reset */
+#define         AT91_RSTC_EXTRST        (1 << 3)                /* External Reset */
+#define         AT91_RSTC_KEY           (0xff << 24)            /* KEY Password */
+
+#define AT91_RSTC_SR            (AT91_RSTC + 0x04)      /* Reset Controller Status Register */
+#define         AT91_RSTC_URSTS         (1 << 0)                /* User Reset Status */
+#define         AT91_RSTC_RSTTYP        (7 << 8)                /* Reset Type */
+#define                 AT91_RSTC_RSTTYP_GENERAL        (0 << 8)
+#define                 AT91_RSTC_RSTTYP_WAKEUP         (1 << 8)
+#define                 AT91_RSTC_RSTTYP_WATCHDOG       (2 << 8)
+#define                 AT91_RSTC_RSTTYP_SOFTWARE       (3 << 8)
+#define                 AT91_RSTC_RSTTYP_USER   (4 << 8)
+#define         AT91_RSTC_NRSTL         (1 << 16)               /* NRST Pin Level */
+#define         AT91_RSTC_SRCMP         (1 << 17)               /* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR            (AT91_RSTC + 0x08)      /* Reset Controller Mode Register */
+#define         AT91_RSTC_URSTEN        (1 << 0)                /* User Reset Enable */
+#define         AT91_RSTC_URSTIEN       (1 << 4)                /* User Reset Interrupt Enable */
+#define         AT91_RSTC_ERSTL         (0xf << 8)              /* External Reset Length */
+#define         AT91_RSTC_KEY           (0xff << 24)            /* KEY Password */
+
+#endif