diff options
| author | Ingo Molnar <mingo@elte.hu> | 2008-07-18 13:31:12 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-18 13:31:12 -0400 |
| commit | 3e370b29d35fb01bfb92c2814d6f79bf6a2cb970 (patch) | |
| tree | 3b8fb467d60bfe6a34686f4abdc3a60050ba40a4 /include/asm-arm/arch-at91/at91_pmc.h | |
| parent | 88d1dce3a74367291f65a757fbdcaf17f042f30c (diff) | |
| parent | 5b664cb235e97afbf34db9c4d77f08ebd725335e (diff) | |
Merge branch 'linus' into x86/pci-ioapic-boot-irq-quirks
Conflicts:
drivers/pci/quirks.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-arm/arch-at91/at91_pmc.h')
| -rw-r--r-- | include/asm-arm/arch-at91/at91_pmc.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index c2b13c280155..2001e81f2267 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h | |||
| @@ -39,10 +39,14 @@ | |||
| 39 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | 39 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ |
| 40 | 40 | ||
| 41 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ | 41 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ |
| 42 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ | ||
| 43 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ | ||
| 44 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ | ||
| 45 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ | ||
| 42 | 46 | ||
| 43 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | 47 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ |
| 44 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | 48 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ |
| 45 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ | 49 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ |
| 46 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | 50 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ |
| 47 | 51 | ||
| 48 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | 52 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ |
| @@ -97,6 +101,7 @@ | |||
| 97 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | 101 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ |
| 98 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | 102 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ |
| 99 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | 103 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ |
| 104 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ | ||
| 100 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | 105 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ |
| 101 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | 106 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ |
| 102 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | 107 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ |