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authorLen Brown <len.brown@intel.com>2005-08-05 00:44:28 -0400
committerLen Brown <len.brown@intel.com>2005-08-05 00:45:14 -0400
commit4be44fcd3bf648b782f4460fd06dfae6c42ded4b (patch)
tree5b5b7d296ea58786f53b95e5eac9565ff66890b0 /include/acpi/actbl1.h
parentc65ade4dc8b486e8c8b9b0a6399789a5428e2039 (diff)
[ACPI] Lindent all ACPI files
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'include/acpi/actbl1.h')
-rw-r--r--include/acpi/actbl1.h133
1 files changed, 63 insertions, 70 deletions
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 93c175a4f446..67312c3a915a 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -49,94 +49,87 @@
49/* 49/*
50 * ACPI 1.0 Root System Description Table (RSDT) 50 * ACPI 1.0 Root System Description Table (RSDT)
51 */ 51 */
52struct rsdt_descriptor_rev1 52struct rsdt_descriptor_rev1 {
53{ 53 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
54 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 54 u32 table_offset_entry[1]; /* Array of pointers to ACPI tables */
55 u32 table_offset_entry[1]; /* Array of pointers to ACPI tables */
56}; 55};
57 56
58
59/* 57/*
60 * ACPI 1.0 Firmware ACPI Control Structure (FACS) 58 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
61 */ 59 */
62struct facs_descriptor_rev1 60struct facs_descriptor_rev1 {
63{ 61 char signature[4]; /* ASCII table signature */
64 char signature[4]; /* ASCII table signature */ 62 u32 length; /* Length of structure in bytes */
65 u32 length; /* Length of structure in bytes */ 63 u32 hardware_signature; /* Hardware configuration signature */
66 u32 hardware_signature; /* Hardware configuration signature */ 64 u32 firmware_waking_vector; /* ACPI OS waking vector */
67 u32 firmware_waking_vector; /* ACPI OS waking vector */ 65 u32 global_lock; /* Global Lock */
68 u32 global_lock; /* Global Lock */
69 66
70 /* Flags (32 bits) */ 67 /* Flags (32 bits) */
71 68
72 u8 S4bios_f : 1; /* 00: S4BIOS support is present */ 69 u8 S4bios_f:1; /* 00: S4BIOS support is present */
73 u8 : 7; /* 01-07: Reserved, must be zero */ 70 u8:7; /* 01-07: Reserved, must be zero */
74 u8 reserved1[3]; /* 08-31: Reserved, must be zero */ 71 u8 reserved1[3]; /* 08-31: Reserved, must be zero */
75 72
76 u8 reserved2[40]; /* Reserved, must be zero */ 73 u8 reserved2[40]; /* Reserved, must be zero */
77}; 74};
78 75
79
80/* 76/*
81 * ACPI 1.0 Fixed ACPI Description Table (FADT) 77 * ACPI 1.0 Fixed ACPI Description Table (FADT)
82 */ 78 */
83struct fadt_descriptor_rev1 79struct fadt_descriptor_rev1 {
84{ 80 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
85 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 81 u32 firmware_ctrl; /* Physical address of FACS */
86 u32 firmware_ctrl; /* Physical address of FACS */ 82 u32 dsdt; /* Physical address of DSDT */
87 u32 dsdt; /* Physical address of DSDT */ 83 u8 model; /* System Interrupt Model */
88 u8 model; /* System Interrupt Model */ 84 u8 reserved1; /* Reserved, must be zero */
89 u8 reserved1; /* Reserved, must be zero */ 85 u16 sci_int; /* System vector of SCI interrupt */
90 u16 sci_int; /* System vector of SCI interrupt */ 86 u32 smi_cmd; /* Port address of SMI command port */
91 u32 smi_cmd; /* Port address of SMI command port */ 87 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
92 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */ 88 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
93 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */ 89 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
94 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ 90 u8 reserved2; /* Reserved, must be zero */
95 u8 reserved2; /* Reserved, must be zero */ 91 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
96 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */ 92 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
97 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */ 93 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
98 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ 94 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
99 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ 95 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
100 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ 96 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
101 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ 97 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
102 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ 98 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
103 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ 99 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
104 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ 100 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
105 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ 101 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
106 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ 102 u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
107 u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */ 103 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
108 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ 104 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
109 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ 105 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
110 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */ 106 u8 reserved3; /* Reserved, must be zero */
111 u8 reserved3; /* Reserved, must be zero */ 107 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
112 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ 108 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
113 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ 109 u16 flush_size; /* Size of area read to flush caches */
114 u16 flush_size; /* Size of area read to flush caches */ 110 u16 flush_stride; /* Stride used in flushing caches */
115 u16 flush_stride; /* Stride used in flushing caches */ 111 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
116 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */ 112 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
117 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */ 113 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
118 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ 114 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
119 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ 115 u8 century; /* Index to century in RTC CMOS RAM */
120 u8 century; /* Index to century in RTC CMOS RAM */ 116 u8 reserved4[3]; /* Reserved, must be zero */
121 u8 reserved4[3]; /* Reserved, must be zero */
122 117
123 /* Flags (32 bits) */ 118 /* Flags (32 bits) */
124 119
125 u8 wb_invd : 1; /* 00: The wbinvd instruction works properly */ 120 u8 wb_invd:1; /* 00: The wbinvd instruction works properly */
126 u8 wb_invd_flush : 1; /* 01: The wbinvd flushes but does not invalidate */ 121 u8 wb_invd_flush:1; /* 01: The wbinvd flushes but does not invalidate */
127 u8 proc_c1 : 1; /* 02: All processors support C1 state */ 122 u8 proc_c1:1; /* 02: All processors support C1 state */
128 u8 plvl2_up : 1; /* 03: C2 state works on MP system */ 123 u8 plvl2_up:1; /* 03: C2 state works on MP system */
129 u8 pwr_button : 1; /* 04: Power button is handled as a generic feature */ 124 u8 pwr_button:1; /* 04: Power button is handled as a generic feature */
130 u8 sleep_button : 1; /* 05: Sleep button is handled as a generic feature, or not present */ 125 u8 sleep_button:1; /* 05: Sleep button is handled as a generic feature, or not present */
131 u8 fixed_rTC : 1; /* 06: RTC wakeup stat not in fixed register space */ 126 u8 fixed_rTC:1; /* 06: RTC wakeup stat not in fixed register space */
132 u8 rtcs4 : 1; /* 07: RTC wakeup stat not possible from S4 */ 127 u8 rtcs4:1; /* 07: RTC wakeup stat not possible from S4 */
133 u8 tmr_val_ext : 1; /* 08: tmr_val width is 32 bits (0 = 24 bits) */ 128 u8 tmr_val_ext:1; /* 08: tmr_val width is 32 bits (0 = 24 bits) */
134 u8 : 7; /* 09-15: Reserved, must be zero */ 129 u8:7; /* 09-15: Reserved, must be zero */
135 u8 reserved5[2]; /* 16-31: Reserved, must be zero */ 130 u8 reserved5[2]; /* 16-31: Reserved, must be zero */
136}; 131};
137 132
138#pragma pack() 133#pragma pack()
139 134
140#endif /* __ACTBL1_H__ */ 135#endif /* __ACTBL1_H__ */
141
142
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-19 21:44:03 -0400