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authorBob Moore <robert.moore@intel.com>2012-08-16 22:54:43 -0400
committerLen Brown <len.brown@intel.com>2012-09-21 00:26:16 -0400
commit80187431762989ebade986468d3c548287a12689 (patch)
treebfcd5fda8f6ad0a4fba30cd67f2cb56a9fd47df3 /include/acpi/actbl.h
parentd978348b300595b067b80980f6a78db09fcd584c (diff)
ACPICA: Comment update: Fix some typos in actble.h
No functional change. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'include/acpi/actbl.h')
-rw-r--r--include/acpi/actbl.h48
1 files changed, 24 insertions, 24 deletions
diff --git a/include/acpi/actbl.h b/include/acpi/actbl.h
index 59a73e1b2845..d54e3580b7d1 100644
--- a/include/acpi/actbl.h
+++ b/include/acpi/actbl.h
@@ -94,7 +94,7 @@
94struct acpi_table_header { 94struct acpi_table_header {
95 char signature[ACPI_NAME_SIZE]; /* ASCII table signature */ 95 char signature[ACPI_NAME_SIZE]; /* ASCII table signature */
96 u32 length; /* Length of table in bytes, including this header */ 96 u32 length; /* Length of table in bytes, including this header */
97 u8 revision; /* ACPI Specification minor version # */ 97 u8 revision; /* ACPI Specification minor version number */
98 u8 checksum; /* To make sum of entire table == 0 */ 98 u8 checksum; /* To make sum of entire table == 0 */
99 char oem_id[ACPI_OEM_ID_SIZE]; /* ASCII OEM identification */ 99 char oem_id[ACPI_OEM_ID_SIZE]; /* ASCII OEM identification */
100 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; /* ASCII OEM table identification */ 100 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; /* ASCII OEM table identification */
@@ -108,7 +108,7 @@ struct acpi_table_header {
108 * GAS - Generic Address Structure (ACPI 2.0+) 108 * GAS - Generic Address Structure (ACPI 2.0+)
109 * 109 *
110 * Note: Since this structure is used in the ACPI tables, it is byte aligned. 110 * Note: Since this structure is used in the ACPI tables, it is byte aligned.
111 * If misaliged access is not supported by the hardware, accesses to the 111 * If misaligned access is not supported by the hardware, accesses to the
112 * 64-bit Address field must be performed with care. 112 * 64-bit Address field must be performed with care.
113 * 113 *
114 ******************************************************************************/ 114 ******************************************************************************/
@@ -210,18 +210,18 @@ struct acpi_table_fadt {
210 u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */ 210 u8 preferred_profile; /* Conveys preferred power management profile to OSPM. */
211 u16 sci_interrupt; /* System vector of SCI interrupt */ 211 u16 sci_interrupt; /* System vector of SCI interrupt */
212 u32 smi_command; /* 32-bit Port address of SMI command port */ 212 u32 smi_command; /* 32-bit Port address of SMI command port */
213 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */ 213 u8 acpi_enable; /* Value to write to SMI_CMD to enable ACPI */
214 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */ 214 u8 acpi_disable; /* Value to write to SMI_CMD to disable ACPI */
215 u8 s4_bios_request; /* Value to write to SMI CMD to enter S4BIOS state */ 215 u8 s4_bios_request; /* Value to write to SMI_CMD to enter S4BIOS state */
216 u8 pstate_control; /* Processor performance state control */ 216 u8 pstate_control; /* Processor performance state control */
217 u32 pm1a_event_block; /* 32-bit Port address of Power Mgt 1a Event Reg Blk */ 217 u32 pm1a_event_block; /* 32-bit port address of Power Mgt 1a Event Reg Blk */
218 u32 pm1b_event_block; /* 32-bit Port address of Power Mgt 1b Event Reg Blk */ 218 u32 pm1b_event_block; /* 32-bit port address of Power Mgt 1b Event Reg Blk */
219 u32 pm1a_control_block; /* 32-bit Port address of Power Mgt 1a Control Reg Blk */ 219 u32 pm1a_control_block; /* 32-bit port address of Power Mgt 1a Control Reg Blk */
220 u32 pm1b_control_block; /* 32-bit Port address of Power Mgt 1b Control Reg Blk */ 220 u32 pm1b_control_block; /* 32-bit port address of Power Mgt 1b Control Reg Blk */
221 u32 pm2_control_block; /* 32-bit Port address of Power Mgt 2 Control Reg Blk */ 221 u32 pm2_control_block; /* 32-bit port address of Power Mgt 2 Control Reg Blk */
222 u32 pm_timer_block; /* 32-bit Port address of Power Mgt Timer Ctrl Reg Blk */ 222 u32 pm_timer_block; /* 32-bit port address of Power Mgt Timer Ctrl Reg Blk */
223 u32 gpe0_block; /* 32-bit Port address of General Purpose Event 0 Reg Blk */ 223 u32 gpe0_block; /* 32-bit port address of General Purpose Event 0 Reg Blk */
224 u32 gpe1_block; /* 32-bit Port address of General Purpose Event 1 Reg Blk */ 224 u32 gpe1_block; /* 32-bit port address of General Purpose Event 1 Reg Blk */
225 u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */ 225 u8 pm1_event_length; /* Byte Length of ports at pm1x_event_block */
226 u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */ 226 u8 pm1_control_length; /* Byte Length of ports at pm1x_control_block */
227 u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */ 227 u8 pm2_control_length; /* Byte Length of ports at pm2_control_block */
@@ -229,12 +229,12 @@ struct acpi_table_fadt {
229 u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */ 229 u8 gpe0_block_length; /* Byte Length of ports at gpe0_block */
230 u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */ 230 u8 gpe1_block_length; /* Byte Length of ports at gpe1_block */
231 u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */ 231 u8 gpe1_base; /* Offset in GPE number space where GPE1 events start */
232 u8 cst_control; /* Support for the _CST object and C States change notification */ 232 u8 cst_control; /* Support for the _CST object and C-States change notification */
233 u16 c2_latency; /* Worst case HW latency to enter/exit C2 state */ 233 u16 c2_latency; /* Worst case HW latency to enter/exit C2 state */
234 u16 c3_latency; /* Worst case HW latency to enter/exit C3 state */ 234 u16 c3_latency; /* Worst case HW latency to enter/exit C3 state */
235 u16 flush_size; /* Processor's memory cache line width, in bytes */ 235 u16 flush_size; /* Processor memory cache line width, in bytes */
236 u16 flush_stride; /* Number of flush strides that need to be read */ 236 u16 flush_stride; /* Number of flush strides that need to be read */
237 u8 duty_offset; /* Processor duty cycle index in processor's P_CNT reg */ 237 u8 duty_offset; /* Processor duty cycle index in processor P_CNT reg */
238 u8 duty_width; /* Processor duty cycle value bit width in P_CNT register */ 238 u8 duty_width; /* Processor duty cycle value bit width in P_CNT register */
239 u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */ 239 u8 day_alarm; /* Index to day-of-month alarm in RTC CMOS RAM */
240 u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */ 240 u8 month_alarm; /* Index to month-of-year alarm in RTC CMOS RAM */
@@ -255,11 +255,11 @@ struct acpi_table_fadt {
255 struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ 255 struct acpi_generic_address xpm_timer_block; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
256 struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */ 256 struct acpi_generic_address xgpe0_block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
257 struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */ 257 struct acpi_generic_address xgpe1_block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
258 struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register */ 258 struct acpi_generic_address sleep_control; /* 64-bit Sleep Control register (ACPI 5.0) */
259 struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register */ 259 struct acpi_generic_address sleep_status; /* 64-bit Sleep Status register (ACPI 5.0) */
260}; 260};
261 261
262/* Masks for FADT Boot Architecture Flags (boot_flags) */ 262/* Masks for FADT Boot Architecture Flags (boot_flags) [Vx]=Introduced in this FADT revision */
263 263
264#define ACPI_FADT_LEGACY_DEVICES (1) /* 00: [V2] System has LPC or ISA bus devices */ 264#define ACPI_FADT_LEGACY_DEVICES (1) /* 00: [V2] System has LPC or ISA bus devices */
265#define ACPI_FADT_8042 (1<<1) /* 01: [V3] System has an 8042 controller on port 60/64 */ 265#define ACPI_FADT_8042 (1<<1) /* 01: [V3] System has an 8042 controller on port 60/64 */
@@ -272,13 +272,13 @@ struct acpi_table_fadt {
272 272
273/* Masks for FADT flags */ 273/* Masks for FADT flags */
274 274
275#define ACPI_FADT_WBINVD (1) /* 00: [V1] The wbinvd instruction works properly */ 275#define ACPI_FADT_WBINVD (1) /* 00: [V1] The WBINVD instruction works properly */
276#define ACPI_FADT_WBINVD_FLUSH (1<<1) /* 01: [V1] wbinvd flushes but does not invalidate caches */ 276#define ACPI_FADT_WBINVD_FLUSH (1<<1) /* 01: [V1] WBINVD flushes but does not invalidate caches */
277#define ACPI_FADT_C1_SUPPORTED (1<<2) /* 02: [V1] All processors support C1 state */ 277#define ACPI_FADT_C1_SUPPORTED (1<<2) /* 02: [V1] All processors support C1 state */
278#define ACPI_FADT_C2_MP_SUPPORTED (1<<3) /* 03: [V1] C2 state works on MP system */ 278#define ACPI_FADT_C2_MP_SUPPORTED (1<<3) /* 03: [V1] C2 state works on MP system */
279#define ACPI_FADT_POWER_BUTTON (1<<4) /* 04: [V1] Power button is handled as a control method device */ 279#define ACPI_FADT_POWER_BUTTON (1<<4) /* 04: [V1] Power button is handled as a control method device */
280#define ACPI_FADT_SLEEP_BUTTON (1<<5) /* 05: [V1] Sleep button is handled as a control method device */ 280#define ACPI_FADT_SLEEP_BUTTON (1<<5) /* 05: [V1] Sleep button is handled as a control method device */
281#define ACPI_FADT_FIXED_RTC (1<<6) /* 06: [V1] RTC wakeup status not in fixed register space */ 281#define ACPI_FADT_FIXED_RTC (1<<6) /* 06: [V1] RTC wakeup status is not in fixed register space */
282#define ACPI_FADT_S4_RTC_WAKE (1<<7) /* 07: [V1] RTC alarm can wake system from S4 */ 282#define ACPI_FADT_S4_RTC_WAKE (1<<7) /* 07: [V1] RTC alarm can wake system from S4 */
283#define ACPI_FADT_32BIT_TIMER (1<<8) /* 08: [V1] ACPI timer width is 32-bit (0=24-bit) */ 283#define ACPI_FADT_32BIT_TIMER (1<<8) /* 08: [V1] ACPI timer width is 32-bit (0=24-bit) */
284#define ACPI_FADT_DOCKING_SUPPORTED (1<<9) /* 09: [V1] Docking supported */ 284#define ACPI_FADT_DOCKING_SUPPORTED (1<<9) /* 09: [V1] Docking supported */
@@ -297,7 +297,7 @@ struct acpi_table_fadt {
297 297
298/* Values for preferred_profile (Preferred Power Management Profiles) */ 298/* Values for preferred_profile (Preferred Power Management Profiles) */
299 299
300enum acpi_prefered_pm_profiles { 300enum acpi_preferred_pm_profiles {
301 PM_UNSPECIFIED = 0, 301 PM_UNSPECIFIED = 0,
302 PM_DESKTOP = 1, 302 PM_DESKTOP = 1,
303 PM_MOBILE = 2, 303 PM_MOBILE = 2,
@@ -335,7 +335,7 @@ union acpi_name_union {
335struct acpi_table_desc { 335struct acpi_table_desc {
336 acpi_physical_address address; 336 acpi_physical_address address;
337 struct acpi_table_header *pointer; 337 struct acpi_table_header *pointer;
338 u32 length; /* Length fixed at 32 bits */ 338 u32 length; /* Length fixed at 32 bits (fixed in table header) */
339 union acpi_name_union signature; 339 union acpi_name_union signature;
340 acpi_owner_id owner_id; 340 acpi_owner_id owner_id;
341 u8 flags; 341 u8 flags;