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authorDavid S. Miller <davem@davemloft.net>2008-01-21 20:15:40 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:10:16 -0500
commitf86e82fb547efe05457391df069cce7ab530b181 (patch)
tree31365a448cbf0327c329f9ea3393875f6f54f9e4 /drivers
parentfeebb33183cee0fdf8e8a9c4f0da3231f0cfa2bb (diff)
[BNX2]: Fix driver software flag namespace.
Prefix "bnx2->flags" names with BNX2_* for consistency. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2.c92
-rw-r--r--drivers/net/bnx2.h25
2 files changed, 59 insertions, 58 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 65812870c5ac..5605d419128e 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -580,7 +580,7 @@ bnx2_alloc_mem(struct bnx2 *bp)
580 580
581 /* Combine status and statistics blocks into one allocation. */ 581 /* Combine status and statistics blocks into one allocation. */
582 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block)); 582 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
583 if (bp->flags & MSIX_CAP_FLAG) 583 if (bp->flags & BNX2_FLAG_MSIX_CAP)
584 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC * 584 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
585 BNX2_SBLK_MSIX_ALIGN_SIZE); 585 BNX2_SBLK_MSIX_ALIGN_SIZE);
586 bp->status_stats_size = status_blk_size + 586 bp->status_stats_size = status_blk_size +
@@ -594,7 +594,7 @@ bnx2_alloc_mem(struct bnx2 *bp)
594 memset(bp->status_blk, 0, bp->status_stats_size); 594 memset(bp->status_blk, 0, bp->status_stats_size);
595 595
596 bp->bnx2_napi[0].status_blk = bp->status_blk; 596 bp->bnx2_napi[0].status_blk = bp->status_blk;
597 if (bp->flags & MSIX_CAP_FLAG) { 597 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
598 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) { 598 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
599 struct bnx2_napi *bnapi = &bp->bnx2_napi[i]; 599 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
600 600
@@ -3014,7 +3014,7 @@ static int bnx2_poll(struct napi_struct *napi, int budget)
3014 rmb(); 3014 rmb();
3015 if (likely(!bnx2_has_work(bnapi))) { 3015 if (likely(!bnx2_has_work(bnapi))) {
3016 netif_rx_complete(bp->dev, napi); 3016 netif_rx_complete(bp->dev, napi);
3017 if (likely(bp->flags & USING_MSI_OR_MSIX_FLAG)) { 3017 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3018 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 3018 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3019 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 3019 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3020 bnapi->last_status_idx); 3020 bnapi->last_status_idx);
@@ -3051,10 +3051,10 @@ bnx2_set_rx_mode(struct net_device *dev)
3051 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); 3051 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3052 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; 3052 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3053#ifdef BCM_VLAN 3053#ifdef BCM_VLAN
3054 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG)) 3054 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
3055 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 3055 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3056#else 3056#else
3057 if (!(bp->flags & ASF_ENABLE_FLAG)) 3057 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
3058 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; 3058 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3059#endif 3059#endif
3060 if (dev->flags & IFF_PROMISC) { 3060 if (dev->flags & IFF_PROMISC) {
@@ -3492,7 +3492,7 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3492 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; 3492 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3493 } 3493 }
3494 3494
3495 if (!(bp->flags & NO_WOL_FLAG)) 3495 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3496 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0); 3496 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3497 3497
3498 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 3498 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
@@ -4283,7 +4283,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4283 rc = bnx2_alloc_bad_rbuf(bp); 4283 rc = bnx2_alloc_bad_rbuf(bp);
4284 } 4284 }
4285 4285
4286 if (bp->flags & USING_MSIX_FLAG) 4286 if (bp->flags & BNX2_FLAG_USING_MSIX)
4287 bnx2_setup_msix_tbl(bp); 4287 bnx2_setup_msix_tbl(bp);
4288 4288
4289 return rc; 4289 return rc;
@@ -4309,11 +4309,11 @@ bnx2_init_chip(struct bnx2 *bp)
4309 4309
4310 val |= (0x2 << 20) | (1 << 11); 4310 val |= (0x2 << 20) | (1 << 11);
4311 4311
4312 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133)) 4312 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4313 val |= (1 << 23); 4313 val |= (1 << 23);
4314 4314
4315 if ((CHIP_NUM(bp) == CHIP_NUM_5706) && 4315 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4316 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG)) 4316 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4317 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; 4317 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4318 4318
4319 REG_WR(bp, BNX2_DMA_CONFIG, val); 4319 REG_WR(bp, BNX2_DMA_CONFIG, val);
@@ -4324,7 +4324,7 @@ bnx2_init_chip(struct bnx2 *bp)
4324 REG_WR(bp, BNX2_TDMA_CONFIG, val); 4324 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4325 } 4325 }
4326 4326
4327 if (bp->flags & PCIX_FLAG) { 4327 if (bp->flags & BNX2_FLAG_PCIX) {
4328 u16 val16; 4328 u16 val16;
4329 4329
4330 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, 4330 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
@@ -4438,7 +4438,7 @@ bnx2_init_chip(struct bnx2 *bp)
4438 BNX2_HC_CONFIG_COLLECT_STATS; 4438 BNX2_HC_CONFIG_COLLECT_STATS;
4439 } 4439 }
4440 4440
4441 if (bp->flags & USING_MSIX_FLAG) { 4441 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4442 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR, 4442 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4443 BNX2_HC_MSIX_BIT_VECTOR_VAL); 4443 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4444 4444
@@ -4456,7 +4456,7 @@ bnx2_init_chip(struct bnx2 *bp)
4456 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B; 4456 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4457 } 4457 }
4458 4458
4459 if (bp->flags & ONE_SHOT_MSI_FLAG) 4459 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4460 val |= BNX2_HC_CONFIG_ONE_SHOT; 4460 val |= BNX2_HC_CONFIG_ONE_SHOT;
4461 4461
4462 REG_WR(bp, BNX2_HC_CONFIG, val); 4462 REG_WR(bp, BNX2_HC_CONFIG, val);
@@ -4543,7 +4543,7 @@ bnx2_init_tx_ring(struct bnx2 *bp)
4543 struct bnx2_napi *bnapi; 4543 struct bnx2_napi *bnapi;
4544 4544
4545 bp->tx_vec = 0; 4545 bp->tx_vec = 0;
4546 if (bp->flags & USING_MSIX_FLAG) { 4546 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4547 cid = TX_TSS_CID; 4547 cid = TX_TSS_CID;
4548 bp->tx_vec = BNX2_TX_VEC; 4548 bp->tx_vec = BNX2_TX_VEC;
4549 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM | 4549 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
@@ -4693,7 +4693,7 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4693 bp->rx_pg_ring_size = 0; 4693 bp->rx_pg_ring_size = 0;
4694 bp->rx_max_pg_ring = 0; 4694 bp->rx_max_pg_ring = 0;
4695 bp->rx_max_pg_ring_idx = 0; 4695 bp->rx_max_pg_ring_idx = 0;
4696 if ((rx_space > PAGE_SIZE) && !(bp->flags & JUMBO_BROKEN_FLAG)) { 4696 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4697 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; 4697 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4698 4698
4699 jumbo_size = size * pages; 4699 jumbo_size = size * pages;
@@ -5075,7 +5075,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5075 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi; 5075 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5076 5076
5077 tx_napi = bnapi; 5077 tx_napi = bnapi;
5078 if (bp->flags & USING_MSIX_FLAG) 5078 if (bp->flags & BNX2_FLAG_USING_MSIX)
5079 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC]; 5079 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
5080 5080
5081 if (loopback_mode == BNX2_MAC_LOOPBACK) { 5081 if (loopback_mode == BNX2_MAC_LOOPBACK) {
@@ -5467,7 +5467,7 @@ bnx2_request_irq(struct bnx2 *bp)
5467 struct bnx2_irq *irq; 5467 struct bnx2_irq *irq;
5468 int rc = 0, i; 5468 int rc = 0, i;
5469 5469
5470 if (bp->flags & USING_MSI_OR_MSIX_FLAG) 5470 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5471 flags = 0; 5471 flags = 0;
5472 else 5472 else
5473 flags = IRQF_SHARED; 5473 flags = IRQF_SHARED;
@@ -5496,12 +5496,12 @@ bnx2_free_irq(struct bnx2 *bp)
5496 free_irq(irq->vector, dev); 5496 free_irq(irq->vector, dev);
5497 irq->requested = 0; 5497 irq->requested = 0;
5498 } 5498 }
5499 if (bp->flags & USING_MSI_FLAG) 5499 if (bp->flags & BNX2_FLAG_USING_MSI)
5500 pci_disable_msi(bp->pdev); 5500 pci_disable_msi(bp->pdev);
5501 else if (bp->flags & USING_MSIX_FLAG) 5501 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5502 pci_disable_msix(bp->pdev); 5502 pci_disable_msix(bp->pdev);
5503 5503
5504 bp->flags &= ~(USING_MSI_OR_MSIX_FLAG | ONE_SHOT_MSI_FLAG); 5504 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5505} 5505}
5506 5506
5507static void 5507static void
@@ -5533,7 +5533,7 @@ bnx2_enable_msix(struct bnx2 *bp)
5533 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx"); 5533 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5534 5534
5535 bp->irq_nvecs = BNX2_MAX_MSIX_VEC; 5535 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
5536 bp->flags |= USING_MSIX_FLAG | ONE_SHOT_MSI_FLAG; 5536 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5537 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) 5537 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5538 bp->irq_tbl[i].vector = msix_ent[i].vector; 5538 bp->irq_tbl[i].vector = msix_ent[i].vector;
5539} 5539}
@@ -5546,15 +5546,15 @@ bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5546 bp->irq_nvecs = 1; 5546 bp->irq_nvecs = 1;
5547 bp->irq_tbl[0].vector = bp->pdev->irq; 5547 bp->irq_tbl[0].vector = bp->pdev->irq;
5548 5548
5549 if ((bp->flags & MSIX_CAP_FLAG) && !dis_msi) 5549 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5550 bnx2_enable_msix(bp); 5550 bnx2_enable_msix(bp);
5551 5551
5552 if ((bp->flags & MSI_CAP_FLAG) && !dis_msi && 5552 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5553 !(bp->flags & USING_MSIX_FLAG)) { 5553 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5554 if (pci_enable_msi(bp->pdev) == 0) { 5554 if (pci_enable_msi(bp->pdev) == 0) {
5555 bp->flags |= USING_MSI_FLAG; 5555 bp->flags |= BNX2_FLAG_USING_MSI;
5556 if (CHIP_NUM(bp) == CHIP_NUM_5709) { 5556 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5557 bp->flags |= ONE_SHOT_MSI_FLAG; 5557 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5558 bp->irq_tbl[0].handler = bnx2_msi_1shot; 5558 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5559 } else 5559 } else
5560 bp->irq_tbl[0].handler = bnx2_msi; 5560 bp->irq_tbl[0].handler = bnx2_msi;
@@ -5606,7 +5606,7 @@ bnx2_open(struct net_device *dev)
5606 5606
5607 bnx2_enable_int(bp); 5607 bnx2_enable_int(bp);
5608 5608
5609 if (bp->flags & USING_MSI_FLAG) { 5609 if (bp->flags & BNX2_FLAG_USING_MSI) {
5610 /* Test MSI to make sure it is working 5610 /* Test MSI to make sure it is working
5611 * If MSI test fails, go back to INTx mode 5611 * If MSI test fails, go back to INTx mode
5612 */ 5612 */
@@ -5637,9 +5637,9 @@ bnx2_open(struct net_device *dev)
5637 bnx2_enable_int(bp); 5637 bnx2_enable_int(bp);
5638 } 5638 }
5639 } 5639 }
5640 if (bp->flags & USING_MSI_FLAG) 5640 if (bp->flags & BNX2_FLAG_USING_MSI)
5641 printk(KERN_INFO PFX "%s: using MSI\n", dev->name); 5641 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5642 else if (bp->flags & USING_MSIX_FLAG) 5642 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5643 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name); 5643 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5644 5644
5645 netif_start_queue(dev); 5645 netif_start_queue(dev);
@@ -5848,7 +5848,7 @@ bnx2_close(struct net_device *dev)
5848 bnx2_disable_int_sync(bp); 5848 bnx2_disable_int_sync(bp);
5849 bnx2_napi_disable(bp); 5849 bnx2_napi_disable(bp);
5850 del_timer_sync(&bp->timer); 5850 del_timer_sync(&bp->timer);
5851 if (bp->flags & NO_WOL_FLAG) 5851 if (bp->flags & BNX2_FLAG_NO_WOL)
5852 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; 5852 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5853 else if (bp->wol) 5853 else if (bp->wol)
5854 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 5854 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
@@ -6171,7 +6171,7 @@ bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6171{ 6171{
6172 struct bnx2 *bp = netdev_priv(dev); 6172 struct bnx2 *bp = netdev_priv(dev);
6173 6173
6174 if (bp->flags & NO_WOL_FLAG) { 6174 if (bp->flags & BNX2_FLAG_NO_WOL) {
6175 wol->supported = 0; 6175 wol->supported = 0;
6176 wol->wolopts = 0; 6176 wol->wolopts = 0;
6177 } 6177 }
@@ -6194,7 +6194,7 @@ bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6194 return -EINVAL; 6194 return -EINVAL;
6195 6195
6196 if (wol->wolopts & WAKE_MAGIC) { 6196 if (wol->wolopts & WAKE_MAGIC) {
6197 if (bp->flags & NO_WOL_FLAG) 6197 if (bp->flags & BNX2_FLAG_NO_WOL)
6198 return -EINVAL; 6198 return -EINVAL;
6199 6199
6200 bp->wol = 1; 6200 bp->wol = 1;
@@ -6966,7 +6966,7 @@ bnx2_get_pci_speed(struct bnx2 *bp)
6966 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { 6966 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
6967 u32 clkreg; 6967 u32 clkreg;
6968 6968
6969 bp->flags |= PCIX_FLAG; 6969 bp->flags |= BNX2_FLAG_PCIX;
6970 6970
6971 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); 6971 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
6972 6972
@@ -7005,7 +7005,7 @@ bnx2_get_pci_speed(struct bnx2 *bp)
7005 } 7005 }
7006 7006
7007 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) 7007 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7008 bp->flags |= PCI_32BIT_FLAG; 7008 bp->flags |= BNX2_FLAG_PCI_32BIT;
7009 7009
7010} 7010}
7011 7011
@@ -7093,9 +7093,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7093 rc = -EIO; 7093 rc = -EIO;
7094 goto err_out_unmap; 7094 goto err_out_unmap;
7095 } 7095 }
7096 bp->flags |= PCIE_FLAG; 7096 bp->flags |= BNX2_FLAG_PCIE;
7097 if (CHIP_REV(bp) == CHIP_REV_Ax) 7097 if (CHIP_REV(bp) == CHIP_REV_Ax)
7098 bp->flags |= JUMBO_BROKEN_FLAG; 7098 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7099 } else { 7099 } else {
7100 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); 7100 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7101 if (bp->pcix_cap == 0) { 7101 if (bp->pcix_cap == 0) {
@@ -7108,12 +7108,12 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7108 7108
7109 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) { 7109 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7110 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX)) 7110 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7111 bp->flags |= MSIX_CAP_FLAG; 7111 bp->flags |= BNX2_FLAG_MSIX_CAP;
7112 } 7112 }
7113 7113
7114 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) { 7114 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7115 if (pci_find_capability(pdev, PCI_CAP_ID_MSI)) 7115 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7116 bp->flags |= MSI_CAP_FLAG; 7116 bp->flags |= BNX2_FLAG_MSI_CAP;
7117 } 7117 }
7118 7118
7119 /* 5708 cannot support DMA addresses > 40-bit. */ 7119 /* 5708 cannot support DMA addresses > 40-bit. */
@@ -7136,7 +7136,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7136 goto err_out_unmap; 7136 goto err_out_unmap;
7137 } 7137 }
7138 7138
7139 if (!(bp->flags & PCIE_FLAG)) 7139 if (!(bp->flags & BNX2_FLAG_PCIE))
7140 bnx2_get_pci_speed(bp); 7140 bnx2_get_pci_speed(bp);
7141 7141
7142 /* 5706A0 may falsely detect SERR and PERR. */ 7142 /* 5706A0 may falsely detect SERR and PERR. */
@@ -7146,7 +7146,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7146 REG_WR(bp, PCI_COMMAND, reg); 7146 REG_WR(bp, PCI_COMMAND, reg);
7147 } 7147 }
7148 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && 7148 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7149 !(bp->flags & PCIX_FLAG)) { 7149 !(bp->flags & BNX2_FLAG_PCIX)) {
7150 7150
7151 dev_err(&pdev->dev, 7151 dev_err(&pdev->dev,
7152 "5706 A1 can only be used in a PCIX bus, aborting.\n"); 7152 "5706 A1 can only be used in a PCIX bus, aborting.\n");
@@ -7196,7 +7196,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7196 bp->wol = 1; 7196 bp->wol = 1;
7197 7197
7198 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) { 7198 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7199 bp->flags |= ASF_ENABLE_FLAG; 7199 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7200 7200
7201 for (i = 0; i < 30; i++) { 7201 for (i = 0; i < 30; i++) {
7202 reg = REG_RD_IND(bp, bp->shmem_base + 7202 reg = REG_RD_IND(bp, bp->shmem_base +
@@ -7268,7 +7268,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7268 reg = REG_RD_IND(bp, bp->shmem_base + 7268 reg = REG_RD_IND(bp, bp->shmem_base +
7269 BNX2_SHARED_HW_CFG_CONFIG); 7269 BNX2_SHARED_HW_CFG_CONFIG);
7270 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) { 7270 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7271 bp->flags |= NO_WOL_FLAG; 7271 bp->flags |= BNX2_FLAG_NO_WOL;
7272 bp->wol = 0; 7272 bp->wol = 0;
7273 } 7273 }
7274 if (CHIP_NUM(bp) != CHIP_NUM_5706) { 7274 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
@@ -7289,7 +7289,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7289 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || 7289 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7290 (CHIP_ID(bp) == CHIP_ID_5708_B0) || 7290 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7291 (CHIP_ID(bp) == CHIP_ID_5708_B1)) { 7291 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7292 bp->flags |= NO_WOL_FLAG; 7292 bp->flags |= BNX2_FLAG_NO_WOL;
7293 bp->wol = 0; 7293 bp->wol = 0;
7294 } 7294 }
7295 7295
@@ -7363,13 +7363,13 @@ bnx2_bus_string(struct bnx2 *bp, char *str)
7363{ 7363{
7364 char *s = str; 7364 char *s = str;
7365 7365
7366 if (bp->flags & PCIE_FLAG) { 7366 if (bp->flags & BNX2_FLAG_PCIE) {
7367 s += sprintf(s, "PCI Express"); 7367 s += sprintf(s, "PCI Express");
7368 } else { 7368 } else {
7369 s += sprintf(s, "PCI"); 7369 s += sprintf(s, "PCI");
7370 if (bp->flags & PCIX_FLAG) 7370 if (bp->flags & BNX2_FLAG_PCIX)
7371 s += sprintf(s, "-X"); 7371 s += sprintf(s, "-X");
7372 if (bp->flags & PCI_32BIT_FLAG) 7372 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7373 s += sprintf(s, " 32-bit"); 7373 s += sprintf(s, " 32-bit");
7374 else 7374 else
7375 s += sprintf(s, " 64-bit"); 7375 s += sprintf(s, " 64-bit");
@@ -7519,7 +7519,7 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7519 bnx2_netif_stop(bp); 7519 bnx2_netif_stop(bp);
7520 netif_device_detach(dev); 7520 netif_device_detach(dev);
7521 del_timer_sync(&bp->timer); 7521 del_timer_sync(&bp->timer);
7522 if (bp->flags & NO_WOL_FLAG) 7522 if (bp->flags & BNX2_FLAG_NO_WOL)
7523 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; 7523 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
7524 else if (bp->wol) 7524 else if (bp->wol)
7525 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; 7525 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 31a030a6e2a5..cd79b5cb01a8 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6580,18 +6580,19 @@ struct bnx2 {
6580 atomic_t intr_sem; 6580 atomic_t intr_sem;
6581 6581
6582 u32 flags; 6582 u32 flags;
6583#define PCIX_FLAG 0x00000001 6583#define BNX2_FLAG_PCIX 0x00000001
6584#define PCI_32BIT_FLAG 0x00000002 6584#define BNX2_FLAG_PCI_32BIT 0x00000002
6585#define MSIX_CAP_FLAG 0x00000004 6585#define BNX2_FLAG_MSIX_CAP 0x00000004
6586#define NO_WOL_FLAG 0x00000008 6586#define BNX2_FLAG_NO_WOL 0x00000008
6587#define USING_MSI_FLAG 0x00000020 6587#define BNX2_FLAG_USING_MSI 0x00000020
6588#define ASF_ENABLE_FLAG 0x00000040 6588#define BNX2_FLAG_ASF_ENABLE 0x00000040
6589#define MSI_CAP_FLAG 0x00000080 6589#define BNX2_FLAG_MSI_CAP 0x00000080
6590#define ONE_SHOT_MSI_FLAG 0x00000100 6590#define BNX2_FLAG_ONE_SHOT_MSI 0x00000100
6591#define PCIE_FLAG 0x00000200 6591#define BNX2_FLAG_PCIE 0x00000200
6592#define USING_MSIX_FLAG 0x00000400 6592#define BNX2_FLAG_USING_MSIX 0x00000400
6593#define USING_MSI_OR_MSIX_FLAG (USING_MSI_FLAG | USING_MSIX_FLAG) 6593#define BNX2_FLAG_USING_MSI_OR_MSIX (BNX2_FLAG_USING_MSI | \
6594#define JUMBO_BROKEN_FLAG 0x00000800 6594 BNX2_FLAG_USING_MSIX)
6595#define BNX2_FLAG_JUMBO_BROKEN 0x00000800
6595 6596
6596 /* Put tx producer and consumer fields in separate cache lines. */ 6597 /* Put tx producer and consumer fields in separate cache lines. */
6597 6598