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authorChris Wilson <chris@chris-wilson.co.uk>2012-12-07 05:43:25 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-12-17 06:39:11 -0500
commitf20e0b08b8b2a8432e6abf3683960099f0ab2958 (patch)
tree47a0df2f7bb51060896add32a35981859ce9d121 /drivers
parent52bd02d8e3fd83201a1a81bdb4ec6fc0b54d24a0 (diff)
drm/i915: Prefer CRTC 'active' rather than 'enabled' during WM computations
Only the intel_crtc->active is accurate at the point where we wish to perform WM computations, so use it instead of crtc->enabled. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfc46529f6df..5835277d9632 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -405,7 +405,7 @@ void intel_update_fbc(struct drm_device *dev)
405 * - going to an unsupported config (interlace, pixel multiply, etc.) 405 * - going to an unsupported config (interlace, pixel multiply, etc.)
406 */ 406 */
407 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { 407 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
408 if (tmp_crtc->enabled && 408 if (to_intel_crtc(tmp_crtc)->active &&
409 !to_intel_crtc(tmp_crtc)->primary_disabled && 409 !to_intel_crtc(tmp_crtc)->primary_disabled &&
410 tmp_crtc->fb) { 410 tmp_crtc->fb) {
411 if (crtc) { 411 if (crtc) {
@@ -992,7 +992,7 @@ static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
992 struct drm_crtc *crtc, *enabled = NULL; 992 struct drm_crtc *crtc, *enabled = NULL;
993 993
994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
995 if (crtc->enabled && crtc->fb) { 995 if (to_intel_crtc(crtc)->active && crtc->fb) {
996 if (enabled) 996 if (enabled)
997 return NULL; 997 return NULL;
998 enabled = crtc; 998 enabled = crtc;
@@ -1086,7 +1086,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
1086 int entries, tlb_miss; 1086 int entries, tlb_miss;
1087 1087
1088 crtc = intel_get_crtc_for_plane(dev, plane); 1088 crtc = intel_get_crtc_for_plane(dev, plane);
1089 if (crtc->fb == NULL || !crtc->enabled) { 1089 if (crtc->fb == NULL || !to_intel_crtc(crtc)->active) {
1090 *cursor_wm = cursor->guard_size; 1090 *cursor_wm = cursor->guard_size;
1091 *plane_wm = display->guard_size; 1091 *plane_wm = display->guard_size;
1092 return false; 1092 return false;
@@ -1215,7 +1215,7 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
1215 int entries; 1215 int entries;
1216 1216
1217 crtc = intel_get_crtc_for_plane(dev, plane); 1217 crtc = intel_get_crtc_for_plane(dev, plane);
1218 if (crtc->fb == NULL || !crtc->enabled) 1218 if (crtc->fb == NULL || !to_intel_crtc(crtc)->active)
1219 return false; 1219 return false;
1220 1220
1221 clock = crtc->mode.clock; /* VESA DOT Clock */ 1221 clock = crtc->mode.clock; /* VESA DOT Clock */
@@ -1476,7 +1476,7 @@ static void i9xx_update_wm(struct drm_device *dev)
1476 1476
1477 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1477 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1478 crtc = intel_get_crtc_for_plane(dev, 0); 1478 crtc = intel_get_crtc_for_plane(dev, 0);
1479 if (crtc->enabled && crtc->fb) { 1479 if (to_intel_crtc(crtc)->active && crtc->fb) {
1480 int cpp = crtc->fb->bits_per_pixel / 8; 1480 int cpp = crtc->fb->bits_per_pixel / 8;
1481 if (IS_GEN2(dev)) 1481 if (IS_GEN2(dev))
1482 cpp = 4; 1482 cpp = 4;
@@ -1490,7 +1490,7 @@ static void i9xx_update_wm(struct drm_device *dev)
1490 1490
1491 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1491 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1492 crtc = intel_get_crtc_for_plane(dev, 1); 1492 crtc = intel_get_crtc_for_plane(dev, 1);
1493 if (crtc->enabled && crtc->fb) { 1493 if (to_intel_crtc(crtc)->active && crtc->fb) {
1494 int cpp = crtc->fb->bits_per_pixel / 8; 1494 int cpp = crtc->fb->bits_per_pixel / 8;
1495 if (IS_GEN2(dev)) 1495 if (IS_GEN2(dev))
1496 cpp = 4; 1496 cpp = 4;
@@ -2044,7 +2044,7 @@ sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2044 int entries, tlb_miss; 2044 int entries, tlb_miss;
2045 2045
2046 crtc = intel_get_crtc_for_plane(dev, plane); 2046 crtc = intel_get_crtc_for_plane(dev, plane);
2047 if (crtc->fb == NULL || !crtc->enabled) { 2047 if (crtc->fb == NULL || !to_intel_crtc(crtc)->active) {
2048 *sprite_wm = display->guard_size; 2048 *sprite_wm = display->guard_size;
2049 return false; 2049 return false;
2050 } 2050 }