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authorAntti Palosaari <crope@iki.fi>2011-11-06 18:01:13 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-01-10 19:56:55 -0500
commitee9b8c8c27679b2b8ab5e8749cb3813d55b49755 (patch)
treec0a4674ebfac58505e08ea071623c7fc20e52918 /drivers
parent53b667eb12edd1bb33beca73ab14dbdf4d536c37 (diff)
[media] HDIC HD29L2 DMB-TH demodulator driver
Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/dvb/frontends/Kconfig7
-rw-r--r--drivers/media/dvb/frontends/Makefile1
-rw-r--r--drivers/media/dvb/frontends/hd29l2.c863
-rw-r--r--drivers/media/dvb/frontends/hd29l2.h66
-rw-r--r--drivers/media/dvb/frontends/hd29l2_priv.h314
5 files changed, 1251 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 4a2d2e6c91ab..ebb5ed7a7783 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -404,6 +404,13 @@ config DVB_EC100
404 help 404 help
405 Say Y when you want to support this frontend. 405 Say Y when you want to support this frontend.
406 406
407config DVB_HD29L2
408 tristate "HDIC HD29L2"
409 depends on DVB_CORE && I2C
410 default m if DVB_FE_CUSTOMISE
411 help
412 Say Y when you want to support this frontend.
413
407config DVB_STV0367 414config DVB_STV0367
408 tristate "ST STV0367 based" 415 tristate "ST STV0367 based"
409 depends on DVB_CORE && I2C 416 depends on DVB_CORE && I2C
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index f639f6781551..00a20636df62 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -84,6 +84,7 @@ obj-$(CONFIG_DVB_STV090x) += stv090x.o
84obj-$(CONFIG_DVB_STV6110x) += stv6110x.o 84obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
85obj-$(CONFIG_DVB_ISL6423) += isl6423.o 85obj-$(CONFIG_DVB_ISL6423) += isl6423.o
86obj-$(CONFIG_DVB_EC100) += ec100.o 86obj-$(CONFIG_DVB_EC100) += ec100.o
87obj-$(CONFIG_DVB_HD29L2) += hd29l2.o
87obj-$(CONFIG_DVB_DS3000) += ds3000.o 88obj-$(CONFIG_DVB_DS3000) += ds3000.o
88obj-$(CONFIG_DVB_MB86A16) += mb86a16.o 89obj-$(CONFIG_DVB_MB86A16) += mb86a16.o
89obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o 90obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
diff --git a/drivers/media/dvb/frontends/hd29l2.c b/drivers/media/dvb/frontends/hd29l2.c
new file mode 100644
index 000000000000..a85ed47da810
--- /dev/null
+++ b/drivers/media/dvb/frontends/hd29l2.c
@@ -0,0 +1,863 @@
1/*
2 * HDIC HD29L2 DMB-TH demodulator driver
3 *
4 * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
5 *
6 * Author: Antti Palosaari <crope@iki.fi>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include "hd29l2_priv.h"
24
25int hd29l2_debug;
26module_param_named(debug, hd29l2_debug, int, 0644);
27MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
28
29/* write multiple registers */
30static int hd29l2_wr_regs(struct hd29l2_priv *priv, u8 reg, u8 *val, int len)
31{
32 int ret;
33 u8 buf[2+len];
34 struct i2c_msg msg[1] = {
35 {
36 .addr = priv->cfg.i2c_addr,
37 .flags = 0,
38 .len = sizeof(buf),
39 .buf = buf,
40 }
41 };
42
43 buf[0] = 0x00;
44 buf[1] = reg;
45 memcpy(&buf[2], val, len);
46
47 ret = i2c_transfer(priv->i2c, msg, 1);
48 if (ret == 1) {
49 ret = 0;
50 } else {
51 warn("i2c wr failed=%d reg=%02x len=%d", ret, reg, len);
52 ret = -EREMOTEIO;
53 }
54
55 return ret;
56}
57
58/* read multiple registers */
59static int hd29l2_rd_regs(struct hd29l2_priv *priv, u8 reg, u8 *val, int len)
60{
61 int ret;
62 u8 buf[2] = { 0x00, reg };
63 struct i2c_msg msg[2] = {
64 {
65 .addr = priv->cfg.i2c_addr,
66 .flags = 0,
67 .len = 2,
68 .buf = buf,
69 }, {
70 .addr = priv->cfg.i2c_addr,
71 .flags = I2C_M_RD,
72 .len = len,
73 .buf = val,
74 }
75 };
76
77 ret = i2c_transfer(priv->i2c, msg, 2);
78 if (ret == 2) {
79 ret = 0;
80 } else {
81 warn("i2c rd failed=%d reg=%02x len=%d", ret, reg, len);
82 ret = -EREMOTEIO;
83 }
84
85 return ret;
86}
87
88/* write single register */
89static int hd29l2_wr_reg(struct hd29l2_priv *priv, u8 reg, u8 val)
90{
91 return hd29l2_wr_regs(priv, reg, &val, 1);
92}
93
94/* read single register */
95static int hd29l2_rd_reg(struct hd29l2_priv *priv, u8 reg, u8 *val)
96{
97 return hd29l2_rd_regs(priv, reg, val, 1);
98}
99
100/* write single register with mask */
101static int hd29l2_wr_reg_mask(struct hd29l2_priv *priv, u8 reg, u8 val, u8 mask)
102{
103 int ret;
104 u8 tmp;
105
106 /* no need for read if whole reg is written */
107 if (mask != 0xff) {
108 ret = hd29l2_rd_regs(priv, reg, &tmp, 1);
109 if (ret)
110 return ret;
111
112 val &= mask;
113 tmp &= ~mask;
114 val |= tmp;
115 }
116
117 return hd29l2_wr_regs(priv, reg, &val, 1);
118}
119
120/* read single register with mask */
121int hd29l2_rd_reg_mask(struct hd29l2_priv *priv, u8 reg, u8 *val, u8 mask)
122{
123 int ret, i;
124 u8 tmp;
125
126 ret = hd29l2_rd_regs(priv, reg, &tmp, 1);
127 if (ret)
128 return ret;
129
130 tmp &= mask;
131
132 /* find position of the first bit */
133 for (i = 0; i < 8; i++) {
134 if ((mask >> i) & 0x01)
135 break;
136 }
137 *val = tmp >> i;
138
139 return 0;
140}
141
142static int hd29l2_soft_reset(struct hd29l2_priv *priv)
143{
144 int ret;
145 u8 tmp;
146
147 ret = hd29l2_rd_reg(priv, 0x26, &tmp);
148 if (ret)
149 goto err;
150
151 ret = hd29l2_wr_reg(priv, 0x26, 0x0d);
152 if (ret)
153 goto err;
154
155 usleep_range(10000, 20000);
156
157 ret = hd29l2_wr_reg(priv, 0x26, tmp);
158 if (ret)
159 goto err;
160
161 return 0;
162err:
163 dbg("%s: failed=%d", __func__, ret);
164 return ret;
165}
166
167static int hd29l2_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
168{
169 int ret, i;
170 struct hd29l2_priv *priv = fe->demodulator_priv;
171 u8 tmp;
172
173 dbg("%s: enable=%d", __func__, enable);
174
175 /* set tuner address for demod */
176 if (!priv->tuner_i2c_addr_programmed && enable) {
177 /* no need to set tuner address every time, once is enough */
178 ret = hd29l2_wr_reg(priv, 0x9d, priv->cfg.tuner_i2c_addr << 1);
179 if (ret)
180 goto err;
181
182 priv->tuner_i2c_addr_programmed = true;
183 }
184
185 /* open / close gate */
186 ret = hd29l2_wr_reg(priv, 0x9f, enable);
187 if (ret)
188 goto err;
189
190 /* wait demod ready */
191 for (i = 10; i; i--) {
192 ret = hd29l2_rd_reg(priv, 0x9e, &tmp);
193 if (ret)
194 goto err;
195
196 if (tmp == enable)
197 break;
198
199 usleep_range(5000, 10000);
200 }
201
202 dbg("%s: loop=%d", __func__, i);
203
204 return ret;
205err:
206 dbg("%s: failed=%d", __func__, ret);
207 return ret;
208}
209
210static int hd29l2_read_status(struct dvb_frontend *fe, fe_status_t *status)
211{
212 int ret;
213 struct hd29l2_priv *priv = fe->demodulator_priv;
214 u8 buf[2];
215
216 *status = 0;
217
218 ret = hd29l2_rd_reg(priv, 0x05, &buf[0]);
219 if (ret)
220 goto err;
221
222 if (buf[0] & 0x01) {
223 /* full lock */
224 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI |
225 FE_HAS_SYNC | FE_HAS_LOCK;
226 } else {
227 ret = hd29l2_rd_reg(priv, 0x0d, &buf[1]);
228 if (ret)
229 goto err;
230
231 if ((buf[1] & 0xfe) == 0x78)
232 /* partial lock */
233 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
234 FE_HAS_VITERBI | FE_HAS_SYNC;
235 }
236
237 priv->fe_status = *status;
238
239 return 0;
240err:
241 dbg("%s: failed=%d", __func__, ret);
242 return ret;
243}
244
245static int hd29l2_read_snr(struct dvb_frontend *fe, u16 *snr)
246{
247 int ret;
248 struct hd29l2_priv *priv = fe->demodulator_priv;
249 u8 buf[2];
250 u16 tmp;
251
252 if (!(priv->fe_status & FE_HAS_LOCK)) {
253 *snr = 0;
254 ret = 0;
255 goto err;
256 }
257
258 ret = hd29l2_rd_regs(priv, 0x0b, buf, 2);
259 if (ret)
260 goto err;
261
262 tmp = (buf[0] << 8) | buf[1];
263
264 /* report SNR in dB * 10 */
265 #define LOG10_20736_24 72422627 /* log10(20736) << 24 */
266 if (tmp)
267 *snr = (LOG10_20736_24 - intlog10(tmp)) / ((1 << 24) / 100);
268 else
269 *snr = 0;
270
271 return 0;
272err:
273 dbg("%s: failed=%d", __func__, ret);
274 return ret;
275}
276
277static int hd29l2_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
278{
279 int ret;
280 struct hd29l2_priv *priv = fe->demodulator_priv;
281 u8 buf[2];
282 u16 tmp;
283
284 *strength = 0;
285
286 ret = hd29l2_rd_regs(priv, 0xd5, buf, 2);
287 if (ret)
288 goto err;
289
290 tmp = buf[0] << 8 | buf[1];
291 tmp = ~tmp & 0x0fff;
292
293 /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
294 *strength = tmp * 0xffff / 0x0fff;
295
296 return 0;
297err:
298 dbg("%s: failed=%d", __func__, ret);
299 return ret;
300}
301
302static int hd29l2_read_ber(struct dvb_frontend *fe, u32 *ber)
303{
304 int ret;
305 struct hd29l2_priv *priv = fe->demodulator_priv;
306 u8 buf[2];
307
308 if (!(priv->fe_status & FE_HAS_SYNC)) {
309 *ber = 0;
310 ret = 0;
311 goto err;
312 }
313
314 ret = hd29l2_rd_regs(priv, 0xd9, buf, 2);
315 if (ret) {
316 *ber = 0;
317 goto err;
318 }
319
320 /* LDPC BER */
321 *ber = ((buf[0] & 0x0f) << 8) | buf[1];
322
323 return 0;
324err:
325 dbg("%s: failed=%d", __func__, ret);
326 return ret;
327}
328
329static int hd29l2_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
330{
331 /* no way to read? */
332 *ucblocks = 0;
333 return 0;
334}
335
336static enum dvbfe_search hd29l2_search(struct dvb_frontend *fe,
337 struct dvb_frontend_parameters *p)
338{
339 int ret, i;
340 struct hd29l2_priv *priv = fe->demodulator_priv;
341 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
342 u8 tmp, buf[3];
343 u8 modulation, carrier, guard_interval, interleave, code_rate;
344 u64 num64;
345 u32 if_freq, if_ctl;
346 bool auto_mode;
347
348 dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d " \
349 "modulation=%d inversion=%d fec_inner=%d guard_interval=%d",
350 __func__,
351 c->delivery_system, c->frequency, c->bandwidth_hz,
352 c->modulation, c->inversion, c->fec_inner, c->guard_interval);
353
354 /* as for now we detect always params automatically */
355 auto_mode = true;
356
357 /* program tuner */
358 if (fe->ops.tuner_ops.set_params)
359 fe->ops.tuner_ops.set_params(fe, p);
360
361 /* get and program IF */
362 if (fe->ops.tuner_ops.get_if_frequency)
363 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
364 else
365 if_freq = 0;
366
367 if (if_freq) {
368 /* normal IF */
369
370 /* calc IF control value */
371 num64 = if_freq;
372 num64 *= 0x800000;
373 num64 = div_u64(num64, HD29L2_XTAL);
374 num64 -= 0x800000;
375 if_ctl = num64;
376
377 tmp = 0xfc; /* tuner type normal */
378 } else {
379 /* zero IF */
380 if_ctl = 0;
381 tmp = 0xfe; /* tuner type Zero-IF */
382 }
383
384 buf[0] = ((if_ctl >> 0) & 0xff);
385 buf[1] = ((if_ctl >> 8) & 0xff);
386 buf[2] = ((if_ctl >> 16) & 0xff);
387
388 /* program IF control */
389 ret = hd29l2_wr_regs(priv, 0x14, buf, 3);
390 if (ret)
391 goto err;
392
393 /* program tuner type */
394 ret = hd29l2_wr_reg(priv, 0xab, tmp);
395 if (ret)
396 goto err;
397
398 dbg("%s: if_ctl=%x", __func__, if_ctl);
399
400 if (auto_mode) {
401 /*
402 * use auto mode
403 */
404
405 /* disable quick mode */
406 ret = hd29l2_wr_reg_mask(priv, 0xac, 0 << 7, 0x80);
407 if (ret)
408 goto err;
409
410 ret = hd29l2_wr_reg_mask(priv, 0x82, 1 << 1, 0x02);
411 if (ret)
412 goto err;
413
414 /* enable auto mode */
415 ret = hd29l2_wr_reg_mask(priv, 0x7d, 1 << 6, 0x40);
416 if (ret)
417 goto err;
418
419 ret = hd29l2_wr_reg_mask(priv, 0x81, 1 << 3, 0x08);
420 if (ret)
421 goto err;
422
423 /* soft reset */
424 ret = hd29l2_soft_reset(priv);
425 if (ret)
426 goto err;
427
428 /* detect modulation */
429 for (i = 30; i; i--) {
430 msleep(100);
431
432 ret = hd29l2_rd_reg(priv, 0x0d, &tmp);
433 if (ret)
434 goto err;
435
436 if ((((tmp & 0xf0) >= 0x10) &&
437 ((tmp & 0x0f) == 0x08)) || (tmp >= 0x2c))
438 break;
439 }
440
441 dbg("%s: loop=%d", __func__, i);
442
443 if (i == 0)
444 /* detection failed */
445 return DVBFE_ALGO_SEARCH_FAILED;
446
447 /* read modulation */
448 ret = hd29l2_rd_reg_mask(priv, 0x7d, &modulation, 0x07);
449 if (ret)
450 goto err;
451 } else {
452 /*
453 * use manual mode
454 */
455
456 modulation = HD29L2_QAM64;
457 carrier = HD29L2_CARRIER_MULTI;
458 guard_interval = HD29L2_PN945;
459 interleave = HD29L2_INTERLEAVER_420;
460 code_rate = HD29L2_CODE_RATE_08;
461
462 tmp = (code_rate << 3) | modulation;
463 ret = hd29l2_wr_reg_mask(priv, 0x7d, tmp, 0x5f);
464 if (ret)
465 goto err;
466
467 tmp = (carrier << 2) | guard_interval;
468 ret = hd29l2_wr_reg_mask(priv, 0x81, tmp, 0x0f);
469 if (ret)
470 goto err;
471
472 tmp = interleave;
473 ret = hd29l2_wr_reg_mask(priv, 0x82, tmp, 0x03);
474 if (ret)
475 goto err;
476 }
477
478 /* ensure modulation validy */
479 /* 0=QAM4_NR, 1=QAM4, 2=QAM16, 3=QAM32, 4=QAM64 */
480 if (modulation > 4) {
481 dbg("%s: modulation=%d not valid", __func__, modulation);
482 goto err;
483 }
484
485 /* program registers according to modulation */
486 for (i = 0; i < ARRAY_SIZE(reg_mod_vals_tab); i++) {
487 ret = hd29l2_wr_reg(priv, reg_mod_vals_tab[i].reg,
488 reg_mod_vals_tab[i].val[modulation]);
489 if (ret)
490 goto err;
491 }
492
493 /* read guard interval */
494 ret = hd29l2_rd_reg_mask(priv, 0x81, &guard_interval, 0x03);
495 if (ret)
496 goto err;
497
498 /* read carrier mode */
499 ret = hd29l2_rd_reg_mask(priv, 0x81, &carrier, 0x04);
500 if (ret)
501 goto err;
502
503 dbg("%s: modulation=%d guard_interval=%d carrier=%d",
504 __func__, modulation, guard_interval, carrier);
505
506 if ((carrier == HD29L2_CARRIER_MULTI) && (modulation == HD29L2_QAM64) &&
507 (guard_interval == HD29L2_PN945)) {
508 dbg("%s: C=3780 && QAM64 && PN945", __func__);
509
510 ret = hd29l2_wr_reg(priv, 0x42, 0x33);
511 if (ret)
512 goto err;
513
514 ret = hd29l2_wr_reg(priv, 0xdd, 0x01);
515 if (ret)
516 goto err;
517 }
518
519 usleep_range(10000, 20000);
520
521 /* soft reset */
522 ret = hd29l2_soft_reset(priv);
523 if (ret)
524 goto err;
525
526 /* wait demod lock */
527 for (i = 30; i; i--) {
528 msleep(100);
529
530 /* read lock bit */
531 ret = hd29l2_rd_reg_mask(priv, 0x05, &tmp, 0x01);
532 if (ret)
533 goto err;
534
535 if (tmp)
536 break;
537 }
538
539 dbg("%s: loop=%d", __func__, i);
540
541 if (i == 0)
542 return DVBFE_ALGO_SEARCH_AGAIN;
543
544 return DVBFE_ALGO_SEARCH_SUCCESS;
545err:
546 dbg("%s: failed=%d", __func__, ret);
547 return DVBFE_ALGO_SEARCH_ERROR;
548}
549
550static int hd29l2_get_frontend_algo(struct dvb_frontend *fe)
551{
552 return DVBFE_ALGO_CUSTOM;
553}
554
555static int hd29l2_get_frontend(struct dvb_frontend *fe,
556 struct dvb_frontend_parameters *p)
557{
558 int ret;
559 struct hd29l2_priv *priv = fe->demodulator_priv;
560 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
561 u8 buf[3];
562 u32 if_ctl;
563 char *str_constellation, *str_code_rate, *str_constellation_code_rate,
564 *str_guard_interval, *str_carrier, *str_guard_interval_carrier,
565 *str_interleave, *str_interleave_;
566
567 ret = hd29l2_rd_reg(priv, 0x7d, &buf[0]);
568 if (ret)
569 goto err;
570
571 ret = hd29l2_rd_regs(priv, 0x81, &buf[1], 2);
572 if (ret)
573 goto err;
574
575 /* constellation, 0x7d[2:0] */
576 switch ((buf[0] >> 0) & 0x07) {
577 case 0: /* QAM4NR */
578 str_constellation = "QAM4NR";
579 c->modulation = QAM_AUTO; /* FIXME */
580 break;
581 case 1: /* QAM4 */
582 str_constellation = "QAM4";
583 c->modulation = QPSK; /* FIXME */
584 break;
585 case 2:
586 str_constellation = "QAM16";
587 c->modulation = QAM_16;
588 break;
589 case 3:
590 str_constellation = "QAM32";
591 c->modulation = QAM_32;
592 break;
593 case 4:
594 str_constellation = "QAM64";
595 c->modulation = QAM_64;
596 break;
597 default:
598 str_constellation = "?";
599 }
600
601 /* LDPC code rate, 0x7d[4:3] */
602 switch ((buf[0] >> 3) & 0x03) {
603 case 0: /* 0.4 */
604 str_code_rate = "0.4";
605 c->fec_inner = FEC_AUTO; /* FIXME */
606 break;
607 case 1: /* 0.6 */
608 str_code_rate = "0.6";
609 c->fec_inner = FEC_3_5;
610 break;
611 case 2: /* 0.8 */
612 str_code_rate = "0.8";
613 c->fec_inner = FEC_4_5;
614 break;
615 default:
616 str_code_rate = "?";
617 }
618
619 /* constellation & code rate set, 0x7d[6] */
620 switch ((buf[0] >> 6) & 0x01) {
621 case 0:
622 str_constellation_code_rate = "manual";
623 break;
624 case 1:
625 str_constellation_code_rate = "auto";
626 break;
627 default:
628 str_constellation_code_rate = "?";
629 }
630
631 /* frame header, 0x81[1:0] */
632 switch ((buf[1] >> 0) & 0x03) {
633 case 0: /* PN945 */
634 str_guard_interval = "PN945";
635 c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
636 break;
637 case 1: /* PN595 */
638 str_guard_interval = "PN595";
639 c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
640 break;
641 case 2: /* PN420 */
642 str_guard_interval = "PN420";
643 c->guard_interval = GUARD_INTERVAL_AUTO; /* FIXME */
644 break;
645 default:
646 str_guard_interval = "?";
647 }
648
649 /* carrier, 0x81[2] */
650 switch ((buf[1] >> 2) & 0x01) {
651 case 0:
652 str_carrier = "C=1";
653 break;
654 case 1:
655 str_carrier = "C=3780";
656 break;
657 default:
658 str_carrier = "?";
659 }
660
661 /* frame header & carrier set, 0x81[3] */
662 switch ((buf[1] >> 3) & 0x01) {
663 case 0:
664 str_guard_interval_carrier = "manual";
665 break;
666 case 1:
667 str_guard_interval_carrier = "auto";
668 break;
669 default:
670 str_guard_interval_carrier = "?";
671 }
672
673 /* interleave, 0x82[0] */
674 switch ((buf[2] >> 0) & 0x01) {
675 case 0:
676 str_interleave = "M=720";
677 break;
678 case 1:
679 str_interleave = "M=240";
680 break;
681 default:
682 str_interleave = "?";
683 }
684
685 /* interleave set, 0x82[1] */
686 switch ((buf[2] >> 1) & 0x01) {
687 case 0:
688 str_interleave_ = "manual";
689 break;
690 case 1:
691 str_interleave_ = "auto";
692 break;
693 default:
694 str_interleave_ = "?";
695 }
696
697 /*
698 * We can read out current detected NCO and use that value next
699 * time instead of calculating new value from targed IF.
700 * I think it will not effect receiver sensitivity but gaining lock
701 * after tune could be easier...
702 */
703 ret = hd29l2_rd_regs(priv, 0xb1, &buf[0], 3);
704 if (ret)
705 goto err;
706
707 if_ctl = (buf[0] << 16) | ((buf[1] - 7) << 8) | buf[2];
708
709 dbg("%s: %s %s %s | %s %s %s | %s %s | NCO=%06x", __func__,
710 str_constellation, str_code_rate, str_constellation_code_rate,
711 str_guard_interval, str_carrier, str_guard_interval_carrier,
712 str_interleave, str_interleave_, if_ctl);
713
714 return 0;
715err:
716 dbg("%s: failed=%d", __func__, ret);
717 return ret;
718}
719
720static int hd29l2_init(struct dvb_frontend *fe)
721{
722 int ret, i;
723 struct hd29l2_priv *priv = fe->demodulator_priv;
724 u8 tmp;
725 static const struct reg_val tab[] = {
726 { 0x3a, 0x06 },
727 { 0x3b, 0x03 },
728 { 0x3c, 0x04 },
729 { 0xaf, 0x06 },
730 { 0xb0, 0x1b },
731 { 0x80, 0x64 },
732 { 0x10, 0x38 },
733 };
734
735 dbg("%s:", __func__);
736
737 /* reset demod */
738 /* it is recommended to HW reset chip using RST_N pin */
739 if (fe->callback) {
740 ret = fe->callback(fe, 0, 0, 0);
741 if (ret)
742 goto err;
743
744 /* reprogramming needed because HW reset clears registers */
745 priv->tuner_i2c_addr_programmed = false;
746 }
747
748 /* init */
749 for (i = 0; i < ARRAY_SIZE(tab); i++) {
750 ret = hd29l2_wr_reg(priv, tab[i].reg, tab[i].val);
751 if (ret)
752 goto err;
753 }
754
755 /* TS params */
756 ret = hd29l2_rd_reg(priv, 0x36, &tmp);
757 if (ret)
758 goto err;
759
760 tmp &= 0x1b;
761 tmp |= priv->cfg.ts_mode;
762 ret = hd29l2_wr_reg(priv, 0x36, tmp);
763 if (ret)
764 goto err;
765
766 ret = hd29l2_rd_reg(priv, 0x31, &tmp);
767 tmp &= 0xef;
768
769 if (!(priv->cfg.ts_mode >> 7))
770 /* set b4 for serial TS */
771 tmp |= 0x10;
772
773 ret = hd29l2_wr_reg(priv, 0x31, tmp);
774 if (ret)
775 goto err;
776
777 return ret;
778err:
779 dbg("%s: failed=%d", __func__, ret);
780 return ret;
781}
782
783static void hd29l2_release(struct dvb_frontend *fe)
784{
785 struct hd29l2_priv *priv = fe->demodulator_priv;
786 kfree(priv);
787}
788
789static struct dvb_frontend_ops hd29l2_ops;
790
791struct dvb_frontend *hd29l2_attach(const struct hd29l2_config *config,
792 struct i2c_adapter *i2c)
793{
794 int ret;
795 struct hd29l2_priv *priv = NULL;
796 u8 tmp;
797
798 /* allocate memory for the internal state */
799 priv = kzalloc(sizeof(struct hd29l2_priv), GFP_KERNEL);
800 if (priv == NULL)
801 goto err;
802
803 /* setup the state */
804 priv->i2c = i2c;
805 memcpy(&priv->cfg, config, sizeof(struct hd29l2_config));
806
807
808 /* check if the demod is there */
809 ret = hd29l2_rd_reg(priv, 0x00, &tmp);
810 if (ret)
811 goto err;
812
813 /* create dvb_frontend */
814 memcpy(&priv->fe.ops, &hd29l2_ops, sizeof(struct dvb_frontend_ops));
815 priv->fe.demodulator_priv = priv;
816
817 return &priv->fe;
818err:
819 kfree(priv);
820 return NULL;
821}
822EXPORT_SYMBOL(hd29l2_attach);
823
824static struct dvb_frontend_ops hd29l2_ops = {
825 .info = {
826 .name = "HDIC HD29L2 DMB-TH",
827 .type = FE_OFDM,
828 .frequency_min = 474000000,
829 .frequency_max = 858000000,
830 .frequency_stepsize = 10000,
831 .caps = FE_CAN_FEC_AUTO |
832 FE_CAN_QPSK |
833 FE_CAN_QAM_16 |
834 FE_CAN_QAM_32 |
835 FE_CAN_QAM_64 |
836 FE_CAN_QAM_AUTO |
837 FE_CAN_TRANSMISSION_MODE_AUTO |
838 FE_CAN_BANDWIDTH_AUTO |
839 FE_CAN_GUARD_INTERVAL_AUTO |
840 FE_CAN_HIERARCHY_AUTO |
841 FE_CAN_RECOVER
842 },
843
844 .release = hd29l2_release,
845
846 .init = hd29l2_init,
847
848 .get_frontend_algo = hd29l2_get_frontend_algo,
849 .search = hd29l2_search,
850 .get_frontend = hd29l2_get_frontend,
851
852 .read_status = hd29l2_read_status,
853 .read_snr = hd29l2_read_snr,
854 .read_signal_strength = hd29l2_read_signal_strength,
855 .read_ber = hd29l2_read_ber,
856 .read_ucblocks = hd29l2_read_ucblocks,
857
858 .i2c_gate_ctrl = hd29l2_i2c_gate_ctrl,
859};
860
861MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
862MODULE_DESCRIPTION("HDIC HD29L2 DMB-TH demodulator driver");
863MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/hd29l2.h b/drivers/media/dvb/frontends/hd29l2.h
new file mode 100644
index 000000000000..a7a64431364d
--- /dev/null
+++ b/drivers/media/dvb/frontends/hd29l2.h
@@ -0,0 +1,66 @@
1/*
2 * HDIC HD29L2 DMB-TH demodulator driver
3 *
4 * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
5 *
6 * Author: Antti Palosaari <crope@iki.fi>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef HD29L2_H
24#define HD29L2_H
25
26#include <linux/dvb/frontend.h>
27
28struct hd29l2_config {
29 /*
30 * demodulator I2C address
31 */
32 u8 i2c_addr;
33
34 /*
35 * tuner I2C address
36 * only needed when tuner is behind demod I2C-gate
37 */
38 u8 tuner_i2c_addr;
39
40 /*
41 * TS settings
42 */
43#define HD29L2_TS_SERIAL 0x00
44#define HD29L2_TS_PARALLEL 0x80
45#define HD29L2_TS_CLK_NORMAL 0x40
46#define HD29L2_TS_CLK_INVERTED 0x00
47#define HD29L2_TS_CLK_GATED 0x20
48#define HD29L2_TS_CLK_FREE 0x00
49 u8 ts_mode;
50};
51
52
53#if defined(CONFIG_DVB_HD29L2) || \
54 (defined(CONFIG_DVB_HD29L2_MODULE) && defined(MODULE))
55extern struct dvb_frontend *hd29l2_attach(const struct hd29l2_config *config,
56 struct i2c_adapter *i2c);
57#else
58static inline struct dvb_frontend *hd29l2_attach(
59const struct hd29l2_config *config, struct i2c_adapter *i2c)
60{
61 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
62 return NULL;
63}
64#endif
65
66#endif /* HD29L2_H */
diff --git a/drivers/media/dvb/frontends/hd29l2_priv.h b/drivers/media/dvb/frontends/hd29l2_priv.h
new file mode 100644
index 000000000000..ba16dc3ec2bd
--- /dev/null
+++ b/drivers/media/dvb/frontends/hd29l2_priv.h
@@ -0,0 +1,314 @@
1/*
2 * HDIC HD29L2 DMB-TH demodulator driver
3 *
4 * Copyright (C) 2011 Metropolia University of Applied Sciences, Electria R&D
5 *
6 * Author: Antti Palosaari <crope@iki.fi>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef HD29L2_PRIV
24#define HD29L2_PRIV
25
26#include <linux/dvb/version.h>
27#include "dvb_frontend.h"
28#include "dvb_math.h"
29#include "hd29l2.h"
30
31#define LOG_PREFIX "hd29l2"
32
33#undef dbg
34#define dbg(f, arg...) \
35 if (hd29l2_debug) \
36 printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
37#undef err
38#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
39#undef info
40#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
41#undef warn
42#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
43
44#define HD29L2_XTAL 30400000 /* Hz */
45
46
47#define HD29L2_QAM4NR 0x00
48#define HD29L2_QAM4 0x01
49#define HD29L2_QAM16 0x02
50#define HD29L2_QAM32 0x03
51#define HD29L2_QAM64 0x04
52
53#define HD29L2_CODE_RATE_04 0x00
54#define HD29L2_CODE_RATE_06 0x08
55#define HD29L2_CODE_RATE_08 0x10
56
57#define HD29L2_PN945 0x00
58#define HD29L2_PN595 0x01
59#define HD29L2_PN420 0x02
60
61#define HD29L2_CARRIER_SINGLE 0x00
62#define HD29L2_CARRIER_MULTI 0x01
63
64#define HD29L2_INTERLEAVER_720 0x00
65#define HD29L2_INTERLEAVER_420 0x01
66
67struct reg_val {
68 u8 reg;
69 u8 val;
70};
71
72struct reg_mod_vals {
73 u8 reg;
74 u8 val[5];
75};
76
77struct hd29l2_priv {
78 struct i2c_adapter *i2c;
79 struct dvb_frontend fe;
80 struct hd29l2_config cfg;
81 u8 tuner_i2c_addr_programmed:1;
82
83 fe_status_t fe_status;
84};
85
86static const struct reg_mod_vals reg_mod_vals_tab[] = {
87 /* REG, QAM4NR, QAM4,QAM16,QAM32,QAM64 */
88 { 0x01, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
89 { 0x02, { 0x07, 0x07, 0x07, 0x07, 0x07 } },
90 { 0x03, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
91 { 0x04, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
92 { 0x05, { 0x61, 0x60, 0x60, 0x61, 0x60 } },
93 { 0x06, { 0xff, 0xff, 0xff, 0xff, 0xff } },
94 { 0x07, { 0xff, 0xff, 0xff, 0xff, 0xff } },
95 { 0x08, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
96 { 0x09, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
97 { 0x0a, { 0x15, 0x15, 0x03, 0x03, 0x03 } },
98 { 0x0d, { 0x78, 0x78, 0x88, 0x78, 0x78 } },
99 { 0x0e, { 0xa0, 0x90, 0xa0, 0xa0, 0xa0 } },
100 { 0x0f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
101 { 0x10, { 0xa0, 0xa0, 0x58, 0x38, 0x38 } },
102 { 0x11, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
103 { 0x12, { 0x5a, 0x5a, 0x5a, 0x5a, 0x5a } },
104 { 0x13, { 0xa2, 0xa2, 0xa2, 0xa2, 0xa2 } },
105 { 0x17, { 0x40, 0x40, 0x40, 0x40, 0x40 } },
106 { 0x18, { 0x21, 0x21, 0x42, 0x52, 0x42 } },
107 { 0x19, { 0x21, 0x21, 0x62, 0x72, 0x62 } },
108 { 0x1a, { 0x32, 0x43, 0xa9, 0xb9, 0xa9 } },
109 { 0x1b, { 0x32, 0x43, 0xb9, 0xd8, 0xb9 } },
110 { 0x1c, { 0x02, 0x02, 0x03, 0x02, 0x03 } },
111 { 0x1d, { 0x0c, 0x0c, 0x01, 0x02, 0x02 } },
112 { 0x1e, { 0x02, 0x02, 0x02, 0x01, 0x02 } },
113 { 0x1f, { 0x02, 0x02, 0x01, 0x02, 0x04 } },
114 { 0x20, { 0x01, 0x02, 0x01, 0x01, 0x01 } },
115 { 0x21, { 0x08, 0x08, 0x0a, 0x0a, 0x0a } },
116 { 0x22, { 0x06, 0x06, 0x04, 0x05, 0x05 } },
117 { 0x23, { 0x06, 0x06, 0x05, 0x03, 0x05 } },
118 { 0x24, { 0x08, 0x08, 0x05, 0x07, 0x07 } },
119 { 0x25, { 0x16, 0x10, 0x10, 0x0a, 0x10 } },
120 { 0x26, { 0x14, 0x14, 0x04, 0x04, 0x04 } },
121 { 0x27, { 0x58, 0x58, 0x58, 0x5c, 0x58 } },
122 { 0x28, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
123 { 0x29, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
124 { 0x2a, { 0x08, 0x0a, 0x08, 0x08, 0x08 } },
125 { 0x2b, { 0x08, 0x08, 0x08, 0x08, 0x08 } },
126 { 0x2c, { 0x06, 0x06, 0x06, 0x06, 0x06 } },
127 { 0x2d, { 0x05, 0x06, 0x06, 0x06, 0x06 } },
128 { 0x2e, { 0x21, 0x21, 0x21, 0x21, 0x21 } },
129 { 0x2f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
130 { 0x30, { 0x14, 0x14, 0x14, 0x14, 0x14 } },
131 { 0x33, { 0xb7, 0xb7, 0xb7, 0xb7, 0xb7 } },
132 { 0x34, { 0x81, 0x81, 0x81, 0x81, 0x81 } },
133 { 0x35, { 0x80, 0x80, 0x80, 0x80, 0x80 } },
134 { 0x37, { 0x70, 0x70, 0x70, 0x70, 0x70 } },
135 { 0x38, { 0x04, 0x04, 0x02, 0x02, 0x02 } },
136 { 0x39, { 0x07, 0x07, 0x05, 0x05, 0x05 } },
137 { 0x3a, { 0x06, 0x06, 0x06, 0x06, 0x06 } },
138 { 0x3b, { 0x03, 0x03, 0x03, 0x03, 0x03 } },
139 { 0x3c, { 0x07, 0x06, 0x04, 0x04, 0x04 } },
140 { 0x3d, { 0xf0, 0xf0, 0xf0, 0xf0, 0x80 } },
141 { 0x3e, { 0x60, 0x60, 0x60, 0x60, 0xff } },
142 { 0x3f, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
143 { 0x40, { 0x5b, 0x5b, 0x5b, 0x57, 0x50 } },
144 { 0x41, { 0x30, 0x30, 0x30, 0x30, 0x18 } },
145 { 0x42, { 0x20, 0x20, 0x20, 0x00, 0x30 } },
146 { 0x43, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
147 { 0x44, { 0x3f, 0x3f, 0x3f, 0x3f, 0x3f } },
148 { 0x45, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
149 { 0x46, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
150 { 0x47, { 0x00, 0x00, 0x95, 0x00, 0x95 } },
151 { 0x48, { 0xc0, 0xc0, 0xc0, 0xc0, 0xc0 } },
152 { 0x49, { 0xc0, 0xc0, 0xc0, 0xc0, 0xc0 } },
153 { 0x4a, { 0x40, 0x40, 0x33, 0x11, 0x11 } },
154 { 0x4b, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
155 { 0x4c, { 0x40, 0x40, 0x99, 0x11, 0x11 } },
156 { 0x4d, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
157 { 0x4e, { 0x40, 0x40, 0x66, 0x77, 0x77 } },
158 { 0x4f, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
159 { 0x50, { 0x40, 0x40, 0x88, 0x33, 0x11 } },
160 { 0x51, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
161 { 0x52, { 0x40, 0x40, 0x88, 0x02, 0x02 } },
162 { 0x53, { 0x40, 0x40, 0x00, 0x02, 0x02 } },
163 { 0x54, { 0x00, 0x00, 0x88, 0x33, 0x33 } },
164 { 0x55, { 0x40, 0x40, 0x00, 0x00, 0x00 } },
165 { 0x56, { 0x00, 0x00, 0x00, 0x0b, 0x00 } },
166 { 0x57, { 0x40, 0x40, 0x0a, 0x0b, 0x0a } },
167 { 0x58, { 0xaa, 0x00, 0x00, 0x00, 0x00 } },
168 { 0x59, { 0x7a, 0x40, 0x02, 0x02, 0x02 } },
169 { 0x5a, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
170 { 0x5b, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
171 { 0x5c, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
172 { 0x5d, { 0x18, 0x18, 0x01, 0x01, 0x01 } },
173 { 0x5e, { 0xc0, 0xc0, 0xc0, 0xff, 0xc0 } },
174 { 0x5f, { 0xc0, 0xc0, 0xc0, 0xff, 0xc0 } },
175 { 0x60, { 0x40, 0x40, 0x00, 0x30, 0x30 } },
176 { 0x61, { 0x40, 0x40, 0x10, 0x30, 0x30 } },
177 { 0x62, { 0x40, 0x40, 0x00, 0x30, 0x30 } },
178 { 0x63, { 0x40, 0x40, 0x05, 0x30, 0x30 } },
179 { 0x64, { 0x40, 0x40, 0x06, 0x00, 0x30 } },
180 { 0x65, { 0x40, 0x40, 0x06, 0x08, 0x30 } },
181 { 0x66, { 0x40, 0x40, 0x00, 0x00, 0x20 } },
182 { 0x67, { 0x40, 0x40, 0x01, 0x04, 0x20 } },
183 { 0x68, { 0x00, 0x00, 0x30, 0x00, 0x20 } },
184 { 0x69, { 0xa0, 0xa0, 0x00, 0x08, 0x20 } },
185 { 0x6a, { 0x00, 0x00, 0x30, 0x00, 0x25 } },
186 { 0x6b, { 0xa0, 0xa0, 0x00, 0x06, 0x25 } },
187 { 0x6c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
188 { 0x6d, { 0xa0, 0x60, 0x0c, 0x03, 0x0c } },
189 { 0x6e, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
190 { 0x6f, { 0xa0, 0x60, 0x04, 0x01, 0x04 } },
191 { 0x70, { 0x58, 0x58, 0xaa, 0xaa, 0xaa } },
192 { 0x71, { 0x58, 0x58, 0xaa, 0xaa, 0xaa } },
193 { 0x72, { 0x58, 0x58, 0xff, 0xff, 0xff } },
194 { 0x73, { 0x58, 0x58, 0xff, 0xff, 0xff } },
195 { 0x74, { 0x06, 0x06, 0x09, 0x05, 0x05 } },
196 { 0x75, { 0x06, 0x06, 0x0a, 0x10, 0x10 } },
197 { 0x76, { 0x10, 0x10, 0x06, 0x0a, 0x0a } },
198 { 0x77, { 0x12, 0x18, 0x28, 0x10, 0x28 } },
199 { 0x78, { 0xf8, 0xf8, 0xf8, 0xf8, 0xf8 } },
200 { 0x79, { 0x15, 0x15, 0x03, 0x03, 0x03 } },
201 { 0x7a, { 0x02, 0x02, 0x01, 0x04, 0x03 } },
202 { 0x7b, { 0x01, 0x02, 0x03, 0x03, 0x03 } },
203 { 0x7c, { 0x28, 0x28, 0x28, 0x28, 0x28 } },
204 { 0x7f, { 0x25, 0x92, 0x5f, 0x17, 0x2d } },
205 { 0x80, { 0x64, 0x64, 0x64, 0x74, 0x64 } },
206 { 0x83, { 0x06, 0x03, 0x04, 0x04, 0x04 } },
207 { 0x84, { 0xff, 0xff, 0xff, 0xff, 0xff } },
208 { 0x85, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
209 { 0x86, { 0x00, 0x00, 0x11, 0x11, 0x11 } },
210 { 0x87, { 0x03, 0x03, 0x03, 0x03, 0x03 } },
211 { 0x88, { 0x09, 0x09, 0x09, 0x09, 0x09 } },
212 { 0x89, { 0x20, 0x20, 0x30, 0x20, 0x20 } },
213 { 0x8a, { 0x03, 0x03, 0x02, 0x03, 0x02 } },
214 { 0x8b, { 0x00, 0x07, 0x09, 0x00, 0x09 } },
215 { 0x8c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
216 { 0x8d, { 0x4f, 0x4f, 0x4f, 0x3f, 0x4f } },
217 { 0x8e, { 0xf0, 0xf0, 0x60, 0xf0, 0xa0 } },
218 { 0x8f, { 0xe8, 0xe8, 0xe8, 0xe8, 0xe8 } },
219 { 0x90, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
220 { 0x91, { 0x40, 0x40, 0x70, 0x70, 0x10 } },
221 { 0x92, { 0x00, 0x00, 0x00, 0x00, 0x04 } },
222 { 0x93, { 0x60, 0x60, 0x60, 0x60, 0x60 } },
223 { 0x94, { 0x00, 0x00, 0x00, 0x00, 0x03 } },
224 { 0x95, { 0x09, 0x09, 0x47, 0x47, 0x47 } },
225 { 0x96, { 0x80, 0xa0, 0xa0, 0x40, 0xa0 } },
226 { 0x97, { 0x60, 0x60, 0x60, 0x60, 0x60 } },
227 { 0x98, { 0x50, 0x50, 0x50, 0x30, 0x50 } },
228 { 0x99, { 0x10, 0x10, 0x10, 0x10, 0x10 } },
229 { 0x9a, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
230 { 0x9b, { 0x40, 0x40, 0x40, 0x30, 0x40 } },
231 { 0x9c, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
232 { 0xa0, { 0xf0, 0xf0, 0xf0, 0xf0, 0xf0 } },
233 { 0xa1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
234 { 0xa2, { 0x30, 0x30, 0x00, 0x30, 0x00 } },
235 { 0xa3, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
236 { 0xa4, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
237 { 0xa5, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
238 { 0xa6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
239 { 0xa7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
240 { 0xa8, { 0x77, 0x77, 0x77, 0x77, 0x77 } },
241 { 0xa9, { 0x02, 0x02, 0x02, 0x02, 0x02 } },
242 { 0xaa, { 0x40, 0x40, 0x40, 0x40, 0x40 } },
243 { 0xac, { 0x1f, 0x1f, 0x1f, 0x1f, 0x1f } },
244 { 0xad, { 0x14, 0x14, 0x14, 0x14, 0x14 } },
245 { 0xae, { 0x78, 0x78, 0x78, 0x78, 0x78 } },
246 { 0xaf, { 0x06, 0x06, 0x06, 0x06, 0x07 } },
247 { 0xb0, { 0x1b, 0x1b, 0x1b, 0x19, 0x1b } },
248 { 0xb1, { 0x18, 0x17, 0x17, 0x18, 0x17 } },
249 { 0xb2, { 0x35, 0x82, 0x82, 0x38, 0x82 } },
250 { 0xb3, { 0xb6, 0xce, 0xc7, 0x5c, 0xb0 } },
251 { 0xb4, { 0x3f, 0x3e, 0x3e, 0x3f, 0x3e } },
252 { 0xb5, { 0x70, 0x58, 0x50, 0x68, 0x50 } },
253 { 0xb6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
254 { 0xb7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
255 { 0xb8, { 0x03, 0x03, 0x01, 0x01, 0x01 } },
256 { 0xb9, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
257 { 0xba, { 0x06, 0x06, 0x0a, 0x05, 0x0a } },
258 { 0xbb, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
259 { 0xbc, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
260 { 0xbd, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
261 { 0xbe, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
262 { 0xbf, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
263 { 0xc0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
264 { 0xc1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
265 { 0xc2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
266 { 0xc3, { 0x00, 0x00, 0x88, 0x66, 0x88 } },
267 { 0xc4, { 0x10, 0x10, 0x00, 0x00, 0x00 } },
268 { 0xc5, { 0x00, 0x00, 0x44, 0x60, 0x44 } },
269 { 0xc6, { 0x10, 0x0a, 0x00, 0x00, 0x00 } },
270 { 0xc7, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
271 { 0xc8, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
272 { 0xc9, { 0x90, 0x04, 0x00, 0x00, 0x00 } },
273 { 0xca, { 0x90, 0x08, 0x01, 0x01, 0x01 } },
274 { 0xcb, { 0xa0, 0x04, 0x00, 0x44, 0x00 } },
275 { 0xcc, { 0xa0, 0x10, 0x03, 0x00, 0x03 } },
276 { 0xcd, { 0x06, 0x06, 0x06, 0x05, 0x06 } },
277 { 0xce, { 0x05, 0x05, 0x01, 0x01, 0x01 } },
278 { 0xcf, { 0x40, 0x20, 0x18, 0x18, 0x18 } },
279 { 0xd0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
280 { 0xd1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
281 { 0xd2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
282 { 0xd3, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
283 { 0xd4, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
284 { 0xd5, { 0x05, 0x05, 0x05, 0x03, 0x05 } },
285 { 0xd6, { 0xac, 0x22, 0xca, 0x8f, 0xca } },
286 { 0xd7, { 0x20, 0x20, 0x20, 0x20, 0x20 } },
287 { 0xd8, { 0x01, 0x01, 0x01, 0x01, 0x01 } },
288 { 0xd9, { 0x00, 0x00, 0x0f, 0x00, 0x0f } },
289 { 0xda, { 0x00, 0xff, 0xff, 0x0e, 0xff } },
290 { 0xdb, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
291 { 0xdc, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
292 { 0xdd, { 0x05, 0x05, 0x05, 0x05, 0x05 } },
293 { 0xde, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
294 { 0xdf, { 0x42, 0x42, 0x44, 0x44, 0x04 } },
295 { 0xe0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
296 { 0xe1, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
297 { 0xe2, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
298 { 0xe3, { 0x00, 0x00, 0x26, 0x06, 0x26 } },
299 { 0xe4, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
300 { 0xe5, { 0x01, 0x0a, 0x01, 0x01, 0x01 } },
301 { 0xe6, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
302 { 0xe7, { 0x08, 0x08, 0x08, 0x08, 0x08 } },
303 { 0xe8, { 0x63, 0x63, 0x63, 0x63, 0x63 } },
304 { 0xe9, { 0x59, 0x59, 0x59, 0x59, 0x59 } },
305 { 0xea, { 0x80, 0x80, 0x20, 0x80, 0x80 } },
306 { 0xeb, { 0x37, 0x37, 0x78, 0x37, 0x77 } },
307 { 0xec, { 0x1f, 0x1f, 0x25, 0x25, 0x25 } },
308 { 0xed, { 0x0a, 0x0a, 0x0a, 0x0a, 0x0a } },
309 { 0xee, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
310 { 0xef, { 0x70, 0x70, 0x58, 0x38, 0x58 } },
311 { 0xf0, { 0x00, 0x00, 0x00, 0x00, 0x00 } },
312};
313
314#endif /* HD29L2_PRIV */