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authorJiri Slaby <jirislaby@gmail.com>2007-02-10 04:45:18 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-11 13:51:29 -0500
commited79ba12e981538a399012f226360db635b50570 (patch)
tree66abf8865411033c0abf4a2fba01d26bb100c5bf /drivers
parentf574874bc861414bbae220b1fe623cbdd098243b (diff)
[PATCH] Char: mxser_new, header file cleanup
- Remove no longer used macros - Move some macros from the header to the code - Remove c++ comments - Align backslashes to one column Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/char/mxser_new.c7
-rw-r--r--drivers/char/mxser_new.h461
2 files changed, 154 insertions, 314 deletions
diff --git a/drivers/char/mxser_new.c b/drivers/char/mxser_new.c
index ec61cf81b7e6..945c7e1b4c34 100644
--- a/drivers/char/mxser_new.c
+++ b/drivers/char/mxser_new.c
@@ -53,8 +53,6 @@
53#define MXSERMAJOR 174 53#define MXSERMAJOR 174
54#define MXSERCUMAJOR 175 54#define MXSERCUMAJOR 175
55 55
56#define MXSER_EVENT_TXLOW 1
57
58#define MXSER_BOARDS 4 /* Max. boards */ 56#define MXSER_BOARDS 4 /* Max. boards */
59#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ 57#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
60#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) 58#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
@@ -65,6 +63,11 @@
65#define MXSER_ERR_IRQ_CONFLIT -3 63#define MXSER_ERR_IRQ_CONFLIT -3
66#define MXSER_ERR_VECTOR -4 64#define MXSER_ERR_VECTOR -4
67 65
66/*CheckIsMoxaMust return value*/
67#define MOXA_OTHER_UART 0x00
68#define MOXA_MUST_MU150_HWID 0x01
69#define MOXA_MUST_MU860_HWID 0x02
70
68#define WAKEUP_CHARS 256 71#define WAKEUP_CHARS 256
69 72
70#define UART_MCR_AFE 0x20 73#define UART_MCR_AFE 0x20
diff --git a/drivers/char/mxser_new.h b/drivers/char/mxser_new.h
index 55b34a0e8cf6..04fa5fc9226d 100644
--- a/drivers/char/mxser_new.h
+++ b/drivers/char/mxser_new.h
@@ -26,18 +26,8 @@
26#define RS422_MODE 2 26#define RS422_MODE 2
27#define RS485_4WIRE_MODE 3 27#define RS485_4WIRE_MODE 3
28#define OP_MODE_MASK 3 28#define OP_MODE_MASK 3
29// above add by Victor Yu. 01-05-2004
30
31#define TTY_THRESHOLD_THROTTLE 128
32
33#define LO_WATER (TTY_FLIPBUF_SIZE)
34#define HI_WATER (TTY_FLIPBUF_SIZE*2*3/4)
35
36// added by James. 03-11-2004.
37#define MOXA_SDS_GETICOUNTER (MOXA + 68)
38#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
39// (above) added by James.
40 29
30#define MOXA_SDS_RSTICOUNTER (MOXA + 69)
41#define MOXA_ASPP_OQUEUE (MOXA + 70) 31#define MOXA_ASPP_OQUEUE (MOXA + 70)
42#define MOXA_ASPP_SETBAUD (MOXA + 71) 32#define MOXA_ASPP_SETBAUD (MOXA + 71)
43#define MOXA_ASPP_GETBAUD (MOXA + 72) 33#define MOXA_ASPP_GETBAUD (MOXA + 72)
@@ -46,7 +36,6 @@
46#define MOXA_ASPP_MON_EXT (MOXA + 75) 36#define MOXA_ASPP_MON_EXT (MOXA + 75)
47#define MOXA_SET_BAUD_METHOD (MOXA + 76) 37#define MOXA_SET_BAUD_METHOD (MOXA + 76)
48 38
49
50/* --------------------------------------------------- */ 39/* --------------------------------------------------- */
51 40
52#define NPPI_NOTIFY_PARITY 0x01 41#define NPPI_NOTIFY_PARITY 0x01
@@ -55,51 +44,46 @@
55#define NPPI_NOTIFY_SW_OVERRUN 0x08 44#define NPPI_NOTIFY_SW_OVERRUN 0x08
56#define NPPI_NOTIFY_BREAK 0x10 45#define NPPI_NOTIFY_BREAK 0x10
57 46
58#define NPPI_NOTIFY_CTSHOLD 0x01 // Tx hold by CTS low 47#define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
59#define NPPI_NOTIFY_DSRHOLD 0x02 // Tx hold by DSR low 48#define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
60#define NPPI_NOTIFY_XOFFHOLD 0x08 // Tx hold by Xoff received 49#define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
61#define NPPI_NOTIFY_XOFFXENT 0x10 // Xoff Sent 50#define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
62 51
63//CheckIsMoxaMust return value 52/* follow just for Moxa Must chip define. */
64#define MOXA_OTHER_UART 0x00 53/* */
65#define MOXA_MUST_MU150_HWID 0x01 54/* when LCR register (offset 0x03) write following value, */
66#define MOXA_MUST_MU860_HWID 0x02 55/* the Must chip will enter enchance mode. And write value */
67 56/* on EFR (offset 0x02) bit 6,7 to change bank. */
68// follow just for Moxa Must chip define.
69//
70// when LCR register (offset 0x03) write following value,
71// the Must chip will enter enchance mode. And write value
72// on EFR (offset 0x02) bit 6,7 to change bank.
73#define MOXA_MUST_ENTER_ENCHANCE 0xBF 57#define MOXA_MUST_ENTER_ENCHANCE 0xBF
74 58
75// when enhance mode enable, access on general bank register 59/* when enhance mode enable, access on general bank register */
76#define MOXA_MUST_GDL_REGISTER 0x07 60#define MOXA_MUST_GDL_REGISTER 0x07
77#define MOXA_MUST_GDL_MASK 0x7F 61#define MOXA_MUST_GDL_MASK 0x7F
78#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 62#define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
79 63
80#define MOXA_MUST_LSR_RERR 0x80 // error in receive FIFO 64#define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
81// enchance register bank select and enchance mode setting register 65/* enchance register bank select and enchance mode setting register */
82// when LCR register equal to 0xBF 66/* when LCR register equal to 0xBF */
83#define MOXA_MUST_EFR_REGISTER 0x02 67#define MOXA_MUST_EFR_REGISTER 0x02
84// enchance mode enable 68/* enchance mode enable */
85#define MOXA_MUST_EFR_EFRB_ENABLE 0x10 69#define MOXA_MUST_EFR_EFRB_ENABLE 0x10
86// enchance reister bank set 0, 1, 2 70/* enchance reister bank set 0, 1, 2 */
87#define MOXA_MUST_EFR_BANK0 0x00 71#define MOXA_MUST_EFR_BANK0 0x00
88#define MOXA_MUST_EFR_BANK1 0x40 72#define MOXA_MUST_EFR_BANK1 0x40
89#define MOXA_MUST_EFR_BANK2 0x80 73#define MOXA_MUST_EFR_BANK2 0x80
90#define MOXA_MUST_EFR_BANK3 0xC0 74#define MOXA_MUST_EFR_BANK3 0xC0
91#define MOXA_MUST_EFR_BANK_MASK 0xC0 75#define MOXA_MUST_EFR_BANK_MASK 0xC0
92 76
93// set XON1 value register, when LCR=0xBF and change to bank0 77/* set XON1 value register, when LCR=0xBF and change to bank0 */
94#define MOXA_MUST_XON1_REGISTER 0x04 78#define MOXA_MUST_XON1_REGISTER 0x04
95 79
96// set XON2 value register, when LCR=0xBF and change to bank0 80/* set XON2 value register, when LCR=0xBF and change to bank0 */
97#define MOXA_MUST_XON2_REGISTER 0x05 81#define MOXA_MUST_XON2_REGISTER 0x05
98 82
99// set XOFF1 value register, when LCR=0xBF and change to bank0 83/* set XOFF1 value register, when LCR=0xBF and change to bank0 */
100#define MOXA_MUST_XOFF1_REGISTER 0x06 84#define MOXA_MUST_XOFF1_REGISTER 0x06
101 85
102// set XOFF2 value register, when LCR=0xBF and change to bank0 86/* set XOFF2 value register, when LCR=0xBF and change to bank0 */
103#define MOXA_MUST_XOFF2_REGISTER 0x07 87#define MOXA_MUST_XOFF2_REGISTER 0x07
104 88
105#define MOXA_MUST_RBRTL_REGISTER 0x04 89#define MOXA_MUST_RBRTL_REGISTER 0x04
@@ -111,32 +95,32 @@
111#define MOXA_MUST_ECR_REGISTER 0x06 95#define MOXA_MUST_ECR_REGISTER 0x06
112#define MOXA_MUST_CSR_REGISTER 0x07 96#define MOXA_MUST_CSR_REGISTER 0x07
113 97
114// good data mode enable 98/* good data mode enable */
115#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 99#define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
116// only good data put into RxFIFO 100/* only good data put into RxFIFO */
117#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 101#define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
118 102
119// enable CTS interrupt 103/* enable CTS interrupt */
120#define MOXA_MUST_IER_ECTSI 0x80 104#define MOXA_MUST_IER_ECTSI 0x80
121// enable RTS interrupt 105/* enable RTS interrupt */
122#define MOXA_MUST_IER_ERTSI 0x40 106#define MOXA_MUST_IER_ERTSI 0x40
123// enable Xon/Xoff interrupt 107/* enable Xon/Xoff interrupt */
124#define MOXA_MUST_IER_XINT 0x20 108#define MOXA_MUST_IER_XINT 0x20
125// enable GDA interrupt 109/* enable GDA interrupt */
126#define MOXA_MUST_IER_EGDAI 0x10 110#define MOXA_MUST_IER_EGDAI 0x10
127 111
128#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 112#define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
129 113
130// GDA interrupt pending 114/* GDA interrupt pending */
131#define MOXA_MUST_IIR_GDA 0x1C 115#define MOXA_MUST_IIR_GDA 0x1C
132#define MOXA_MUST_IIR_RDA 0x04 116#define MOXA_MUST_IIR_RDA 0x04
133#define MOXA_MUST_IIR_RTO 0x0C 117#define MOXA_MUST_IIR_RTO 0x0C
134#define MOXA_MUST_IIR_LSR 0x06 118#define MOXA_MUST_IIR_LSR 0x06
135 119
136// recieved Xon/Xoff or specical interrupt pending 120/* recieved Xon/Xoff or specical interrupt pending */
137#define MOXA_MUST_IIR_XSC 0x10 121#define MOXA_MUST_IIR_XSC 0x10
138 122
139// RTS/CTS change state interrupt pending 123/* RTS/CTS change state interrupt pending */
140#define MOXA_MUST_IIR_RTSCTS 0x20 124#define MOXA_MUST_IIR_RTSCTS 0x20
141#define MOXA_MUST_IIR_MASK 0x3E 125#define MOXA_MUST_IIR_MASK 0x3E
142 126
@@ -144,299 +128,152 @@
144#define MOXA_MUST_MCR_XON_ANY 0x80 128#define MOXA_MUST_MCR_XON_ANY 0x80
145#define MOXA_MUST_MCR_TX_XON 0x08 129#define MOXA_MUST_MCR_TX_XON 0x08
146 130
147 131/* software flow control on chip mask value */
148// software flow control on chip mask value
149#define MOXA_MUST_EFR_SF_MASK 0x0F 132#define MOXA_MUST_EFR_SF_MASK 0x0F
150// send Xon1/Xoff1 133/* send Xon1/Xoff1 */
151#define MOXA_MUST_EFR_SF_TX1 0x08 134#define MOXA_MUST_EFR_SF_TX1 0x08
152// send Xon2/Xoff2 135/* send Xon2/Xoff2 */
153#define MOXA_MUST_EFR_SF_TX2 0x04 136#define MOXA_MUST_EFR_SF_TX2 0x04
154// send Xon1,Xon2/Xoff1,Xoff2 137/* send Xon1,Xon2/Xoff1,Xoff2 */
155#define MOXA_MUST_EFR_SF_TX12 0x0C 138#define MOXA_MUST_EFR_SF_TX12 0x0C
156// don't send Xon/Xoff 139/* don't send Xon/Xoff */
157#define MOXA_MUST_EFR_SF_TX_NO 0x00 140#define MOXA_MUST_EFR_SF_TX_NO 0x00
158// Tx software flow control mask 141/* Tx software flow control mask */
159#define MOXA_MUST_EFR_SF_TX_MASK 0x0C 142#define MOXA_MUST_EFR_SF_TX_MASK 0x0C
160// don't receive Xon/Xoff 143/* don't receive Xon/Xoff */
161#define MOXA_MUST_EFR_SF_RX_NO 0x00 144#define MOXA_MUST_EFR_SF_RX_NO 0x00
162// receive Xon1/Xoff1 145/* receive Xon1/Xoff1 */
163#define MOXA_MUST_EFR_SF_RX1 0x02 146#define MOXA_MUST_EFR_SF_RX1 0x02
164// receive Xon2/Xoff2 147/* receive Xon2/Xoff2 */
165#define MOXA_MUST_EFR_SF_RX2 0x01 148#define MOXA_MUST_EFR_SF_RX2 0x01
166// receive Xon1,Xon2/Xoff1,Xoff2 149/* receive Xon1,Xon2/Xoff1,Xoff2 */
167#define MOXA_MUST_EFR_SF_RX12 0x03 150#define MOXA_MUST_EFR_SF_RX12 0x03
168// Rx software flow control mask 151/* Rx software flow control mask */
169#define MOXA_MUST_EFR_SF_RX_MASK 0x03 152#define MOXA_MUST_EFR_SF_RX_MASK 0x03
170 153
171//#define MOXA_MUST_MIN_XOFFLIMIT 66 154#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
172//#define MOXA_MUST_MIN_XONLIMIT 20 155 u8 __oldlcr, __efr; \
173//#define ID1_RX_TRIG 120 156 __oldlcr = inb((baseio)+UART_LCR); \
174
175
176#define CHECK_MOXA_MUST_XOFFLIMIT(info) { \
177 if ( (info)->IsMoxaMustChipFlag && \
178 (info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) { \
179 (info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT; \
180 (info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT; \
181 } \
182}
183
184#define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \
185 u8 __oldlcr, __efr; \
186 __oldlcr = inb((baseio)+UART_LCR); \
187 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 157 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
188 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 158 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
189 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \ 159 __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
190 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 160 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
191 outb(__oldlcr, (baseio)+UART_LCR); \ 161 outb(__oldlcr, (baseio)+UART_LCR); \
192} 162} while (0)
193 163
194#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \ 164#define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
195 u8 __oldlcr, __efr; \ 165 u8 __oldlcr, __efr; \
196 __oldlcr = inb((baseio)+UART_LCR); \ 166 __oldlcr = inb((baseio)+UART_LCR); \
197 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 167 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
198 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 168 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
199 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \ 169 __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
200 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 170 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
201 outb(__oldlcr, (baseio)+UART_LCR); \ 171 outb(__oldlcr, (baseio)+UART_LCR); \
202} 172} while (0)
203 173
204#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) { \ 174#define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
205 u8 __oldlcr, __efr; \ 175 u8 __oldlcr, __efr; \
206 __oldlcr = inb((baseio)+UART_LCR); \ 176 __oldlcr = inb((baseio)+UART_LCR); \
207 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 177 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
208 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 178 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
209 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 179 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
210 __efr |= MOXA_MUST_EFR_BANK0; \ 180 __efr |= MOXA_MUST_EFR_BANK0; \
211 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 181 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
212 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \ 182 outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
213 outb(__oldlcr, (baseio)+UART_LCR); \ 183 outb(__oldlcr, (baseio)+UART_LCR); \
214} 184} while (0)
215 185
216#define SET_MOXA_MUST_XON2_VALUE(baseio, Value) { \ 186#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
217 u8 __oldlcr, __efr; \ 187 u8 __oldlcr, __efr; \
218 __oldlcr = inb((baseio)+UART_LCR); \ 188 __oldlcr = inb((baseio)+UART_LCR); \
219 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 189 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
220 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 190 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
221 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 191 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
222 __efr |= MOXA_MUST_EFR_BANK0; \ 192 __efr |= MOXA_MUST_EFR_BANK0; \
223 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 193 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
224 outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER); \
225 outb(__oldlcr, (baseio)+UART_LCR); \
226}
227
228#define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) { \
229 u8 __oldlcr, __efr; \
230 __oldlcr = inb((baseio)+UART_LCR); \
231 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
232 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
233 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
234 __efr |= MOXA_MUST_EFR_BANK0; \
235 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
236 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \ 194 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
237 outb(__oldlcr, (baseio)+UART_LCR); \ 195 outb(__oldlcr, (baseio)+UART_LCR); \
238} 196} while (0)
239 197
240#define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) { \ 198#define SET_MOXA_MUST_FIFO_VALUE(info) do { \
241 u8 __oldlcr, __efr; \ 199 u8 __oldlcr, __efr; \
242 __oldlcr = inb((baseio)+UART_LCR); \ 200 __oldlcr = inb((info)->ioaddr+UART_LCR); \
243 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 201 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
244 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
245 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
246 __efr |= MOXA_MUST_EFR_BANK0; \
247 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
248 outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER); \
249 outb(__oldlcr, (baseio)+UART_LCR); \
250}
251
252#define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) { \
253 u8 __oldlcr, __efr; \
254 __oldlcr = inb((baseio)+UART_LCR); \
255 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
256 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
257 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
258 __efr |= MOXA_MUST_EFR_BANK1; \
259 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
260 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER); \
261 outb(__oldlcr, (baseio)+UART_LCR); \
262}
263
264#define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) { \
265 u8 __oldlcr, __efr; \
266 __oldlcr = inb((baseio)+UART_LCR); \
267 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
268 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
269 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
270 __efr |= MOXA_MUST_EFR_BANK1; \
271 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
272 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER); \
273 outb(__oldlcr, (baseio)+UART_LCR); \
274}
275
276#define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) { \
277 u8 __oldlcr, __efr; \
278 __oldlcr = inb((baseio)+UART_LCR); \
279 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
280 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
281 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
282 __efr |= MOXA_MUST_EFR_BANK1; \
283 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
284 outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER); \
285 outb(__oldlcr, (baseio)+UART_LCR); \
286}
287
288#define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) { \
289 u8 __oldlcr, __efr; \
290 __oldlcr = inb((baseio)+UART_LCR); \
291 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
292 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
293 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
294 __efr |= MOXA_MUST_EFR_BANK1; \
295 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
296 outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER); \
297 outb(__oldlcr, (baseio)+UART_LCR); \
298}
299
300//#define MOXA_MUST_RBRL_VALUE 4
301#define SET_MOXA_MUST_FIFO_VALUE(info) { \
302 u8 __oldlcr, __efr; \
303 __oldlcr = inb((info)->ioaddr+UART_LCR); \
304 outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR); \
305 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \ 202 __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
306 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ 203 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
307 __efr |= MOXA_MUST_EFR_BANK1; \ 204 __efr |= MOXA_MUST_EFR_BANK1; \
308 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \ 205 outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
309 outb((u8)((info)->rx_high_water), (info)->ioaddr+MOXA_MUST_RBRTH_REGISTER); \ 206 outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
310 outb((u8)((info)->rx_trigger), (info)->ioaddr+MOXA_MUST_RBRTI_REGISTER); \ 207 MOXA_MUST_RBRTH_REGISTER); \
311 outb((u8)((info)->rx_low_water), (info)->ioaddr+MOXA_MUST_RBRTL_REGISTER); \ 208 outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
312 outb(__oldlcr, (info)->ioaddr+UART_LCR); \ 209 MOXA_MUST_RBRTI_REGISTER); \
313} 210 outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
314 211 MOXA_MUST_RBRTL_REGISTER); \
315 212 outb(__oldlcr, (info)->ioaddr+UART_LCR); \
316 213} while (0)
317#define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) { \ 214
318 u8 __oldlcr, __efr; \ 215#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
319 __oldlcr = inb((baseio)+UART_LCR); \ 216 u8 __oldlcr, __efr; \
320 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 217 __oldlcr = inb((baseio)+UART_LCR); \
321 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
322 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
323 __efr |= MOXA_MUST_EFR_BANK2; \
324 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
325 outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
326 outb(__oldlcr, (baseio)+UART_LCR); \
327}
328
329#define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) { \
330 u8 __oldlcr, __efr; \
331 __oldlcr = inb((baseio)+UART_LCR); \
332 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
333 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
334 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
335 __efr |= MOXA_MUST_EFR_BANK2; \
336 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
337 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
338 outb(__oldlcr, (baseio)+UART_LCR); \
339}
340
341#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) { \
342 u8 __oldlcr, __efr; \
343 __oldlcr = inb((baseio)+UART_LCR); \
344 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
345 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
346 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
347 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
348 outb(__oldlcr, (baseio)+UART_LCR); \
349}
350
351#define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
352 u8 __oldlcr, __efr; \
353 __oldlcr = inb((baseio)+UART_LCR); \
354 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
355 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
356 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
357 __efr |= MOXA_MUST_EFR_SF_TX1; \
358 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
359 outb(__oldlcr, (baseio)+UART_LCR); \
360}
361
362#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \
363 u8 __oldlcr, __efr; \
364 __oldlcr = inb((baseio)+UART_LCR); \
365 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 218 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
366 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 219 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
367 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ 220 __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
368 __efr |= MOXA_MUST_EFR_SF_TX1; \ 221 __efr |= MOXA_MUST_EFR_BANK2; \
369 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 222 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
370 outb(__oldlcr, (baseio)+UART_LCR); \ 223 *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
371} 224 outb(__oldlcr, (baseio)+UART_LCR); \
372 225} while (0)
373#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ 226
374 u8 __oldlcr, __efr; \ 227#define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
375 __oldlcr = inb((baseio)+UART_LCR); \ 228 u8 __oldlcr, __efr; \
229 __oldlcr = inb((baseio)+UART_LCR); \
376 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 230 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
377 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 231 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
378 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ 232 __efr &= ~MOXA_MUST_EFR_SF_MASK; \
379 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 233 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
380 outb(__oldlcr, (baseio)+UART_LCR); \ 234 outb(__oldlcr, (baseio)+UART_LCR); \
381} 235} while (0)
382 236
383#define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 237#define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
384 u8 __oldlcr, __efr; \ 238 u8 __oldlcr, __efr; \
385 __oldlcr = inb((baseio)+UART_LCR); \ 239 __oldlcr = inb((baseio)+UART_LCR); \
386 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 240 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
387 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 241 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
388 __efr &= ~MOXA_MUST_EFR_SF_MASK; \ 242 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
389 __efr |= MOXA_MUST_EFR_SF_RX1; \ 243 __efr |= MOXA_MUST_EFR_SF_TX1; \
390 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 244 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
391 outb(__oldlcr, (baseio)+UART_LCR); \ 245 outb(__oldlcr, (baseio)+UART_LCR); \
392} 246} while (0)
393 247
394#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 248#define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
395 u8 __oldlcr, __efr; \ 249 u8 __oldlcr, __efr; \
396 __oldlcr = inb((baseio)+UART_LCR); \ 250 __oldlcr = inb((baseio)+UART_LCR); \
397 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 251 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
398 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 252 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
399 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ 253 __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
400 __efr |= MOXA_MUST_EFR_SF_RX1; \ 254 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
401 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 255 outb(__oldlcr, (baseio)+UART_LCR); \
402 outb(__oldlcr, (baseio)+UART_LCR); \ 256} while (0)
403} 257
404 258#define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
405#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 259 u8 __oldlcr, __efr; \
406 u8 __oldlcr, __efr; \ 260 __oldlcr = inb((baseio)+UART_LCR); \
407 __oldlcr = inb((baseio)+UART_LCR); \
408 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 261 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
409 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 262 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
410 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ 263 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
411 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 264 __efr |= MOXA_MUST_EFR_SF_RX1; \
412 outb(__oldlcr, (baseio)+UART_LCR); \ 265 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
413} 266 outb(__oldlcr, (baseio)+UART_LCR); \
414 267} while (0)
415#define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ 268
416 u8 __oldlcr, __efr; \ 269#define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
417 __oldlcr = inb((baseio)+UART_LCR); \ 270 u8 __oldlcr, __efr; \
271 __oldlcr = inb((baseio)+UART_LCR); \
418 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ 272 outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
419 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ 273 __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
420 __efr &= ~MOXA_MUST_EFR_SF_MASK; \ 274 __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
421 __efr |= (MOXA_MUST_EFR_SF_RX1|MOXA_MUST_EFR_SF_TX1); \ 275 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
422 outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ 276 outb(__oldlcr, (baseio)+UART_LCR); \
423 outb(__oldlcr, (baseio)+UART_LCR); \ 277} while (0)
424}
425
426#define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
427 u8 __oldmcr; \
428 __oldmcr = inb((baseio)+UART_MCR); \
429 __oldmcr |= MOXA_MUST_MCR_XON_ANY; \
430 outb(__oldmcr, (baseio)+UART_MCR); \
431}
432
433#define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \
434 u8 __oldmcr; \
435 __oldmcr = inb((baseio)+UART_MCR); \
436 __oldmcr &= ~MOXA_MUST_MCR_XON_ANY; \
437 outb(__oldmcr, (baseio)+UART_MCR); \
438}
439
440#define READ_MOXA_MUST_GDL(baseio) inb((baseio)+MOXA_MUST_GDL_REGISTER)
441 278
442#endif 279#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 12:36:37 -0500