diff options
author | Omar Ramirez Luna <omar.ramirez@ti.com> | 2011-11-18 17:18:54 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-12-13 19:12:06 -0500 |
commit | ed625b9143ee53fe610320908c89e22635ee6e87 (patch) | |
tree | af583ca87a18c133d2e5bdf52e22f06b270b6bd2 /drivers | |
parent | 0a7e22e61e07a2ea479511f9620858be2f1507e8 (diff) |
staging: tidspbridge: request dmtimer clocks on init
Given that dm timer framework doesn't support request of clocks
by soft | hard irqs because some recent changes, tidspbridge needs
to request its clocks on init and enable/disable them on demand.
This was first seen on 3.2-rc1.
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/staging/tidspbridge/core/dsp-clock.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/staging/tidspbridge/core/dsp-clock.c b/drivers/staging/tidspbridge/core/dsp-clock.c index 3d1279c424a8..7eb56178fb64 100644 --- a/drivers/staging/tidspbridge/core/dsp-clock.c +++ b/drivers/staging/tidspbridge/core/dsp-clock.c | |||
@@ -54,6 +54,7 @@ | |||
54 | 54 | ||
55 | /* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */ | 55 | /* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */ |
56 | #define DMT_ID(id) ((id) + 4) | 56 | #define DMT_ID(id) ((id) + 4) |
57 | #define DM_TIMER_CLOCKS 4 | ||
57 | 58 | ||
58 | /* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (0 - 4) */ | 59 | /* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (0 - 4) */ |
59 | #define MCBSP_ID(id) ((id) - 6) | 60 | #define MCBSP_ID(id) ((id) - 6) |
@@ -114,8 +115,13 @@ static s8 get_clk_type(u8 id) | |||
114 | */ | 115 | */ |
115 | void dsp_clk_exit(void) | 116 | void dsp_clk_exit(void) |
116 | { | 117 | { |
118 | int i; | ||
119 | |||
117 | dsp_clock_disable_all(dsp_clocks); | 120 | dsp_clock_disable_all(dsp_clocks); |
118 | 121 | ||
122 | for (i = 0; i < DM_TIMER_CLOCKS; i++) | ||
123 | omap_dm_timer_free(timer[i]); | ||
124 | |||
119 | clk_put(iva2_clk); | 125 | clk_put(iva2_clk); |
120 | clk_put(ssi.sst_fck); | 126 | clk_put(ssi.sst_fck); |
121 | clk_put(ssi.ssr_fck); | 127 | clk_put(ssi.ssr_fck); |
@@ -130,9 +136,13 @@ void dsp_clk_exit(void) | |||
130 | void dsp_clk_init(void) | 136 | void dsp_clk_init(void) |
131 | { | 137 | { |
132 | static struct platform_device dspbridge_device; | 138 | static struct platform_device dspbridge_device; |
139 | int i, id; | ||
133 | 140 | ||
134 | dspbridge_device.dev.bus = &platform_bus_type; | 141 | dspbridge_device.dev.bus = &platform_bus_type; |
135 | 142 | ||
143 | for (i = 0, id = 5; i < DM_TIMER_CLOCKS; i++, id++) | ||
144 | timer[i] = omap_dm_timer_request_specific(id); | ||
145 | |||
136 | iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck"); | 146 | iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck"); |
137 | if (IS_ERR(iva2_clk)) | 147 | if (IS_ERR(iva2_clk)) |
138 | dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk); | 148 | dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk); |
@@ -204,8 +214,7 @@ int dsp_clk_enable(enum dsp_clk_id clk_id) | |||
204 | clk_enable(iva2_clk); | 214 | clk_enable(iva2_clk); |
205 | break; | 215 | break; |
206 | case GPT_CLK: | 216 | case GPT_CLK: |
207 | timer[clk_id - 1] = | 217 | status = omap_dm_timer_start(timer[clk_id - 1]); |
208 | omap_dm_timer_request_specific(DMT_ID(clk_id)); | ||
209 | break; | 218 | break; |
210 | #ifdef CONFIG_OMAP_MCBSP | 219 | #ifdef CONFIG_OMAP_MCBSP |
211 | case MCBSP_CLK: | 220 | case MCBSP_CLK: |
@@ -281,7 +290,7 @@ int dsp_clk_disable(enum dsp_clk_id clk_id) | |||
281 | clk_disable(iva2_clk); | 290 | clk_disable(iva2_clk); |
282 | break; | 291 | break; |
283 | case GPT_CLK: | 292 | case GPT_CLK: |
284 | omap_dm_timer_free(timer[clk_id - 1]); | 293 | status = omap_dm_timer_stop(timer[clk_id - 1]); |
285 | break; | 294 | break; |
286 | #ifdef CONFIG_OMAP_MCBSP | 295 | #ifdef CONFIG_OMAP_MCBSP |
287 | case MCBSP_CLK: | 296 | case MCBSP_CLK: |