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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-03 17:06:07 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-07-27 16:55:44 -0400
commitea90f011fdcc3d4fde78532eab8af09637176765 (patch)
treeb1ba42bbecd833fda9638d46af4da9a100701c3f /drivers
parentb01fbc10e3c789763b2c953984bc4b80f59bcdf3 (diff)
[media] drxk: Remove the CHK_ERROR macro
The CHK_ERROR macro does a flow control, violating chapter 12 of the Documentation/CodingStyle. Doing flow controls inside macros is a bad idea, as it hides what's happening. It also hides the var "status" with is also a bad idea. The changes were done by this small perl script: my $blk=0; while (<>) { s /^\s+// if ($blk); $f =~ s/\s+$// if ($blk && /^\(/); $blk = 1 if (!m/\#/ && m/CHK_ERROR/); $blk=0 if ($blk && m/\;/); s/\n/ / if ($blk); $f.=$_; }; $f=~ s,\n(\t+)CHK_ERROR\((.*)\)\;([^\n]*),\n\1status = \2;\3\n\1if (status < 0)\n\1\tbreak;,g; print $f; And manually fixed. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/dvb/frontends/drxk_hard.c3479
-rw-r--r--drivers/media/dvb/frontends/tda18271c2dd.c4
2 files changed, 2170 insertions, 1313 deletions
diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c
index 5ac5e7653cba..f2c5a9261608 100644
--- a/drivers/media/dvb/frontends/drxk_hard.c
+++ b/drivers/media/dvb/frontends/drxk_hard.c
@@ -77,10 +77,6 @@ bool IsA1WithRomCode(struct drxk_state *state)
77 77
78#define NOA1ROM 0 78#define NOA1ROM 0
79 79
80#ifndef CHK_ERROR
81#define CHK_ERROR(s) if ((status = s) < 0) break
82#endif
83
84#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0) 80#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
85#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0) 81#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
86 82
@@ -519,12 +515,16 @@ int PowerUpDevice(struct drxk_state *state)
519 return -1; 515 return -1;
520 do { 516 do {
521 /* Make sure all clk domains are active */ 517 /* Make sure all clk domains are active */
522 CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, 518 status = Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
523 SIO_CC_PWD_MODE_LEVEL_NONE)); 519 if (status < 0)
524 CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, 520 break;
525 SIO_CC_UPDATE_KEY)); 521 status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
522 if (status < 0)
523 break;
526 /* Enable pll lock tests */ 524 /* Enable pll lock tests */
527 CHK_ERROR(Write16_0(state, SIO_CC_PLL_LOCK__A, 1)); 525 status = Write16_0(state, SIO_CC_PLL_LOCK__A, 1);
526 if (status < 0)
527 break;
528 state->m_currentPowerMode = DRX_POWER_UP; 528 state->m_currentPowerMode = DRX_POWER_UP;
529 } while (0); 529 } while (0);
530 return status; 530 return status;
@@ -795,15 +795,25 @@ static int DRXX_Open(struct drxk_state *state)
795 795
796 do { 796 do {
797 /* stop lock indicator process */ 797 /* stop lock indicator process */
798 CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, 798 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
799 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); 799 if (status < 0)
800 break;
800 /* Check device id */ 801 /* Check device id */
801 CHK_ERROR(Read16(state, SIO_TOP_COMM_KEY__A, &key, 0)); 802 status = Read16(state, SIO_TOP_COMM_KEY__A, &key, 0);
802 CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 803 if (status < 0)
803 SIO_TOP_COMM_KEY_KEY)); 804 break;
804 CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0)); 805 status = Write16_0(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
805 CHK_ERROR(Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0)); 806 if (status < 0)
806 CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, key)); 807 break;
808 status = Read32(state, SIO_TOP_JTAGID_LO__A, &jtag, 0);
809 if (status < 0)
810 break;
811 status = Read16(state, SIO_PDR_UIO_IN_HI__A, &bid, 0);
812 if (status < 0)
813 break;
814 status = Write16_0(state, SIO_TOP_COMM_KEY__A, key);
815 if (status < 0)
816 break;
807 } while (0); 817 } while (0);
808 return status; 818 return status;
809} 819}
@@ -817,13 +827,19 @@ static int GetDeviceCapabilities(struct drxk_state *state)
817 do { 827 do {
818 /* driver 0.9.0 */ 828 /* driver 0.9.0 */
819 /* stop lock indicator process */ 829 /* stop lock indicator process */
820 CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, 830 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
821 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); 831 if (status < 0)
832 break;
822 833
823 CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); 834 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA);
824 CHK_ERROR(Read16 835 if (status < 0)
825 (state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0)); 836 break;
826 CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); 837 status = Read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg, 0);
838 if (status < 0)
839 break;
840 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000);
841 if (status < 0)
842 break;
827 843
828 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { 844 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
829 case 0: 845 case 0:
@@ -848,8 +864,9 @@ static int GetDeviceCapabilities(struct drxk_state *state)
848 Determine device capabilities 864 Determine device capabilities
849 Based on pinning v14 865 Based on pinning v14
850 */ 866 */
851 CHK_ERROR(Read32(state, SIO_TOP_JTAGID_LO__A, 867 status = Read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo, 0);
852 &sioTopJtagidLo, 0)); 868 if (status < 0)
869 break;
853 /* driver 0.9.0 */ 870 /* driver 0.9.0 */
854 switch ((sioTopJtagidLo >> 29) & 0xF) { 871 switch ((sioTopJtagidLo >> 29) & 0xF) {
855 case 0: 872 case 0:
@@ -1024,19 +1041,27 @@ static int HI_CfgCommand(struct drxk_state *state)
1024 1041
1025 mutex_lock(&state->mutex); 1042 mutex_lock(&state->mutex);
1026 do { 1043 do {
1027 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_6__A, 1044 status = Write16_0(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1028 state->m_HICfgTimeout)); 1045 if (status < 0)
1029 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_5__A, 1046 break;
1030 state->m_HICfgCtrl)); 1047 status = Write16_0(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1031 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_4__A, 1048 if (status < 0)
1032 state->m_HICfgWakeUpKey)); 1049 break;
1033 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_3__A, 1050 status = Write16_0(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1034 state->m_HICfgBridgeDelay)); 1051 if (status < 0)
1035 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, 1052 break;
1036 state->m_HICfgTimingDiv)); 1053 status = Write16_0(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1037 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, 1054 if (status < 0)
1038 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); 1055 break;
1039 CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0)); 1056 status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1057 if (status < 0)
1058 break;
1059 status = Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1060 if (status < 0)
1061 break;
1062 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1063 if (status < 0)
1064 break;
1040 1065
1041 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1066 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1042 } while (0); 1067 } while (0);
@@ -1061,38 +1086,53 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1061 1086
1062 do { 1087 do {
1063 /* stop lock indicator process */ 1088 /* stop lock indicator process */
1064 CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, 1089 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1065 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); 1090 if (status < 0)
1091 break;
1066 1092
1067 /* MPEG TS pad configuration */ 1093 /* MPEG TS pad configuration */
1068 CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA)); 1094 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1095 if (status < 0)
1096 break;
1069 1097
1070 if (mpegEnable == false) { 1098 if (mpegEnable == false) {
1071 /* Set MPEG TS pads to inputmode */ 1099 /* Set MPEG TS pads to inputmode */
1072 CHK_ERROR(Write16_0(state, 1100 status = Write16_0(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1073 SIO_PDR_MSTRT_CFG__A, 0x0000)); 1101 if (status < 0)
1074 CHK_ERROR(Write16_0(state, 1102 break;
1075 SIO_PDR_MERR_CFG__A, 0x0000)); 1103 status = Write16_0(state, SIO_PDR_MERR_CFG__A, 0x0000);
1076 CHK_ERROR(Write16_0(state, 1104 if (status < 0)
1077 SIO_PDR_MCLK_CFG__A, 0x0000)); 1105 break;
1078 CHK_ERROR(Write16_0(state, 1106 status = Write16_0(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1079 SIO_PDR_MVAL_CFG__A, 0x0000)); 1107 if (status < 0)
1080 CHK_ERROR(Write16_0 1108 break;
1081 (state, SIO_PDR_MD0_CFG__A, 0x0000)); 1109 status = Write16_0(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1082 CHK_ERROR(Write16_0 1110 if (status < 0)
1083 (state, SIO_PDR_MD1_CFG__A, 0x0000)); 1111 break;
1084 CHK_ERROR(Write16_0 1112 status = Write16_0(state, SIO_PDR_MD0_CFG__A, 0x0000);
1085 (state, SIO_PDR_MD2_CFG__A, 0x0000)); 1113 if (status < 0)
1086 CHK_ERROR(Write16_0 1114 break;
1087 (state, SIO_PDR_MD3_CFG__A, 0x0000)); 1115 status = Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000);
1088 CHK_ERROR(Write16_0 1116 if (status < 0)
1089 (state, SIO_PDR_MD4_CFG__A, 0x0000)); 1117 break;
1090 CHK_ERROR(Write16_0 1118 status = Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000);
1091 (state, SIO_PDR_MD5_CFG__A, 0x0000)); 1119 if (status < 0)
1092 CHK_ERROR(Write16_0 1120 break;
1093 (state, SIO_PDR_MD6_CFG__A, 0x0000)); 1121 status = Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000);
1094 CHK_ERROR(Write16_0 1122 if (status < 0)
1095 (state, SIO_PDR_MD7_CFG__A, 0x0000)); 1123 break;
1124 status = Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000);
1125 if (status < 0)
1126 break;
1127 status = Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000);
1128 if (status < 0)
1129 break;
1130 status = Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000);
1131 if (status < 0)
1132 break;
1133 status = Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000);
1134 if (status < 0)
1135 break;
1096 } else { 1136 } else {
1097 /* Enable MPEG output */ 1137 /* Enable MPEG output */
1098 sioPdrMdxCfg = 1138 sioPdrMdxCfg =
@@ -1102,69 +1142,80 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1102 SIO_PDR_MCLK_CFG_DRIVE__B) | 1142 SIO_PDR_MCLK_CFG_DRIVE__B) |
1103 0x0003); 1143 0x0003);
1104 1144
1105 CHK_ERROR(Write16_0(state, SIO_PDR_MSTRT_CFG__A, 1145 status = Write16_0(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1106 sioPdrMdxCfg)); 1146 if (status < 0)
1107 CHK_ERROR(Write16_0(state, SIO_PDR_MERR_CFG__A, 0x0000)); /* Disable */ 1147 break;
1108 CHK_ERROR(Write16_0(state, SIO_PDR_MVAL_CFG__A, 0x0000)); /* Disable */ 1148 status = Write16_0(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1149 if (status < 0)
1150 break;
1151 status = Write16_0(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1152 if (status < 0)
1153 break;
1109 if (state->m_enableParallel == true) { 1154 if (state->m_enableParallel == true) {
1110 /* paralel -> enable MD1 to MD7 */ 1155 /* paralel -> enable MD1 to MD7 */
1111 CHK_ERROR(Write16_0 1156 status = Write16_0(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1112 (state, SIO_PDR_MD1_CFG__A, 1157 if (status < 0)
1113 sioPdrMdxCfg)); 1158 break;
1114 CHK_ERROR(Write16_0 1159 status = Write16_0(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1115 (state, SIO_PDR_MD2_CFG__A, 1160 if (status < 0)
1116 sioPdrMdxCfg)); 1161 break;
1117 CHK_ERROR(Write16_0 1162 status = Write16_0(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1118 (state, SIO_PDR_MD3_CFG__A, 1163 if (status < 0)
1119 sioPdrMdxCfg)); 1164 break;
1120 CHK_ERROR(Write16_0 1165 status = Write16_0(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1121 (state, SIO_PDR_MD4_CFG__A, 1166 if (status < 0)
1122 sioPdrMdxCfg)); 1167 break;
1123 CHK_ERROR(Write16_0 1168 status = Write16_0(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1124 (state, SIO_PDR_MD5_CFG__A, 1169 if (status < 0)
1125 sioPdrMdxCfg)); 1170 break;
1126 CHK_ERROR(Write16_0 1171 status = Write16_0(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1127 (state, SIO_PDR_MD6_CFG__A, 1172 if (status < 0)
1128 sioPdrMdxCfg)); 1173 break;
1129 CHK_ERROR(Write16_0 1174 status = Write16_0(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1130 (state, SIO_PDR_MD7_CFG__A, 1175 if (status < 0)
1131 sioPdrMdxCfg)); 1176 break;
1132 } else { 1177 } else {
1133 sioPdrMdxCfg = ((state->m_TSDataStrength << 1178 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1134 SIO_PDR_MD0_CFG_DRIVE__B) 1179 SIO_PDR_MD0_CFG_DRIVE__B)
1135 | 0x0003); 1180 | 0x0003);
1136 /* serial -> disable MD1 to MD7 */ 1181 /* serial -> disable MD1 to MD7 */
1137 CHK_ERROR(Write16_0 1182 status = Write16_0(state, SIO_PDR_MD1_CFG__A, 0x0000);
1138 (state, SIO_PDR_MD1_CFG__A, 1183 if (status < 0)
1139 0x0000)); 1184 break;
1140 CHK_ERROR(Write16_0 1185 status = Write16_0(state, SIO_PDR_MD2_CFG__A, 0x0000);
1141 (state, SIO_PDR_MD2_CFG__A, 1186 if (status < 0)
1142 0x0000)); 1187 break;
1143 CHK_ERROR(Write16_0 1188 status = Write16_0(state, SIO_PDR_MD3_CFG__A, 0x0000);
1144 (state, SIO_PDR_MD3_CFG__A, 1189 if (status < 0)
1145 0x0000)); 1190 break;
1146 CHK_ERROR(Write16_0 1191 status = Write16_0(state, SIO_PDR_MD4_CFG__A, 0x0000);
1147 (state, SIO_PDR_MD4_CFG__A, 1192 if (status < 0)
1148 0x0000)); 1193 break;
1149 CHK_ERROR(Write16_0 1194 status = Write16_0(state, SIO_PDR_MD5_CFG__A, 0x0000);
1150 (state, SIO_PDR_MD5_CFG__A, 1195 if (status < 0)
1151 0x0000)); 1196 break;
1152 CHK_ERROR(Write16_0 1197 status = Write16_0(state, SIO_PDR_MD6_CFG__A, 0x0000);
1153 (state, SIO_PDR_MD6_CFG__A, 1198 if (status < 0)
1154 0x0000)); 1199 break;
1155 CHK_ERROR(Write16_0 1200 status = Write16_0(state, SIO_PDR_MD7_CFG__A, 0x0000);
1156 (state, SIO_PDR_MD7_CFG__A, 1201 if (status < 0)
1157 0x0000)); 1202 break;
1158 } 1203 }
1159 CHK_ERROR(Write16_0(state, SIO_PDR_MCLK_CFG__A, 1204 status = Write16_0(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1160 sioPdrMclkCfg)); 1205 if (status < 0)
1161 CHK_ERROR(Write16_0(state, SIO_PDR_MD0_CFG__A, 1206 break;
1162 sioPdrMdxCfg)); 1207 status = Write16_0(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1208 if (status < 0)
1209 break;
1163 } 1210 }
1164 /* Enable MB output over MPEG pads and ctl input */ 1211 /* Enable MB output over MPEG pads and ctl input */
1165 CHK_ERROR(Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000)); 1212 status = Write16_0(state, SIO_PDR_MON_CFG__A, 0x0000);
1213 if (status < 0)
1214 break;
1166 /* Write nomagic word to enable pdr reg write */ 1215 /* Write nomagic word to enable pdr reg write */
1167 CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); 1216 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000);
1217 if (status < 0)
1218 break;
1168 } while (0); 1219 } while (0);
1169 return status; 1220 return status;
1170} 1221}
@@ -1183,20 +1234,25 @@ static int BLChainCmd(struct drxk_state *state,
1183 1234
1184 mutex_lock(&state->mutex); 1235 mutex_lock(&state->mutex);
1185 do { 1236 do {
1186 CHK_ERROR(Write16_0(state, SIO_BL_MODE__A, 1237 status = Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1187 SIO_BL_MODE_CHAIN)); 1238 if (status < 0)
1188 CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_ADDR__A, 1239 break;
1189 romOffset)); 1240 status = Write16_0(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1190 CHK_ERROR(Write16_0(state, SIO_BL_CHAIN_LEN__A, 1241 if (status < 0)
1191 nrOfElements)); 1242 break;
1192 CHK_ERROR(Write16_0(state, SIO_BL_ENABLE__A, 1243 status = Write16_0(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1193 SIO_BL_ENABLE_ON)); 1244 if (status < 0)
1245 break;
1246 status = Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1247 if (status < 0)
1248 break;
1194 end = jiffies + msecs_to_jiffies(timeOut); 1249 end = jiffies + msecs_to_jiffies(timeOut);
1195 1250
1196 do { 1251 do {
1197 msleep(1); 1252 msleep(1);
1198 CHK_ERROR(Read16(state, SIO_BL_STATUS__A, 1253 status = Read16(state, SIO_BL_STATUS__A, &blStatus, 0);
1199 &blStatus, 0)); 1254 if (status < 0)
1255 break;
1200 } while ((blStatus == 0x1) && 1256 } while ((blStatus == 0x1) &&
1201 ((time_is_after_jiffies(end)))); 1257 ((time_is_after_jiffies(end))));
1202 if (blStatus == 0x1) { 1258 if (blStatus == 0x1) {
@@ -1282,10 +1338,11 @@ static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1282 Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); 1338 Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1283 1339
1284 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); 1340 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1285 do 1341 do {
1286 CHK_ERROR(Read16_0 1342 status = Read16_0(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1287 (state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data)); 1343 if (status < 0)
1288 while ((data != desiredStatus) && ((time_is_after_jiffies(end)))); 1344 break;
1345 } while ((data != desiredStatus) && ((time_is_after_jiffies(end))));
1289 if (data != desiredStatus) { 1346 if (data != desiredStatus) {
1290 printk(KERN_ERR "SIO not ready\n"); 1347 printk(KERN_ERR "SIO not ready\n");
1291 return -1; 1348 return -1;
@@ -1301,18 +1358,22 @@ static int MPEGTSStop(struct drxk_state *state)
1301 1358
1302 do { 1359 do {
1303 /* Gracefull shutdown (byte boundaries) */ 1360 /* Gracefull shutdown (byte boundaries) */
1304 CHK_ERROR(Read16_0 1361 status = Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1305 (state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); 1362 if (status < 0)
1363 break;
1306 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; 1364 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1307 CHK_ERROR(Write16_0 1365 status = Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1308 (state, FEC_OC_SNC_MODE__A, fecOcSncMode)); 1366 if (status < 0)
1367 break;
1309 1368
1310 /* Suppress MCLK during absence of data */ 1369 /* Suppress MCLK during absence of data */
1311 CHK_ERROR(Read16_0 1370 status = Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1312 (state, FEC_OC_IPR_MODE__A, &fecOcIprMode)); 1371 if (status < 0)
1372 break;
1313 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; 1373 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1314 CHK_ERROR(Write16_0 1374 status = Write16_0(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1315 (state, FEC_OC_IPR_MODE__A, fecOcIprMode)); 1375 if (status < 0)
1376 break;
1316 } while (0); 1377 } while (0);
1317 return status; 1378 return status;
1318} 1379}
@@ -1352,8 +1413,9 @@ static int scu_command(struct drxk_state *state,
1352 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); 1413 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1353 do { 1414 do {
1354 msleep(1); 1415 msleep(1);
1355 CHK_ERROR(Read16_0 1416 status = Read16_0(state, SCU_RAM_COMMAND__A, &curCmd);
1356 (state, SCU_RAM_COMMAND__A, &curCmd)); 1417 if (status < 0)
1418 break;
1357 } while (!(curCmd == DRX_SCU_READY) 1419 } while (!(curCmd == DRX_SCU_READY)
1358 && (time_is_after_jiffies(end))); 1420 && (time_is_after_jiffies(end)));
1359 if (curCmd != DRX_SCU_READY) { 1421 if (curCmd != DRX_SCU_READY) {
@@ -1367,9 +1429,9 @@ static int scu_command(struct drxk_state *state,
1367 int ii; 1429 int ii;
1368 1430
1369 for (ii = resultLen - 1; ii >= 0; ii -= 1) { 1431 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1370 CHK_ERROR(Read16_0(state, 1432 status = Read16_0(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1371 SCU_RAM_PARAM_0__A - ii, 1433 if (status < 0)
1372 &result[ii])); 1434 break;
1373 } 1435 }
1374 1436
1375 /* Check if an error was reported by SCU */ 1437 /* Check if an error was reported by SCU */
@@ -1408,7 +1470,9 @@ static int SetIqmAf(struct drxk_state *state, bool active)
1408 1470
1409 do { 1471 do {
1410 /* Configure IQM */ 1472 /* Configure IQM */
1411 CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); 1473 status = Read16_0(state, IQM_AF_STDBY__A, &data);
1474 if (status < 0)
1475 break;
1412 if (!active) { 1476 if (!active) {
1413 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY 1477 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1414 | IQM_AF_STDBY_STDBY_AMP_STANDBY 1478 | IQM_AF_STDBY_STDBY_AMP_STANDBY
@@ -1424,7 +1488,9 @@ static int SetIqmAf(struct drxk_state *state, bool active)
1424 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY) 1488 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1425 ); 1489 );
1426 } 1490 }
1427 CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); 1491 status = Write16_0(state, IQM_AF_STDBY__A, data);
1492 if (status < 0)
1493 break;
1428 } while (0); 1494 } while (0);
1429 return status; 1495 return status;
1430} 1496}
@@ -1467,8 +1533,12 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1467 /* For next steps make sure to start from DRX_POWER_UP mode */ 1533 /* For next steps make sure to start from DRX_POWER_UP mode */
1468 if (state->m_currentPowerMode != DRX_POWER_UP) { 1534 if (state->m_currentPowerMode != DRX_POWER_UP) {
1469 do { 1535 do {
1470 CHK_ERROR(PowerUpDevice(state)); 1536 status = PowerUpDevice(state);
1471 CHK_ERROR(DVBTEnableOFDMTokenRing(state, true)); 1537 if (status < 0)
1538 break;
1539 status = DVBTEnableOFDMTokenRing(state, true);
1540 if (status < 0)
1541 break;
1472 } while (0); 1542 } while (0);
1473 } 1543 }
1474 1544
@@ -1487,27 +1557,41 @@ static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1487 do { 1557 do {
1488 switch (state->m_OperationMode) { 1558 switch (state->m_OperationMode) {
1489 case OM_DVBT: 1559 case OM_DVBT:
1490 CHK_ERROR(MPEGTSStop(state)); 1560 status = MPEGTSStop(state);
1491 CHK_ERROR(PowerDownDVBT(state, false)); 1561 if (status < 0)
1562 break;
1563 status = PowerDownDVBT(state, false);
1564 if (status < 0)
1565 break;
1492 break; 1566 break;
1493 case OM_QAM_ITU_A: 1567 case OM_QAM_ITU_A:
1494 case OM_QAM_ITU_C: 1568 case OM_QAM_ITU_C:
1495 CHK_ERROR(MPEGTSStop(state)); 1569 status = MPEGTSStop(state);
1496 CHK_ERROR(PowerDownQAM(state)); 1570 if (status < 0)
1571 break;
1572 status = PowerDownQAM(state);
1573 if (status < 0)
1574 break;
1497 break; 1575 break;
1498 default: 1576 default:
1499 break; 1577 break;
1500 } 1578 }
1501 CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); 1579 status = DVBTEnableOFDMTokenRing(state, false);
1502 CHK_ERROR(Write16_0(state, SIO_CC_PWD_MODE__A, 1580 if (status < 0)
1503 sioCcPwdMode)); 1581 break;
1504 CHK_ERROR(Write16_0(state, SIO_CC_UPDATE__A, 1582 status = Write16_0(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1505 SIO_CC_UPDATE_KEY)); 1583 if (status < 0)
1584 break;
1585 status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1586 if (status < 0)
1587 break;
1506 1588
1507 if (*mode != DRXK_POWER_DOWN_OFDM) { 1589 if (*mode != DRXK_POWER_DOWN_OFDM) {
1508 state->m_HICfgCtrl |= 1590 state->m_HICfgCtrl |=
1509 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 1591 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1510 CHK_ERROR(HI_CfgCommand(state)); 1592 status = HI_CfgCommand(state);
1593 if (status < 0)
1594 break;
1511 } 1595 }
1512 } while (0); 1596 } while (0);
1513 } 1597 }
@@ -1523,36 +1607,41 @@ static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1523 int status; 1607 int status;
1524 1608
1525 do { 1609 do {
1526 CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); 1610 status = Read16_0(state, SCU_COMM_EXEC__A, &data);
1611 if (status < 0)
1612 break;
1527 if (data == SCU_COMM_EXEC_ACTIVE) { 1613 if (data == SCU_COMM_EXEC_ACTIVE) {
1528 /* Send OFDM stop command */ 1614 /* Send OFDM stop command */
1529 CHK_ERROR(scu_command(state, 1615 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1530 SCU_RAM_COMMAND_STANDARD_OFDM 1616 if (status < 0)
1531 | 1617 break;
1532 SCU_RAM_COMMAND_CMD_DEMOD_STOP,
1533 0, NULL, 1, &cmdResult));
1534 /* Send OFDM reset command */ 1618 /* Send OFDM reset command */
1535 CHK_ERROR(scu_command(state, 1619 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1536 SCU_RAM_COMMAND_STANDARD_OFDM 1620 if (status < 0)
1537 | 1621 break;
1538 SCU_RAM_COMMAND_CMD_DEMOD_RESET,
1539 0, NULL, 1, &cmdResult));
1540 } 1622 }
1541 1623
1542 /* Reset datapath for OFDM, processors first */ 1624 /* Reset datapath for OFDM, processors first */
1543 CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, 1625 status = Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1544 OFDM_SC_COMM_EXEC_STOP)); 1626 if (status < 0)
1545 CHK_ERROR(Write16_0(state, OFDM_LC_COMM_EXEC__A, 1627 break;
1546 OFDM_LC_COMM_EXEC_STOP)); 1628 status = Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1547 CHK_ERROR(Write16_0(state, IQM_COMM_EXEC__A, 1629 if (status < 0)
1548 IQM_COMM_EXEC_B_STOP)); 1630 break;
1631 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1632 if (status < 0)
1633 break;
1549 1634
1550 /* powerdown AFE */ 1635 /* powerdown AFE */
1551 CHK_ERROR(SetIqmAf(state, false)); 1636 status = SetIqmAf(state, false);
1637 if (status < 0)
1638 break;
1552 1639
1553 /* powerdown to OFDM mode */ 1640 /* powerdown to OFDM mode */
1554 if (setPowerMode) { 1641 if (setPowerMode) {
1555 CHK_ERROR(CtrlPowerMode(state, &powerMode)); 1642 status = CtrlPowerMode(state, &powerMode);
1643 if (status < 0)
1644 break;
1556 } 1645 }
1557 } while (0); 1646 } while (0);
1558 return status; 1647 return status;
@@ -1570,8 +1659,9 @@ static int SetOperationMode(struct drxk_state *state,
1570 */ 1659 */
1571 do { 1660 do {
1572 /* disable HW lock indicator */ 1661 /* disable HW lock indicator */
1573 CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, 1662 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1574 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); 1663 if (status < 0)
1664 break;
1575 1665
1576 if (state->m_OperationMode != oMode) { 1666 if (state->m_OperationMode != oMode) {
1577 switch (state->m_OperationMode) { 1667 switch (state->m_OperationMode) {
@@ -1579,8 +1669,12 @@ static int SetOperationMode(struct drxk_state *state,
1579 case OM_NONE: 1669 case OM_NONE:
1580 break; 1670 break;
1581 case OM_DVBT: 1671 case OM_DVBT:
1582 CHK_ERROR(MPEGTSStop(state)); 1672 status = MPEGTSStop(state);
1583 CHK_ERROR(PowerDownDVBT(state, true)); 1673 if (status < 0)
1674 break;
1675 status = PowerDownDVBT(state, true);
1676 if (status < 0)
1677 break;
1584 state->m_OperationMode = OM_NONE; 1678 state->m_OperationMode = OM_NONE;
1585 break; 1679 break;
1586 case OM_QAM_ITU_B: 1680 case OM_QAM_ITU_B:
@@ -1588,14 +1682,20 @@ static int SetOperationMode(struct drxk_state *state,
1588 break; 1682 break;
1589 case OM_QAM_ITU_A: /* fallthrough */ 1683 case OM_QAM_ITU_A: /* fallthrough */
1590 case OM_QAM_ITU_C: 1684 case OM_QAM_ITU_C:
1591 CHK_ERROR(MPEGTSStop(state)); 1685 status = MPEGTSStop(state);
1592 CHK_ERROR(PowerDownQAM(state)); 1686 if (status < 0)
1687 break;
1688 status = PowerDownQAM(state);
1689 if (status < 0)
1690 break;
1593 state->m_OperationMode = OM_NONE; 1691 state->m_OperationMode = OM_NONE;
1594 break; 1692 break;
1595 default: 1693 default:
1596 status = -1; 1694 status = -1;
1597 } 1695 }
1598 CHK_ERROR(status); 1696 status = status;
1697 if (status < 0)
1698 break;
1599 1699
1600 /* 1700 /*
1601 Power up new standard 1701 Power up new standard
@@ -1603,7 +1703,9 @@ static int SetOperationMode(struct drxk_state *state,
1603 switch (oMode) { 1703 switch (oMode) {
1604 case OM_DVBT: 1704 case OM_DVBT:
1605 state->m_OperationMode = oMode; 1705 state->m_OperationMode = oMode;
1606 CHK_ERROR(SetDVBTStandard(state, oMode)); 1706 status = SetDVBTStandard(state, oMode);
1707 if (status < 0)
1708 break;
1607 break; 1709 break;
1608 case OM_QAM_ITU_B: 1710 case OM_QAM_ITU_B:
1609 status = -1; 1711 status = -1;
@@ -1611,13 +1713,17 @@ static int SetOperationMode(struct drxk_state *state,
1611 case OM_QAM_ITU_A: /* fallthrough */ 1713 case OM_QAM_ITU_A: /* fallthrough */
1612 case OM_QAM_ITU_C: 1714 case OM_QAM_ITU_C:
1613 state->m_OperationMode = oMode; 1715 state->m_OperationMode = oMode;
1614 CHK_ERROR(SetQAMStandard(state, oMode)); 1716 status = SetQAMStandard(state, oMode);
1717 if (status < 0)
1718 break;
1615 break; 1719 break;
1616 default: 1720 default:
1617 status = -1; 1721 status = -1;
1618 } 1722 }
1619 } 1723 }
1620 CHK_ERROR(status); 1724 status = status;
1725 if (status < 0)
1726 break;
1621 } while (0); 1727 } while (0);
1622 return 0; 1728 return 0;
1623} 1729}
@@ -1649,14 +1755,22 @@ static int Start(struct drxk_state *state, s32 offsetFreq,
1649 case OM_QAM_ITU_A: 1755 case OM_QAM_ITU_A:
1650 case OM_QAM_ITU_C: 1756 case OM_QAM_ITU_C:
1651 IFreqkHz = (IntermediateFrequency / 1000); 1757 IFreqkHz = (IntermediateFrequency / 1000);
1652 CHK_ERROR(SetQAM(state, IFreqkHz, OffsetkHz)); 1758 status = SetQAM(state, IFreqkHz, OffsetkHz);
1759 if (status < 0)
1760 break;
1653 state->m_DrxkState = DRXK_DTV_STARTED; 1761 state->m_DrxkState = DRXK_DTV_STARTED;
1654 break; 1762 break;
1655 case OM_DVBT: 1763 case OM_DVBT:
1656 IFreqkHz = (IntermediateFrequency / 1000); 1764 IFreqkHz = (IntermediateFrequency / 1000);
1657 CHK_ERROR(MPEGTSStop(state)); 1765 status = MPEGTSStop(state);
1658 CHK_ERROR(SetDVBT(state, IFreqkHz, OffsetkHz)); 1766 if (status < 0)
1659 CHK_ERROR(DVBTStart(state)); 1767 break;
1768 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1769 if (status < 0)
1770 break;
1771 status = DVBTStart(state);
1772 if (status < 0)
1773 break;
1660 state->m_DrxkState = DRXK_DTV_STARTED; 1774 state->m_DrxkState = DRXK_DTV_STARTED;
1661 break; 1775 break;
1662 default: 1776 default:
@@ -1706,12 +1820,16 @@ static int MPEGTSStart(struct drxk_state *state)
1706 1820
1707 do { 1821 do {
1708 /* Allow OC to sync again */ 1822 /* Allow OC to sync again */
1709 CHK_ERROR(Read16_0 1823 status = Read16_0(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1710 (state, FEC_OC_SNC_MODE__A, &fecOcSncMode)); 1824 if (status < 0)
1825 break;
1711 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; 1826 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1712 CHK_ERROR(Write16_0 1827 status = Write16_0(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1713 (state, FEC_OC_SNC_MODE__A, fecOcSncMode)); 1828 if (status < 0)
1714 CHK_ERROR(Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1)); 1829 break;
1830 status = Write16_0(state, FEC_OC_SNC_UNLOCK__A, 1);
1831 if (status < 0)
1832 break;
1715 } while (0); 1833 } while (0);
1716 return status; 1834 return status;
1717} 1835}
@@ -1722,23 +1840,41 @@ static int MPEGTSDtoInit(struct drxk_state *state)
1722 1840
1723 do { 1841 do {
1724 /* Rate integration settings */ 1842 /* Rate integration settings */
1725 CHK_ERROR(Write16_0 1843 status = Write16_0(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1726 (state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000)); 1844 if (status < 0)
1727 CHK_ERROR(Write16_0 1845 break;
1728 (state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C)); 1846 status = Write16_0(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1729 CHK_ERROR(Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A)); 1847 if (status < 0)
1730 CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008)); 1848 break;
1731 CHK_ERROR(Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006)); 1849 status = Write16_0(state, FEC_OC_RCN_GAIN__A, 0x000A);
1732 CHK_ERROR(Write16_0 1850 if (status < 0)
1733 (state, FEC_OC_TMD_HI_MARGIN__A, 0x0680)); 1851 break;
1734 CHK_ERROR(Write16_0 1852 status = Write16_0(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1735 (state, FEC_OC_TMD_LO_MARGIN__A, 0x0080)); 1853 if (status < 0)
1736 CHK_ERROR(Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4)); 1854 break;
1855 status = Write16_0(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1856 if (status < 0)
1857 break;
1858 status = Write16_0(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1859 if (status < 0)
1860 break;
1861 status = Write16_0(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1862 if (status < 0)
1863 break;
1864 status = Write16_0(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1865 if (status < 0)
1866 break;
1737 1867
1738 /* Additional configuration */ 1868 /* Additional configuration */
1739 CHK_ERROR(Write16_0(state, FEC_OC_OCR_INVERT__A, 0)); 1869 status = Write16_0(state, FEC_OC_OCR_INVERT__A, 0);
1740 CHK_ERROR(Write16_0(state, FEC_OC_SNC_LWM__A, 2)); 1870 if (status < 0)
1741 CHK_ERROR(Write16_0(state, FEC_OC_SNC_HWM__A, 12)); 1871 break;
1872 status = Write16_0(state, FEC_OC_SNC_LWM__A, 2);
1873 if (status < 0)
1874 break;
1875 status = Write16_0(state, FEC_OC_SNC_HWM__A, 12);
1876 if (status < 0)
1877 break;
1742 } while (0); 1878 } while (0);
1743 return status; 1879 return status;
1744} 1880}
@@ -1762,9 +1898,12 @@ static int MPEGTSDtoSetup(struct drxk_state *state,
1762 1898
1763 do { 1899 do {
1764 /* Check insertion of the Reed-Solomon parity bytes */ 1900 /* Check insertion of the Reed-Solomon parity bytes */
1765 CHK_ERROR(Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode)); 1901 status = Read16_0(state, FEC_OC_MODE__A, &fecOcRegMode);
1766 CHK_ERROR(Read16_0(state, FEC_OC_IPR_MODE__A, 1902 if (status < 0)
1767 &fecOcRegIprMode)); 1903 break;
1904 status = Read16_0(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
1905 if (status < 0)
1906 break;
1768 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); 1907 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
1769 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); 1908 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
1770 if (state->m_insertRSByte == true) { 1909 if (state->m_insertRSByte == true) {
@@ -1800,7 +1939,9 @@ static int MPEGTSDtoSetup(struct drxk_state *state,
1800 default: 1939 default:
1801 status = -1; 1940 status = -1;
1802 } /* switch (standard) */ 1941 } /* switch (standard) */
1803 CHK_ERROR(status); 1942 status = status;
1943 if (status < 0)
1944 break;
1804 1945
1805 /* Configure DTO's */ 1946 /* Configure DTO's */
1806 if (staticCLK) { 1947 if (staticCLK) {
@@ -1841,25 +1982,35 @@ static int MPEGTSDtoSetup(struct drxk_state *state,
1841 } 1982 }
1842 1983
1843 /* Write appropriate registers with requested configuration */ 1984 /* Write appropriate registers with requested configuration */
1844 CHK_ERROR(Write16_0(state, FEC_OC_DTO_BURST_LEN__A, 1985 status = Write16_0(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
1845 fecOcDtoBurstLen)); 1986 if (status < 0)
1846 CHK_ERROR(Write16_0(state, FEC_OC_DTO_PERIOD__A, 1987 break;
1847 fecOcDtoPeriod)); 1988 status = Write16_0(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
1848 CHK_ERROR(Write16_0(state, FEC_OC_DTO_MODE__A, 1989 if (status < 0)
1849 fecOcDtoMode)); 1990 break;
1850 CHK_ERROR(Write16_0(state, FEC_OC_FCT_MODE__A, 1991 status = Write16_0(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
1851 fecOcFctMode)); 1992 if (status < 0)
1852 CHK_ERROR(Write16_0(state, FEC_OC_MODE__A, fecOcRegMode)); 1993 break;
1853 CHK_ERROR(Write16_0(state, FEC_OC_IPR_MODE__A, 1994 status = Write16_0(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
1854 fecOcRegIprMode)); 1995 if (status < 0)
1996 break;
1997 status = Write16_0(state, FEC_OC_MODE__A, fecOcRegMode);
1998 if (status < 0)
1999 break;
2000 status = Write16_0(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2001 if (status < 0)
2002 break;
1855 2003
1856 /* Rate integration settings */ 2004 /* Rate integration settings */
1857 CHK_ERROR(Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, 2005 status = Write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate, 0);
1858 fecOcRcnCtlRate, 0)); 2006 if (status < 0)
1859 CHK_ERROR(Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, 2007 break;
1860 fecOcTmdIntUpdRate)); 2008 status = Write16_0(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
1861 CHK_ERROR(Write16_0(state, FEC_OC_TMD_MODE__A, 2009 if (status < 0)
1862 fecOcTmdMode)); 2010 break;
2011 status = Write16_0(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2012 if (status < 0)
2013 break;
1863 } while (0); 2014 } while (0);
1864 return status; 2015 return status;
1865} 2016}
@@ -1914,12 +2065,17 @@ static int SetAgcRf(struct drxk_state *state,
1914 case DRXK_AGC_CTRL_AUTO: 2065 case DRXK_AGC_CTRL_AUTO:
1915 2066
1916 /* Enable RF AGC DAC */ 2067 /* Enable RF AGC DAC */
1917 CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); 2068 status = Read16_0(state, IQM_AF_STDBY__A, &data);
2069 if (status < 0)
2070 break;
1918 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2071 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
1919 CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); 2072 status = Write16_0(state, IQM_AF_STDBY__A, data);
2073 if (status < 0)
2074 break;
1920 2075
1921 CHK_ERROR(Read16(state, SCU_RAM_AGC_CONFIG__A, 2076 status = Read16(state, SCU_RAM_AGC_CONFIG__A, &data, 0);
1922 &data, 0)); 2077 if (status < 0)
2078 break;
1923 2079
1924 /* Enable SCU RF AGC loop */ 2080 /* Enable SCU RF AGC loop */
1925 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2081 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
@@ -1929,20 +2085,23 @@ static int SetAgcRf(struct drxk_state *state,
1929 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2085 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
1930 else 2086 else
1931 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2087 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
1932 CHK_ERROR(Write16_0(state, 2088 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data);
1933 SCU_RAM_AGC_CONFIG__A, data)); 2089 if (status < 0)
2090 break;
1934 2091
1935 /* Set speed (using complementary reduction value) */ 2092 /* Set speed (using complementary reduction value) */
1936 CHK_ERROR(Read16(state, SCU_RAM_AGC_KI_RED__A, 2093 status = Read16(state, SCU_RAM_AGC_KI_RED__A, &data, 0);
1937 &data, 0)); 2094 if (status < 0)
2095 break;
1938 2096
1939 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; 2097 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
1940 data |= (~(pAgcCfg->speed << 2098 data |= (~(pAgcCfg->speed <<
1941 SCU_RAM_AGC_KI_RED_RAGC_RED__B) 2099 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
1942 & SCU_RAM_AGC_KI_RED_RAGC_RED__M); 2100 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
1943 2101
1944 CHK_ERROR(Write16_0(state, 2102 status = Write16_0(state, SCU_RAM_AGC_KI_RED__A, data);
1945 SCU_RAM_AGC_KI_RED__A, data)); 2103 if (status < 0)
2104 break;
1946 2105
1947 if (IsDVBT(state)) 2106 if (IsDVBT(state))
1948 pIfAgcSettings = &state->m_dvbtIfAgcCfg; 2107 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
@@ -1955,61 +2114,74 @@ static int SetAgcRf(struct drxk_state *state,
1955 2114
1956 /* Set TOP, only if IF-AGC is in AUTO mode */ 2115 /* Set TOP, only if IF-AGC is in AUTO mode */
1957 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) 2116 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
1958 CHK_ERROR(Write16_0(state, 2117 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
1959 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2118 if (status < 0)
1960 pAgcCfg->top)); 2119 break;
1961 2120
1962 /* Cut-Off current */ 2121 /* Cut-Off current */
1963 CHK_ERROR(Write16_0(state, 2122 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
1964 SCU_RAM_AGC_RF_IACCU_HI_CO__A, 2123 if (status < 0)
1965 pAgcCfg->cutOffCurrent)); 2124 break;
1966 2125
1967 /* Max. output level */ 2126 /* Max. output level */
1968 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_MAX__A, 2127 status = Write16_0(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
1969 pAgcCfg->maxOutputLevel)); 2128 if (status < 0)
2129 break;
1970 2130
1971 break; 2131 break;
1972 2132
1973 case DRXK_AGC_CTRL_USER: 2133 case DRXK_AGC_CTRL_USER:
1974 /* Enable RF AGC DAC */ 2134 /* Enable RF AGC DAC */
1975 CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); 2135 status = Read16_0(state, IQM_AF_STDBY__A, &data);
2136 if (status < 0)
2137 break;
1976 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2138 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
1977 CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); 2139 status = Write16_0(state, IQM_AF_STDBY__A, data);
2140 if (status < 0)
2141 break;
1978 2142
1979 /* Disable SCU RF AGC loop */ 2143 /* Disable SCU RF AGC loop */
1980 CHK_ERROR(Read16_0(state, 2144 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data);
1981 SCU_RAM_AGC_CONFIG__A, &data)); 2145 if (status < 0)
2146 break;
1982 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2147 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
1983 if (state->m_RfAgcPol) 2148 if (state->m_RfAgcPol)
1984 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2149 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
1985 else 2150 else
1986 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; 2151 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
1987 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CONFIG__A, 2152 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data);
1988 data)); 2153 if (status < 0)
2154 break;
1989 2155
1990 /* SCU c.o.c. to 0, enabling full control range */ 2156 /* SCU c.o.c. to 0, enabling full control range */
1991 CHK_ERROR(Write16_0 2157 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
1992 (state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 2158 if (status < 0)
1993 0)); 2159 break;
1994 2160
1995 /* Write value to output pin */ 2161 /* Write value to output pin */
1996 CHK_ERROR(Write16_0 2162 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
1997 (state, SCU_RAM_AGC_RF_IACCU_HI__A, 2163 if (status < 0)
1998 pAgcCfg->outputLevel)); 2164 break;
1999 break; 2165 break;
2000 2166
2001 case DRXK_AGC_CTRL_OFF: 2167 case DRXK_AGC_CTRL_OFF:
2002 /* Disable RF AGC DAC */ 2168 /* Disable RF AGC DAC */
2003 CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); 2169 status = Read16_0(state, IQM_AF_STDBY__A, &data);
2170 if (status < 0)
2171 break;
2004 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY; 2172 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2005 CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); 2173 status = Write16_0(state, IQM_AF_STDBY__A, data);
2174 if (status < 0)
2175 break;
2006 2176
2007 /* Disable SCU RF AGC loop */ 2177 /* Disable SCU RF AGC loop */
2008 CHK_ERROR(Read16_0(state, 2178 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data);
2009 SCU_RAM_AGC_CONFIG__A, &data)); 2179 if (status < 0)
2180 break;
2010 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; 2181 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2011 CHK_ERROR(Write16_0(state, 2182 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data);
2012 SCU_RAM_AGC_CONFIG__A, data)); 2183 if (status < 0)
2184 break;
2013 break; 2185 break;
2014 2186
2015 default: 2187 default:
@@ -2034,12 +2206,17 @@ static int SetAgcIf(struct drxk_state *state,
2034 case DRXK_AGC_CTRL_AUTO: 2206 case DRXK_AGC_CTRL_AUTO:
2035 2207
2036 /* Enable IF AGC DAC */ 2208 /* Enable IF AGC DAC */
2037 CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); 2209 status = Read16_0(state, IQM_AF_STDBY__A, &data);
2210 if (status < 0)
2211 break;
2038 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2212 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2039 CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); 2213 status = Write16_0(state, IQM_AF_STDBY__A, data);
2214 if (status < 0)
2215 break;
2040 2216
2041 CHK_ERROR(Read16_0(state, SCU_RAM_AGC_CONFIG__A, 2217 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data);
2042 &data)); 2218 if (status < 0)
2219 break;
2043 2220
2044 /* Enable SCU IF AGC loop */ 2221 /* Enable SCU IF AGC loop */
2045 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2222 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
@@ -2049,19 +2226,22 @@ static int SetAgcIf(struct drxk_state *state,
2049 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2226 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2050 else 2227 else
2051 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2228 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2052 CHK_ERROR(Write16_0(state, 2229 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data);
2053 SCU_RAM_AGC_CONFIG__A, data)); 2230 if (status < 0)
2231 break;
2054 2232
2055 /* Set speed (using complementary reduction value) */ 2233 /* Set speed (using complementary reduction value) */
2056 CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI_RED__A, 2234 status = Read16_0(state, SCU_RAM_AGC_KI_RED__A, &data);
2057 &data)); 2235 if (status < 0)
2236 break;
2058 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; 2237 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2059 data |= (~(pAgcCfg->speed << 2238 data |= (~(pAgcCfg->speed <<
2060 SCU_RAM_AGC_KI_RED_IAGC_RED__B) 2239 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2061 & SCU_RAM_AGC_KI_RED_IAGC_RED__M); 2240 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2062 2241
2063 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_RED__A, 2242 status = Write16_0(state, SCU_RAM_AGC_KI_RED__A, data);
2064 data)); 2243 if (status < 0)
2244 break;
2065 2245
2066 if (IsQAM(state)) 2246 if (IsQAM(state))
2067 pRfAgcSettings = &state->m_qamRfAgcCfg; 2247 pRfAgcSettings = &state->m_qamRfAgcCfg;
@@ -2070,20 +2250,25 @@ static int SetAgcIf(struct drxk_state *state,
2070 if (pRfAgcSettings == NULL) 2250 if (pRfAgcSettings == NULL)
2071 return -1; 2251 return -1;
2072 /* Restore TOP */ 2252 /* Restore TOP */
2073 CHK_ERROR(Write16_0(state, 2253 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2074 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2254 if (status < 0)
2075 pRfAgcSettings->top)); 2255 break;
2076 break; 2256 break;
2077 2257
2078 case DRXK_AGC_CTRL_USER: 2258 case DRXK_AGC_CTRL_USER:
2079 2259
2080 /* Enable IF AGC DAC */ 2260 /* Enable IF AGC DAC */
2081 CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); 2261 status = Read16_0(state, IQM_AF_STDBY__A, &data);
2262 if (status < 0)
2263 break;
2082 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2264 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2083 CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); 2265 status = Write16_0(state, IQM_AF_STDBY__A, data);
2266 if (status < 0)
2267 break;
2084 2268
2085 CHK_ERROR(Read16_0(state, 2269 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data);
2086 SCU_RAM_AGC_CONFIG__A, &data)); 2270 if (status < 0)
2271 break;
2087 2272
2088 /* Disable SCU IF AGC loop */ 2273 /* Disable SCU IF AGC loop */
2089 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2274 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
@@ -2093,35 +2278,43 @@ static int SetAgcIf(struct drxk_state *state,
2093 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2278 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2094 else 2279 else
2095 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; 2280 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2096 CHK_ERROR(Write16_0(state, 2281 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data);
2097 SCU_RAM_AGC_CONFIG__A, data)); 2282 if (status < 0)
2283 break;
2098 2284
2099 /* Write value to output pin */ 2285 /* Write value to output pin */
2100 CHK_ERROR(Write16_0(state, 2286 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2101 SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2287 if (status < 0)
2102 pAgcCfg->outputLevel)); 2288 break;
2103 break; 2289 break;
2104 2290
2105 case DRXK_AGC_CTRL_OFF: 2291 case DRXK_AGC_CTRL_OFF:
2106 2292
2107 /* Disable If AGC DAC */ 2293 /* Disable If AGC DAC */
2108 CHK_ERROR(Read16_0(state, IQM_AF_STDBY__A, &data)); 2294 status = Read16_0(state, IQM_AF_STDBY__A, &data);
2295 if (status < 0)
2296 break;
2109 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY; 2297 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2110 CHK_ERROR(Write16_0(state, IQM_AF_STDBY__A, data)); 2298 status = Write16_0(state, IQM_AF_STDBY__A, data);
2299 if (status < 0)
2300 break;
2111 2301
2112 /* Disable SCU IF AGC loop */ 2302 /* Disable SCU IF AGC loop */
2113 CHK_ERROR(Read16_0(state, 2303 status = Read16_0(state, SCU_RAM_AGC_CONFIG__A, &data);
2114 SCU_RAM_AGC_CONFIG__A, &data)); 2304 if (status < 0)
2305 break;
2115 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; 2306 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2116 CHK_ERROR(Write16_0(state, 2307 status = Write16_0(state, SCU_RAM_AGC_CONFIG__A, data);
2117 SCU_RAM_AGC_CONFIG__A, data)); 2308 if (status < 0)
2309 break;
2118 break; 2310 break;
2119 } /* switch (agcSettingsIf->ctrlMode) */ 2311 } /* switch (agcSettingsIf->ctrlMode) */
2120 2312
2121 /* always set the top to support 2313 /* always set the top to support
2122 configurations without if-loop */ 2314 configurations without if-loop */
2123 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, 2315 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2124 pAgcCfg->top)); 2316 if (status < 0)
2317 break;
2125 2318
2126 2319
2127 } while (0); 2320 } while (0);
@@ -2161,8 +2354,9 @@ static int GetQAMSignalToNoise(struct drxk_state *state,
2161 u32 qamSlMer = 0; /* QAM MER */ 2354 u32 qamSlMer = 0; /* QAM MER */
2162 2355
2163 /* get the register value needed for MER */ 2356 /* get the register value needed for MER */
2164 CHK_ERROR(Read16_0 2357 status = Read16_0(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2165 (state, QAM_SL_ERR_POWER__A, &qamSlErrPower)); 2358 if (status < 0)
2359 break;
2166 2360
2167 switch (state->param.u.qam.modulation) { 2361 switch (state->param.u.qam.modulation) {
2168 case QAM_16: 2362 case QAM_16:
@@ -2212,30 +2406,36 @@ static int GetDVBTSignalToNoise(struct drxk_state *state,
2212 u16 transmissionParams = 0; 2406 u16 transmissionParams = 0;
2213 2407
2214 do { 2408 do {
2215 CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, 2409 status = Read16_0(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2216 &EqRegTdTpsPwrOfs)); 2410 if (status < 0)
2217 CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, 2411 break;
2218 &EqRegTdReqSmbCnt)); 2412 status = Read16_0(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2219 CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, 2413 if (status < 0)
2220 &EqRegTdSqrErrExp)); 2414 break;
2221 CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, 2415 status = Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2222 &regData)); 2416 if (status < 0)
2417 break;
2418 status = Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2419 if (status < 0)
2420 break;
2223 /* Extend SQR_ERR_I operational range */ 2421 /* Extend SQR_ERR_I operational range */
2224 EqRegTdSqrErrI = (u32) regData; 2422 EqRegTdSqrErrI = (u32) regData;
2225 if ((EqRegTdSqrErrExp > 11) && 2423 if ((EqRegTdSqrErrExp > 11) &&
2226 (EqRegTdSqrErrI < 0x00000FFFUL)) { 2424 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2227 EqRegTdSqrErrI += 0x00010000UL; 2425 EqRegTdSqrErrI += 0x00010000UL;
2228 } 2426 }
2229 CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, 2427 status = Read16_0(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2230 &regData)); 2428 if (status < 0)
2429 break;
2231 /* Extend SQR_ERR_Q operational range */ 2430 /* Extend SQR_ERR_Q operational range */
2232 EqRegTdSqrErrQ = (u32) regData; 2431 EqRegTdSqrErrQ = (u32) regData;
2233 if ((EqRegTdSqrErrExp > 11) && 2432 if ((EqRegTdSqrErrExp > 11) &&
2234 (EqRegTdSqrErrQ < 0x00000FFFUL)) 2433 (EqRegTdSqrErrQ < 0x00000FFFUL))
2235 EqRegTdSqrErrQ += 0x00010000UL; 2434 EqRegTdSqrErrQ += 0x00010000UL;
2236 2435
2237 CHK_ERROR(Read16_0(state, OFDM_SC_RA_RAM_OP_PARAM__A, 2436 status = Read16_0(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2238 &transmissionParams)); 2437 if (status < 0)
2438 break;
2239 2439
2240 /* Check input data for MER */ 2440 /* Check input data for MER */
2241 2441
@@ -2336,13 +2536,17 @@ static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2336 u32 SignalToNoiseRel; 2536 u32 SignalToNoiseRel;
2337 u32 BERQuality; 2537 u32 BERQuality;
2338 2538
2339 CHK_ERROR(GetDVBTSignalToNoise(state, &SignalToNoise)); 2539 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2340 CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_CONST__A, 2540 if (status < 0)
2341 &Constellation)); 2541 break;
2542 status = Read16_0(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2543 if (status < 0)
2544 break;
2342 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; 2545 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2343 2546
2344 CHK_ERROR(Read16_0(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, 2547 status = Read16_0(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2345 &CodeRate)); 2548 if (status < 0)
2549 break;
2346 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; 2550 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2347 2551
2348 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || 2552 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
@@ -2373,7 +2577,9 @@ static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2373 u32 BERQuality = 100; 2577 u32 BERQuality = 100;
2374 u32 SignalToNoiseRel = 0; 2578 u32 SignalToNoiseRel = 0;
2375 2579
2376 CHK_ERROR(GetQAMSignalToNoise(state, &SignalToNoise)); 2580 status = GetQAMSignalToNoise(state, &SignalToNoise);
2581 if (status < 0)
2582 break;
2377 2583
2378 switch (state->param.u.qam.modulation) { 2584 switch (state->param.u.qam.modulation) {
2379 case QAM_16: 2585 case QAM_16:
@@ -2444,17 +2650,22 @@ static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2444 return -1; 2650 return -1;
2445 2651
2446 do { 2652 do {
2447 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, 2653 status = Write16_0(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2448 SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY)); 2654 if (status < 0)
2655 break;
2449 if (bEnableBridge) { 2656 if (bEnableBridge) {
2450 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, 2657 status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2451 SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED)); 2658 if (status < 0)
2659 break;
2452 } else { 2660 } else {
2453 CHK_ERROR(Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, 2661 status = Write16_0(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2454 SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN)); 2662 if (status < 0)
2663 break;
2455 } 2664 }
2456 2665
2457 CHK_ERROR(HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0)); 2666 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2667 if (status < 0)
2668 break;
2458 } while (0); 2669 } while (0);
2459 return status; 2670 return status;
2460} 2671}
@@ -2483,20 +2694,30 @@ static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2483 2694
2484 mutex_lock(&state->mutex); 2695 mutex_lock(&state->mutex);
2485 do { 2696 do {
2486 CHK_ERROR(Write16_0 2697 status = Write16_0(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2487 (state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT)); 2698 if (status < 0)
2488 CHK_ERROR(Write16_0(state, SIO_BL_TGT_HDR__A, blockbank)); 2699 break;
2489 CHK_ERROR(Write16_0(state, SIO_BL_TGT_ADDR__A, offset)); 2700 status = Write16_0(state, SIO_BL_TGT_HDR__A, blockbank);
2490 CHK_ERROR(Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset)); 2701 if (status < 0)
2491 CHK_ERROR(Write16_0 2702 break;
2492 (state, SIO_BL_SRC_LEN__A, nrOfElements)); 2703 status = Write16_0(state, SIO_BL_TGT_ADDR__A, offset);
2493 CHK_ERROR(Write16_0 2704 if (status < 0)
2494 (state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON)); 2705 break;
2706 status = Write16_0(state, SIO_BL_SRC_ADDR__A, romOffset);
2707 if (status < 0)
2708 break;
2709 status = Write16_0(state, SIO_BL_SRC_LEN__A, nrOfElements);
2710 if (status < 0)
2711 break;
2712 status = Write16_0(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2713 if (status < 0)
2714 break;
2495 2715
2496 end = jiffies + msecs_to_jiffies(timeOut); 2716 end = jiffies + msecs_to_jiffies(timeOut);
2497 do { 2717 do {
2498 CHK_ERROR(Read16_0 2718 status = Read16_0(state, SIO_BL_STATUS__A, &blStatus);
2499 (state, SIO_BL_STATUS__A, &blStatus)); 2719 if (status < 0)
2720 break;
2500 } while ((blStatus == 0x1) && time_is_after_jiffies(end)); 2721 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2501 if (blStatus == 0x1) { 2722 if (blStatus == 0x1) {
2502 printk(KERN_ERR "SIO not ready\n"); 2723 printk(KERN_ERR "SIO not ready\n");
@@ -2516,18 +2737,27 @@ static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2516 2737
2517 do { 2738 do {
2518 /* Start measurement */ 2739 /* Start measurement */
2519 CHK_ERROR(Write16_0(state, IQM_AF_COMM_EXEC__A, 2740 status = Write16_0(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2520 IQM_AF_COMM_EXEC_ACTIVE)); 2741 if (status < 0)
2521 CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 1)); 2742 break;
2743 status = Write16_0(state, IQM_AF_START_LOCK__A, 1);
2744 if (status < 0)
2745 break;
2522 2746
2523 *count = 0; 2747 *count = 0;
2524 CHK_ERROR(Read16_0(state, IQM_AF_PHASE0__A, &data)); 2748 status = Read16_0(state, IQM_AF_PHASE0__A, &data);
2749 if (status < 0)
2750 break;
2525 if (data == 127) 2751 if (data == 127)
2526 *count = *count + 1; 2752 *count = *count + 1;
2527 CHK_ERROR(Read16_0(state, IQM_AF_PHASE1__A, &data)); 2753 status = Read16_0(state, IQM_AF_PHASE1__A, &data);
2754 if (status < 0)
2755 break;
2528 if (data == 127) 2756 if (data == 127)
2529 *count = *count + 1; 2757 *count = *count + 1;
2530 CHK_ERROR(Read16_0(state, IQM_AF_PHASE2__A, &data)); 2758 status = Read16_0(state, IQM_AF_PHASE2__A, &data);
2759 if (status < 0)
2760 break;
2531 if (data == 127) 2761 if (data == 127)
2532 *count = *count + 1; 2762 *count = *count + 1;
2533 } while (0); 2763 } while (0);
@@ -2540,14 +2770,17 @@ static int ADCSynchronization(struct drxk_state *state)
2540 int status; 2770 int status;
2541 2771
2542 do { 2772 do {
2543 CHK_ERROR(ADCSyncMeasurement(state, &count)); 2773 status = ADCSyncMeasurement(state, &count);
2774 if (status < 0)
2775 break;
2544 2776
2545 if (count == 1) { 2777 if (count == 1) {
2546 /* Try sampling on a diffrent edge */ 2778 /* Try sampling on a diffrent edge */
2547 u16 clkNeg = 0; 2779 u16 clkNeg = 0;
2548 2780
2549 CHK_ERROR(Read16_0 2781 status = Read16_0(state, IQM_AF_CLKNEG__A, &clkNeg);
2550 (state, IQM_AF_CLKNEG__A, &clkNeg)); 2782 if (status < 0)
2783 break;
2551 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == 2784 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2552 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { 2785 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2553 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); 2786 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
@@ -2558,9 +2791,12 @@ static int ADCSynchronization(struct drxk_state *state)
2558 clkNeg |= 2791 clkNeg |=
2559 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; 2792 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2560 } 2793 }
2561 CHK_ERROR(Write16_0 2794 status = Write16_0(state, IQM_AF_CLKNEG__A, clkNeg);
2562 (state, IQM_AF_CLKNEG__A, clkNeg)); 2795 if (status < 0)
2563 CHK_ERROR(ADCSyncMeasurement(state, &count)); 2796 break;
2797 status = ADCSyncMeasurement(state, &count);
2798 if (status < 0)
2799 break;
2564 } 2800 }
2565 2801
2566 if (count < 2) 2802 if (count < 2)
@@ -2669,7 +2905,9 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
2669 kiInnergainMin = (u16) -1030; 2905 kiInnergainMin = (u16) -1030;
2670 } else 2906 } else
2671 status = -1; 2907 status = -1;
2672 CHK_ERROR((status)); 2908 status = (status);
2909 if (status < 0)
2910 break;
2673 if (IsQAM(state)) { 2911 if (IsQAM(state)) {
2674 ifIaccuHiTgtMax = 0x2380; 2912 ifIaccuHiTgtMax = 0x2380;
2675 ifIaccuHiTgt = 0x2380; 2913 ifIaccuHiTgt = 0x2380;
@@ -2687,77 +2925,129 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
2687 fastClpCtrlDelay = 2925 fastClpCtrlDelay =
2688 state->m_dvbtIfAgcCfg.FastClipCtrlDelay; 2926 state->m_dvbtIfAgcCfg.FastClipCtrlDelay;
2689 } 2927 }
2690 CHK_ERROR(Write16_0 2928 status = Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
2691 (state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 2929 if (status < 0)
2692 fastClpCtrlDelay)); 2930 break;
2693 2931
2694 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, 2932 status = Write16_0(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
2695 clpCtrlMode)); 2933 if (status < 0)
2696 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, 2934 break;
2697 ingainTgt)); 2935 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
2698 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, 2936 if (status < 0)
2699 ingainTgtMin)); 2937 break;
2700 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, 2938 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
2701 ingainTgtMax)); 2939 if (status < 0)
2702 CHK_ERROR(Write16_0 2940 break;
2703 (state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, 2941 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
2704 ifIaccuHiTgtMin)); 2942 if (status < 0)
2705 CHK_ERROR(Write16_0 2943 break;
2706 (state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 2944 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
2707 ifIaccuHiTgtMax)); 2945 if (status < 0)
2708 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0)); 2946 break;
2709 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0)); 2947 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
2710 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0)); 2948 if (status < 0)
2711 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0)); 2949 break;
2712 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, 2950 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
2713 clpSumMax)); 2951 if (status < 0)
2714 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, 2952 break;
2715 snsSumMax)); 2953 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
2716 2954 if (status < 0)
2717 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, 2955 break;
2718 kiInnergainMin)); 2956 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
2719 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 2957 if (status < 0)
2720 ifIaccuHiTgt)); 2958 break;
2721 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, 2959 status = Write16_0(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
2722 clpCyclen)); 2960 if (status < 0)
2723 2961 break;
2724 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 2962 status = Write16_0(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
2725 1023)); 2963 if (status < 0)
2726 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, 2964 break;
2727 (u16) -1023)); 2965 status = Write16_0(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
2728 CHK_ERROR(Write16_0 2966 if (status < 0)
2729 (state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50)); 2967 break;
2730 2968
2731 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 2969 status = Write16_0(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
2732 20)); 2970 if (status < 0)
2733 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, 2971 break;
2734 clpSumMin)); 2972 status = Write16_0(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
2735 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, 2973 if (status < 0)
2736 snsSumMin)); 2974 break;
2737 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, 2975 status = Write16_0(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
2738 clpDirTo)); 2976 if (status < 0)
2739 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, 2977 break;
2740 snsDirTo)); 2978
2741 CHK_ERROR(Write16_0 2979 status = Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
2742 (state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff)); 2980 if (status < 0)
2743 CHK_ERROR(Write16_0 2981 break;
2744 (state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0)); 2982 status = Write16_0(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
2745 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117)); 2983 if (status < 0)
2746 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657)); 2984 break;
2747 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0)); 2985 status = Write16_0(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
2748 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0)); 2986 if (status < 0)
2749 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0)); 2987 break;
2750 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1)); 2988
2751 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0)); 2989 status = Write16_0(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
2752 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0)); 2990 if (status < 0)
2753 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0)); 2991 break;
2754 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1)); 2992 status = Write16_0(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
2755 CHK_ERROR(Write16_0 2993 if (status < 0)
2756 (state, SCU_RAM_AGC_SNS_CYCLEN__A, 500)); 2994 break;
2757 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500)); 2995 status = Write16_0(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
2996 if (status < 0)
2997 break;
2998 status = Write16_0(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
2999 if (status < 0)
3000 break;
3001 status = Write16_0(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3002 if (status < 0)
3003 break;
3004 status = Write16_0(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3005 if (status < 0)
3006 break;
3007 status = Write16_0(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3008 if (status < 0)
3009 break;
3010 status = Write16_0(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3011 if (status < 0)
3012 break;
3013 status = Write16_0(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3014 if (status < 0)
3015 break;
3016 status = Write16_0(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3017 if (status < 0)
3018 break;
3019 status = Write16_0(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3020 if (status < 0)
3021 break;
3022 status = Write16_0(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3023 if (status < 0)
3024 break;
3025 status = Write16_0(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3026 if (status < 0)
3027 break;
3028 status = Write16_0(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3029 if (status < 0)
3030 break;
3031 status = Write16_0(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3032 if (status < 0)
3033 break;
3034 status = Write16_0(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3035 if (status < 0)
3036 break;
3037 status = Write16_0(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3038 if (status < 0)
3039 break;
3040 status = Write16_0(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3041 if (status < 0)
3042 break;
3043 status = Write16_0(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3044 if (status < 0)
3045 break;
2758 3046
2759 /* Initialize inner-loop KI gain factors */ 3047 /* Initialize inner-loop KI gain factors */
2760 CHK_ERROR(Read16_0(state, SCU_RAM_AGC_KI__A, &data)); 3048 status = Read16_0(state, SCU_RAM_AGC_KI__A, &data);
3049 if (status < 0)
3050 break;
2761 if (IsQAM(state)) { 3051 if (IsQAM(state)) {
2762 data = 0x0657; 3052 data = 0x0657;
2763 data &= ~SCU_RAM_AGC_KI_RF__M; 3053 data &= ~SCU_RAM_AGC_KI_RF__M;
@@ -2765,7 +3055,9 @@ static int InitAGC(struct drxk_state *state, bool isDTV)
2765 data &= ~SCU_RAM_AGC_KI_IF__M; 3055 data &= ~SCU_RAM_AGC_KI_IF__M;
2766 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B); 3056 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
2767 } 3057 }
2768 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_KI__A, data)); 3058 status = Write16_0(state, SCU_RAM_AGC_KI__A, data);
3059 if (status < 0)
3060 break;
2769 } while (0); 3061 } while (0);
2770 return status; 3062 return status;
2771} 3063}
@@ -2776,13 +3068,13 @@ static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
2776 3068
2777 do { 3069 do {
2778 if (packetErr == NULL) { 3070 if (packetErr == NULL) {
2779 CHK_ERROR(Write16_0(state, 3071 status = Write16_0(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
2780 SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 3072 if (status < 0)
2781 0)); 3073 break;
2782 } else { 3074 } else {
2783 CHK_ERROR(Read16_0(state, 3075 status = Read16_0(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
2784 SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 3076 if (status < 0)
2785 packetErr)); 3077 break;
2786 } 3078 }
2787 } while (0); 3079 } while (0);
2788 return status; 3080 return status;
@@ -2905,7 +3197,9 @@ static int PowerUpDVBT(struct drxk_state *state)
2905 int status; 3197 int status;
2906 3198
2907 do { 3199 do {
2908 CHK_ERROR(CtrlPowerMode(state, &powerMode)); 3200 status = CtrlPowerMode(state, &powerMode);
3201 if (status < 0)
3202 break;
2909 } while (0); 3203 } while (0);
2910 return status; 3204 return status;
2911} 3205}
@@ -2947,8 +3241,9 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
2947 int status; 3241 int status;
2948 3242
2949 do { 3243 do {
2950 CHK_ERROR(Read16_0 3244 status = Read16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
2951 (state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data)); 3245 if (status < 0)
3246 break;
2952 3247
2953 switch (echoThres->fftMode) { 3248 switch (echoThres->fftMode) {
2954 case DRX_FFTMODE_2K: 3249 case DRX_FFTMODE_2K:
@@ -2970,8 +3265,9 @@ static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
2970 break; 3265 break;
2971 } 3266 }
2972 3267
2973 CHK_ERROR(Write16_0 3268 status = Write16_0(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
2974 (state, OFDM_SC_RA_RAM_ECHO_THRES__A, data)); 3269 if (status < 0)
3270 break;
2975 } while (0); 3271 } while (0);
2976 3272
2977 return status; 3273 return status;
@@ -3015,12 +3311,21 @@ static int DVBTActivatePresets(struct drxk_state *state)
3015 do { 3311 do {
3016 bool setincenable = false; 3312 bool setincenable = false;
3017 bool setfrenable = true; 3313 bool setfrenable = true;
3018 CHK_ERROR(DVBTCtrlSetIncEnable(state, &setincenable)); 3314 status = DVBTCtrlSetIncEnable(state, &setincenable);
3019 CHK_ERROR(DVBTCtrlSetFrEnable(state, &setfrenable)); 3315 if (status < 0)
3020 CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres2k)); 3316 break;
3021 CHK_ERROR(DVBTCtrlSetEchoThreshold(state, &echoThres8k)); 3317 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3022 CHK_ERROR(Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, 3318 if (status < 0)
3023 state->m_dvbtIfAgcCfg.IngainTgtMax)); 3319 break;
3320 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3321 if (status < 0)
3322 break;
3323 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3324 if (status < 0)
3325 break;
3326 status = Write16_0(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3327 if (status < 0)
3328 break;
3024 } while (0); 3329 } while (0);
3025 3330
3026 return status; 3331 return status;
@@ -3049,128 +3354,182 @@ static int SetDVBTStandard(struct drxk_state *state,
3049 /* added antenna switch */ 3354 /* added antenna switch */
3050 SwitchAntennaToDVBT(state); 3355 SwitchAntennaToDVBT(state);
3051 /* send OFDM reset command */ 3356 /* send OFDM reset command */
3052 CHK_ERROR(scu_command 3357 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3053 (state, 3358 if (status < 0)
3054 SCU_RAM_COMMAND_STANDARD_OFDM | 3359 break;
3055 SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1,
3056 &cmdResult));
3057 3360
3058 /* send OFDM setenv command */ 3361 /* send OFDM setenv command */
3059 CHK_ERROR(scu_command 3362 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3060 (state, 3363 if (status < 0)
3061 SCU_RAM_COMMAND_STANDARD_OFDM | 3364 break;
3062 SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1,
3063 &cmdResult));
3064 3365
3065 /* reset datapath for OFDM, processors first */ 3366 /* reset datapath for OFDM, processors first */
3066 CHK_ERROR(Write16_0 3367 status = Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3067 (state, OFDM_SC_COMM_EXEC__A, 3368 if (status < 0)
3068 OFDM_SC_COMM_EXEC_STOP)); 3369 break;
3069 CHK_ERROR(Write16_0 3370 status = Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3070 (state, OFDM_LC_COMM_EXEC__A, 3371 if (status < 0)
3071 OFDM_LC_COMM_EXEC_STOP)); 3372 break;
3072 CHK_ERROR(Write16_0 3373 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3073 (state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); 3374 if (status < 0)
3375 break;
3074 3376
3075 /* IQM setup */ 3377 /* IQM setup */
3076 /* synchronize on ofdstate->m_festart */ 3378 /* synchronize on ofdstate->m_festart */
3077 CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 1)); 3379 status = Write16_0(state, IQM_AF_UPD_SEL__A, 1);
3380 if (status < 0)
3381 break;
3078 /* window size for clipping ADC detection */ 3382 /* window size for clipping ADC detection */
3079 CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); 3383 status = Write16_0(state, IQM_AF_CLP_LEN__A, 0);
3384 if (status < 0)
3385 break;
3080 /* window size for for sense pre-SAW detection */ 3386 /* window size for for sense pre-SAW detection */
3081 CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); 3387 status = Write16_0(state, IQM_AF_SNS_LEN__A, 0);
3388 if (status < 0)
3389 break;
3082 /* sense threshold for sense pre-SAW detection */ 3390 /* sense threshold for sense pre-SAW detection */
3083 CHK_ERROR(Write16_0 3391 status = Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3084 (state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); 3392 if (status < 0)
3085 CHK_ERROR(SetIqmAf(state, true)); 3393 break;
3394 status = SetIqmAf(state, true);
3395 if (status < 0)
3396 break;
3086 3397
3087 CHK_ERROR(Write16_0(state, IQM_AF_AGC_RF__A, 0)); 3398 status = Write16_0(state, IQM_AF_AGC_RF__A, 0);
3399 if (status < 0)
3400 break;
3088 3401
3089 /* Impulse noise cruncher setup */ 3402 /* Impulse noise cruncher setup */
3090 CHK_ERROR(Write16_0(state, IQM_AF_INC_LCT__A, 0)); /* crunch in IQM_CF */ 3403 status = Write16_0(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3091 CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); /* detect in IQM_CF */ 3404 if (status < 0)
3092 CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 3)); /* peak detector window length */ 3405 break;
3406 status = Write16_0(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3407 if (status < 0)
3408 break;
3409 status = Write16_0(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3410 if (status < 0)
3411 break;
3093 3412
3094 CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 16)); 3413 status = Write16_0(state, IQM_RC_STRETCH__A, 16);
3095 CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 0x4)); /* enable output 2 */ 3414 if (status < 0)
3096 CHK_ERROR(Write16_0(state, IQM_CF_DS_ENA__A, 0x4)); /* decimate output 2 */ 3415 break;
3097 CHK_ERROR(Write16_0(state, IQM_CF_SCALE__A, 1600)); 3416 status = Write16_0(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3098 CHK_ERROR(Write16_0(state, IQM_CF_SCALE_SH__A, 0)); 3417 if (status < 0)
3418 break;
3419 status = Write16_0(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3420 if (status < 0)
3421 break;
3422 status = Write16_0(state, IQM_CF_SCALE__A, 1600);
3423 if (status < 0)
3424 break;
3425 status = Write16_0(state, IQM_CF_SCALE_SH__A, 0);
3426 if (status < 0)
3427 break;
3099 3428
3100 /* virtual clipping threshold for clipping ADC detection */ 3429 /* virtual clipping threshold for clipping ADC detection */
3101 CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); 3430 status = Write16_0(state, IQM_AF_CLP_TH__A, 448);
3102 CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 495)); /* crunching threshold */ 3431 if (status < 0)
3432 break;
3433 status = Write16_0(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3434 if (status < 0)
3435 break;
3103 3436
3104 CHK_ERROR(BLChainCmd(state, 3437 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3105 DRXK_BL_ROM_OFFSET_TAPS_DVBT, 3438 if (status < 0)
3106 DRXK_BLCC_NR_ELEMENTS_TAPS, 3439 break;
3107 DRXK_BLC_TIMEOUT));
3108 3440
3109 CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 2)); /* peak detector threshold */ 3441 status = Write16_0(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3110 CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2)); 3442 if (status < 0)
3443 break;
3444 status = Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 2);
3445 if (status < 0)
3446 break;
3111 /* enable power measurement interrupt */ 3447 /* enable power measurement interrupt */
3112 CHK_ERROR(Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1)); 3448 status = Write16_0(state, IQM_CF_COMM_INT_MSK__A, 1);
3113 CHK_ERROR(Write16_0 3449 if (status < 0)
3114 (state, IQM_COMM_EXEC__A, 3450 break;
3115 IQM_COMM_EXEC_B_ACTIVE)); 3451 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3452 if (status < 0)
3453 break;
3116 3454
3117 /* IQM will not be reset from here, sync ADC and update/init AGC */ 3455 /* IQM will not be reset from here, sync ADC and update/init AGC */
3118 CHK_ERROR(ADCSynchronization(state)); 3456 status = ADCSynchronization(state);
3119 CHK_ERROR(SetPreSaw(state, &state->m_dvbtPreSawCfg)); 3457 if (status < 0)
3458 break;
3459 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3460 if (status < 0)
3461 break;
3120 3462
3121 /* Halt SCU to enable safe non-atomic accesses */ 3463 /* Halt SCU to enable safe non-atomic accesses */
3122 CHK_ERROR(Write16_0 3464 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3123 (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); 3465 if (status < 0)
3466 break;
3124 3467
3125 CHK_ERROR(SetAgcRf(state, &state->m_dvbtRfAgcCfg, true)); 3468 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3126 CHK_ERROR(SetAgcIf(state, &state->m_dvbtIfAgcCfg, true)); 3469 if (status < 0)
3470 break;
3471 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3472 if (status < 0)
3473 break;
3127 3474
3128 /* Set Noise Estimation notch width and enable DC fix */ 3475 /* Set Noise Estimation notch width and enable DC fix */
3129 CHK_ERROR(Read16_0 3476 status = Read16_0(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3130 (state, OFDM_SC_RA_RAM_CONFIG__A, &data)); 3477 if (status < 0)
3478 break;
3131 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M; 3479 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3132 CHK_ERROR(Write16_0 3480 status = Write16_0(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3133 (state, OFDM_SC_RA_RAM_CONFIG__A, data)); 3481 if (status < 0)
3482 break;
3134 3483
3135 /* Activate SCU to enable SCU commands */ 3484 /* Activate SCU to enable SCU commands */
3136 CHK_ERROR(Write16_0 3485 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3137 (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); 3486 if (status < 0)
3487 break;
3138 3488
3139 if (!state->m_DRXK_A3_ROM_CODE) { 3489 if (!state->m_DRXK_A3_ROM_CODE) {
3140 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ 3490 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3141 CHK_ERROR(Write16_0 3491 status = Write16_0(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3142 (state, 3492 if (status < 0)
3143 SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 3493 break;
3144 state->
3145 m_dvbtIfAgcCfg.FastClipCtrlDelay));
3146 } 3494 }
3147 3495
3148 /* OFDM_SC setup */ 3496 /* OFDM_SC setup */
3149#ifdef COMPILE_FOR_NONRT 3497#ifdef COMPILE_FOR_NONRT
3150 CHK_ERROR(Write16_0 3498 status = Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3151 (state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1)); 3499 if (status < 0)
3152 CHK_ERROR(Write16_0 3500 break;
3153 (state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2)); 3501 status = Write16_0(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3502 if (status < 0)
3503 break;
3154#endif 3504#endif
3155 3505
3156 /* FEC setup */ 3506 /* FEC setup */
3157 CHK_ERROR(Write16_0(state, FEC_DI_INPUT_CTL__A, 1)); /* OFDM input */ 3507 status = Write16_0(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3508 if (status < 0)
3509 break;
3158 3510
3159 3511
3160#ifdef COMPILE_FOR_NONRT 3512#ifdef COMPILE_FOR_NONRT
3161 CHK_ERROR(Write16_0 3513 status = Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3162 (state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400)); 3514 if (status < 0)
3515 break;
3163#else 3516#else
3164 CHK_ERROR(Write16_0 3517 status = Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3165 (state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000)); 3518 if (status < 0)
3519 break;
3166#endif 3520#endif
3167 CHK_ERROR(Write16_0 3521 status = Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3168 (state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001)); 3522 if (status < 0)
3523 break;
3169 3524
3170 /* Setup MPEG bus */ 3525 /* Setup MPEG bus */
3171 CHK_ERROR(MPEGTSDtoSetup(state, OM_DVBT)); 3526 status = MPEGTSDtoSetup(state, OM_DVBT);
3527 if (status < 0)
3528 break;
3172 /* Set DVBT Presets */ 3529 /* Set DVBT Presets */
3173 CHK_ERROR(DVBTActivatePresets(state)); 3530 status = DVBTActivatePresets(state);
3531 if (status < 0)
3532 break;
3174 3533
3175 } while (0); 3534 } while (0);
3176 3535
@@ -3196,14 +3555,16 @@ static int DVBTStart(struct drxk_state *state)
3196 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ 3555 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3197 do { 3556 do {
3198 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; 3557 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3199 CHK_ERROR(DVBTScCommand 3558 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3200 (state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, 3559 if (status < 0)
3201 OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 3560 break;
3202 0, 0));
3203 /* Start FEC OC */ 3561 /* Start FEC OC */
3204 CHK_ERROR(MPEGTSStart(state)); 3562 status = MPEGTSStart(state);
3205 CHK_ERROR(Write16_0 3563 if (status < 0)
3206 (state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); 3564 break;
3565 status = Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3566 if (status < 0)
3567 break;
3207 } while (0); 3568 } while (0);
3208 return status; 3569 return status;
3209} 3570}
@@ -3230,29 +3591,28 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3230 3591
3231 /* printk(KERN_DEBUG "%s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */ 3592 /* printk(KERN_DEBUG "%s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */
3232 do { 3593 do {
3233 CHK_ERROR(scu_command 3594 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3234 (state, 3595 if (status < 0)
3235 SCU_RAM_COMMAND_STANDARD_OFDM | 3596 break;
3236 SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1,
3237 &cmdResult));
3238 3597
3239 /* Halt SCU to enable safe non-atomic accesses */ 3598 /* Halt SCU to enable safe non-atomic accesses */
3240 CHK_ERROR(Write16_0 3599 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3241 (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); 3600 if (status < 0)
3601 break;
3242 3602
3243 /* Stop processors */ 3603 /* Stop processors */
3244 CHK_ERROR(Write16_0 3604 status = Write16_0(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3245 (state, OFDM_SC_COMM_EXEC__A, 3605 if (status < 0)
3246 OFDM_SC_COMM_EXEC_STOP)); 3606 break;
3247 CHK_ERROR(Write16_0 3607 status = Write16_0(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3248 (state, OFDM_LC_COMM_EXEC__A, 3608 if (status < 0)
3249 OFDM_LC_COMM_EXEC_STOP)); 3609 break;
3250 3610
3251 /* Mandatory fix, always stop CP, required to set spl offset back to 3611 /* Mandatory fix, always stop CP, required to set spl offset back to
3252 hardware default (is set to 0 by ucode during pilot detection */ 3612 hardware default (is set to 0 by ucode during pilot detection */
3253 CHK_ERROR(Write16_0 3613 status = Write16_0(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3254 (state, OFDM_CP_COMM_EXEC__A, 3614 if (status < 0)
3255 OFDM_CP_COMM_EXEC_STOP)); 3615 break;
3256 3616
3257 /*== Write channel settings to device =====================================*/ 3617 /*== Write channel settings to device =====================================*/
3258 3618
@@ -3363,9 +3723,9 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3363#else 3723#else
3364 /* Set Priorty high */ 3724 /* Set Priorty high */
3365 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; 3725 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3366 CHK_ERROR(Write16_0 3726 status = Write16_0(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3367 (state, OFDM_EC_SB_PRIOR__A, 3727 if (status < 0)
3368 OFDM_EC_SB_PRIOR_HI)); 3728 break;
3369#endif 3729#endif
3370 3730
3371 /* coderate */ 3731 /* coderate */
@@ -3407,75 +3767,60 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3407 case BANDWIDTH_AUTO: 3767 case BANDWIDTH_AUTO:
3408 case BANDWIDTH_8_MHZ: 3768 case BANDWIDTH_8_MHZ:
3409 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; 3769 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3410 CHK_ERROR(Write16_0 3770 status = Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3411 (state, 3771 if (status < 0)
3412 OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3772 break;
3413 3052));
3414 /* cochannel protection for PAL 8 MHz */ 3773 /* cochannel protection for PAL 8 MHz */
3415 CHK_ERROR(Write16_0 3774 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3416 (state, 3775 if (status < 0)
3417 OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3776 break;
3418 7)); 3777 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3419 CHK_ERROR(Write16_0 3778 if (status < 0)
3420 (state, 3779 break;
3421 OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3780 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3422 7)); 3781 if (status < 0)
3423 CHK_ERROR(Write16_0 3782 break;
3424 (state, 3783 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3425 OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3784 if (status < 0)
3426 7)); 3785 break;
3427 CHK_ERROR(Write16_0
3428 (state,
3429 OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3430 1));
3431 break; 3786 break;
3432 case BANDWIDTH_7_MHZ: 3787 case BANDWIDTH_7_MHZ:
3433 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; 3788 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3434 CHK_ERROR(Write16_0 3789 status = Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3435 (state, 3790 if (status < 0)
3436 OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3791 break;
3437 3491));
3438 /* cochannel protection for PAL 7 MHz */ 3792 /* cochannel protection for PAL 7 MHz */
3439 CHK_ERROR(Write16_0 3793 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3440 (state, 3794 if (status < 0)
3441 OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3795 break;
3442 8)); 3796 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3443 CHK_ERROR(Write16_0 3797 if (status < 0)
3444 (state, 3798 break;
3445 OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3799 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3446 8)); 3800 if (status < 0)
3447 CHK_ERROR(Write16_0 3801 break;
3448 (state, 3802 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3449 OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3803 if (status < 0)
3450 4)); 3804 break;
3451 CHK_ERROR(Write16_0
3452 (state,
3453 OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3454 1));
3455 break; 3805 break;
3456 case BANDWIDTH_6_MHZ: 3806 case BANDWIDTH_6_MHZ:
3457 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; 3807 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3458 CHK_ERROR(Write16_0 3808 status = Write16_0(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3459 (state, 3809 if (status < 0)
3460 OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3810 break;
3461 4073));
3462 /* cochannel protection for NTSC 6 MHz */ 3811 /* cochannel protection for NTSC 6 MHz */
3463 CHK_ERROR(Write16_0 3812 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3464 (state, 3813 if (status < 0)
3465 OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 3814 break;
3466 19)); 3815 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3467 CHK_ERROR(Write16_0 3816 if (status < 0)
3468 (state, 3817 break;
3469 OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 3818 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3470 19)); 3819 if (status < 0)
3471 CHK_ERROR(Write16_0 3820 break;
3472 (state, 3821 status = Write16_0(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3473 OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 3822 if (status < 0)
3474 14)); 3823 break;
3475 CHK_ERROR(Write16_0
3476 (state,
3477 OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3478 1));
3479 break; 3824 break;
3480 } 3825 }
3481 3826
@@ -3503,32 +3848,40 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3503 iqmRcRateOfs &= 3848 iqmRcRateOfs &=
3504 ((((u32) IQM_RC_RATE_OFS_HI__M) << 3849 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
3505 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); 3850 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
3506 CHK_ERROR(Write32 3851 status = Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs, 0);
3507 (state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs, 0)); 3852 if (status < 0)
3853 break;
3508 3854
3509 /* Bandwidth setting done */ 3855 /* Bandwidth setting done */
3510 3856
3511 /* CHK_ERROR(DVBTSetFrequencyShift(demod, channel, tunerOffset)); */ 3857#if 0
3512 CHK_ERROR(SetFrequencyShifter 3858 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
3513 (state, IntermediateFreqkHz, tunerFreqOffset, 3859 if (status < 0)
3514 true)); 3860 break;
3861#endif
3862 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
3863 if (status < 0)
3864 break;
3515 3865
3516 /*== Start SC, write channel settings to SC ===============================*/ 3866 /*== Start SC, write channel settings to SC ===============================*/
3517 3867
3518 /* Activate SCU to enable SCU commands */ 3868 /* Activate SCU to enable SCU commands */
3519 CHK_ERROR(Write16_0 3869 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3520 (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); 3870 if (status < 0)
3871 break;
3521 3872
3522 /* Enable SC after setting all other parameters */ 3873 /* Enable SC after setting all other parameters */
3523 CHK_ERROR(Write16_0(state, OFDM_SC_COMM_STATE__A, 0)); 3874 status = Write16_0(state, OFDM_SC_COMM_STATE__A, 0);
3524 CHK_ERROR(Write16_0(state, OFDM_SC_COMM_EXEC__A, 1)); 3875 if (status < 0)
3876 break;
3877 status = Write16_0(state, OFDM_SC_COMM_EXEC__A, 1);
3878 if (status < 0)
3879 break;
3525 3880
3526 3881
3527 CHK_ERROR(scu_command 3882 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
3528 (state, 3883 if (status < 0)
3529 SCU_RAM_COMMAND_STANDARD_OFDM | 3884 break;
3530 SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1,
3531 &cmdResult));
3532 3885
3533 /* Write SC parameter registers, set all AUTO flags in operation mode */ 3886 /* Write SC parameter registers, set all AUTO flags in operation mode */
3534 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M | 3887 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
@@ -3540,8 +3893,9 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3540 DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, 3893 DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
3541 0, transmissionParams, param1, 0, 0, 0); 3894 0, transmissionParams, param1, 0, 0, 0);
3542 if (!state->m_DRXK_A3_ROM_CODE) 3895 if (!state->m_DRXK_A3_ROM_CODE)
3543 CHK_ERROR(DVBTCtrlSetSqiSpeed 3896 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
3544 (state, &state->m_sqiSpeed)); 3897 if (status < 0)
3898 break;
3545 3899
3546 } while (0); 3900 } while (0);
3547 3901
@@ -3600,7 +3954,9 @@ static int PowerUpQAM(struct drxk_state *state)
3600 int status = 0; 3954 int status = 0;
3601 3955
3602 do { 3956 do {
3603 CHK_ERROR(CtrlPowerMode(state, &powerMode)); 3957 status = CtrlPowerMode(state, &powerMode);
3958 if (status < 0)
3959 break;
3604 3960
3605 } while (0); 3961 } while (0);
3606 3962
@@ -3616,24 +3972,26 @@ static int PowerDownQAM(struct drxk_state *state)
3616 int status = 0; 3972 int status = 0;
3617 3973
3618 do { 3974 do {
3619 CHK_ERROR(Read16_0(state, SCU_COMM_EXEC__A, &data)); 3975 status = Read16_0(state, SCU_COMM_EXEC__A, &data);
3976 if (status < 0)
3977 break;
3620 if (data == SCU_COMM_EXEC_ACTIVE) { 3978 if (data == SCU_COMM_EXEC_ACTIVE) {
3621 /* 3979 /*
3622 STOP demodulator 3980 STOP demodulator
3623 QAM and HW blocks 3981 QAM and HW blocks
3624 */ 3982 */
3625 /* stop all comstate->m_exec */ 3983 /* stop all comstate->m_exec */
3626 CHK_ERROR(Write16_0 3984 status = Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
3627 (state, QAM_COMM_EXEC__A, 3985 if (status < 0)
3628 QAM_COMM_EXEC_STOP)); 3986 break;
3629 CHK_ERROR(scu_command 3987 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3630 (state, 3988 if (status < 0)
3631 SCU_RAM_COMMAND_STANDARD_QAM | 3989 break;
3632 SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL,
3633 1, &cmdResult));
3634 } 3990 }
3635 /* powerdown AFE */ 3991 /* powerdown AFE */
3636 CHK_ERROR(SetIqmAf(state, false)); 3992 status = SetIqmAf(state, false);
3993 if (status < 0)
3994 break;
3637 } while (0); 3995 } while (0);
3638 3996
3639 return status; 3997 return status;
@@ -3691,7 +4049,9 @@ static int SetQAMMeasurement(struct drxk_state *state,
3691 default: 4049 default:
3692 status = -EINVAL; 4050 status = -EINVAL;
3693 } 4051 }
3694 CHK_ERROR(status); 4052 status = status;
4053 if (status < 0)
4054 break;
3695 4055
3696 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ 4056 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
3697 fecBitsDesired *= 500; /* meas. period [ms] */ 4057 fecBitsDesired *= 500; /* meas. period [ms] */
@@ -3706,20 +4066,23 @@ static int SetQAMMeasurement(struct drxk_state *state,
3706 /* Divide by zero (though impossible) */ 4066 /* Divide by zero (though impossible) */
3707 status = -1; 4067 status = -1;
3708 } 4068 }
3709 CHK_ERROR(status); 4069 status = status;
4070 if (status < 0)
4071 break;
3710 fecRsPeriod = 4072 fecRsPeriod =
3711 ((u16) fecRsPeriodTotal + 4073 ((u16) fecRsPeriodTotal +
3712 (fecRsPrescale >> 1)) / fecRsPrescale; 4074 (fecRsPrescale >> 1)) / fecRsPrescale;
3713 4075
3714 /* write corresponding registers */ 4076 /* write corresponding registers */
3715 CHK_ERROR(Write16_0 4077 status = Write16_0(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
3716 (state, FEC_RS_MEASUREMENT_PERIOD__A, 4078 if (status < 0)
3717 fecRsPeriod)); 4079 break;
3718 CHK_ERROR(Write16_0 4080 status = Write16_0(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
3719 (state, FEC_RS_MEASUREMENT_PRESCALE__A, 4081 if (status < 0)
3720 fecRsPrescale)); 4082 break;
3721 CHK_ERROR(Write16_0 4083 status = Write16_0(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
3722 (state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod)); 4084 if (status < 0)
4085 break;
3723 4086
3724 } while (0); 4087 } while (0);
3725 4088
@@ -3736,112 +4099,178 @@ static int SetQAM16(struct drxk_state *state)
3736 do { 4099 do {
3737 /* QAM Equalizer Setup */ 4100 /* QAM Equalizer Setup */
3738 /* Equalizer */ 4101 /* Equalizer */
3739 CHK_ERROR(Write16_0 4102 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
3740 (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517)); 4103 if (status < 0)
3741 CHK_ERROR(Write16_0 4104 break;
3742 (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517)); 4105 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
3743 CHK_ERROR(Write16_0 4106 if (status < 0)
3744 (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517)); 4107 break;
3745 CHK_ERROR(Write16_0 4108 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
3746 (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517)); 4109 if (status < 0)
3747 CHK_ERROR(Write16_0 4110 break;
3748 (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517)); 4111 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
3749 CHK_ERROR(Write16_0 4112 if (status < 0)
3750 (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517)); 4113 break;
4114 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4115 if (status < 0)
4116 break;
4117 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4118 if (status < 0)
4119 break;
3751 /* Decision Feedback Equalizer */ 4120 /* Decision Feedback Equalizer */
3752 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2)); 4121 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 2);
3753 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2)); 4122 if (status < 0)
3754 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2)); 4123 break;
3755 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2)); 4124 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 2);
3756 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2)); 4125 if (status < 0)
3757 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); 4126 break;
4127 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 2);
4128 if (status < 0)
4129 break;
4130 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 2);
4131 if (status < 0)
4132 break;
4133 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 2);
4134 if (status < 0)
4135 break;
4136 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0);
4137 if (status < 0)
4138 break;
3758 4139
3759 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); 4140 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 5);
3760 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); 4141 if (status < 0)
3761 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); 4142 break;
4143 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 4);
4144 if (status < 0)
4145 break;
4146 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3);
4147 if (status < 0)
4148 break;
3762 4149
3763 /* QAM Slicer Settings */ 4150 /* QAM Slicer Settings */
3764 CHK_ERROR(Write16_0 4151 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
3765 (state, SCU_RAM_QAM_SL_SIG_POWER__A, 4152 if (status < 0)
3766 DRXK_QAM_SL_SIG_POWER_QAM16)); 4153 break;
3767 4154
3768 /* QAM Loop Controller Coeficients */ 4155 /* QAM Loop Controller Coeficients */
3769 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); 4156 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
3770 CHK_ERROR(Write16_0 4157 if (status < 0)
3771 (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); 4158 break;
3772 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); 4159 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
3773 CHK_ERROR(Write16_0 4160 if (status < 0)
3774 (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); 4161 break;
3775 CHK_ERROR(Write16_0 4162 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
3776 (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); 4163 if (status < 0)
3777 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); 4164 break;
3778 CHK_ERROR(Write16_0 4165 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
3779 (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); 4166 if (status < 0)
3780 CHK_ERROR(Write16_0 4167 break;
3781 (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); 4168 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
3782 4169 if (status < 0)
3783 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); 4170 break;
3784 CHK_ERROR(Write16_0 4171 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
3785 (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); 4172 if (status < 0)
3786 CHK_ERROR(Write16_0 4173 break;
3787 (state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); 4174 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
3788 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); 4175 if (status < 0)
3789 CHK_ERROR(Write16_0 4176 break;
3790 (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); 4177 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
3791 CHK_ERROR(Write16_0 4178 if (status < 0)
3792 (state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); 4179 break;
3793 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); 4180
3794 CHK_ERROR(Write16_0 4181 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
3795 (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); 4182 if (status < 0)
3796 CHK_ERROR(Write16_0 4183 break;
3797 (state, SCU_RAM_QAM_LC_CF_COARSE__A, 32)); 4184 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
3798 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); 4185 if (status < 0)
3799 CHK_ERROR(Write16_0 4186 break;
3800 (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); 4187 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
3801 CHK_ERROR(Write16_0 4188 if (status < 0)
3802 (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); 4189 break;
4190 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4191 if (status < 0)
4192 break;
4193 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4194 if (status < 0)
4195 break;
4196 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4197 if (status < 0)
4198 break;
4199 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4200 if (status < 0)
4201 break;
4202 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4203 if (status < 0)
4204 break;
4205 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4206 if (status < 0)
4207 break;
4208 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4209 if (status < 0)
4210 break;
4211 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4212 if (status < 0)
4213 break;
4214 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4215 if (status < 0)
4216 break;
3803 4217
3804 4218
3805 /* QAM State Machine (FSM) Thresholds */ 4219 /* QAM State Machine (FSM) Thresholds */
3806 4220
3807 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140)); 4221 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 140);
3808 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); 4222 if (status < 0)
3809 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95)); 4223 break;
3810 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120)); 4224 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50);
3811 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230)); 4225 if (status < 0)
3812 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105)); 4226 break;
4227 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4228 if (status < 0)
4229 break;
4230 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4231 if (status < 0)
4232 break;
4233 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4234 if (status < 0)
4235 break;
4236 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4237 if (status < 0)
4238 break;
3813 4239
3814 CHK_ERROR(Write16_0 4240 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
3815 (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); 4241 if (status < 0)
3816 CHK_ERROR(Write16_0 4242 break;
3817 (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); 4243 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
3818 CHK_ERROR(Write16_0 4244 if (status < 0)
3819 (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24)); 4245 break;
4246 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4247 if (status < 0)
4248 break;
3820 4249
3821 4250
3822 /* QAM FSM Tracking Parameters */ 4251 /* QAM FSM Tracking Parameters */
3823 4252
3824 CHK_ERROR(Write16_0 4253 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
3825 (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 4254 if (status < 0)
3826 (u16) 16)); 4255 break;
3827 CHK_ERROR(Write16_0 4256 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
3828 (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 4257 if (status < 0)
3829 (u16) 220)); 4258 break;
3830 CHK_ERROR(Write16_0 4259 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
3831 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 4260 if (status < 0)
3832 (u16) 25)); 4261 break;
3833 CHK_ERROR(Write16_0 4262 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
3834 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 4263 if (status < 0)
3835 (u16) 6)); 4264 break;
3836 CHK_ERROR(Write16_0 4265 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
3837 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 4266 if (status < 0)
3838 (u16) -24)); 4267 break;
3839 CHK_ERROR(Write16_0 4268 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
3840 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 4269 if (status < 0)
3841 (u16) -65)); 4270 break;
3842 CHK_ERROR(Write16_0 4271 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
3843 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, 4272 if (status < 0)
3844 (u16) -127)); 4273 break;
3845 } while (0); 4274 } while (0);
3846 4275
3847 return status; 4276 return status;
@@ -3861,116 +4290,182 @@ static int SetQAM32(struct drxk_state *state)
3861 do { 4290 do {
3862 /* QAM Equalizer Setup */ 4291 /* QAM Equalizer Setup */
3863 /* Equalizer */ 4292 /* Equalizer */
3864 CHK_ERROR(Write16_0 4293 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
3865 (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707)); 4294 if (status < 0)
3866 CHK_ERROR(Write16_0 4295 break;
3867 (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707)); 4296 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
3868 CHK_ERROR(Write16_0 4297 if (status < 0)
3869 (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707)); 4298 break;
3870 CHK_ERROR(Write16_0 4299 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
3871 (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707)); 4300 if (status < 0)
3872 CHK_ERROR(Write16_0 4301 break;
3873 (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707)); 4302 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
3874 CHK_ERROR(Write16_0 4303 if (status < 0)
3875 (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707)); 4304 break;
4305 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4306 if (status < 0)
4307 break;
4308 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4309 if (status < 0)
4310 break;
3876 4311
3877 /* Decision Feedback Equalizer */ 4312 /* Decision Feedback Equalizer */
3878 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3)); 4313 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 3);
3879 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3)); 4314 if (status < 0)
3880 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3)); 4315 break;
3881 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3)); 4316 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 3);
3882 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); 4317 if (status < 0)
3883 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); 4318 break;
4319 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 3);
4320 if (status < 0)
4321 break;
4322 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 3);
4323 if (status < 0)
4324 break;
4325 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3);
4326 if (status < 0)
4327 break;
4328 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0);
4329 if (status < 0)
4330 break;
3884 4331
3885 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); 4332 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 6);
3886 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); 4333 if (status < 0)
3887 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); 4334 break;
4335 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 5);
4336 if (status < 0)
4337 break;
4338 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3);
4339 if (status < 0)
4340 break;
3888 4341
3889 /* QAM Slicer Settings */ 4342 /* QAM Slicer Settings */
3890 4343
3891 CHK_ERROR(Write16_0 4344 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
3892 (state, SCU_RAM_QAM_SL_SIG_POWER__A, 4345 if (status < 0)
3893 DRXK_QAM_SL_SIG_POWER_QAM32)); 4346 break;
3894 4347
3895 4348
3896 /* QAM Loop Controller Coeficients */ 4349 /* QAM Loop Controller Coeficients */
3897 4350
3898 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); 4351 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
3899 CHK_ERROR(Write16_0 4352 if (status < 0)
3900 (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); 4353 break;
3901 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); 4354 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
3902 CHK_ERROR(Write16_0 4355 if (status < 0)
3903 (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); 4356 break;
3904 CHK_ERROR(Write16_0 4357 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
3905 (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); 4358 if (status < 0)
3906 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); 4359 break;
3907 CHK_ERROR(Write16_0 4360 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
3908 (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); 4361 if (status < 0)
3909 CHK_ERROR(Write16_0 4362 break;
3910 (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); 4363 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
3911 4364 if (status < 0)
3912 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); 4365 break;
3913 CHK_ERROR(Write16_0 4366 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
3914 (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20)); 4367 if (status < 0)
3915 CHK_ERROR(Write16_0 4368 break;
3916 (state, SCU_RAM_QAM_LC_CP_COARSE__A, 80)); 4369 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
3917 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); 4370 if (status < 0)
3918 CHK_ERROR(Write16_0 4371 break;
3919 (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20)); 4372 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
3920 CHK_ERROR(Write16_0 4373 if (status < 0)
3921 (state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); 4374 break;
3922 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); 4375
3923 CHK_ERROR(Write16_0 4376 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
3924 (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16)); 4377 if (status < 0)
3925 CHK_ERROR(Write16_0 4378 break;
3926 (state, SCU_RAM_QAM_LC_CF_COARSE__A, 16)); 4379 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
3927 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); 4380 if (status < 0)
3928 CHK_ERROR(Write16_0 4381 break;
3929 (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); 4382 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
3930 CHK_ERROR(Write16_0 4383 if (status < 0)
3931 (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); 4384 break;
4385 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4386 if (status < 0)
4387 break;
4388 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4389 if (status < 0)
4390 break;
4391 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4392 if (status < 0)
4393 break;
4394 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4395 if (status < 0)
4396 break;
4397 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4398 if (status < 0)
4399 break;
4400 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4401 if (status < 0)
4402 break;
4403 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4404 if (status < 0)
4405 break;
4406 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4407 if (status < 0)
4408 break;
4409 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4410 if (status < 0)
4411 break;
3932 4412
3933 4413
3934 /* QAM State Machine (FSM) Thresholds */ 4414 /* QAM State Machine (FSM) Thresholds */
3935 4415
3936 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90)); 4416 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 90);
3937 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50)); 4417 if (status < 0)
3938 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); 4418 break;
3939 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); 4419 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 50);
3940 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170)); 4420 if (status < 0)
3941 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); 4421 break;
4422 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4423 if (status < 0)
4424 break;
4425 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4426 if (status < 0)
4427 break;
4428 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4429 if (status < 0)
4430 break;
4431 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4432 if (status < 0)
4433 break;
3942 4434
3943 CHK_ERROR(Write16_0 4435 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
3944 (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); 4436 if (status < 0)
3945 CHK_ERROR(Write16_0 4437 break;
3946 (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); 4438 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
3947 CHK_ERROR(Write16_0 4439 if (status < 0)
3948 (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10)); 4440 break;
4441 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4442 if (status < 0)
4443 break;
3949 4444
3950 4445
3951 /* QAM FSM Tracking Parameters */ 4446 /* QAM FSM Tracking Parameters */
3952 4447
3953 CHK_ERROR(Write16_0 4448 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
3954 (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 4449 if (status < 0)
3955 (u16) 12)); 4450 break;
3956 CHK_ERROR(Write16_0 4451 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
3957 (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 4452 if (status < 0)
3958 (u16) 140)); 4453 break;
3959 CHK_ERROR(Write16_0 4454 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
3960 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 4455 if (status < 0)
3961 (u16) -8)); 4456 break;
3962 CHK_ERROR(Write16_0 4457 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
3963 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 4458 if (status < 0)
3964 (u16) -16)); 4459 break;
3965 CHK_ERROR(Write16_0 4460 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
3966 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 4461 if (status < 0)
3967 (u16) -26)); 4462 break;
3968 CHK_ERROR(Write16_0 4463 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
3969 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 4464 if (status < 0)
3970 (u16) -56)); 4465 break;
3971 CHK_ERROR(Write16_0 4466 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
3972 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, 4467 if (status < 0)
3973 (u16) -86)); 4468 break;
3974 } while (0); 4469 } while (0);
3975 4470
3976 return status; 4471 return status;
@@ -3990,115 +4485,181 @@ static int SetQAM64(struct drxk_state *state)
3990 do { 4485 do {
3991 /* QAM Equalizer Setup */ 4486 /* QAM Equalizer Setup */
3992 /* Equalizer */ 4487 /* Equalizer */
3993 CHK_ERROR(Write16_0 4488 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
3994 (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336)); 4489 if (status < 0)
3995 CHK_ERROR(Write16_0 4490 break;
3996 (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618)); 4491 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
3997 CHK_ERROR(Write16_0 4492 if (status < 0)
3998 (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988)); 4493 break;
3999 CHK_ERROR(Write16_0 4494 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4000 (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809)); 4495 if (status < 0)
4001 CHK_ERROR(Write16_0 4496 break;
4002 (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809)); 4497 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4003 CHK_ERROR(Write16_0 4498 if (status < 0)
4004 (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609)); 4499 break;
4500 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4501 if (status < 0)
4502 break;
4503 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4504 if (status < 0)
4505 break;
4005 4506
4006 /* Decision Feedback Equalizer */ 4507 /* Decision Feedback Equalizer */
4007 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4)); 4508 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 4);
4008 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4)); 4509 if (status < 0)
4009 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4)); 4510 break;
4010 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4)); 4511 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 4);
4011 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3)); 4512 if (status < 0)
4012 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); 4513 break;
4514 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 4);
4515 if (status < 0)
4516 break;
4517 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 4);
4518 if (status < 0)
4519 break;
4520 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 3);
4521 if (status < 0)
4522 break;
4523 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0);
4524 if (status < 0)
4525 break;
4013 4526
4014 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); 4527 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 5);
4015 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); 4528 if (status < 0)
4016 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); 4529 break;
4530 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 4);
4531 if (status < 0)
4532 break;
4533 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3);
4534 if (status < 0)
4535 break;
4017 4536
4018 /* QAM Slicer Settings */ 4537 /* QAM Slicer Settings */
4019 CHK_ERROR(Write16_0 4538 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4020 (state, SCU_RAM_QAM_SL_SIG_POWER__A, 4539 if (status < 0)
4021 DRXK_QAM_SL_SIG_POWER_QAM64)); 4540 break;
4022 4541
4023 4542
4024 /* QAM Loop Controller Coeficients */ 4543 /* QAM Loop Controller Coeficients */
4025 4544
4026 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); 4545 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4027 CHK_ERROR(Write16_0 4546 if (status < 0)
4028 (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); 4547 break;
4029 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); 4548 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4030 CHK_ERROR(Write16_0 4549 if (status < 0)
4031 (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); 4550 break;
4032 CHK_ERROR(Write16_0 4551 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4033 (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); 4552 if (status < 0)
4034 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); 4553 break;
4035 CHK_ERROR(Write16_0 4554 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4036 (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); 4555 if (status < 0)
4037 CHK_ERROR(Write16_0 4556 break;
4038 (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); 4557 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4039 4558 if (status < 0)
4040 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); 4559 break;
4041 CHK_ERROR(Write16_0 4560 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4042 (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30)); 4561 if (status < 0)
4043 CHK_ERROR(Write16_0 4562 break;
4044 (state, SCU_RAM_QAM_LC_CP_COARSE__A, 100)); 4563 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4045 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); 4564 if (status < 0)
4046 CHK_ERROR(Write16_0 4565 break;
4047 (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30)); 4566 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4048 CHK_ERROR(Write16_0 4567 if (status < 0)
4049 (state, SCU_RAM_QAM_LC_CI_COARSE__A, 50)); 4568 break;
4050 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); 4569
4051 CHK_ERROR(Write16_0 4570 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4052 (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); 4571 if (status < 0)
4053 CHK_ERROR(Write16_0 4572 break;
4054 (state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); 4573 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4055 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); 4574 if (status < 0)
4056 CHK_ERROR(Write16_0 4575 break;
4057 (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); 4576 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4058 CHK_ERROR(Write16_0 4577 if (status < 0)
4059 (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); 4578 break;
4579 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4580 if (status < 0)
4581 break;
4582 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4583 if (status < 0)
4584 break;
4585 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4586 if (status < 0)
4587 break;
4588 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4589 if (status < 0)
4590 break;
4591 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4592 if (status < 0)
4593 break;
4594 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4595 if (status < 0)
4596 break;
4597 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4598 if (status < 0)
4599 break;
4600 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4601 if (status < 0)
4602 break;
4603 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4604 if (status < 0)
4605 break;
4060 4606
4061 4607
4062 /* QAM State Machine (FSM) Thresholds */ 4608 /* QAM State Machine (FSM) Thresholds */
4063 4609
4064 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100)); 4610 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4065 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); 4611 if (status < 0)
4066 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); 4612 break;
4067 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110)); 4613 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4068 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200)); 4614 if (status < 0)
4069 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95)); 4615 break;
4616 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4617 if (status < 0)
4618 break;
4619 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4620 if (status < 0)
4621 break;
4622 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4623 if (status < 0)
4624 break;
4625 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4626 if (status < 0)
4627 break;
4070 4628
4071 CHK_ERROR(Write16_0 4629 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4072 (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); 4630 if (status < 0)
4073 CHK_ERROR(Write16_0 4631 break;
4074 (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); 4632 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4075 CHK_ERROR(Write16_0 4633 if (status < 0)
4076 (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15)); 4634 break;
4635 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4636 if (status < 0)
4637 break;
4077 4638
4078 4639
4079 /* QAM FSM Tracking Parameters */ 4640 /* QAM FSM Tracking Parameters */
4080 4641
4081 CHK_ERROR(Write16_0 4642 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4082 (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 4643 if (status < 0)
4083 (u16) 12)); 4644 break;
4084 CHK_ERROR(Write16_0 4645 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4085 (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 4646 if (status < 0)
4086 (u16) 141)); 4647 break;
4087 CHK_ERROR(Write16_0 4648 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4088 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 4649 if (status < 0)
4089 (u16) 7)); 4650 break;
4090 CHK_ERROR(Write16_0 4651 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4091 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 4652 if (status < 0)
4092 (u16) 0)); 4653 break;
4093 CHK_ERROR(Write16_0 4654 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4094 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 4655 if (status < 0)
4095 (u16) -15)); 4656 break;
4096 CHK_ERROR(Write16_0 4657 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4097 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 4658 if (status < 0)
4098 (u16) -45)); 4659 break;
4099 CHK_ERROR(Write16_0 4660 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4100 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, 4661 if (status < 0)
4101 (u16) -80)); 4662 break;
4102 } while (0); 4663 } while (0);
4103 4664
4104 return status; 4665 return status;
@@ -4118,117 +4679,183 @@ static int SetQAM128(struct drxk_state *state)
4118 do { 4679 do {
4119 /* QAM Equalizer Setup */ 4680 /* QAM Equalizer Setup */
4120 /* Equalizer */ 4681 /* Equalizer */
4121 CHK_ERROR(Write16_0 4682 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4122 (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564)); 4683 if (status < 0)
4123 CHK_ERROR(Write16_0 4684 break;
4124 (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598)); 4685 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4125 CHK_ERROR(Write16_0 4686 if (status < 0)
4126 (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394)); 4687 break;
4127 CHK_ERROR(Write16_0 4688 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4128 (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409)); 4689 if (status < 0)
4129 CHK_ERROR(Write16_0 4690 break;
4130 (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656)); 4691 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4131 CHK_ERROR(Write16_0 4692 if (status < 0)
4132 (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238)); 4693 break;
4694 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4695 if (status < 0)
4696 break;
4697 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4698 if (status < 0)
4699 break;
4133 4700
4134 /* Decision Feedback Equalizer */ 4701 /* Decision Feedback Equalizer */
4135 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6)); 4702 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 6);
4136 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6)); 4703 if (status < 0)
4137 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6)); 4704 break;
4138 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6)); 4705 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 6);
4139 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5)); 4706 if (status < 0)
4140 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); 4707 break;
4708 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 6);
4709 if (status < 0)
4710 break;
4711 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 6);
4712 if (status < 0)
4713 break;
4714 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 5);
4715 if (status < 0)
4716 break;
4717 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0);
4718 if (status < 0)
4719 break;
4141 4720
4142 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 6)); 4721 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 6);
4143 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 5)); 4722 if (status < 0)
4144 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); 4723 break;
4724 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 5);
4725 if (status < 0)
4726 break;
4727 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3);
4728 if (status < 0)
4729 break;
4145 4730
4146 4731
4147 /* QAM Slicer Settings */ 4732 /* QAM Slicer Settings */
4148 4733
4149 CHK_ERROR(Write16_0 4734 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4150 (state, SCU_RAM_QAM_SL_SIG_POWER__A, 4735 if (status < 0)
4151 DRXK_QAM_SL_SIG_POWER_QAM128)); 4736 break;
4152 4737
4153 4738
4154 /* QAM Loop Controller Coeficients */ 4739 /* QAM Loop Controller Coeficients */
4155 4740
4156 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); 4741 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4157 CHK_ERROR(Write16_0 4742 if (status < 0)
4158 (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); 4743 break;
4159 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); 4744 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4160 CHK_ERROR(Write16_0 4745 if (status < 0)
4161 (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); 4746 break;
4162 CHK_ERROR(Write16_0 4747 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4163 (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); 4748 if (status < 0)
4164 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); 4749 break;
4165 CHK_ERROR(Write16_0 4750 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4166 (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); 4751 if (status < 0)
4167 CHK_ERROR(Write16_0 4752 break;
4168 (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); 4753 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4169 4754 if (status < 0)
4170 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); 4755 break;
4171 CHK_ERROR(Write16_0 4756 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4172 (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40)); 4757 if (status < 0)
4173 CHK_ERROR(Write16_0 4758 break;
4174 (state, SCU_RAM_QAM_LC_CP_COARSE__A, 120)); 4759 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4175 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); 4760 if (status < 0)
4176 CHK_ERROR(Write16_0 4761 break;
4177 (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40)); 4762 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4178 CHK_ERROR(Write16_0 4763 if (status < 0)
4179 (state, SCU_RAM_QAM_LC_CI_COARSE__A, 60)); 4764 break;
4180 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); 4765
4181 CHK_ERROR(Write16_0 4766 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4182 (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); 4767 if (status < 0)
4183 CHK_ERROR(Write16_0 4768 break;
4184 (state, SCU_RAM_QAM_LC_CF_COARSE__A, 64)); 4769 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4185 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); 4770 if (status < 0)
4186 CHK_ERROR(Write16_0 4771 break;
4187 (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); 4772 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4188 CHK_ERROR(Write16_0 4773 if (status < 0)
4189 (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0)); 4774 break;
4775 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4776 if (status < 0)
4777 break;
4778 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4779 if (status < 0)
4780 break;
4781 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4782 if (status < 0)
4783 break;
4784 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4785 if (status < 0)
4786 break;
4787 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4788 if (status < 0)
4789 break;
4790 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4791 if (status < 0)
4792 break;
4793 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4794 if (status < 0)
4795 break;
4796 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4797 if (status < 0)
4798 break;
4799 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4800 if (status < 0)
4801 break;
4190 4802
4191 4803
4192 /* QAM State Machine (FSM) Thresholds */ 4804 /* QAM State Machine (FSM) Thresholds */
4193 4805
4194 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); 4806 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4195 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); 4807 if (status < 0)
4196 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); 4808 break;
4197 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); 4809 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4198 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140)); 4810 if (status < 0)
4199 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100)); 4811 break;
4812 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4813 if (status < 0)
4814 break;
4815 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4816 if (status < 0)
4817 break;
4818 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4819 if (status < 0)
4820 break;
4821 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4822 if (status < 0)
4823 break;
4200 4824
4201 CHK_ERROR(Write16_0 4825 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4202 (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); 4826 if (status < 0)
4203 CHK_ERROR(Write16_0 4827 break;
4204 (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5)); 4828 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4829 if (status < 0)
4830 break;
4205 4831
4206 CHK_ERROR(Write16_0 4832 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4207 (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); 4833 if (status < 0)
4834 break;
4208 4835
4209 /* QAM FSM Tracking Parameters */ 4836 /* QAM FSM Tracking Parameters */
4210 4837
4211 CHK_ERROR(Write16_0 4838 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4212 (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 4839 if (status < 0)
4213 (u16) 8)); 4840 break;
4214 CHK_ERROR(Write16_0 4841 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
4215 (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 4842 if (status < 0)
4216 (u16) 65)); 4843 break;
4217 CHK_ERROR(Write16_0 4844 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
4218 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 4845 if (status < 0)
4219 (u16) 5)); 4846 break;
4220 CHK_ERROR(Write16_0 4847 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
4221 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 4848 if (status < 0)
4222 (u16) 3)); 4849 break;
4223 CHK_ERROR(Write16_0 4850 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
4224 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 4851 if (status < 0)
4225 (u16) -1)); 4852 break;
4226 CHK_ERROR(Write16_0 4853 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
4227 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 4854 if (status < 0)
4228 (u16) -12)); 4855 break;
4229 CHK_ERROR(Write16_0 4856 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
4230 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, 4857 if (status < 0)
4231 (u16) -23)); 4858 break;
4232 } while (0); 4859 } while (0);
4233 4860
4234 return status; 4861 return status;
@@ -4248,116 +4875,182 @@ static int SetQAM256(struct drxk_state *state)
4248 do { 4875 do {
4249 /* QAM Equalizer Setup */ 4876 /* QAM Equalizer Setup */
4250 /* Equalizer */ 4877 /* Equalizer */
4251 CHK_ERROR(Write16_0 4878 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
4252 (state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502)); 4879 if (status < 0)
4253 CHK_ERROR(Write16_0 4880 break;
4254 (state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084)); 4881 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
4255 CHK_ERROR(Write16_0 4882 if (status < 0)
4256 (state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543)); 4883 break;
4257 CHK_ERROR(Write16_0 4884 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
4258 (state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931)); 4885 if (status < 0)
4259 CHK_ERROR(Write16_0 4886 break;
4260 (state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629)); 4887 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
4261 CHK_ERROR(Write16_0 4888 if (status < 0)
4262 (state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385)); 4889 break;
4890 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
4891 if (status < 0)
4892 break;
4893 status = Write16_0(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
4894 if (status < 0)
4895 break;
4263 4896
4264 /* Decision Feedback Equalizer */ 4897 /* Decision Feedback Equalizer */
4265 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8)); 4898 status = Write16_0(state, QAM_DQ_QUAL_FUN0__A, 8);
4266 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8)); 4899 if (status < 0)
4267 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8)); 4900 break;
4268 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8)); 4901 status = Write16_0(state, QAM_DQ_QUAL_FUN1__A, 8);
4269 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6)); 4902 if (status < 0)
4270 CHK_ERROR(Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0)); 4903 break;
4904 status = Write16_0(state, QAM_DQ_QUAL_FUN2__A, 8);
4905 if (status < 0)
4906 break;
4907 status = Write16_0(state, QAM_DQ_QUAL_FUN3__A, 8);
4908 if (status < 0)
4909 break;
4910 status = Write16_0(state, QAM_DQ_QUAL_FUN4__A, 6);
4911 if (status < 0)
4912 break;
4913 status = Write16_0(state, QAM_DQ_QUAL_FUN5__A, 0);
4914 if (status < 0)
4915 break;
4271 4916
4272 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_HWM__A, 5)); 4917 status = Write16_0(state, QAM_SY_SYNC_HWM__A, 5);
4273 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_AWM__A, 4)); 4918 if (status < 0)
4274 CHK_ERROR(Write16_0(state, QAM_SY_SYNC_LWM__A, 3)); 4919 break;
4920 status = Write16_0(state, QAM_SY_SYNC_AWM__A, 4);
4921 if (status < 0)
4922 break;
4923 status = Write16_0(state, QAM_SY_SYNC_LWM__A, 3);
4924 if (status < 0)
4925 break;
4275 4926
4276 /* QAM Slicer Settings */ 4927 /* QAM Slicer Settings */
4277 4928
4278 CHK_ERROR(Write16_0 4929 status = Write16_0(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
4279 (state, SCU_RAM_QAM_SL_SIG_POWER__A, 4930 if (status < 0)
4280 DRXK_QAM_SL_SIG_POWER_QAM256)); 4931 break;
4281 4932
4282 4933
4283 /* QAM Loop Controller Coeficients */ 4934 /* QAM Loop Controller Coeficients */
4284 4935
4285 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15)); 4936 status = Write16_0(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4286 CHK_ERROR(Write16_0 4937 if (status < 0)
4287 (state, SCU_RAM_QAM_LC_CA_COARSE__A, 40)); 4938 break;
4288 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12)); 4939 status = Write16_0(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4289 CHK_ERROR(Write16_0 4940 if (status < 0)
4290 (state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24)); 4941 break;
4291 CHK_ERROR(Write16_0 4942 status = Write16_0(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4292 (state, SCU_RAM_QAM_LC_EP_COARSE__A, 24)); 4943 if (status < 0)
4293 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12)); 4944 break;
4294 CHK_ERROR(Write16_0 4945 status = Write16_0(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4295 (state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16)); 4946 if (status < 0)
4296 CHK_ERROR(Write16_0 4947 break;
4297 (state, SCU_RAM_QAM_LC_EI_COARSE__A, 16)); 4948 status = Write16_0(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4298 4949 if (status < 0)
4299 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5)); 4950 break;
4300 CHK_ERROR(Write16_0 4951 status = Write16_0(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4301 (state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50)); 4952 if (status < 0)
4302 CHK_ERROR(Write16_0 4953 break;
4303 (state, SCU_RAM_QAM_LC_CP_COARSE__A, 250)); 4954 status = Write16_0(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4304 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5)); 4955 if (status < 0)
4305 CHK_ERROR(Write16_0 4956 break;
4306 (state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50)); 4957 status = Write16_0(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4307 CHK_ERROR(Write16_0 4958 if (status < 0)
4308 (state, SCU_RAM_QAM_LC_CI_COARSE__A, 125)); 4959 break;
4309 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16)); 4960
4310 CHK_ERROR(Write16_0 4961 status = Write16_0(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4311 (state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25)); 4962 if (status < 0)
4312 CHK_ERROR(Write16_0 4963 break;
4313 (state, SCU_RAM_QAM_LC_CF_COARSE__A, 48)); 4964 status = Write16_0(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
4314 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5)); 4965 if (status < 0)
4315 CHK_ERROR(Write16_0 4966 break;
4316 (state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10)); 4967 status = Write16_0(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
4317 CHK_ERROR(Write16_0 4968 if (status < 0)
4318 (state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10)); 4969 break;
4970 status = Write16_0(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4971 if (status < 0)
4972 break;
4973 status = Write16_0(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
4974 if (status < 0)
4975 break;
4976 status = Write16_0(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
4977 if (status < 0)
4978 break;
4979 status = Write16_0(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4980 if (status < 0)
4981 break;
4982 status = Write16_0(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4983 if (status < 0)
4984 break;
4985 status = Write16_0(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4986 if (status < 0)
4987 break;
4988 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4989 if (status < 0)
4990 break;
4991 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4992 if (status < 0)
4993 break;
4994 status = Write16_0(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4995 if (status < 0)
4996 break;
4319 4997
4320 4998
4321 /* QAM State Machine (FSM) Thresholds */ 4999 /* QAM State Machine (FSM) Thresholds */
4322 5000
4323 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50)); 5001 status = Write16_0(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4324 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60)); 5002 if (status < 0)
4325 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80)); 5003 break;
4326 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100)); 5004 status = Write16_0(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4327 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150)); 5005 if (status < 0)
4328 CHK_ERROR(Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110)); 5006 break;
5007 status = Write16_0(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5008 if (status < 0)
5009 break;
5010 status = Write16_0(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5011 if (status < 0)
5012 break;
5013 status = Write16_0(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5014 if (status < 0)
5015 break;
5016 status = Write16_0(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5017 if (status < 0)
5018 break;
4329 5019
4330 CHK_ERROR(Write16_0 5020 status = Write16_0(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4331 (state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40)); 5021 if (status < 0)
4332 CHK_ERROR(Write16_0 5022 break;
4333 (state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4)); 5023 status = Write16_0(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4334 CHK_ERROR(Write16_0 5024 if (status < 0)
4335 (state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12)); 5025 break;
5026 status = Write16_0(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5027 if (status < 0)
5028 break;
4336 5029
4337 5030
4338 /* QAM FSM Tracking Parameters */ 5031 /* QAM FSM Tracking Parameters */
4339 5032
4340 CHK_ERROR(Write16_0 5033 status = Write16_0(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4341 (state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 5034 if (status < 0)
4342 (u16) 8)); 5035 break;
4343 CHK_ERROR(Write16_0 5036 status = Write16_0(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
4344 (state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 5037 if (status < 0)
4345 (u16) 74)); 5038 break;
4346 CHK_ERROR(Write16_0 5039 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
4347 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5040 if (status < 0)
4348 (u16) 18)); 5041 break;
4349 CHK_ERROR(Write16_0 5042 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
4350 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 5043 if (status < 0)
4351 (u16) 13)); 5044 break;
4352 CHK_ERROR(Write16_0 5045 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
4353 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 5046 if (status < 0)
4354 (u16) 7)); 5047 break;
4355 CHK_ERROR(Write16_0 5048 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
4356 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 5049 if (status < 0)
4357 (u16) 0)); 5050 break;
4358 CHK_ERROR(Write16_0 5051 status = Write16_0(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
4359 (state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, 5052 if (status < 0)
4360 (u16) -8)); 5053 break;
4361 } while (0); 5054 } while (0);
4362 5055
4363 return status; 5056 return status;
@@ -4378,14 +5071,13 @@ static int QAMResetQAM(struct drxk_state *state)
4378 5071
4379 do { 5072 do {
4380 /* Stop QAM comstate->m_exec */ 5073 /* Stop QAM comstate->m_exec */
4381 CHK_ERROR(Write16_0 5074 status = Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4382 (state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP)); 5075 if (status < 0)
4383 5076 break;
4384 CHK_ERROR(scu_command 5077
4385 (state, 5078 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
4386 SCU_RAM_COMMAND_STANDARD_QAM | 5079 if (status < 0)
4387 SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, 5080 break;
4388 &cmdResult));
4389 } while (0); 5081 } while (0);
4390 5082
4391 /* All done, all OK */ 5083 /* All done, all OK */
@@ -4420,7 +5112,9 @@ static int QAMSetSymbolrate(struct drxk_state *state)
4420 ratesel = 2; 5112 ratesel = 2;
4421 else if (state->param.u.qam.symbol_rate <= 4755000) 5113 else if (state->param.u.qam.symbol_rate <= 4755000)
4422 ratesel = 1; 5114 ratesel = 1;
4423 CHK_ERROR(Write16_0(state, IQM_FD_RATESEL__A, ratesel)); 5115 status = Write16_0(state, IQM_FD_RATESEL__A, ratesel);
5116 if (status < 0)
5117 break;
4424 5118
4425 /* 5119 /*
4426 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) 5120 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
@@ -4433,8 +5127,9 @@ static int QAMSetSymbolrate(struct drxk_state *state)
4433 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) + 5127 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
4434 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) - 5128 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
4435 (1 << 23); 5129 (1 << 23);
4436 CHK_ERROR(Write32 5130 status = Write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate, 0);
4437 (state, IQM_RC_RATE_OFS_LO__A, iqmRcRate, 0)); 5131 if (status < 0)
5132 break;
4438 state->m_iqmRcRate = iqmRcRate; 5133 state->m_iqmRcRate = iqmRcRate;
4439 /* 5134 /*
4440 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) 5135 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
@@ -4449,9 +5144,9 @@ static int QAMSetSymbolrate(struct drxk_state *state)
4449 16); 5144 16);
4450 if (lcSymbRate > 511) 5145 if (lcSymbRate > 511)
4451 lcSymbRate = 511; 5146 lcSymbRate = 511;
4452 CHK_ERROR(Write16_0 5147 status = Write16_0(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
4453 (state, QAM_LC_SYMBOL_FREQ__A, 5148 if (status < 0)
4454 (u16) lcSymbRate)); 5149 break;
4455 } while (0); 5150 } while (0);
4456 5151
4457 return status; 5152 return status;
@@ -4521,20 +5216,24 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
4521 resets QAM block 5216 resets QAM block
4522 resets SCU variables 5217 resets SCU variables
4523 */ 5218 */
4524 CHK_ERROR(Write16_0 5219 status = Write16_0(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
4525 (state, FEC_DI_COMM_EXEC__A, 5220 if (status < 0)
4526 FEC_DI_COMM_EXEC_STOP)); 5221 break;
4527 CHK_ERROR(Write16_0 5222 status = Write16_0(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
4528 (state, FEC_RS_COMM_EXEC__A, 5223 if (status < 0)
4529 FEC_RS_COMM_EXEC_STOP)); 5224 break;
4530 CHK_ERROR(QAMResetQAM(state)); 5225 status = QAMResetQAM(state);
5226 if (status < 0)
5227 break;
4531 5228
4532 /* 5229 /*
4533 STEP 2: configure demodulator 5230 STEP 2: configure demodulator
4534 -set env 5231 -set env
4535 -set params; resets IQM,QAM,FEC HW; initializes some SCU variables 5232 -set params; resets IQM,QAM,FEC HW; initializes some SCU variables
4536 */ 5233 */
4537 CHK_ERROR(QAMSetSymbolrate(state)); 5234 status = QAMSetSymbolrate(state);
5235 if (status < 0)
5236 break;
4538 5237
4539 /* Env parameters */ 5238 /* Env parameters */
4540 setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */ 5239 setEnvParameters[2] = QAM_TOP_ANNEX_A; /* Annex */
@@ -4567,114 +5266,174 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
4567 status = -EINVAL; 5266 status = -EINVAL;
4568 break; 5267 break;
4569 } 5268 }
4570 CHK_ERROR(status); 5269 status = status;
5270 if (status < 0)
5271 break;
4571 setParamParameters[0] = state->m_Constellation; /* constellation */ 5272 setParamParameters[0] = state->m_Constellation; /* constellation */
4572 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ 5273 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
4573 5274
4574 CHK_ERROR(scu_command 5275 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
4575 (state, 5276 if (status < 0)
4576 SCU_RAM_COMMAND_STANDARD_QAM | 5277 break;
4577 SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4,
4578 setParamParameters, 1, &cmdResult));
4579 5278
4580 5279
4581 /* STEP 3: enable the system in a mode where the ADC provides valid signal 5280 /* STEP 3: enable the system in a mode where the ADC provides valid signal
4582 setup constellation independent registers */ 5281 setup constellation independent registers */
4583 /* CHK_ERROR (SetFrequency (channel, tunerFreqOffset)); */ 5282#if 0
4584 CHK_ERROR(SetFrequencyShifter 5283 status = SetFrequency (channel, tunerFreqOffset));
4585 (state, IntermediateFreqkHz, tunerFreqOffset, 5284 if (status < 0)
4586 true)); 5285 break;
5286#endif
5287 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5288 if (status < 0)
5289 break;
4587 5290
4588 /* Setup BER measurement */ 5291 /* Setup BER measurement */
4589 CHK_ERROR(SetQAMMeasurement(state, 5292 status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate);
4590 state->m_Constellation, 5293 if (status < 0)
4591 state->param.u. 5294 break;
4592 qam.symbol_rate));
4593 5295
4594 /* Reset default values */ 5296 /* Reset default values */
4595 CHK_ERROR(Write16_0 5297 status = Write16_0(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
4596 (state, IQM_CF_SCALE_SH__A, 5298 if (status < 0)
4597 IQM_CF_SCALE_SH__PRE)); 5299 break;
4598 CHK_ERROR(Write16_0 5300 status = Write16_0(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
4599 (state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE)); 5301 if (status < 0)
5302 break;
4600 5303
4601 /* Reset default LC values */ 5304 /* Reset default LC values */
4602 CHK_ERROR(Write16_0(state, QAM_LC_RATE_LIMIT__A, 3)); 5305 status = Write16_0(state, QAM_LC_RATE_LIMIT__A, 3);
4603 CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORP__A, 4)); 5306 if (status < 0)
4604 CHK_ERROR(Write16_0(state, QAM_LC_LPF_FACTORI__A, 4)); 5307 break;
4605 CHK_ERROR(Write16_0(state, QAM_LC_MODE__A, 7)); 5308 status = Write16_0(state, QAM_LC_LPF_FACTORP__A, 4);
4606 5309 if (status < 0)
4607 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB0__A, 1)); 5310 break;
4608 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB1__A, 1)); 5311 status = Write16_0(state, QAM_LC_LPF_FACTORI__A, 4);
4609 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB2__A, 1)); 5312 if (status < 0)
4610 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB3__A, 1)); 5313 break;
4611 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB4__A, 2)); 5314 status = Write16_0(state, QAM_LC_MODE__A, 7);
4612 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB5__A, 2)); 5315 if (status < 0)
4613 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB6__A, 2)); 5316 break;
4614 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB8__A, 2)); 5317
4615 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB9__A, 2)); 5318 status = Write16_0(state, QAM_LC_QUAL_TAB0__A, 1);
4616 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB10__A, 2)); 5319 if (status < 0)
4617 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB12__A, 2)); 5320 break;
4618 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB15__A, 3)); 5321 status = Write16_0(state, QAM_LC_QUAL_TAB1__A, 1);
4619 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB16__A, 3)); 5322 if (status < 0)
4620 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB20__A, 4)); 5323 break;
4621 CHK_ERROR(Write16_0(state, QAM_LC_QUAL_TAB25__A, 4)); 5324 status = Write16_0(state, QAM_LC_QUAL_TAB2__A, 1);
5325 if (status < 0)
5326 break;
5327 status = Write16_0(state, QAM_LC_QUAL_TAB3__A, 1);
5328 if (status < 0)
5329 break;
5330 status = Write16_0(state, QAM_LC_QUAL_TAB4__A, 2);
5331 if (status < 0)
5332 break;
5333 status = Write16_0(state, QAM_LC_QUAL_TAB5__A, 2);
5334 if (status < 0)
5335 break;
5336 status = Write16_0(state, QAM_LC_QUAL_TAB6__A, 2);
5337 if (status < 0)
5338 break;
5339 status = Write16_0(state, QAM_LC_QUAL_TAB8__A, 2);
5340 if (status < 0)
5341 break;
5342 status = Write16_0(state, QAM_LC_QUAL_TAB9__A, 2);
5343 if (status < 0)
5344 break;
5345 status = Write16_0(state, QAM_LC_QUAL_TAB10__A, 2);
5346 if (status < 0)
5347 break;
5348 status = Write16_0(state, QAM_LC_QUAL_TAB12__A, 2);
5349 if (status < 0)
5350 break;
5351 status = Write16_0(state, QAM_LC_QUAL_TAB15__A, 3);
5352 if (status < 0)
5353 break;
5354 status = Write16_0(state, QAM_LC_QUAL_TAB16__A, 3);
5355 if (status < 0)
5356 break;
5357 status = Write16_0(state, QAM_LC_QUAL_TAB20__A, 4);
5358 if (status < 0)
5359 break;
5360 status = Write16_0(state, QAM_LC_QUAL_TAB25__A, 4);
5361 if (status < 0)
5362 break;
4622 5363
4623 /* Mirroring, QAM-block starting point not inverted */ 5364 /* Mirroring, QAM-block starting point not inverted */
4624 CHK_ERROR(Write16_0 5365 status = Write16_0(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
4625 (state, QAM_SY_SP_INV__A, 5366 if (status < 0)
4626 QAM_SY_SP_INV_SPECTRUM_INV_DIS)); 5367 break;
4627 5368
4628 /* Halt SCU to enable safe non-atomic accesses */ 5369 /* Halt SCU to enable safe non-atomic accesses */
4629 CHK_ERROR(Write16_0 5370 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
4630 (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); 5371 if (status < 0)
5372 break;
4631 5373
4632 /* STEP 4: constellation specific setup */ 5374 /* STEP 4: constellation specific setup */
4633 switch (state->param.u.qam.modulation) { 5375 switch (state->param.u.qam.modulation) {
4634 case QAM_16: 5376 case QAM_16:
4635 CHK_ERROR(SetQAM16(state)); 5377 status = SetQAM16(state);
5378 if (status < 0)
5379 break;
4636 break; 5380 break;
4637 case QAM_32: 5381 case QAM_32:
4638 CHK_ERROR(SetQAM32(state)); 5382 status = SetQAM32(state);
5383 if (status < 0)
5384 break;
4639 break; 5385 break;
4640 case QAM_AUTO: 5386 case QAM_AUTO:
4641 case QAM_64: 5387 case QAM_64:
4642 CHK_ERROR(SetQAM64(state)); 5388 status = SetQAM64(state);
5389 if (status < 0)
5390 break;
4643 break; 5391 break;
4644 case QAM_128: 5392 case QAM_128:
4645 CHK_ERROR(SetQAM128(state)); 5393 status = SetQAM128(state);
5394 if (status < 0)
5395 break;
4646 break; 5396 break;
4647 case QAM_256: 5397 case QAM_256:
4648 CHK_ERROR(SetQAM256(state)); 5398 status = SetQAM256(state);
5399 if (status < 0)
5400 break;
4649 break; 5401 break;
4650 default: 5402 default:
4651 return -1; 5403 return -1;
4652 break; 5404 break;
4653 } /* switch */ 5405 } /* switch */
4654 /* Activate SCU to enable SCU commands */ 5406 /* Activate SCU to enable SCU commands */
4655 CHK_ERROR(Write16_0 5407 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4656 (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); 5408 if (status < 0)
5409 break;
4657 5410
4658 5411
4659 /* Re-configure MPEG output, requires knowledge of channel bitrate */ 5412 /* Re-configure MPEG output, requires knowledge of channel bitrate */
4660 /* extAttr->currentChannel.constellation = channel->constellation; */ 5413 /* extAttr->currentChannel.constellation = channel->constellation; */
4661 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ 5414 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
4662 CHK_ERROR(MPEGTSDtoSetup(state, state->m_OperationMode)); 5415 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5416 if (status < 0)
5417 break;
4663 5418
4664 /* Start processes */ 5419 /* Start processes */
4665 CHK_ERROR(MPEGTSStart(state)); 5420 status = MPEGTSStart(state);
4666 CHK_ERROR(Write16_0 5421 if (status < 0)
4667 (state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE)); 5422 break;
4668 CHK_ERROR(Write16_0 5423 status = Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
4669 (state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE)); 5424 if (status < 0)
4670 CHK_ERROR(Write16_0 5425 break;
4671 (state, IQM_COMM_EXEC__A, 5426 status = Write16_0(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
4672 IQM_COMM_EXEC_B_ACTIVE)); 5427 if (status < 0)
5428 break;
5429 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5430 if (status < 0)
5431 break;
4673 5432
4674 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ 5433 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
4675 CHK_ERROR(scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | 5434 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4676 SCU_RAM_COMMAND_CMD_DEMOD_START, 0, 5435 if (status < 0)
4677 NULL, 1, &cmdResult)); 5436 break;
4678 5437
4679 /* update global DRXK data container */ 5438 /* update global DRXK data container */
4680 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ 5439 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
@@ -4704,96 +5463,153 @@ static int SetQAMStandard(struct drxk_state *state,
4704 SwitchAntennaToQAM(state); 5463 SwitchAntennaToQAM(state);
4705 5464
4706 /* Ensure correct power-up mode */ 5465 /* Ensure correct power-up mode */
4707 CHK_ERROR(PowerUpQAM(state)); 5466 status = PowerUpQAM(state);
5467 if (status < 0)
5468 break;
4708 /* Reset QAM block */ 5469 /* Reset QAM block */
4709 CHK_ERROR(QAMResetQAM(state)); 5470 status = QAMResetQAM(state);
5471 if (status < 0)
5472 break;
4710 5473
4711 /* Setup IQM */ 5474 /* Setup IQM */
4712 5475
4713 CHK_ERROR(Write16_0 5476 status = Write16_0(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
4714 (state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP)); 5477 if (status < 0)
4715 CHK_ERROR(Write16_0 5478 break;
4716 (state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC)); 5479 status = Write16_0(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5480 if (status < 0)
5481 break;
4717 5482
4718 /* Upload IQM Channel Filter settings by 5483 /* Upload IQM Channel Filter settings by
4719 boot loader from ROM table */ 5484 boot loader from ROM table */
4720 switch (oMode) { 5485 switch (oMode) {
4721 case OM_QAM_ITU_A: 5486 case OM_QAM_ITU_A:
4722 CHK_ERROR(BLChainCmd(state, 5487 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
4723 DRXK_BL_ROM_OFFSET_TAPS_ITU_A, 5488 if (status < 0)
4724 DRXK_BLCC_NR_ELEMENTS_TAPS, 5489 break;
4725 DRXK_BLC_TIMEOUT));
4726 break; 5490 break;
4727 case OM_QAM_ITU_C: 5491 case OM_QAM_ITU_C:
4728 CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_RE0__A, 5492 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
4729 DRXK_BL_ROM_OFFSET_TAPS_ITU_C, 5493 if (status < 0)
4730 DRXK_BLDC_NR_ELEMENTS_TAPS, 5494 break;
4731 DRXK_BLC_TIMEOUT)); 5495 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
4732 CHK_ERROR(BLDirectCmd(state, IQM_CF_TAP_IM0__A, 5496 if (status < 0)
4733 DRXK_BL_ROM_OFFSET_TAPS_ITU_C, 5497 break;
4734 DRXK_BLDC_NR_ELEMENTS_TAPS,
4735 DRXK_BLC_TIMEOUT));
4736 break; 5498 break;
4737 default: 5499 default:
4738 status = -EINVAL; 5500 status = -EINVAL;
4739 } 5501 }
4740 CHK_ERROR(status); 5502 status = status;
4741 5503 if (status < 0)
4742 CHK_ERROR(Write16_0(state, IQM_CF_OUT_ENA__A, 5504 break;
4743 (1 << IQM_CF_OUT_ENA_QAM__B))); 5505
4744 CHK_ERROR(Write16_0(state, IQM_CF_SYMMETRIC__A, 0)); 5506 status = Write16_0(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
4745 CHK_ERROR(Write16_0(state, IQM_CF_MIDTAP__A, 5507 if (status < 0)
4746 ((1 << IQM_CF_MIDTAP_RE__B) | 5508 break;
4747 (1 << IQM_CF_MIDTAP_IM__B)))); 5509 status = Write16_0(state, IQM_CF_SYMMETRIC__A, 0);
4748 5510 if (status < 0)
4749 CHK_ERROR(Write16_0(state, IQM_RC_STRETCH__A, 21)); 5511 break;
4750 CHK_ERROR(Write16_0(state, IQM_AF_CLP_LEN__A, 0)); 5512 status = Write16_0(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
4751 CHK_ERROR(Write16_0(state, IQM_AF_CLP_TH__A, 448)); 5513 if (status < 0)
4752 CHK_ERROR(Write16_0(state, IQM_AF_SNS_LEN__A, 0)); 5514 break;
4753 CHK_ERROR(Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0)); 5515
4754 5516 status = Write16_0(state, IQM_RC_STRETCH__A, 21);
4755 CHK_ERROR(Write16_0(state, IQM_FS_ADJ_SEL__A, 1)); 5517 if (status < 0)
4756 CHK_ERROR(Write16_0(state, IQM_RC_ADJ_SEL__A, 1)); 5518 break;
4757 CHK_ERROR(Write16_0(state, IQM_CF_ADJ_SEL__A, 1)); 5519 status = Write16_0(state, IQM_AF_CLP_LEN__A, 0);
4758 CHK_ERROR(Write16_0(state, IQM_AF_UPD_SEL__A, 0)); 5520 if (status < 0)
5521 break;
5522 status = Write16_0(state, IQM_AF_CLP_TH__A, 448);
5523 if (status < 0)
5524 break;
5525 status = Write16_0(state, IQM_AF_SNS_LEN__A, 0);
5526 if (status < 0)
5527 break;
5528 status = Write16_0(state, IQM_CF_POW_MEAS_LEN__A, 0);
5529 if (status < 0)
5530 break;
5531
5532 status = Write16_0(state, IQM_FS_ADJ_SEL__A, 1);
5533 if (status < 0)
5534 break;
5535 status = Write16_0(state, IQM_RC_ADJ_SEL__A, 1);
5536 if (status < 0)
5537 break;
5538 status = Write16_0(state, IQM_CF_ADJ_SEL__A, 1);
5539 if (status < 0)
5540 break;
5541 status = Write16_0(state, IQM_AF_UPD_SEL__A, 0);
5542 if (status < 0)
5543 break;
4759 5544
4760 /* IQM Impulse Noise Processing Unit */ 5545 /* IQM Impulse Noise Processing Unit */
4761 CHK_ERROR(Write16_0(state, IQM_CF_CLP_VAL__A, 500)); 5546 status = Write16_0(state, IQM_CF_CLP_VAL__A, 500);
4762 CHK_ERROR(Write16_0(state, IQM_CF_DATATH__A, 1000)); 5547 if (status < 0)
4763 CHK_ERROR(Write16_0(state, IQM_CF_BYPASSDET__A, 1)); 5548 break;
4764 CHK_ERROR(Write16_0(state, IQM_CF_DET_LCT__A, 0)); 5549 status = Write16_0(state, IQM_CF_DATATH__A, 1000);
4765 CHK_ERROR(Write16_0(state, IQM_CF_WND_LEN__A, 1)); 5550 if (status < 0)
4766 CHK_ERROR(Write16_0(state, IQM_CF_PKDTH__A, 1)); 5551 break;
4767 CHK_ERROR(Write16_0(state, IQM_AF_INC_BYPASS__A, 1)); 5552 status = Write16_0(state, IQM_CF_BYPASSDET__A, 1);
5553 if (status < 0)
5554 break;
5555 status = Write16_0(state, IQM_CF_DET_LCT__A, 0);
5556 if (status < 0)
5557 break;
5558 status = Write16_0(state, IQM_CF_WND_LEN__A, 1);
5559 if (status < 0)
5560 break;
5561 status = Write16_0(state, IQM_CF_PKDTH__A, 1);
5562 if (status < 0)
5563 break;
5564 status = Write16_0(state, IQM_AF_INC_BYPASS__A, 1);
5565 if (status < 0)
5566 break;
4768 5567
4769 /* turn on IQMAF. Must be done before setAgc**() */ 5568 /* turn on IQMAF. Must be done before setAgc**() */
4770 CHK_ERROR(SetIqmAf(state, true)); 5569 status = SetIqmAf(state, true);
4771 CHK_ERROR(Write16_0(state, IQM_AF_START_LOCK__A, 0x01)); 5570 if (status < 0)
5571 break;
5572 status = Write16_0(state, IQM_AF_START_LOCK__A, 0x01);
5573 if (status < 0)
5574 break;
4772 5575
4773 /* IQM will not be reset from here, sync ADC and update/init AGC */ 5576 /* IQM will not be reset from here, sync ADC and update/init AGC */
4774 CHK_ERROR(ADCSynchronization(state)); 5577 status = ADCSynchronization(state);
5578 if (status < 0)
5579 break;
4775 5580
4776 /* Set the FSM step period */ 5581 /* Set the FSM step period */
4777 CHK_ERROR(Write16_0 5582 status = Write16_0(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
4778 (state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000)); 5583 if (status < 0)
5584 break;
4779 5585
4780 /* Halt SCU to enable safe non-atomic accesses */ 5586 /* Halt SCU to enable safe non-atomic accesses */
4781 CHK_ERROR(Write16_0 5587 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
4782 (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD)); 5588 if (status < 0)
5589 break;
4783 5590
4784 /* No more resets of the IQM, current standard correctly set => 5591 /* No more resets of the IQM, current standard correctly set =>
4785 now AGCs can be configured. */ 5592 now AGCs can be configured. */
4786 5593
4787 CHK_ERROR(InitAGC(state, true)); 5594 status = InitAGC(state, true);
4788 CHK_ERROR(SetPreSaw(state, &(state->m_qamPreSawCfg))); 5595 if (status < 0)
5596 break;
5597 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5598 if (status < 0)
5599 break;
4789 5600
4790 /* Configure AGC's */ 5601 /* Configure AGC's */
4791 CHK_ERROR(SetAgcRf(state, &(state->m_qamRfAgcCfg), true)); 5602 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
4792 CHK_ERROR(SetAgcIf(state, &(state->m_qamIfAgcCfg), true)); 5603 if (status < 0)
5604 break;
5605 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5606 if (status < 0)
5607 break;
4793 5608
4794 /* Activate SCU to enable SCU commands */ 5609 /* Activate SCU to enable SCU commands */
4795 CHK_ERROR(Write16_0 5610 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4796 (state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE)); 5611 if (status < 0)
5612 break;
4797 } while (0); 5613 } while (0);
4798 return status; 5614 return status;
4799} 5615}
@@ -4805,32 +5621,39 @@ static int WriteGPIO(struct drxk_state *state)
4805 5621
4806 do { 5622 do {
4807 /* stop lock indicator process */ 5623 /* stop lock indicator process */
4808 CHK_ERROR(Write16_0(state, SCU_RAM_GPIO__A, 5624 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
4809 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); 5625 if (status < 0)
5626 break;
4810 5627
4811 /* Write magic word to enable pdr reg write */ 5628 /* Write magic word to enable pdr reg write */
4812 CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 5629 status = Write16_0(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
4813 SIO_TOP_COMM_KEY_KEY)); 5630 if (status < 0)
5631 break;
4814 5632
4815 if (state->m_hasSAWSW) { 5633 if (state->m_hasSAWSW) {
4816 /* write to io pad configuration register - output mode */ 5634 /* write to io pad configuration register - output mode */
4817 CHK_ERROR(Write16_0(state, SIO_PDR_SMA_TX_CFG__A, 5635 status = Write16_0(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
4818 state->m_GPIOCfg)); 5636 if (status < 0)
5637 break;
4819 5638
4820 /* use corresponding bit in io data output registar */ 5639 /* use corresponding bit in io data output registar */
4821 CHK_ERROR(Read16_0 5640 status = Read16_0(state, SIO_PDR_UIO_OUT_LO__A, &value);
4822 (state, SIO_PDR_UIO_OUT_LO__A, &value)); 5641 if (status < 0)
5642 break;
4823 if (state->m_GPIO == 0) 5643 if (state->m_GPIO == 0)
4824 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ 5644 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
4825 else 5645 else
4826 value |= 0x8000; /* write one to 15th bit - 1st UIO */ 5646 value |= 0x8000; /* write one to 15th bit - 1st UIO */
4827 /* write back to io data output register */ 5647 /* write back to io data output register */
4828 CHK_ERROR(Write16_0 5648 status = Write16_0(state, SIO_PDR_UIO_OUT_LO__A, value);
4829 (state, SIO_PDR_UIO_OUT_LO__A, value)); 5649 if (status < 0)
5650 break;
4830 5651
4831 } 5652 }
4832 /* Write magic word to disable pdr reg write */ 5653 /* Write magic word to disable pdr reg write */
4833 CHK_ERROR(Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000)); 5654 status = Write16_0(state, SIO_TOP_COMM_KEY__A, 0x0000);
5655 if (status < 0)
5656 break;
4834 } while (0); 5657 } while (0);
4835 return status; 5658 return status;
4836} 5659}
@@ -4874,18 +5697,25 @@ static int PowerDownDevice(struct drxk_state *state)
4874 do { 5697 do {
4875 if (state->m_bPDownOpenBridge) { 5698 if (state->m_bPDownOpenBridge) {
4876 /* Open I2C bridge before power down of DRXK */ 5699 /* Open I2C bridge before power down of DRXK */
4877 CHK_ERROR(ConfigureI2CBridge(state, true)); 5700 status = ConfigureI2CBridge(state, true);
5701 if (status < 0)
5702 break;
4878 } 5703 }
4879 /* driver 0.9.0 */ 5704 /* driver 0.9.0 */
4880 CHK_ERROR(DVBTEnableOFDMTokenRing(state, false)); 5705 status = DVBTEnableOFDMTokenRing(state, false);
5706 if (status < 0)
5707 break;
4881 5708
4882 CHK_ERROR(Write16_0 5709 status = Write16_0(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
4883 (state, SIO_CC_PWD_MODE__A, 5710 if (status < 0)
4884 SIO_CC_PWD_MODE_LEVEL_CLOCK)); 5711 break;
4885 CHK_ERROR(Write16_0 5712 status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
4886 (state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY)); 5713 if (status < 0)
5714 break;
4887 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; 5715 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
4888 CHK_ERROR(HI_CfgCommand(state)); 5716 status = HI_CfgCommand(state);
5717 if (status < 0)
5718 break;
4889 } while (0); 5719 } while (0);
4890 5720
4891 if (status < 0) 5721 if (status < 0)
@@ -4920,20 +5750,25 @@ static int init_drxk(struct drxk_state *state)
4920 5750
4921 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { 5751 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
4922 do { 5752 do {
4923 CHK_ERROR(PowerUpDevice(state)); 5753 status = PowerUpDevice(state);
4924 CHK_ERROR(DRXX_Open(state)); 5754 if (status < 0)
5755 break;
5756 status = DRXX_Open(state);
5757 if (status < 0)
5758 break;
4925 /* Soft reset of OFDM-, sys- and osc-clockdomain */ 5759 /* Soft reset of OFDM-, sys- and osc-clockdomain */
4926 CHK_ERROR(Write16_0(state, SIO_CC_SOFT_RST__A, 5760 status = Write16_0(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
4927 SIO_CC_SOFT_RST_OFDM__M | 5761 if (status < 0)
4928 SIO_CC_SOFT_RST_SYS__M | 5762 break;
4929 SIO_CC_SOFT_RST_OSC__M)); 5763 status = Write16_0(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
4930 CHK_ERROR(Write16_0 5764 if (status < 0)
4931 (state, SIO_CC_UPDATE__A, 5765 break;
4932 SIO_CC_UPDATE_KEY));
4933 /* TODO is this needed, if yes how much delay in worst case scenario */ 5766 /* TODO is this needed, if yes how much delay in worst case scenario */
4934 msleep(1); 5767 msleep(1);
4935 state->m_DRXK_A3_PATCH_CODE = true; 5768 state->m_DRXK_A3_PATCH_CODE = true;
4936 CHK_ERROR(GetDeviceCapabilities(state)); 5769 status = GetDeviceCapabilities(state);
5770 if (status < 0)
5771 break;
4937 5772
4938 /* Bridge delay, uses oscilator clock */ 5773 /* Bridge delay, uses oscilator clock */
4939 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ 5774 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
@@ -4952,69 +5787,79 @@ static int init_drxk(struct drxk_state *state)
4952 state->m_HICfgBridgeDelay << 5787 state->m_HICfgBridgeDelay <<
4953 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; 5788 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
4954 5789
4955 CHK_ERROR(InitHI(state)); 5790 status = InitHI(state);
5791 if (status < 0)
5792 break;
4956 /* disable various processes */ 5793 /* disable various processes */
4957#if NOA1ROM 5794#if NOA1ROM
4958 if (!(state->m_DRXK_A1_ROM_CODE) 5795 if (!(state->m_DRXK_A1_ROM_CODE)
4959 && !(state->m_DRXK_A2_ROM_CODE)) 5796 && !(state->m_DRXK_A2_ROM_CODE))
4960#endif 5797#endif
4961 { 5798 {
4962 CHK_ERROR(Write16_0 5799 status = Write16_0(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
4963 (state, SCU_RAM_GPIO__A, 5800 if (status < 0)
4964 SCU_RAM_GPIO_HW_LOCK_IND_DISABLE)); 5801 break;
4965 } 5802 }
4966 5803
4967 /* disable MPEG port */ 5804 /* disable MPEG port */
4968 CHK_ERROR(MPEGTSDisable(state)); 5805 status = MPEGTSDisable(state);
5806 if (status < 0)
5807 break;
4969 5808
4970 /* Stop AUD and SCU */ 5809 /* Stop AUD and SCU */
4971 CHK_ERROR(Write16_0 5810 status = Write16_0(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
4972 (state, AUD_COMM_EXEC__A, 5811 if (status < 0)
4973 AUD_COMM_EXEC_STOP)); 5812 break;
4974 CHK_ERROR(Write16_0 5813 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
4975 (state, SCU_COMM_EXEC__A, 5814 if (status < 0)
4976 SCU_COMM_EXEC_STOP)); 5815 break;
4977 5816
4978 /* enable token-ring bus through OFDM block for possible ucode upload */ 5817 /* enable token-ring bus through OFDM block for possible ucode upload */
4979 CHK_ERROR(Write16_0 5818 status = Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
4980 (state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, 5819 if (status < 0)
4981 SIO_OFDM_SH_OFDM_RING_ENABLE_ON)); 5820 break;
4982 5821
4983 /* include boot loader section */ 5822 /* include boot loader section */
4984 CHK_ERROR(Write16_0 5823 status = Write16_0(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
4985 (state, SIO_BL_COMM_EXEC__A, 5824 if (status < 0)
4986 SIO_BL_COMM_EXEC_ACTIVE)); 5825 break;
4987 CHK_ERROR(BLChainCmd(state, 0, 6, 100)); 5826 status = BLChainCmd(state, 0, 6, 100);
5827 if (status < 0)
5828 break;
4988 5829
4989#if 0 5830#if 0
4990 if (state->m_DRXK_A3_PATCH_CODE) 5831 if (state->m_DRXK_A3_PATCH_CODE)
4991 CHK_ERROR(DownloadMicrocode(state, 5832 status = DownloadMicrocode(state, DRXK_A3_microcode, DRXK_A3_microcode_length);
4992 DRXK_A3_microcode, 5833 if (status < 0)
4993 DRXK_A3_microcode_length)); 5834 break;
4994#else 5835#else
4995 load_microcode(state, "drxk_a3.mc"); 5836 load_microcode(state, "drxk_a3.mc");
4996#endif 5837#endif
4997#if NOA1ROM 5838#if NOA1ROM
4998 if (state->m_DRXK_A2_PATCH_CODE) 5839 if (state->m_DRXK_A2_PATCH_CODE)
4999 CHK_ERROR(DownloadMicrocode(state, 5840 status = DownloadMicrocode(state, DRXK_A2_microcode, DRXK_A2_microcode_length);
5000 DRXK_A2_microcode, 5841 if (status < 0)
5001 DRXK_A2_microcode_length)); 5842 break;
5002#endif 5843#endif
5003 /* disable token-ring bus through OFDM block for possible ucode upload */ 5844 /* disable token-ring bus through OFDM block for possible ucode upload */
5004 CHK_ERROR(Write16_0 5845 status = Write16_0(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
5005 (state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, 5846 if (status < 0)
5006 SIO_OFDM_SH_OFDM_RING_ENABLE_OFF)); 5847 break;
5007 5848
5008 /* Run SCU for a little while to initialize microcode version numbers */ 5849 /* Run SCU for a little while to initialize microcode version numbers */
5009 CHK_ERROR(Write16_0 5850 status = Write16_0(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5010 (state, SCU_COMM_EXEC__A, 5851 if (status < 0)
5011 SCU_COMM_EXEC_ACTIVE)); 5852 break;
5012 CHK_ERROR(DRXX_Open(state)); 5853 status = DRXX_Open(state);
5854 if (status < 0)
5855 break;
5013 /* added for test */ 5856 /* added for test */
5014 msleep(30); 5857 msleep(30);
5015 5858
5016 powerMode = DRXK_POWER_DOWN_OFDM; 5859 powerMode = DRXK_POWER_DOWN_OFDM;
5017 CHK_ERROR(CtrlPowerMode(state, &powerMode)); 5860 status = CtrlPowerMode(state, &powerMode);
5861 if (status < 0)
5862 break;
5018 5863
5019 /* Stamp driver version number in SCU data RAM in BCD code 5864 /* Stamp driver version number in SCU data RAM in BCD code
5020 Done to enable field application engineers to retreive drxdriver version 5865 Done to enable field application engineers to retreive drxdriver version
@@ -5027,17 +5872,17 @@ static int init_drxk(struct drxk_state *state)
5027 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + 5872 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
5028 ((DRXK_VERSION_MAJOR % 10) << 4) + 5873 ((DRXK_VERSION_MAJOR % 10) << 4) +
5029 (DRXK_VERSION_MINOR % 10); 5874 (DRXK_VERSION_MINOR % 10);
5030 CHK_ERROR(Write16_0 5875 status = Write16_0(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
5031 (state, SCU_RAM_DRIVER_VER_HI__A, 5876 if (status < 0)
5032 driverVersion)); 5877 break;
5033 driverVersion = 5878 driverVersion =
5034 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + 5879 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
5035 (((DRXK_VERSION_PATCH / 100) % 10) << 8) + 5880 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
5036 (((DRXK_VERSION_PATCH / 10) % 10) << 4) + 5881 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
5037 (DRXK_VERSION_PATCH % 10); 5882 (DRXK_VERSION_PATCH % 10);
5038 CHK_ERROR(Write16_0 5883 status = Write16_0(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
5039 (state, SCU_RAM_DRIVER_VER_LO__A, 5884 if (status < 0)
5040 driverVersion)); 5885 break;
5041 5886
5042 printk(KERN_INFO "DRXK driver version %d.%d.%d\n", 5887 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
5043 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, 5888 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
@@ -5051,27 +5896,39 @@ static int init_drxk(struct drxk_state *state)
5051 /* m_dvbtRfAgcCfg.speed = 3; */ 5896 /* m_dvbtRfAgcCfg.speed = 3; */
5052 5897
5053 /* Reset driver debug flags to 0 */ 5898 /* Reset driver debug flags to 0 */
5054 CHK_ERROR(Write16_0 5899 status = Write16_0(state, SCU_RAM_DRIVER_DEBUG__A, 0);
5055 (state, SCU_RAM_DRIVER_DEBUG__A, 0)); 5900 if (status < 0)
5901 break;
5056 /* driver 0.9.0 */ 5902 /* driver 0.9.0 */
5057 /* Setup FEC OC: 5903 /* Setup FEC OC:
5058 NOTE: No more full FEC resets allowed afterwards!! */ 5904 NOTE: No more full FEC resets allowed afterwards!! */
5059 CHK_ERROR(Write16_0 5905 status = Write16_0(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
5060 (state, FEC_COMM_EXEC__A, 5906 if (status < 0)
5061 FEC_COMM_EXEC_STOP)); 5907 break;
5062 /* MPEGTS functions are still the same */ 5908 /* MPEGTS functions are still the same */
5063 CHK_ERROR(MPEGTSDtoInit(state)); 5909 status = MPEGTSDtoInit(state);
5064 CHK_ERROR(MPEGTSStop(state)); 5910 if (status < 0)
5065 CHK_ERROR(MPEGTSConfigurePolarity(state)); 5911 break;
5066 CHK_ERROR(MPEGTSConfigurePins 5912 status = MPEGTSStop(state);
5067 (state, state->m_enableMPEGOutput)); 5913 if (status < 0)
5914 break;
5915 status = MPEGTSConfigurePolarity(state);
5916 if (status < 0)
5917 break;
5918 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
5919 if (status < 0)
5920 break;
5068 /* added: configure GPIO */ 5921 /* added: configure GPIO */
5069 CHK_ERROR(WriteGPIO(state)); 5922 status = WriteGPIO(state);
5923 if (status < 0)
5924 break;
5070 5925
5071 state->m_DrxkState = DRXK_STOPPED; 5926 state->m_DrxkState = DRXK_STOPPED;
5072 5927
5073 if (state->m_bPowerDown) { 5928 if (state->m_bPowerDown) {
5074 CHK_ERROR(PowerDownDevice(state)); 5929 status = PowerDownDevice(state);
5930 if (status < 0)
5931 break;
5075 state->m_DrxkState = DRXK_POWERED_DOWN; 5932 state->m_DrxkState = DRXK_POWERED_DOWN;
5076 } else 5933 } else
5077 state->m_DrxkState = DRXK_STOPPED; 5934 state->m_DrxkState = DRXK_STOPPED;
diff --git a/drivers/media/dvb/frontends/tda18271c2dd.c b/drivers/media/dvb/frontends/tda18271c2dd.c
index a8afc2212728..7f526143ba40 100644
--- a/drivers/media/dvb/frontends/tda18271c2dd.c
+++ b/drivers/media/dvb/frontends/tda18271c2dd.c
@@ -817,7 +817,7 @@ static int ChannelConfiguration(struct tda_state *state,
817 u8 BP_Filter = 0; 817 u8 BP_Filter = 0;
818 u8 RF_Band = 0; 818 u8 RF_Band = 0;
819 u8 GainTaper = 0; 819 u8 GainTaper = 0;
820 u8 IR_Meas; 820 u8 IR_Meas = 0;
821 821
822 state->IF = IntermediateFrequency; 822 state->IF = IntermediateFrequency;
823 /* printk("%s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */ 823 /* printk("%s Freq = %d Standard = %d IF = %d\n", __func__, Frequency, Standard, IntermediateFrequency); */
@@ -884,7 +884,7 @@ static int ChannelConfiguration(struct tda_state *state,
884 state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */ 884 state->m_Regs[EB4] &= ~0x20; /* LO_forceSrce = 0 */
885 CHK_ERROR(UpdateReg(state, EB4)); 885 CHK_ERROR(UpdateReg(state, EB4));
886 } else { 886 } else {
887 u8 PostDiv; 887 u8 PostDiv = 0;
888 u8 Div; 888 u8 Div;
889 CHK_ERROR(CalcCalPLL(state, Frequency + IntermediateFrequency)); 889 CHK_ERROR(CalcCalPLL(state, Frequency + IntermediateFrequency));
890 890
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-08 03:16:14 -0400