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authorOlof Johansson <olof@lixom.net>2012-09-21 00:16:43 -0400
committerOlof Johansson <olof@lixom.net>2012-09-21 00:16:43 -0400
commitea832c41dacbc4a5f3888d9ef7c38213914aba2a (patch)
treebee97817d9a55f000e2bec5fa5d62d325050e6a6 /drivers
parentb74aae9a2074e1caa2e40bf119f3a633f77c94e4 (diff)
parent84bae6c379e362aa017efd417199f51d5c2273ac (diff)
Merge branch 'next/dt' into next/multiplatform
* next/dt: (182 commits) ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support ARM: tegra: Add Avionic Design Medcom-Wide support ARM: tegra: Add Avionic Design Plutux support ARM: tegra: Add Avionic Design Tamonten support ARM: tegra: dts: Add pwm label ARM: dt: tegra: whistler: configure power off ARM: mxs: m28evk: Disable OCOTP OUI loading ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent ARM: dts: imx6q-sabrelite: add usbotg pinctrl support ARM: dts: imx23-olinuxino: Add USB host support ARM: dts: imx6q-sabrelite: add usbmisc device ARM: dts: mx23: Add USB resources ARM: dts: mxs: Add ethernetX to macX aliases ARM: msm: Remove non-DT targets from 8960 ARM: msm: Add DT support for 8960 ARM: msm: Move io mapping prototypes to common.h ARM: msm: Rename board-msm8x60 to signify its DT only status ARM: msm: Make 8660 a DT only target ARM: msm: Move 8660 to DT timer ARM: msm: Add DT support to msm_timer ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/Kconfig13
-rw-r--r--drivers/clk/Makefile8
-rw-r--r--drivers/clk/clk-ls1x.c111
-rw-r--r--drivers/clk/clk-max77686.c244
-rw-r--r--drivers/clk/clk.c57
-rw-r--r--drivers/clk/mmp/Makefile9
-rw-r--r--drivers/clk/mmp/clk-apbc.c152
-rw-r--r--drivers/clk/mmp/clk-apmu.c97
-rw-r--r--drivers/clk/mmp/clk-frac.c153
-rw-r--r--drivers/clk/mmp/clk-mmp2.c449
-rw-r--r--drivers/clk/mmp/clk-pxa168.c346
-rw-r--r--drivers/clk/mmp/clk-pxa910.c320
-rw-r--r--drivers/clk/mmp/clk.h35
-rw-r--r--drivers/clk/mxs/clk-imx23.c55
-rw-r--r--drivers/clk/mxs/clk-imx28.c113
-rw-r--r--drivers/clk/ux500/Makefile12
-rw-r--r--drivers/clk/ux500/clk-prcc.c164
-rw-r--r--drivers/clk/ux500/clk-prcmu.c252
-rw-r--r--drivers/clk/ux500/clk.h48
-rw-r--r--drivers/clk/ux500/u8500_clk.c477
-rw-r--r--drivers/clk/ux500/u8540_clk.c21
-rw-r--r--drivers/clk/ux500/u9540_clk.c21
-rw-r--r--drivers/clk/versatile/Makefile1
-rw-r--r--drivers/clk/versatile/clk-realview.c114
-rw-r--r--drivers/gpio/gpio-pxa.c77
-rw-r--r--drivers/gpio/gpio-samsung.c63
-rw-r--r--drivers/gpio/gpio-twl4030.c77
-rw-r--r--drivers/mfd/db8500-prcmu.c42
-rw-r--r--drivers/mfd/dbx500-prcmu-regs.h4
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c87
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c58
-rw-r--r--drivers/rtc/rtc-pxa.c11
32 files changed, 3427 insertions, 264 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7f0b5ca78516..bace9e98f75d 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -40,4 +40,17 @@ config COMMON_CLK_WM831X
40 Supports the clocking subsystem of the WM831x/2x series of 40 Supports the clocking subsystem of the WM831x/2x series of
41 PMICs from Wolfson Microlectronics. 41 PMICs from Wolfson Microlectronics.
42 42
43config COMMON_CLK_VERSATILE
44 bool "Clock driver for ARM Reference designs"
45 depends on ARCH_INTEGRATOR || ARCH_REALVIEW
46 ---help---
47 Supports clocking on ARM Reference designs Integrator/AP,
48 Integrator/CP, RealView PB1176, EB, PB11MP and PBX.
49
50config COMMON_CLK_MAX77686
51 tristate "Clock driver for Maxim 77686 MFD"
52 depends on MFD_MAX77686
53 ---help---
54 This driver supports Maxim 77686 crystal oscillator clock.
55
43endmenu 56endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d4c7253eb307..6327536b4900 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,8 +9,14 @@ obj-$(CONFIG_ARCH_MXS) += mxs/
9obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/ 9obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
10obj-$(CONFIG_PLAT_SPEAR) += spear/ 10obj-$(CONFIG_PLAT_SPEAR) += spear/
11obj-$(CONFIG_ARCH_U300) += clk-u300.o 11obj-$(CONFIG_ARCH_U300) += clk-u300.o
12obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/ 12obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
13obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o 13obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o
14ifeq ($(CONFIG_COMMON_CLK), y)
15obj-$(CONFIG_ARCH_MMP) += mmp/
16endif
17obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
18obj-$(CONFIG_ARCH_U8500) += ux500/
14 19
15# Chip specific 20# Chip specific
16obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 21obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
22obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
new file mode 100644
index 000000000000..f20b750235f6
--- /dev/null
+++ b/drivers/clk/clk-ls1x.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/clkdev.h>
11#include <linux/clk-provider.h>
12#include <linux/io.h>
13#include <linux/slab.h>
14#include <linux/err.h>
15
16#include <loongson1.h>
17
18#define OSC 33
19
20static DEFINE_SPINLOCK(_lock);
21
22static int ls1x_pll_clk_enable(struct clk_hw *hw)
23{
24 return 0;
25}
26
27static void ls1x_pll_clk_disable(struct clk_hw *hw)
28{
29}
30
31static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
32 unsigned long parent_rate)
33{
34 u32 pll, rate;
35
36 pll = __raw_readl(LS1X_CLK_PLL_FREQ);
37 rate = ((12 + (pll & 0x3f)) * 1000000) +
38 ((((pll >> 8) & 0x3ff) * 1000000) >> 10);
39 rate *= OSC;
40 rate >>= 1;
41
42 return rate;
43}
44
45static const struct clk_ops ls1x_pll_clk_ops = {
46 .enable = ls1x_pll_clk_enable,
47 .disable = ls1x_pll_clk_disable,
48 .recalc_rate = ls1x_pll_recalc_rate,
49};
50
51static struct clk * __init clk_register_pll(struct device *dev,
52 const char *name, const char *parent_name, unsigned long flags)
53{
54 struct clk_hw *hw;
55 struct clk *clk;
56 struct clk_init_data init;
57
58 /* allocate the divider */
59 hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);
60 if (!hw) {
61 pr_err("%s: could not allocate clk_hw\n", __func__);
62 return ERR_PTR(-ENOMEM);
63 }
64
65 init.name = name;
66 init.ops = &ls1x_pll_clk_ops;
67 init.flags = flags | CLK_IS_BASIC;
68 init.parent_names = (parent_name ? &parent_name : NULL);
69 init.num_parents = (parent_name ? 1 : 0);
70 hw->init = &init;
71
72 /* register the clock */
73 clk = clk_register(dev, hw);
74
75 if (IS_ERR(clk))
76 kfree(hw);
77
78 return clk;
79}
80
81void __init ls1x_clk_init(void)
82{
83 struct clk *clk;
84
85 clk = clk_register_pll(NULL, "pll_clk", NULL, CLK_IS_ROOT);
86 clk_prepare_enable(clk);
87
88 clk = clk_register_divider(NULL, "cpu_clk", "pll_clk",
89 CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_CPU_SHIFT,
90 DIV_CPU_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
91 clk_prepare_enable(clk);
92 clk_register_clkdev(clk, "cpu", NULL);
93
94 clk = clk_register_divider(NULL, "dc_clk", "pll_clk",
95 CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
96 DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
97 clk_prepare_enable(clk);
98 clk_register_clkdev(clk, "dc", NULL);
99
100 clk = clk_register_divider(NULL, "ahb_clk", "pll_clk",
101 CLK_SET_RATE_PARENT, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
102 DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
103 clk_prepare_enable(clk);
104 clk_register_clkdev(clk, "ahb", NULL);
105 clk_register_clkdev(clk, "stmmaceth", NULL);
106
107 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 2);
108 clk_prepare_enable(clk);
109 clk_register_clkdev(clk, "apb", NULL);
110 clk_register_clkdev(clk, "serial8250", NULL);
111}
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
new file mode 100644
index 000000000000..ac5f5434cb9a
--- /dev/null
+++ b/drivers/clk/clk-max77686.c
@@ -0,0 +1,244 @@
1/*
2 * clk-max77686.c - Clock driver for Maxim 77686
3 *
4 * Copyright (C) 2012 Samsung Electornics
5 * Jonghwa Lee <jonghwa3.lee@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#include <linux/kernel.h>
24#include <linux/slab.h>
25#include <linux/err.h>
26#include <linux/platform_device.h>
27#include <linux/mfd/max77686.h>
28#include <linux/mfd/max77686-private.h>
29#include <linux/clk-provider.h>
30#include <linux/mutex.h>
31#include <linux/clkdev.h>
32
33enum {
34 MAX77686_CLK_AP = 0,
35 MAX77686_CLK_CP,
36 MAX77686_CLK_PMIC,
37 MAX77686_CLKS_NUM,
38};
39
40struct max77686_clk {
41 struct max77686_dev *iodev;
42 u32 mask;
43 struct clk_hw hw;
44 struct clk_lookup *lookup;
45};
46
47static struct max77686_clk *get_max77686_clk(struct clk_hw *hw)
48{
49 return container_of(hw, struct max77686_clk, hw);
50}
51
52static int max77686_clk_prepare(struct clk_hw *hw)
53{
54 struct max77686_clk *max77686;
55 int ret;
56
57 max77686 = get_max77686_clk(hw);
58 if (!max77686)
59 return -ENOMEM;
60
61 ret = regmap_update_bits(max77686->iodev->regmap,
62 MAX77686_REG_32KHZ, max77686->mask, max77686->mask);
63
64 return ret;
65}
66
67static void max77686_clk_unprepare(struct clk_hw *hw)
68{
69 struct max77686_clk *max77686;
70
71 max77686 = get_max77686_clk(hw);
72 if (!max77686)
73 return;
74
75 regmap_update_bits(max77686->iodev->regmap,
76 MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask);
77}
78
79static int max77686_clk_is_enabled(struct clk_hw *hw)
80{
81 struct max77686_clk *max77686;
82 int ret;
83 u32 val;
84
85 max77686 = get_max77686_clk(hw);
86 if (!max77686)
87 return -ENOMEM;
88
89 ret = regmap_read(max77686->iodev->regmap,
90 MAX77686_REG_32KHZ, &val);
91
92 if (ret < 0)
93 return -EINVAL;
94
95 return val & max77686->mask;
96}
97
98static struct clk_ops max77686_clk_ops = {
99 .prepare = max77686_clk_prepare,
100 .unprepare = max77686_clk_unprepare,
101 .is_enabled = max77686_clk_is_enabled,
102};
103
104static struct clk_init_data max77686_clks_init[MAX77686_CLKS_NUM] = {
105 [MAX77686_CLK_AP] = {
106 .name = "32khz_ap",
107 .ops = &max77686_clk_ops,
108 .flags = CLK_IS_ROOT,
109 },
110 [MAX77686_CLK_CP] = {
111 .name = "32khz_cp",
112 .ops = &max77686_clk_ops,
113 .flags = CLK_IS_ROOT,
114 },
115 [MAX77686_CLK_PMIC] = {
116 .name = "32khz_pmic",
117 .ops = &max77686_clk_ops,
118 .flags = CLK_IS_ROOT,
119 },
120};
121
122static int max77686_clk_register(struct device *dev,
123 struct max77686_clk *max77686)
124{
125 struct clk *clk;
126 struct clk_hw *hw = &max77686->hw;
127
128 clk = clk_register(dev, hw);
129
130 if (IS_ERR(clk))
131 return -ENOMEM;
132
133 max77686->lookup = devm_kzalloc(dev, sizeof(struct clk_lookup),
134 GFP_KERNEL);
135 if (IS_ERR(max77686->lookup))
136 return -ENOMEM;
137
138 max77686->lookup->con_id = hw->init->name;
139 max77686->lookup->clk = clk;
140
141 clkdev_add(max77686->lookup);
142
143 return 0;
144}
145
146static __devinit int max77686_clk_probe(struct platform_device *pdev)
147{
148 struct max77686_dev *iodev = dev_get_drvdata(pdev->dev.parent);
149 struct max77686_clk **max77686_clks;
150 int i, ret;
151
152 max77686_clks = devm_kzalloc(&pdev->dev, sizeof(struct max77686_clk *)
153 * MAX77686_CLKS_NUM, GFP_KERNEL);
154 if (IS_ERR(max77686_clks))
155 return -ENOMEM;
156
157 for (i = 0; i < MAX77686_CLKS_NUM; i++) {
158 max77686_clks[i] = devm_kzalloc(&pdev->dev,
159 sizeof(struct max77686_clk), GFP_KERNEL);
160 if (IS_ERR(max77686_clks[i]))
161 return -ENOMEM;
162 }
163
164 for (i = 0; i < MAX77686_CLKS_NUM; i++) {
165 max77686_clks[i]->iodev = iodev;
166 max77686_clks[i]->mask = 1 << i;
167 max77686_clks[i]->hw.init = &max77686_clks_init[i];
168
169 ret = max77686_clk_register(&pdev->dev, max77686_clks[i]);
170 if (ret) {
171 switch (i) {
172 case MAX77686_CLK_AP:
173 dev_err(&pdev->dev, "Fail to register CLK_AP\n");
174 goto err_clk_ap;
175 break;
176 case MAX77686_CLK_CP:
177 dev_err(&pdev->dev, "Fail to register CLK_CP\n");
178 goto err_clk_cp;
179 break;
180 case MAX77686_CLK_PMIC:
181 dev_err(&pdev->dev, "Fail to register CLK_PMIC\n");
182 goto err_clk_pmic;
183 }
184 }
185 }
186
187 platform_set_drvdata(pdev, max77686_clks);
188
189 goto out;
190
191err_clk_pmic:
192 clkdev_drop(max77686_clks[MAX77686_CLK_CP]->lookup);
193 kfree(max77686_clks[MAX77686_CLK_CP]->hw.clk);
194err_clk_cp:
195 clkdev_drop(max77686_clks[MAX77686_CLK_AP]->lookup);
196 kfree(max77686_clks[MAX77686_CLK_AP]->hw.clk);
197err_clk_ap:
198out:
199 return ret;
200}
201
202static int __devexit max77686_clk_remove(struct platform_device *pdev)
203{
204 struct max77686_clk **max77686_clks = platform_get_drvdata(pdev);
205 int i;
206
207 for (i = 0; i < MAX77686_CLKS_NUM; i++) {
208 clkdev_drop(max77686_clks[i]->lookup);
209 kfree(max77686_clks[i]->hw.clk);
210 }
211 return 0;
212}
213
214static const struct platform_device_id max77686_clk_id[] = {
215 { "max77686-clk", 0},
216 { },
217};
218MODULE_DEVICE_TABLE(platform, max77686_clk_id);
219
220static struct platform_driver max77686_clk_driver = {
221 .driver = {
222 .name = "max77686-clk",
223 .owner = THIS_MODULE,
224 },
225 .probe = max77686_clk_probe,
226 .remove = __devexit_p(max77686_clk_remove),
227 .id_table = max77686_clk_id,
228};
229
230static int __init max77686_clk_init(void)
231{
232 return platform_driver_register(&max77686_clk_driver);
233}
234subsys_initcall(max77686_clk_init);
235
236static void __init max77686_clk_cleanup(void)
237{
238 platform_driver_unregister(&max77686_clk_driver);
239}
240module_exit(max77686_clk_cleanup);
241
242MODULE_DESCRIPTION("MAXIM 77686 Clock Driver");
243MODULE_AUTHOR("Jonghwa Lee <jonghwa3.lee@samsung.com>");
244MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index efdfd009c270..56e4495ebeb1 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -558,25 +558,6 @@ int clk_enable(struct clk *clk)
558EXPORT_SYMBOL_GPL(clk_enable); 558EXPORT_SYMBOL_GPL(clk_enable);
559 559
560/** 560/**
561 * clk_get_rate - return the rate of clk
562 * @clk: the clk whose rate is being returned
563 *
564 * Simply returns the cached rate of the clk. Does not query the hardware. If
565 * clk is NULL then returns 0.
566 */
567unsigned long clk_get_rate(struct clk *clk)
568{
569 unsigned long rate;
570
571 mutex_lock(&prepare_lock);
572 rate = __clk_get_rate(clk);
573 mutex_unlock(&prepare_lock);
574
575 return rate;
576}
577EXPORT_SYMBOL_GPL(clk_get_rate);
578
579/**
580 * __clk_round_rate - round the given rate for a clk 561 * __clk_round_rate - round the given rate for a clk
581 * @clk: round the rate of this clock 562 * @clk: round the rate of this clock
582 * 563 *
@@ -702,6 +683,30 @@ static void __clk_recalc_rates(struct clk *clk, unsigned long msg)
702} 683}
703 684
704/** 685/**
686 * clk_get_rate - return the rate of clk
687 * @clk: the clk whose rate is being returned
688 *
689 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
690 * is set, which means a recalc_rate will be issued.
691 * If clk is NULL then returns 0.
692 */
693unsigned long clk_get_rate(struct clk *clk)
694{
695 unsigned long rate;
696
697 mutex_lock(&prepare_lock);
698
699 if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
700 __clk_recalc_rates(clk, 0);
701
702 rate = __clk_get_rate(clk);
703 mutex_unlock(&prepare_lock);
704
705 return rate;
706}
707EXPORT_SYMBOL_GPL(clk_get_rate);
708
709/**
705 * __clk_speculate_rates 710 * __clk_speculate_rates
706 * @clk: first clk in the subtree 711 * @clk: first clk in the subtree
707 * @parent_rate: the "future" rate of clk's parent 712 * @parent_rate: the "future" rate of clk's parent
@@ -1582,6 +1587,20 @@ struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1582} 1587}
1583EXPORT_SYMBOL_GPL(of_clk_src_simple_get); 1588EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
1584 1589
1590struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
1591{
1592 struct clk_onecell_data *clk_data = data;
1593 unsigned int idx = clkspec->args[0];
1594
1595 if (idx >= clk_data->clk_num) {
1596 pr_err("%s: invalid clock index %d\n", __func__, idx);
1597 return ERR_PTR(-EINVAL);
1598 }
1599
1600 return clk_data->clks[idx];
1601}
1602EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
1603
1585/** 1604/**
1586 * of_clk_add_provider() - Register a clock provider for a node 1605 * of_clk_add_provider() - Register a clock provider for a node
1587 * @np: Device node pointer associated with clock provider 1606 * @np: Device node pointer associated with clock provider
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
new file mode 100644
index 000000000000..392d78044ce3
--- /dev/null
+++ b/drivers/clk/mmp/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for mmp specific clk
3#
4
5obj-y += clk-apbc.o clk-apmu.o clk-frac.o
6
7obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
8obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
9obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c
new file mode 100644
index 000000000000..d14120eaa71f
--- /dev/null
+++ b/drivers/clk/mmp/clk-apbc.c
@@ -0,0 +1,152 @@
1/*
2 * mmp APB clock operation source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/clk.h>
14#include <linux/io.h>
15#include <linux/err.h>
16#include <linux/delay.h>
17#include <linux/slab.h>
18
19#include "clk.h"
20
21/* Common APB clock register bit definitions */
22#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
23#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
24#define APBC_RST (1 << 2) /* Reset Generation */
25#define APBC_POWER (1 << 7) /* Reset Generation */
26
27#define to_clk_apbc(hw) container_of(hw, struct clk_apbc, hw)
28struct clk_apbc {
29 struct clk_hw hw;
30 void __iomem *base;
31 unsigned int delay;
32 unsigned int flags;
33 spinlock_t *lock;
34};
35
36static int clk_apbc_prepare(struct clk_hw *hw)
37{
38 struct clk_apbc *apbc = to_clk_apbc(hw);
39 unsigned int data;
40 unsigned long flags = 0;
41
42 /*
43 * It may share same register as MUX clock,
44 * and it will impact FNCLK enable. Spinlock is needed
45 */
46 if (apbc->lock)
47 spin_lock_irqsave(apbc->lock, flags);
48
49 data = readl_relaxed(apbc->base);
50 if (apbc->flags & APBC_POWER_CTRL)
51 data |= APBC_POWER;
52 data |= APBC_FNCLK;
53 writel_relaxed(data, apbc->base);
54
55 if (apbc->lock)
56 spin_unlock_irqrestore(apbc->lock, flags);
57
58 udelay(apbc->delay);
59
60 if (apbc->lock)
61 spin_lock_irqsave(apbc->lock, flags);
62
63 data = readl_relaxed(apbc->base);
64 data |= APBC_APBCLK;
65 writel_relaxed(data, apbc->base);
66
67 if (apbc->lock)
68 spin_unlock_irqrestore(apbc->lock, flags);
69
70 udelay(apbc->delay);
71
72 if (!(apbc->flags & APBC_NO_BUS_CTRL)) {
73 if (apbc->lock)
74 spin_lock_irqsave(apbc->lock, flags);
75
76 data = readl_relaxed(apbc->base);
77 data &= ~APBC_RST;
78 writel_relaxed(data, apbc->base);
79
80 if (apbc->lock)
81 spin_unlock_irqrestore(apbc->lock, flags);
82 }
83
84 return 0;
85}
86
87static void clk_apbc_unprepare(struct clk_hw *hw)
88{
89 struct clk_apbc *apbc = to_clk_apbc(hw);
90 unsigned long data;
91 unsigned long flags = 0;
92
93 if (apbc->lock)
94 spin_lock_irqsave(apbc->lock, flags);
95
96 data = readl_relaxed(apbc->base);
97 if (apbc->flags & APBC_POWER_CTRL)
98 data &= ~APBC_POWER;
99 data &= ~APBC_FNCLK;
100 writel_relaxed(data, apbc->base);
101
102 if (apbc->lock)
103 spin_unlock_irqrestore(apbc->lock, flags);
104
105 udelay(10);
106
107 if (apbc->lock)
108 spin_lock_irqsave(apbc->lock, flags);
109
110 data = readl_relaxed(apbc->base);
111 data &= ~APBC_APBCLK;
112 writel_relaxed(data, apbc->base);
113
114 if (apbc->lock)
115 spin_unlock_irqrestore(apbc->lock, flags);
116}
117
118struct clk_ops clk_apbc_ops = {
119 .prepare = clk_apbc_prepare,
120 .unprepare = clk_apbc_unprepare,
121};
122
123struct clk *mmp_clk_register_apbc(const char *name, const char *parent_name,
124 void __iomem *base, unsigned int delay,
125 unsigned int apbc_flags, spinlock_t *lock)
126{
127 struct clk_apbc *apbc;
128 struct clk *clk;
129 struct clk_init_data init;
130
131 apbc = kzalloc(sizeof(*apbc), GFP_KERNEL);
132 if (!apbc)
133 return NULL;
134
135 init.name = name;
136 init.ops = &clk_apbc_ops;
137 init.flags = CLK_SET_RATE_PARENT;
138 init.parent_names = (parent_name ? &parent_name : NULL);
139 init.num_parents = (parent_name ? 1 : 0);
140
141 apbc->base = base;
142 apbc->delay = delay;
143 apbc->flags = apbc_flags;
144 apbc->lock = lock;
145 apbc->hw.init = &init;
146
147 clk = clk_register(NULL, &apbc->hw);
148 if (IS_ERR(clk))
149 kfree(apbc);
150
151 return clk;
152}
diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c
new file mode 100644
index 000000000000..abe182b2377f
--- /dev/null
+++ b/drivers/clk/mmp/clk-apmu.c
@@ -0,0 +1,97 @@
1/*
2 * mmp AXI peripharal clock operation source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/clk.h>
14#include <linux/io.h>
15#include <linux/err.h>
16#include <linux/delay.h>
17#include <linux/slab.h>
18
19#include "clk.h"
20
21#define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
22struct clk_apmu {
23 struct clk_hw hw;
24 void __iomem *base;
25 u32 rst_mask;
26 u32 enable_mask;
27 spinlock_t *lock;
28};
29
30static int clk_apmu_enable(struct clk_hw *hw)
31{
32 struct clk_apmu *apmu = to_clk_apmu(hw);
33 unsigned long data;
34 unsigned long flags = 0;
35
36 if (apmu->lock)
37 spin_lock_irqsave(apmu->lock, flags);
38
39 data = readl_relaxed(apmu->base) | apmu->enable_mask;
40 writel_relaxed(data, apmu->base);
41
42 if (apmu->lock)
43 spin_unlock_irqrestore(apmu->lock, flags);
44
45 return 0;
46}
47
48static void clk_apmu_disable(struct clk_hw *hw)
49{
50 struct clk_apmu *apmu = to_clk_apmu(hw);
51 unsigned long data;
52 unsigned long flags = 0;
53
54 if (apmu->lock)
55 spin_lock_irqsave(apmu->lock, flags);
56
57 data = readl_relaxed(apmu->base) & ~apmu->enable_mask;
58 writel_relaxed(data, apmu->base);
59
60 if (apmu->lock)
61 spin_unlock_irqrestore(apmu->lock, flags);
62}
63
64struct clk_ops clk_apmu_ops = {
65 .enable = clk_apmu_enable,
66 .disable = clk_apmu_disable,
67};
68
69struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name,
70 void __iomem *base, u32 enable_mask, spinlock_t *lock)
71{
72 struct clk_apmu *apmu;
73 struct clk *clk;
74 struct clk_init_data init;
75
76 apmu = kzalloc(sizeof(*apmu), GFP_KERNEL);
77 if (!apmu)
78 return NULL;
79
80 init.name = name;
81 init.ops = &clk_apmu_ops;
82 init.flags = CLK_SET_RATE_PARENT;
83 init.parent_names = (parent_name ? &parent_name : NULL);
84 init.num_parents = (parent_name ? 1 : 0);
85
86 apmu->base = base;
87 apmu->enable_mask = enable_mask;
88 apmu->lock = lock;
89 apmu->hw.init = &init;
90
91 clk = clk_register(NULL, &apmu->hw);
92
93 if (IS_ERR(clk))
94 kfree(apmu);
95
96 return clk;
97}
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
new file mode 100644
index 000000000000..80c1dd15d15c
--- /dev/null
+++ b/drivers/clk/mmp/clk-frac.c
@@ -0,0 +1,153 @@
1/*
2 * mmp factor clock operation source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/err.h>
16
17#include "clk.h"
18/*
19 * It is M/N clock
20 *
21 * Fout from synthesizer can be given from two equations:
22 * numerator/denominator = Fin / (Fout * factor)
23 */
24
25#define to_clk_factor(hw) container_of(hw, struct clk_factor, hw)
26struct clk_factor {
27 struct clk_hw hw;
28 void __iomem *base;
29 struct clk_factor_masks *masks;
30 struct clk_factor_tbl *ftbl;
31 unsigned int ftbl_cnt;
32};
33
34static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
35 unsigned long *prate)
36{
37 struct clk_factor *factor = to_clk_factor(hw);
38 unsigned long rate = 0, prev_rate;
39 int i;
40
41 for (i = 0; i < factor->ftbl_cnt; i++) {
42 prev_rate = rate;
43 rate = (((*prate / 10000) * factor->ftbl[i].num) /
44 (factor->ftbl[i].den * factor->masks->factor)) * 10000;
45 if (rate > drate)
46 break;
47 }
48 if (i == 0)
49 return rate;
50 else
51 return prev_rate;
52}
53
54static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
55 unsigned long parent_rate)
56{
57 struct clk_factor *factor = to_clk_factor(hw);
58 struct clk_factor_masks *masks = factor->masks;
59 unsigned int val, num, den;
60
61 val = readl_relaxed(factor->base);
62
63 /* calculate numerator */
64 num = (val >> masks->num_shift) & masks->num_mask;
65
66 /* calculate denominator */
67 den = (val >> masks->den_shift) & masks->num_mask;
68
69 if (!den)
70 return 0;
71
72 return (((parent_rate / 10000) * den) /
73 (num * factor->masks->factor)) * 10000;
74}
75
76/* Configures new clock rate*/
77static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
78 unsigned long prate)
79{
80 struct clk_factor *factor = to_clk_factor(hw);
81 struct clk_factor_masks *masks = factor->masks;
82 int i;
83 unsigned long val;
84 unsigned long prev_rate, rate = 0;
85
86 for (i = 0; i < factor->ftbl_cnt; i++) {
87 prev_rate = rate;
88 rate = (((prate / 10000) * factor->ftbl[i].num) /
89 (factor->ftbl[i].den * factor->masks->factor)) * 10000;
90 if (rate > drate)
91 break;
92 }
93 if (i > 0)
94 i--;
95
96 val = readl_relaxed(factor->base);
97
98 val &= ~(masks->num_mask << masks->num_shift);
99 val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift;
100
101 val &= ~(masks->den_mask << masks->den_shift);
102 val |= (factor->ftbl[i].den & masks->den_mask) << masks->den_shift;
103
104 writel_relaxed(val, factor->base);
105
106 return 0;
107}
108
109static struct clk_ops clk_factor_ops = {
110 .recalc_rate = clk_factor_recalc_rate,
111 .round_rate = clk_factor_round_rate,
112 .set_rate = clk_factor_set_rate,
113};
114
115struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
116 unsigned long flags, void __iomem *base,
117 struct clk_factor_masks *masks, struct clk_factor_tbl *ftbl,
118 unsigned int ftbl_cnt)
119{
120 struct clk_factor *factor;
121 struct clk_init_data init;
122 struct clk *clk;
123
124 if (!masks) {
125 pr_err("%s: must pass a clk_factor_mask\n", __func__);
126 return ERR_PTR(-EINVAL);
127 }
128
129 factor = kzalloc(sizeof(*factor), GFP_KERNEL);
130 if (!factor) {
131 pr_err("%s: could not allocate factor clk\n", __func__);
132 return ERR_PTR(-ENOMEM);
133 }
134
135 /* struct clk_aux assignments */
136 factor->base = base;
137 factor->masks = masks;
138 factor->ftbl = ftbl;
139 factor->ftbl_cnt = ftbl_cnt;
140 factor->hw.init = &init;
141
142 init.name = name;
143 init.ops = &clk_factor_ops;
144 init.flags = flags;
145 init.parent_names = &parent_name;
146 init.num_parents = 1;
147
148 clk = clk_register(NULL, &factor->hw);
149 if (IS_ERR_OR_NULL(clk))
150 kfree(factor);
151
152 return clk;
153}
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
new file mode 100644
index 000000000000..ade435820c7e
--- /dev/null
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -0,0 +1,449 @@
1/*
2 * mmp2 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18
19#include <mach/addr-map.h>
20
21#include "clk.h"
22
23#define APBC_RTC 0x0
24#define APBC_TWSI0 0x4
25#define APBC_TWSI1 0x8
26#define APBC_TWSI2 0xc
27#define APBC_TWSI3 0x10
28#define APBC_TWSI4 0x7c
29#define APBC_TWSI5 0x80
30#define APBC_KPC 0x18
31#define APBC_UART0 0x2c
32#define APBC_UART1 0x30
33#define APBC_UART2 0x34
34#define APBC_UART3 0x88
35#define APBC_GPIO 0x38
36#define APBC_PWM0 0x3c
37#define APBC_PWM1 0x40
38#define APBC_PWM2 0x44
39#define APBC_PWM3 0x48
40#define APBC_SSP0 0x50
41#define APBC_SSP1 0x54
42#define APBC_SSP2 0x58
43#define APBC_SSP3 0x5c
44#define APMU_SDH0 0x54
45#define APMU_SDH1 0x58
46#define APMU_SDH2 0xe8
47#define APMU_SDH3 0xec
48#define APMU_USB 0x5c
49#define APMU_DISP0 0x4c
50#define APMU_DISP1 0x110
51#define APMU_CCIC0 0x50
52#define APMU_CCIC1 0xf4
53#define MPMU_UART_PLL 0x14
54
55static DEFINE_SPINLOCK(clk_lock);
56
57static struct clk_factor_masks uart_factor_masks = {
58 .factor = 2,
59 .num_mask = 0x1fff,
60 .den_mask = 0x1fff,
61 .num_shift = 16,
62 .den_shift = 0,
63};
64
65static struct clk_factor_tbl uart_factor_tbl[] = {
66 {.num = 14634, .den = 2165}, /*14.745MHZ */
67 {.num = 3521, .den = 689}, /*19.23MHZ */
68 {.num = 9679, .den = 5728}, /*58.9824MHZ */
69 {.num = 15850, .den = 9451}, /*59.429MHZ */
70};
71
72static const char *uart_parent[] = {"uart_pll", "vctcxo"};
73static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
74static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
75static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
76static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
77
78void __init mmp2_clk_init(void)
79{
80 struct clk *clk;
81 struct clk *vctcxo;
82 void __iomem *mpmu_base;
83 void __iomem *apmu_base;
84 void __iomem *apbc_base;
85
86 mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
87 if (mpmu_base == NULL) {
88 pr_err("error to ioremap MPMU base\n");
89 return;
90 }
91
92 apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
93 if (apmu_base == NULL) {
94 pr_err("error to ioremap APMU base\n");
95 return;
96 }
97
98 apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
99 if (apbc_base == NULL) {
100 pr_err("error to ioremap APBC base\n");
101 return;
102 }
103
104 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
105 clk_register_clkdev(clk, "clk32", NULL);
106
107 vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
108 26000000);
109 clk_register_clkdev(vctcxo, "vctcxo", NULL);
110
111 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
112 800000000);
113 clk_register_clkdev(clk, "pll1", NULL);
114
115 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
116 480000000);
117 clk_register_clkdev(clk, "usb_pll", NULL);
118
119 clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
120 960000000);
121 clk_register_clkdev(clk, "pll2", NULL);
122
123 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
124 CLK_SET_RATE_PARENT, 1, 2);
125 clk_register_clkdev(clk, "pll1_2", NULL);
126
127 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
128 CLK_SET_RATE_PARENT, 1, 2);
129 clk_register_clkdev(clk, "pll1_4", NULL);
130
131 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
132 CLK_SET_RATE_PARENT, 1, 2);
133 clk_register_clkdev(clk, "pll1_8", NULL);
134
135 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
136 CLK_SET_RATE_PARENT, 1, 2);
137 clk_register_clkdev(clk, "pll1_16", NULL);
138
139 clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
140 CLK_SET_RATE_PARENT, 1, 5);
141 clk_register_clkdev(clk, "pll1_20", NULL);
142
143 clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
144 CLK_SET_RATE_PARENT, 1, 3);
145 clk_register_clkdev(clk, "pll1_3", NULL);
146
147 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
148 CLK_SET_RATE_PARENT, 1, 2);
149 clk_register_clkdev(clk, "pll1_6", NULL);
150
151 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
152 CLK_SET_RATE_PARENT, 1, 2);
153 clk_register_clkdev(clk, "pll1_12", NULL);
154
155 clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
156 CLK_SET_RATE_PARENT, 1, 2);
157 clk_register_clkdev(clk, "pll2_2", NULL);
158
159 clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
160 CLK_SET_RATE_PARENT, 1, 2);
161 clk_register_clkdev(clk, "pll2_4", NULL);
162
163 clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
164 CLK_SET_RATE_PARENT, 1, 2);
165 clk_register_clkdev(clk, "pll2_8", NULL);
166
167 clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
168 CLK_SET_RATE_PARENT, 1, 2);
169 clk_register_clkdev(clk, "pll2_16", NULL);
170
171 clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
172 CLK_SET_RATE_PARENT, 1, 3);
173 clk_register_clkdev(clk, "pll2_3", NULL);
174
175 clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
176 CLK_SET_RATE_PARENT, 1, 2);
177 clk_register_clkdev(clk, "pll2_6", NULL);
178
179 clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
180 CLK_SET_RATE_PARENT, 1, 2);
181 clk_register_clkdev(clk, "pll2_12", NULL);
182
183 clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
184 CLK_SET_RATE_PARENT, 1, 2);
185 clk_register_clkdev(clk, "vctcxo_2", NULL);
186
187 clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
188 CLK_SET_RATE_PARENT, 1, 2);
189 clk_register_clkdev(clk, "vctcxo_4", NULL);
190
191 clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
192 mpmu_base + MPMU_UART_PLL,
193 &uart_factor_masks, uart_factor_tbl,
194 ARRAY_SIZE(uart_factor_tbl));
195 clk_set_rate(clk, 14745600);
196 clk_register_clkdev(clk, "uart_pll", NULL);
197
198 clk = mmp_clk_register_apbc("twsi0", "vctcxo",
199 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
200 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
201
202 clk = mmp_clk_register_apbc("twsi1", "vctcxo",
203 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
204 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
205
206 clk = mmp_clk_register_apbc("twsi2", "vctcxo",
207 apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
208 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
209
210 clk = mmp_clk_register_apbc("twsi3", "vctcxo",
211 apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
212 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
213
214 clk = mmp_clk_register_apbc("twsi4", "vctcxo",
215 apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
216 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
217
218 clk = mmp_clk_register_apbc("twsi5", "vctcxo",
219 apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
220 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
221
222 clk = mmp_clk_register_apbc("gpio", "vctcxo",
223 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
224 clk_register_clkdev(clk, NULL, "pxa-gpio");
225
226 clk = mmp_clk_register_apbc("kpc", "clk32",
227 apbc_base + APBC_KPC, 10, 0, &clk_lock);
228 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
229
230 clk = mmp_clk_register_apbc("rtc", "clk32",
231 apbc_base + APBC_RTC, 10, 0, &clk_lock);
232 clk_register_clkdev(clk, NULL, "mmp-rtc");
233
234 clk = mmp_clk_register_apbc("pwm0", "vctcxo",
235 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
236 clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
237
238 clk = mmp_clk_register_apbc("pwm1", "vctcxo",
239 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
240 clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
241
242 clk = mmp_clk_register_apbc("pwm2", "vctcxo",
243 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
244 clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
245
246 clk = mmp_clk_register_apbc("pwm3", "vctcxo",
247 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
248 clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
249
250 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
251 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
252 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
253 clk_set_parent(clk, vctcxo);
254 clk_register_clkdev(clk, "uart_mux.0", NULL);
255
256 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
257 apbc_base + APBC_UART0, 10, 0, &clk_lock);
258 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
259
260 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
261 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
262 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
263 clk_set_parent(clk, vctcxo);
264 clk_register_clkdev(clk, "uart_mux.1", NULL);
265
266 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
267 apbc_base + APBC_UART1, 10, 0, &clk_lock);
268 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
269
270 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
271 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
272 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
273 clk_set_parent(clk, vctcxo);
274 clk_register_clkdev(clk, "uart_mux.2", NULL);
275
276 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
277 apbc_base + APBC_UART2, 10, 0, &clk_lock);
278 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
279
280 clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
281 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
282 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
283 clk_set_parent(clk, vctcxo);
284 clk_register_clkdev(clk, "uart_mux.3", NULL);
285
286 clk = mmp_clk_register_apbc("uart3", "uart3_mux",
287 apbc_base + APBC_UART3, 10, 0, &clk_lock);
288 clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
289
290 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
291 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
292 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
293 clk_register_clkdev(clk, "uart_mux.0", NULL);
294
295 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
296 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
297 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
298
299 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
300 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
301 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
302 clk_register_clkdev(clk, "ssp_mux.1", NULL);
303
304 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
305 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
306 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
307
308 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
309 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
310 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
311 clk_register_clkdev(clk, "ssp_mux.2", NULL);
312
313 clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
314 apbc_base + APBC_SSP2, 10, 0, &clk_lock);
315 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
316
317 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
318 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
319 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
320 clk_register_clkdev(clk, "ssp_mux.3", NULL);
321
322 clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
323 apbc_base + APBC_SSP3, 10, 0, &clk_lock);
324 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
325
326 clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
327 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
328 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
329 clk_register_clkdev(clk, "sdh_mux", NULL);
330
331 clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
332 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
333 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
334 clk_register_clkdev(clk, "sdh_div", NULL);
335
336 clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
337 0x1b, &clk_lock);
338 clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
339
340 clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
341 0x1b, &clk_lock);
342 clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
343
344 clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
345 0x1b, &clk_lock);
346 clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
347
348 clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
349 0x1b, &clk_lock);
350 clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
351
352 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
353 0x9, &clk_lock);
354 clk_register_clkdev(clk, "usb_clk", NULL);
355
356 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
357 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
358 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
359 clk_register_clkdev(clk, "disp_mux.0", NULL);
360
361 clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
362 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
363 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
364 clk_register_clkdev(clk, "disp_div.0", NULL);
365
366 clk = mmp_clk_register_apmu("disp0", "disp0_div",
367 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
368 clk_register_clkdev(clk, NULL, "mmp-disp.0");
369
370 clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
371 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
372 clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
373
374 clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
375 apmu_base + APMU_DISP0, 0x1024, &clk_lock);
376 clk_register_clkdev(clk, "disp_sphy.0", NULL);
377
378 clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
379 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
380 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
381 clk_register_clkdev(clk, "disp_mux.1", NULL);
382
383 clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
384 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
385 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
386 clk_register_clkdev(clk, "disp_div.1", NULL);
387
388 clk = mmp_clk_register_apmu("disp1", "disp1_div",
389 apmu_base + APMU_DISP1, 0x1b, &clk_lock);
390 clk_register_clkdev(clk, NULL, "mmp-disp.1");
391
392 clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
393 apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
394 clk_register_clkdev(clk, "ccic_arbiter", NULL);
395
396 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
397 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
398 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
399 clk_register_clkdev(clk, "ccic_mux.0", NULL);
400
401 clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
402 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
403 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
404 clk_register_clkdev(clk, "ccic_div.0", NULL);
405
406 clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
407 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
408 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
409
410 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
411 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
412 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
413
414 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
415 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
416 10, 5, 0, &clk_lock);
417 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
418
419 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
420 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
421 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
422
423 clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
424 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
425 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
426 clk_register_clkdev(clk, "ccic_mux.1", NULL);
427
428 clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
429 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
430 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
431 clk_register_clkdev(clk, "ccic_div.1", NULL);
432
433 clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
434 apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
435 clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
436
437 clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
438 apmu_base + APMU_CCIC1, 0x24, &clk_lock);
439 clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
440
441 clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
442 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
443 10, 5, 0, &clk_lock);
444 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
445
446 clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
447 apmu_base + APMU_CCIC1, 0x300, &clk_lock);
448 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
449}
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
new file mode 100644
index 000000000000..e8d036c12cbf
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -0,0 +1,346 @@
1/*
2 * pxa168 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18
19#include <mach/addr-map.h>
20
21#include "clk.h"
22
23#define APBC_RTC 0x28
24#define APBC_TWSI0 0x2c
25#define APBC_KPC 0x30
26#define APBC_UART0 0x0
27#define APBC_UART1 0x4
28#define APBC_GPIO 0x8
29#define APBC_PWM0 0xc
30#define APBC_PWM1 0x10
31#define APBC_PWM2 0x14
32#define APBC_PWM3 0x18
33#define APBC_SSP0 0x81c
34#define APBC_SSP1 0x820
35#define APBC_SSP2 0x84c
36#define APBC_SSP3 0x858
37#define APBC_SSP4 0x85c
38#define APBC_TWSI1 0x6c
39#define APBC_UART2 0x70
40#define APMU_SDH0 0x54
41#define APMU_SDH1 0x58
42#define APMU_USB 0x5c
43#define APMU_DISP0 0x4c
44#define APMU_CCIC0 0x50
45#define APMU_DFC 0x60
46#define MPMU_UART_PLL 0x14
47
48static DEFINE_SPINLOCK(clk_lock);
49
50static struct clk_factor_masks uart_factor_masks = {
51 .factor = 2,
52 .num_mask = 0x1fff,
53 .den_mask = 0x1fff,
54 .num_shift = 16,
55 .den_shift = 0,
56};
57
58static struct clk_factor_tbl uart_factor_tbl[] = {
59 {.num = 8125, .den = 1536}, /*14.745MHZ */
60};
61
62static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
63static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
64static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
65static const char *disp_parent[] = {"pll1_2", "pll1_12"};
66static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
67static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
68
69void __init pxa168_clk_init(void)
70{
71 struct clk *clk;
72 struct clk *uart_pll;
73 void __iomem *mpmu_base;
74 void __iomem *apmu_base;
75 void __iomem *apbc_base;
76
77 mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
78 if (mpmu_base == NULL) {
79 pr_err("error to ioremap MPMU base\n");
80 return;
81 }
82
83 apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
84 if (apmu_base == NULL) {
85 pr_err("error to ioremap APMU base\n");
86 return;
87 }
88
89 apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
90 if (apbc_base == NULL) {
91 pr_err("error to ioremap APBC base\n");
92 return;
93 }
94
95 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
96 clk_register_clkdev(clk, "clk32", NULL);
97
98 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
99 26000000);
100 clk_register_clkdev(clk, "vctcxo", NULL);
101
102 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
103 624000000);
104 clk_register_clkdev(clk, "pll1", NULL);
105
106 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
107 CLK_SET_RATE_PARENT, 1, 2);
108 clk_register_clkdev(clk, "pll1_2", NULL);
109
110 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
111 CLK_SET_RATE_PARENT, 1, 2);
112 clk_register_clkdev(clk, "pll1_4", NULL);
113
114 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
115 CLK_SET_RATE_PARENT, 1, 2);
116 clk_register_clkdev(clk, "pll1_8", NULL);
117
118 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
119 CLK_SET_RATE_PARENT, 1, 2);
120 clk_register_clkdev(clk, "pll1_16", NULL);
121
122 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
123 CLK_SET_RATE_PARENT, 1, 3);
124 clk_register_clkdev(clk, "pll1_6", NULL);
125
126 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
127 CLK_SET_RATE_PARENT, 1, 2);
128 clk_register_clkdev(clk, "pll1_12", NULL);
129
130 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
131 CLK_SET_RATE_PARENT, 1, 2);
132 clk_register_clkdev(clk, "pll1_24", NULL);
133
134 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
135 CLK_SET_RATE_PARENT, 1, 2);
136 clk_register_clkdev(clk, "pll1_48", NULL);
137
138 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
139 CLK_SET_RATE_PARENT, 1, 2);
140 clk_register_clkdev(clk, "pll1_96", NULL);
141
142 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
143 CLK_SET_RATE_PARENT, 1, 13);
144 clk_register_clkdev(clk, "pll1_13", NULL);
145
146 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
147 CLK_SET_RATE_PARENT, 2, 3);
148 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
149
150 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
151 CLK_SET_RATE_PARENT, 2, 3);
152 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
153
154 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
155 CLK_SET_RATE_PARENT, 3, 16);
156 clk_register_clkdev(clk, "pll1_3_16", NULL);
157
158 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
159 mpmu_base + MPMU_UART_PLL,
160 &uart_factor_masks, uart_factor_tbl,
161 ARRAY_SIZE(uart_factor_tbl));
162 clk_set_rate(uart_pll, 14745600);
163 clk_register_clkdev(uart_pll, "uart_pll", NULL);
164
165 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
166 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
167 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
168
169 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
170 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
171 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
172
173 clk = mmp_clk_register_apbc("gpio", "vctcxo",
174 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
175 clk_register_clkdev(clk, NULL, "pxa-gpio");
176
177 clk = mmp_clk_register_apbc("kpc", "clk32",
178 apbc_base + APBC_KPC, 10, 0, &clk_lock);
179 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
180
181 clk = mmp_clk_register_apbc("rtc", "clk32",
182 apbc_base + APBC_RTC, 10, 0, &clk_lock);
183 clk_register_clkdev(clk, NULL, "sa1100-rtc");
184
185 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
186 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
187 clk_register_clkdev(clk, NULL, "pxa168-pwm.0");
188
189 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
190 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
191 clk_register_clkdev(clk, NULL, "pxa168-pwm.1");
192
193 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
194 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
195 clk_register_clkdev(clk, NULL, "pxa168-pwm.2");
196
197 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
198 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
199 clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
200
201 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
202 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
203 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
204 clk_set_parent(clk, uart_pll);
205 clk_register_clkdev(clk, "uart_mux.0", NULL);
206
207 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
208 apbc_base + APBC_UART0, 10, 0, &clk_lock);
209 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
210
211 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
212 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
213 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
214 clk_set_parent(clk, uart_pll);
215 clk_register_clkdev(clk, "uart_mux.1", NULL);
216
217 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
218 apbc_base + APBC_UART1, 10, 0, &clk_lock);
219 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
220
221 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
222 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
223 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
224 clk_set_parent(clk, uart_pll);
225 clk_register_clkdev(clk, "uart_mux.2", NULL);
226
227 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
228 apbc_base + APBC_UART2, 10, 0, &clk_lock);
229 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
230
231 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
232 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
233 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
234 clk_register_clkdev(clk, "uart_mux.0", NULL);
235
236 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0,
237 10, 0, &clk_lock);
238 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
239
240 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
241 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
242 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
243 clk_register_clkdev(clk, "ssp_mux.1", NULL);
244
245 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1,
246 10, 0, &clk_lock);
247 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
248
249 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
250 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
251 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
252 clk_register_clkdev(clk, "ssp_mux.2", NULL);
253
254 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2,
255 10, 0, &clk_lock);
256 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
257
258 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
259 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
260 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
261 clk_register_clkdev(clk, "ssp_mux.3", NULL);
262
263 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3,
264 10, 0, &clk_lock);
265 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
266
267 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
268 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
269 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
270 clk_register_clkdev(clk, "ssp_mux.4", NULL);
271
272 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4,
273 10, 0, &clk_lock);
274 clk_register_clkdev(clk, NULL, "mmp-ssp.4");
275
276 clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC,
277 0x19b, &clk_lock);
278 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
279
280 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
281 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
282 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
283 clk_register_clkdev(clk, "sdh0_mux", NULL);
284
285 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0,
286 0x1b, &clk_lock);
287 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
288
289 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
290 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
291 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
292 clk_register_clkdev(clk, "sdh1_mux", NULL);
293
294 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1,
295 0x1b, &clk_lock);
296 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
297
298 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
299 0x9, &clk_lock);
300 clk_register_clkdev(clk, "usb_clk", NULL);
301
302 clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB,
303 0x12, &clk_lock);
304 clk_register_clkdev(clk, "sph_clk", NULL);
305
306 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
307 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
308 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
309 clk_register_clkdev(clk, "disp_mux.0", NULL);
310
311 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
312 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
313 clk_register_clkdev(clk, "fnclk", "mmp-disp.0");
314
315 clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux",
316 apmu_base + APMU_DISP0, 0x24, &clk_lock);
317 clk_register_clkdev(clk, "hclk", "mmp-disp.0");
318
319 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
320 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
321 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
322 clk_register_clkdev(clk, "ccic_mux.0", NULL);
323
324 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
325 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
326 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
327
328 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
329 ARRAY_SIZE(ccic_phy_parent),
330 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
331 7, 1, 0, &clk_lock);
332 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
333
334 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
335 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
336 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
337
338 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
339 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
340 10, 5, 0, &clk_lock);
341 clk_register_clkdev(clk, "sphyclk_div", NULL);
342
343 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
344 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
345 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
346}
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
new file mode 100644
index 000000000000..7048c31d6e7e
--- /dev/null
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -0,0 +1,320 @@
1/*
2 * pxa910 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18
19#include <mach/addr-map.h>
20
21#include "clk.h"
22
23#define APBC_RTC 0x28
24#define APBC_TWSI0 0x2c
25#define APBC_KPC 0x18
26#define APBC_UART0 0x0
27#define APBC_UART1 0x4
28#define APBC_GPIO 0x8
29#define APBC_PWM0 0xc
30#define APBC_PWM1 0x10
31#define APBC_PWM2 0x14
32#define APBC_PWM3 0x18
33#define APBC_SSP0 0x1c
34#define APBC_SSP1 0x20
35#define APBC_SSP2 0x4c
36#define APBCP_TWSI1 0x28
37#define APBCP_UART2 0x1c
38#define APMU_SDH0 0x54
39#define APMU_SDH1 0x58
40#define APMU_USB 0x5c
41#define APMU_DISP0 0x4c
42#define APMU_CCIC0 0x50
43#define APMU_DFC 0x60
44#define MPMU_UART_PLL 0x14
45
46static DEFINE_SPINLOCK(clk_lock);
47
48static struct clk_factor_masks uart_factor_masks = {
49 .factor = 2,
50 .num_mask = 0x1fff,
51 .den_mask = 0x1fff,
52 .num_shift = 16,
53 .den_shift = 0,
54};
55
56static struct clk_factor_tbl uart_factor_tbl[] = {
57 {.num = 8125, .den = 1536}, /*14.745MHZ */
58};
59
60static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
61static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
62static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
63static const char *disp_parent[] = {"pll1_2", "pll1_12"};
64static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
65static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
66
67void __init pxa910_clk_init(void)
68{
69 struct clk *clk;
70 struct clk *uart_pll;
71 void __iomem *mpmu_base;
72 void __iomem *apmu_base;
73 void __iomem *apbcp_base;
74 void __iomem *apbc_base;
75
76 mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
77 if (mpmu_base == NULL) {
78 pr_err("error to ioremap MPMU base\n");
79 return;
80 }
81
82 apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
83 if (apmu_base == NULL) {
84 pr_err("error to ioremap APMU base\n");
85 return;
86 }
87
88 apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K);
89 if (apbcp_base == NULL) {
90 pr_err("error to ioremap APBC extension base\n");
91 return;
92 }
93
94 apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
95 if (apbc_base == NULL) {
96 pr_err("error to ioremap APBC base\n");
97 return;
98 }
99
100 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
101 clk_register_clkdev(clk, "clk32", NULL);
102
103 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
104 26000000);
105 clk_register_clkdev(clk, "vctcxo", NULL);
106
107 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
108 624000000);
109 clk_register_clkdev(clk, "pll1", NULL);
110
111 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
112 CLK_SET_RATE_PARENT, 1, 2);
113 clk_register_clkdev(clk, "pll1_2", NULL);
114
115 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
116 CLK_SET_RATE_PARENT, 1, 2);
117 clk_register_clkdev(clk, "pll1_4", NULL);
118
119 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
120 CLK_SET_RATE_PARENT, 1, 2);
121 clk_register_clkdev(clk, "pll1_8", NULL);
122
123 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
124 CLK_SET_RATE_PARENT, 1, 2);
125 clk_register_clkdev(clk, "pll1_16", NULL);
126
127 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
128 CLK_SET_RATE_PARENT, 1, 3);
129 clk_register_clkdev(clk, "pll1_6", NULL);
130
131 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
132 CLK_SET_RATE_PARENT, 1, 2);
133 clk_register_clkdev(clk, "pll1_12", NULL);
134
135 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
136 CLK_SET_RATE_PARENT, 1, 2);
137 clk_register_clkdev(clk, "pll1_24", NULL);
138
139 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
140 CLK_SET_RATE_PARENT, 1, 2);
141 clk_register_clkdev(clk, "pll1_48", NULL);
142
143 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
144 CLK_SET_RATE_PARENT, 1, 2);
145 clk_register_clkdev(clk, "pll1_96", NULL);
146
147 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
148 CLK_SET_RATE_PARENT, 1, 13);
149 clk_register_clkdev(clk, "pll1_13", NULL);
150
151 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
152 CLK_SET_RATE_PARENT, 2, 3);
153 clk_register_clkdev(clk, "pll1_13_1_5", NULL);
154
155 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
156 CLK_SET_RATE_PARENT, 2, 3);
157 clk_register_clkdev(clk, "pll1_2_1_5", NULL);
158
159 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
160 CLK_SET_RATE_PARENT, 3, 16);
161 clk_register_clkdev(clk, "pll1_3_16", NULL);
162
163 uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
164 mpmu_base + MPMU_UART_PLL,
165 &uart_factor_masks, uart_factor_tbl,
166 ARRAY_SIZE(uart_factor_tbl));
167 clk_set_rate(uart_pll, 14745600);
168 clk_register_clkdev(uart_pll, "uart_pll", NULL);
169
170 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
171 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
172 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
173
174 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
175 apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
176 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
177
178 clk = mmp_clk_register_apbc("gpio", "vctcxo",
179 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
180 clk_register_clkdev(clk, NULL, "pxa-gpio");
181
182 clk = mmp_clk_register_apbc("kpc", "clk32",
183 apbc_base + APBC_KPC, 10, 0, &clk_lock);
184 clk_register_clkdev(clk, NULL, "pxa27x-keypad");
185
186 clk = mmp_clk_register_apbc("rtc", "clk32",
187 apbc_base + APBC_RTC, 10, 0, &clk_lock);
188 clk_register_clkdev(clk, NULL, "sa1100-rtc");
189
190 clk = mmp_clk_register_apbc("pwm0", "pll1_48",
191 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
192 clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
193
194 clk = mmp_clk_register_apbc("pwm1", "pll1_48",
195 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
196 clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
197
198 clk = mmp_clk_register_apbc("pwm2", "pll1_48",
199 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
200 clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
201
202 clk = mmp_clk_register_apbc("pwm3", "pll1_48",
203 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
204 clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
205
206 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
207 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
208 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
209 clk_set_parent(clk, uart_pll);
210 clk_register_clkdev(clk, "uart_mux.0", NULL);
211
212 clk = mmp_clk_register_apbc("uart0", "uart0_mux",
213 apbc_base + APBC_UART0, 10, 0, &clk_lock);
214 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
215
216 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
217 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
218 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
219 clk_set_parent(clk, uart_pll);
220 clk_register_clkdev(clk, "uart_mux.1", NULL);
221
222 clk = mmp_clk_register_apbc("uart1", "uart1_mux",
223 apbc_base + APBC_UART1, 10, 0, &clk_lock);
224 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
225
226 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
227 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
228 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
229 clk_set_parent(clk, uart_pll);
230 clk_register_clkdev(clk, "uart_mux.2", NULL);
231
232 clk = mmp_clk_register_apbc("uart2", "uart2_mux",
233 apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
234 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
235
236 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
237 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
238 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
239 clk_register_clkdev(clk, "uart_mux.0", NULL);
240
241 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
242 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
243 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
244
245 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
246 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
247 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
248 clk_register_clkdev(clk, "ssp_mux.1", NULL);
249
250 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
251 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
252 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
253
254 clk = mmp_clk_register_apmu("dfc", "pll1_4",
255 apmu_base + APMU_DFC, 0x19b, &clk_lock);
256 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
257
258 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
259 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
260 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
261 clk_register_clkdev(clk, "sdh0_mux", NULL);
262
263 clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
264 apmu_base + APMU_SDH0, 0x1b, &clk_lock);
265 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
266
267 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
268 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
269 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
270 clk_register_clkdev(clk, "sdh1_mux", NULL);
271
272 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
273 apmu_base + APMU_SDH1, 0x1b, &clk_lock);
274 clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
275
276 clk = mmp_clk_register_apmu("usb", "usb_pll",
277 apmu_base + APMU_USB, 0x9, &clk_lock);
278 clk_register_clkdev(clk, "usb_clk", NULL);
279
280 clk = mmp_clk_register_apmu("sph", "usb_pll",
281 apmu_base + APMU_USB, 0x12, &clk_lock);
282 clk_register_clkdev(clk, "sph_clk", NULL);
283
284 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
285 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
286 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
287 clk_register_clkdev(clk, "disp_mux.0", NULL);
288
289 clk = mmp_clk_register_apmu("disp0", "disp0_mux",
290 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
291 clk_register_clkdev(clk, NULL, "mmp-disp.0");
292
293 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
294 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
295 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
296 clk_register_clkdev(clk, "ccic_mux.0", NULL);
297
298 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
299 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
300 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
301
302 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
303 ARRAY_SIZE(ccic_phy_parent),
304 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
305 7, 1, 0, &clk_lock);
306 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
307
308 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
309 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
310 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
311
312 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
313 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
314 10, 5, 0, &clk_lock);
315 clk_register_clkdev(clk, "sphyclk_div", NULL);
316
317 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
318 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
319 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
320}
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
new file mode 100644
index 000000000000..ab86dd4a416a
--- /dev/null
+++ b/drivers/clk/mmp/clk.h
@@ -0,0 +1,35 @@
1#ifndef __MACH_MMP_CLK_H
2#define __MACH_MMP_CLK_H
3
4#include <linux/clk-provider.h>
5#include <linux/clkdev.h>
6
7#define APBC_NO_BUS_CTRL BIT(0)
8#define APBC_POWER_CTRL BIT(1)
9
10struct clk_factor_masks {
11 unsigned int factor;
12 unsigned int num_mask;
13 unsigned int den_mask;
14 unsigned int num_shift;
15 unsigned int den_shift;
16};
17
18struct clk_factor_tbl {
19 unsigned int num;
20 unsigned int den;
21};
22
23extern struct clk *mmp_clk_register_pll2(const char *name,
24 const char *parent_name, unsigned long flags);
25extern struct clk *mmp_clk_register_apbc(const char *name,
26 const char *parent_name, void __iomem *base,
27 unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
28extern struct clk *mmp_clk_register_apmu(const char *name,
29 const char *parent_name, void __iomem *base, u32 enable_mask,
30 spinlock_t *lock);
31extern struct clk *mmp_clk_register_factor(const char *name,
32 const char *parent_name, unsigned long flags,
33 void __iomem *base, struct clk_factor_masks *masks,
34 struct clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
35#endif
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 844043ad0fe4..9f6d15546cbe 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -14,6 +14,7 @@
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/of.h>
17#include <mach/common.h> 18#include <mach/common.h>
18#include <mach/mx23.h> 19#include <mach/mx23.h>
19#include "clk.h" 20#include "clk.h"
@@ -71,44 +72,6 @@ static void __init clk_misc_init(void)
71 __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC); 72 __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
72} 73}
73 74
74static struct clk_lookup uart_lookups[] = {
75 { .dev_id = "duart", },
76 { .dev_id = "mxs-auart.0", },
77 { .dev_id = "mxs-auart.1", },
78 { .dev_id = "8006c000.serial", },
79 { .dev_id = "8006e000.serial", },
80 { .dev_id = "80070000.serial", },
81};
82
83static struct clk_lookup hbus_lookups[] = {
84 { .dev_id = "imx23-dma-apbh", },
85 { .dev_id = "80004000.dma-apbh", },
86};
87
88static struct clk_lookup xbus_lookups[] = {
89 { .dev_id = "duart", .con_id = "apb_pclk"},
90 { .dev_id = "80070000.serial", .con_id = "apb_pclk"},
91 { .dev_id = "imx23-dma-apbx", },
92 { .dev_id = "80024000.dma-apbx", },
93};
94
95static struct clk_lookup ssp_lookups[] = {
96 { .dev_id = "imx23-mmc.0", },
97 { .dev_id = "imx23-mmc.1", },
98 { .dev_id = "80010000.ssp", },
99 { .dev_id = "80034000.ssp", },
100};
101
102static struct clk_lookup lcdif_lookups[] = {
103 { .dev_id = "imx23-fb", },
104 { .dev_id = "80030000.lcdif", },
105};
106
107static struct clk_lookup gpmi_lookups[] = {
108 { .dev_id = "imx23-gpmi-nand", },
109 { .dev_id = "8000c000.gpmi-nand", },
110};
111
112static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; 75static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
113static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; 76static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
114static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; 77static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", };
@@ -127,6 +90,7 @@ enum imx23_clk {
127}; 90};
128 91
129static struct clk *clks[clk_max]; 92static struct clk *clks[clk_max];
93static struct clk_onecell_data clk_data;
130 94
131static enum imx23_clk clks_init_on[] __initdata = { 95static enum imx23_clk clks_init_on[] __initdata = {
132 cpu, hbus, xbus, emi, uart, 96 cpu, hbus, xbus, emi, uart,
@@ -134,6 +98,7 @@ static enum imx23_clk clks_init_on[] __initdata = {
134 98
135int __init mx23_clocks_init(void) 99int __init mx23_clocks_init(void)
136{ 100{
101 struct device_node *np;
137 int i; 102 int i;
138 103
139 clk_misc_init(); 104 clk_misc_init();
@@ -188,14 +153,14 @@ int __init mx23_clocks_init(void)
188 return PTR_ERR(clks[i]); 153 return PTR_ERR(clks[i]);
189 } 154 }
190 155
156 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
157 if (np) {
158 clk_data.clks = clks;
159 clk_data.clk_num = ARRAY_SIZE(clks);
160 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
161 }
162
191 clk_register_clkdev(clks[clk32k], NULL, "timrot"); 163 clk_register_clkdev(clks[clk32k], NULL, "timrot");
192 clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
193 clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
194 clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
195 clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
196 clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups));
197 clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
198 clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
199 164
200 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 165 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
201 clk_prepare_enable(clks[clks_init_on[i]]); 166 clk_prepare_enable(clks[clks_init_on[i]]);
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index e3aab67b3eb7..613e76f3758e 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -14,6 +14,7 @@
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/of.h>
17#include <mach/common.h> 18#include <mach/common.h>
18#include <mach/mx28.h> 19#include <mach/mx28.h>
19#include "clk.h" 20#include "clk.h"
@@ -120,90 +121,6 @@ static void __init clk_misc_init(void)
120 writel_relaxed(val, FRAC0); 121 writel_relaxed(val, FRAC0);
121} 122}
122 123
123static struct clk_lookup uart_lookups[] = {
124 { .dev_id = "duart", },
125 { .dev_id = "mxs-auart.0", },
126 { .dev_id = "mxs-auart.1", },
127 { .dev_id = "mxs-auart.2", },
128 { .dev_id = "mxs-auart.3", },
129 { .dev_id = "mxs-auart.4", },
130 { .dev_id = "8006a000.serial", },
131 { .dev_id = "8006c000.serial", },
132 { .dev_id = "8006e000.serial", },
133 { .dev_id = "80070000.serial", },
134 { .dev_id = "80072000.serial", },
135 { .dev_id = "80074000.serial", },
136};
137
138static struct clk_lookup hbus_lookups[] = {
139 { .dev_id = "imx28-dma-apbh", },
140 { .dev_id = "80004000.dma-apbh", },
141};
142
143static struct clk_lookup xbus_lookups[] = {
144 { .dev_id = "duart", .con_id = "apb_pclk"},
145 { .dev_id = "80074000.serial", .con_id = "apb_pclk"},
146 { .dev_id = "imx28-dma-apbx", },
147 { .dev_id = "80024000.dma-apbx", },
148};
149
150static struct clk_lookup ssp0_lookups[] = {
151 { .dev_id = "imx28-mmc.0", },
152 { .dev_id = "80010000.ssp", },
153};
154
155static struct clk_lookup ssp1_lookups[] = {
156 { .dev_id = "imx28-mmc.1", },
157 { .dev_id = "80012000.ssp", },
158};
159
160static struct clk_lookup ssp2_lookups[] = {
161 { .dev_id = "imx28-mmc.2", },
162 { .dev_id = "80014000.ssp", },
163};
164
165static struct clk_lookup ssp3_lookups[] = {
166 { .dev_id = "imx28-mmc.3", },
167 { .dev_id = "80016000.ssp", },
168};
169
170static struct clk_lookup lcdif_lookups[] = {
171 { .dev_id = "imx28-fb", },
172 { .dev_id = "80030000.lcdif", },
173};
174
175static struct clk_lookup gpmi_lookups[] = {
176 { .dev_id = "imx28-gpmi-nand", },
177 { .dev_id = "8000c000.gpmi-nand", },
178};
179
180static struct clk_lookup fec_lookups[] = {
181 { .dev_id = "imx28-fec.0", },
182 { .dev_id = "imx28-fec.1", },
183 { .dev_id = "800f0000.ethernet", },
184 { .dev_id = "800f4000.ethernet", },
185};
186
187static struct clk_lookup can0_lookups[] = {
188 { .dev_id = "flexcan.0", },
189 { .dev_id = "80032000.can", },
190};
191
192static struct clk_lookup can1_lookups[] = {
193 { .dev_id = "flexcan.1", },
194 { .dev_id = "80034000.can", },
195};
196
197static struct clk_lookup saif0_lookups[] = {
198 { .dev_id = "mxs-saif.0", },
199 { .dev_id = "80042000.saif", },
200};
201
202static struct clk_lookup saif1_lookups[] = {
203 { .dev_id = "mxs-saif.1", },
204 { .dev_id = "80046000.saif", },
205};
206
207static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; 124static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
208static const char *sel_io0[] __initconst = { "ref_io0", "ref_xtal", }; 125static const char *sel_io0[] __initconst = { "ref_io0", "ref_xtal", };
209static const char *sel_io1[] __initconst = { "ref_io1", "ref_xtal", }; 126static const char *sel_io1[] __initconst = { "ref_io1", "ref_xtal", };
@@ -228,6 +145,7 @@ enum imx28_clk {
228}; 145};
229 146
230static struct clk *clks[clk_max]; 147static struct clk *clks[clk_max];
148static struct clk_onecell_data clk_data;
231 149
232static enum imx28_clk clks_init_on[] __initdata = { 150static enum imx28_clk clks_init_on[] __initdata = {
233 cpu, hbus, xbus, emi, uart, 151 cpu, hbus, xbus, emi, uart,
@@ -235,6 +153,7 @@ static enum imx28_clk clks_init_on[] __initdata = {
235 153
236int __init mx28_clocks_init(void) 154int __init mx28_clocks_init(void)
237{ 155{
156 struct device_node *np;
238 int i; 157 int i;
239 158
240 clk_misc_init(); 159 clk_misc_init();
@@ -312,27 +231,15 @@ int __init mx28_clocks_init(void)
312 return PTR_ERR(clks[i]); 231 return PTR_ERR(clks[i]);
313 } 232 }
314 233
234 np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
235 if (np) {
236 clk_data.clks = clks;
237 clk_data.clk_num = ARRAY_SIZE(clks);
238 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
239 }
240
315 clk_register_clkdev(clks[clk32k], NULL, "timrot"); 241 clk_register_clkdev(clks[clk32k], NULL, "timrot");
316 clk_register_clkdev(clks[enet_out], NULL, "enet_out"); 242 clk_register_clkdev(clks[enet_out], NULL, "enet_out");
317 clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
318 clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
319 clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
320 clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
321 clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups));
322 clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups));
323 clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups));
324 clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups));
325 clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
326 clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups));
327 clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups));
328 clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
329 clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
330 clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
331 clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
332 clk_register_clkdev(clks[usb0_pwr], NULL, "8007c000.usbphy");
333 clk_register_clkdev(clks[usb1_pwr], NULL, "8007e000.usbphy");
334 clk_register_clkdev(clks[usb0], NULL, "80080000.usb");
335 clk_register_clkdev(clks[usb1], NULL, "80090000.usb");
336 243
337 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 244 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
338 clk_prepare_enable(clks[clks_init_on[i]]); 245 clk_prepare_enable(clks[clks_init_on[i]]);
diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
new file mode 100644
index 000000000000..858fbfe66281
--- /dev/null
+++ b/drivers/clk/ux500/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for ux500 clocks
3#
4
5# Clock types
6obj-y += clk-prcc.o
7obj-y += clk-prcmu.o
8
9# Clock definitions
10obj-y += u8500_clk.o
11obj-y += u9540_clk.o
12obj-y += u8540_clk.o
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
new file mode 100644
index 000000000000..7eee7f768355
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -0,0 +1,164 @@
1/*
2 * PRCC clock implementation for ux500 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/clk-private.h>
12#include <linux/slab.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <linux/types.h>
16#include <mach/hardware.h>
17
18#include "clk.h"
19
20#define PRCC_PCKEN 0x000
21#define PRCC_PCKDIS 0x004
22#define PRCC_KCKEN 0x008
23#define PRCC_KCKDIS 0x00C
24#define PRCC_PCKSR 0x010
25#define PRCC_KCKSR 0x014
26
27#define to_clk_prcc(_hw) container_of(_hw, struct clk_prcc, hw)
28
29struct clk_prcc {
30 struct clk_hw hw;
31 void __iomem *base;
32 u32 cg_sel;
33 int is_enabled;
34};
35
36/* PRCC clock operations. */
37
38static int clk_prcc_pclk_enable(struct clk_hw *hw)
39{
40 struct clk_prcc *clk = to_clk_prcc(hw);
41
42 writel(clk->cg_sel, (clk->base + PRCC_PCKEN));
43 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel))
44 cpu_relax();
45
46 clk->is_enabled = 1;
47 return 0;
48}
49
50static void clk_prcc_pclk_disable(struct clk_hw *hw)
51{
52 struct clk_prcc *clk = to_clk_prcc(hw);
53
54 writel(clk->cg_sel, (clk->base + PRCC_PCKDIS));
55 clk->is_enabled = 0;
56}
57
58static int clk_prcc_kclk_enable(struct clk_hw *hw)
59{
60 struct clk_prcc *clk = to_clk_prcc(hw);
61
62 writel(clk->cg_sel, (clk->base + PRCC_KCKEN));
63 while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel))
64 cpu_relax();
65
66 clk->is_enabled = 1;
67 return 0;
68}
69
70static void clk_prcc_kclk_disable(struct clk_hw *hw)
71{
72 struct clk_prcc *clk = to_clk_prcc(hw);
73
74 writel(clk->cg_sel, (clk->base + PRCC_KCKDIS));
75 clk->is_enabled = 0;
76}
77
78static int clk_prcc_is_enabled(struct clk_hw *hw)
79{
80 struct clk_prcc *clk = to_clk_prcc(hw);
81 return clk->is_enabled;
82}
83
84static struct clk_ops clk_prcc_pclk_ops = {
85 .enable = clk_prcc_pclk_enable,
86 .disable = clk_prcc_pclk_disable,
87 .is_enabled = clk_prcc_is_enabled,
88};
89
90static struct clk_ops clk_prcc_kclk_ops = {
91 .enable = clk_prcc_kclk_enable,
92 .disable = clk_prcc_kclk_disable,
93 .is_enabled = clk_prcc_is_enabled,
94};
95
96static struct clk *clk_reg_prcc(const char *name,
97 const char *parent_name,
98 resource_size_t phy_base,
99 u32 cg_sel,
100 unsigned long flags,
101 struct clk_ops *clk_prcc_ops)
102{
103 struct clk_prcc *clk;
104 struct clk_init_data clk_prcc_init;
105 struct clk *clk_reg;
106
107 if (!name) {
108 pr_err("clk_prcc: %s invalid arguments passed\n", __func__);
109 return ERR_PTR(-EINVAL);
110 }
111
112 clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL);
113 if (!clk) {
114 pr_err("clk_prcc: %s could not allocate clk\n", __func__);
115 return ERR_PTR(-ENOMEM);
116 }
117
118 clk->base = ioremap(phy_base, SZ_4K);
119 if (!clk->base)
120 goto free_clk;
121
122 clk->cg_sel = cg_sel;
123 clk->is_enabled = 1;
124
125 clk_prcc_init.name = name;
126 clk_prcc_init.ops = clk_prcc_ops;
127 clk_prcc_init.flags = flags;
128 clk_prcc_init.parent_names = (parent_name ? &parent_name : NULL);
129 clk_prcc_init.num_parents = (parent_name ? 1 : 0);
130 clk->hw.init = &clk_prcc_init;
131
132 clk_reg = clk_register(NULL, &clk->hw);
133 if (IS_ERR_OR_NULL(clk_reg))
134 goto unmap_clk;
135
136 return clk_reg;
137
138unmap_clk:
139 iounmap(clk->base);
140free_clk:
141 kfree(clk);
142 pr_err("clk_prcc: %s failed to register clk\n", __func__);
143 return ERR_PTR(-ENOMEM);
144}
145
146struct clk *clk_reg_prcc_pclk(const char *name,
147 const char *parent_name,
148 resource_size_t phy_base,
149 u32 cg_sel,
150 unsigned long flags)
151{
152 return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
153 &clk_prcc_pclk_ops);
154}
155
156struct clk *clk_reg_prcc_kclk(const char *name,
157 const char *parent_name,
158 resource_size_t phy_base,
159 u32 cg_sel,
160 unsigned long flags)
161{
162 return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
163 &clk_prcc_kclk_ops);
164}
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
new file mode 100644
index 000000000000..930cdfeb47ab
--- /dev/null
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -0,0 +1,252 @@
1/*
2 * PRCMU clock implementation for ux500 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/clk-private.h>
12#include <linux/mfd/dbx500-prcmu.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/err.h>
16#include "clk.h"
17
18#define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw)
19
20struct clk_prcmu {
21 struct clk_hw hw;
22 u8 cg_sel;
23 int is_enabled;
24};
25
26/* PRCMU clock operations. */
27
28static int clk_prcmu_prepare(struct clk_hw *hw)
29{
30 struct clk_prcmu *clk = to_clk_prcmu(hw);
31 return prcmu_request_clock(clk->cg_sel, true);
32}
33
34static void clk_prcmu_unprepare(struct clk_hw *hw)
35{
36 struct clk_prcmu *clk = to_clk_prcmu(hw);
37 if (prcmu_request_clock(clk->cg_sel, false))
38 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
39 hw->init->name);
40}
41
42static int clk_prcmu_enable(struct clk_hw *hw)
43{
44 struct clk_prcmu *clk = to_clk_prcmu(hw);
45 clk->is_enabled = 1;
46 return 0;
47}
48
49static void clk_prcmu_disable(struct clk_hw *hw)
50{
51 struct clk_prcmu *clk = to_clk_prcmu(hw);
52 clk->is_enabled = 0;
53}
54
55static int clk_prcmu_is_enabled(struct clk_hw *hw)
56{
57 struct clk_prcmu *clk = to_clk_prcmu(hw);
58 return clk->is_enabled;
59}
60
61static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw,
62 unsigned long parent_rate)
63{
64 struct clk_prcmu *clk = to_clk_prcmu(hw);
65 return prcmu_clock_rate(clk->cg_sel);
66}
67
68static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate,
69 unsigned long *parent_rate)
70{
71 struct clk_prcmu *clk = to_clk_prcmu(hw);
72 return prcmu_round_clock_rate(clk->cg_sel, rate);
73}
74
75static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate,
76 unsigned long parent_rate)
77{
78 struct clk_prcmu *clk = to_clk_prcmu(hw);
79 return prcmu_set_clock_rate(clk->cg_sel, rate);
80}
81
82static int request_ape_opp100(bool enable)
83{
84 static int reqs;
85 int err = 0;
86
87 if (enable) {
88 if (!reqs)
89 err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
90 "clock", 100);
91 if (!err)
92 reqs++;
93 } else {
94 reqs--;
95 if (!reqs)
96 prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
97 "clock");
98 }
99 return err;
100}
101
102static int clk_prcmu_opp_prepare(struct clk_hw *hw)
103{
104 int err;
105 struct clk_prcmu *clk = to_clk_prcmu(hw);
106
107 err = request_ape_opp100(true);
108 if (err) {
109 pr_err("clk_prcmu: %s failed to request APE OPP100 for %s.\n",
110 __func__, hw->init->name);
111 return err;
112 }
113
114 err = prcmu_request_clock(clk->cg_sel, true);
115 if (err)
116 request_ape_opp100(false);
117
118 return err;
119}
120
121static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
122{
123 struct clk_prcmu *clk = to_clk_prcmu(hw);
124
125 if (prcmu_request_clock(clk->cg_sel, false))
126 goto out_error;
127 if (request_ape_opp100(false))
128 goto out_error;
129 return;
130
131out_error:
132 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
133 hw->init->name);
134}
135
136static struct clk_ops clk_prcmu_scalable_ops = {
137 .prepare = clk_prcmu_prepare,
138 .unprepare = clk_prcmu_unprepare,
139 .enable = clk_prcmu_enable,
140 .disable = clk_prcmu_disable,
141 .is_enabled = clk_prcmu_is_enabled,
142 .recalc_rate = clk_prcmu_recalc_rate,
143 .round_rate = clk_prcmu_round_rate,
144 .set_rate = clk_prcmu_set_rate,
145};
146
147static struct clk_ops clk_prcmu_gate_ops = {
148 .prepare = clk_prcmu_prepare,
149 .unprepare = clk_prcmu_unprepare,
150 .enable = clk_prcmu_enable,
151 .disable = clk_prcmu_disable,
152 .is_enabled = clk_prcmu_is_enabled,
153 .recalc_rate = clk_prcmu_recalc_rate,
154};
155
156static struct clk_ops clk_prcmu_rate_ops = {
157 .is_enabled = clk_prcmu_is_enabled,
158 .recalc_rate = clk_prcmu_recalc_rate,
159};
160
161static struct clk_ops clk_prcmu_opp_gate_ops = {
162 .prepare = clk_prcmu_opp_prepare,
163 .unprepare = clk_prcmu_opp_unprepare,
164 .enable = clk_prcmu_enable,
165 .disable = clk_prcmu_disable,
166 .is_enabled = clk_prcmu_is_enabled,
167 .recalc_rate = clk_prcmu_recalc_rate,
168};
169
170static struct clk *clk_reg_prcmu(const char *name,
171 const char *parent_name,
172 u8 cg_sel,
173 unsigned long rate,
174 unsigned long flags,
175 struct clk_ops *clk_prcmu_ops)
176{
177 struct clk_prcmu *clk;
178 struct clk_init_data clk_prcmu_init;
179 struct clk *clk_reg;
180
181 if (!name) {
182 pr_err("clk_prcmu: %s invalid arguments passed\n", __func__);
183 return ERR_PTR(-EINVAL);
184 }
185
186 clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL);
187 if (!clk) {
188 pr_err("clk_prcmu: %s could not allocate clk\n", __func__);
189 return ERR_PTR(-ENOMEM);
190 }
191
192 clk->cg_sel = cg_sel;
193 clk->is_enabled = 1;
194 /* "rate" can be used for changing the initial frequency */
195 if (rate)
196 prcmu_set_clock_rate(cg_sel, rate);
197
198 clk_prcmu_init.name = name;
199 clk_prcmu_init.ops = clk_prcmu_ops;
200 clk_prcmu_init.flags = flags;
201 clk_prcmu_init.parent_names = (parent_name ? &parent_name : NULL);
202 clk_prcmu_init.num_parents = (parent_name ? 1 : 0);
203 clk->hw.init = &clk_prcmu_init;
204
205 clk_reg = clk_register(NULL, &clk->hw);
206 if (IS_ERR_OR_NULL(clk_reg))
207 goto free_clk;
208
209 return clk_reg;
210
211free_clk:
212 kfree(clk);
213 pr_err("clk_prcmu: %s failed to register clk\n", __func__);
214 return ERR_PTR(-ENOMEM);
215}
216
217struct clk *clk_reg_prcmu_scalable(const char *name,
218 const char *parent_name,
219 u8 cg_sel,
220 unsigned long rate,
221 unsigned long flags)
222{
223 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
224 &clk_prcmu_scalable_ops);
225}
226
227struct clk *clk_reg_prcmu_gate(const char *name,
228 const char *parent_name,
229 u8 cg_sel,
230 unsigned long flags)
231{
232 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
233 &clk_prcmu_gate_ops);
234}
235
236struct clk *clk_reg_prcmu_rate(const char *name,
237 const char *parent_name,
238 u8 cg_sel,
239 unsigned long flags)
240{
241 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
242 &clk_prcmu_rate_ops);
243}
244
245struct clk *clk_reg_prcmu_opp_gate(const char *name,
246 const char *parent_name,
247 u8 cg_sel,
248 unsigned long flags)
249{
250 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
251 &clk_prcmu_opp_gate_ops);
252}
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
new file mode 100644
index 000000000000..836d7d16751e
--- /dev/null
+++ b/drivers/clk/ux500/clk.h
@@ -0,0 +1,48 @@
1/*
2 * Clocks for ux500 platforms
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#ifndef __UX500_CLK_H
11#define __UX500_CLK_H
12
13#include <linux/clk.h>
14
15struct clk *clk_reg_prcc_pclk(const char *name,
16 const char *parent_name,
17 unsigned int phy_base,
18 u32 cg_sel,
19 unsigned long flags);
20
21struct clk *clk_reg_prcc_kclk(const char *name,
22 const char *parent_name,
23 unsigned int phy_base,
24 u32 cg_sel,
25 unsigned long flags);
26
27struct clk *clk_reg_prcmu_scalable(const char *name,
28 const char *parent_name,
29 u8 cg_sel,
30 unsigned long rate,
31 unsigned long flags);
32
33struct clk *clk_reg_prcmu_gate(const char *name,
34 const char *parent_name,
35 u8 cg_sel,
36 unsigned long flags);
37
38struct clk *clk_reg_prcmu_rate(const char *name,
39 const char *parent_name,
40 u8 cg_sel,
41 unsigned long flags);
42
43struct clk *clk_reg_prcmu_opp_gate(const char *name,
44 const char *parent_name,
45 u8 cg_sel,
46 unsigned long flags);
47
48#endif /* __UX500_CLK_H */
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
new file mode 100644
index 000000000000..ca4a25ed844c
--- /dev/null
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -0,0 +1,477 @@
1/*
2 * Clock definitions for u8500 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/clk-provider.h>
13#include <linux/mfd/dbx500-prcmu.h>
14#include <linux/platform_data/clk-ux500.h>
15
16#include "clk.h"
17
18void u8500_clk_init(void)
19{
20 struct prcmu_fw_version *fw_version;
21 const char *sgaclk_parent = NULL;
22 struct clk *clk;
23
24 /* Clock sources */
25 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
26 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
27 clk_register_clkdev(clk, "soc0_pll", NULL);
28
29 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
30 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
31 clk_register_clkdev(clk, "soc1_pll", NULL);
32
33 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
34 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
35 clk_register_clkdev(clk, "ddr_pll", NULL);
36
37 /* FIXME: Add sys, ulp and int clocks here. */
38
39 clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
40 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
41 32768);
42 clk_register_clkdev(clk, "clk32k", NULL);
43 clk_register_clkdev(clk, NULL, "rtc-pl031");
44
45 /* PRCMU clocks */
46 fw_version = prcmu_get_fw_version();
47 if (fw_version != NULL) {
48 switch (fw_version->project) {
49 case PRCMU_FW_PROJECT_U8500_C2:
50 case PRCMU_FW_PROJECT_U8520:
51 case PRCMU_FW_PROJECT_U8420:
52 sgaclk_parent = "soc0_pll";
53 break;
54 default:
55 break;
56 }
57 }
58
59 if (sgaclk_parent)
60 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
61 PRCMU_SGACLK, 0);
62 else
63 clk = clk_reg_prcmu_gate("sgclk", NULL,
64 PRCMU_SGACLK, CLK_IS_ROOT);
65 clk_register_clkdev(clk, NULL, "mali");
66
67 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
68 clk_register_clkdev(clk, NULL, "UART");
69
70 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
71 clk_register_clkdev(clk, NULL, "MSP02");
72
73 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
74 clk_register_clkdev(clk, NULL, "MSP1");
75
76 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
77 clk_register_clkdev(clk, NULL, "I2C");
78
79 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
80 clk_register_clkdev(clk, NULL, "slim");
81
82 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
83 clk_register_clkdev(clk, NULL, "PERIPH1");
84
85 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
86 clk_register_clkdev(clk, NULL, "PERIPH2");
87
88 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
89 clk_register_clkdev(clk, NULL, "PERIPH3");
90
91 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
92 clk_register_clkdev(clk, NULL, "PERIPH5");
93
94 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
95 clk_register_clkdev(clk, NULL, "PERIPH6");
96
97 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
98 clk_register_clkdev(clk, NULL, "PERIPH7");
99
100 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
101 CLK_IS_ROOT|CLK_SET_RATE_GATE);
102 clk_register_clkdev(clk, NULL, "lcd");
103 clk_register_clkdev(clk, "lcd", "mcde");
104
105 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
106 clk_register_clkdev(clk, NULL, "bml");
107
108 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
109 CLK_IS_ROOT|CLK_SET_RATE_GATE);
110
111 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
112 CLK_IS_ROOT|CLK_SET_RATE_GATE);
113
114 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
115 CLK_IS_ROOT|CLK_SET_RATE_GATE);
116 clk_register_clkdev(clk, NULL, "hdmi");
117 clk_register_clkdev(clk, "hdmi", "mcde");
118
119 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
120 clk_register_clkdev(clk, NULL, "apeat");
121
122 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
123 CLK_IS_ROOT);
124 clk_register_clkdev(clk, NULL, "apetrace");
125
126 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
127 clk_register_clkdev(clk, NULL, "mcde");
128 clk_register_clkdev(clk, "mcde", "mcde");
129 clk_register_clkdev(clk, "dsisys", "dsilink.0");
130 clk_register_clkdev(clk, "dsisys", "dsilink.1");
131 clk_register_clkdev(clk, "dsisys", "dsilink.2");
132
133 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
134 CLK_IS_ROOT);
135 clk_register_clkdev(clk, NULL, "ipi2");
136
137 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
138 CLK_IS_ROOT);
139 clk_register_clkdev(clk, NULL, "dsialt");
140
141 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
142 clk_register_clkdev(clk, NULL, "dma40.0");
143
144 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
145 clk_register_clkdev(clk, NULL, "b2r2");
146 clk_register_clkdev(clk, NULL, "b2r2_core");
147 clk_register_clkdev(clk, NULL, "U8500-B2R2.0");
148
149 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
150 CLK_IS_ROOT|CLK_SET_RATE_GATE);
151 clk_register_clkdev(clk, NULL, "tv");
152 clk_register_clkdev(clk, "tv", "mcde");
153
154 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
155 clk_register_clkdev(clk, NULL, "SSP");
156
157 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
158 clk_register_clkdev(clk, NULL, "rngclk");
159
160 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
161 clk_register_clkdev(clk, NULL, "uicc");
162
163 /*
164 * FIXME: The MTU clocks might need some kind of "parent muxed join"
165 * and these have no K-clocks. For now, we ignore the missing
166 * connection to the corresponding P-clocks, p6_mtu0_clk and
167 * p6_mtu1_clk. Instead timclk is used which is the valid parent.
168 */
169 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
170 clk_register_clkdev(clk, NULL, "mtu0");
171 clk_register_clkdev(clk, NULL, "mtu1");
172
173 clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);
174 clk_register_clkdev(clk, NULL, "sdmmc");
175
176
177 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
178 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
179 clk_register_clkdev(clk, "dsihs2", "mcde");
180 clk_register_clkdev(clk, "dsihs2", "dsilink.2");
181
182
183 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
184 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
185 clk_register_clkdev(clk, "dsihs0", "mcde");
186 clk_register_clkdev(clk, "dsihs0", "dsilink.0");
187
188 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
189 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
190 clk_register_clkdev(clk, "dsihs1", "mcde");
191 clk_register_clkdev(clk, "dsihs1", "dsilink.1");
192
193 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
194 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
195 clk_register_clkdev(clk, "dsilp0", "dsilink.0");
196 clk_register_clkdev(clk, "dsilp0", "mcde");
197
198 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
199 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
200 clk_register_clkdev(clk, "dsilp1", "dsilink.1");
201 clk_register_clkdev(clk, "dsilp1", "mcde");
202
203 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
204 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
205 clk_register_clkdev(clk, "dsilp2", "dsilink.2");
206 clk_register_clkdev(clk, "dsilp2", "mcde");
207
208 clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS,
209 CLK_IS_ROOT|CLK_GET_RATE_NOCACHE|
210 CLK_IGNORE_UNUSED);
211 clk_register_clkdev(clk, NULL, "smp_twd");
212
213 /*
214 * FIXME: Add special handled PRCMU clocks here:
215 * 1. clk_arm, use PRCMU_ARMCLK.
216 * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
217 * 3. ab9540_clkout1yuv, see clkout0yuv
218 */
219
220 /* PRCC P-clocks */
221 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE,
222 BIT(0), 0);
223 clk_register_clkdev(clk, "apb_pclk", "uart0");
224
225 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE,
226 BIT(1), 0);
227 clk_register_clkdev(clk, "apb_pclk", "uart1");
228
229 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE,
230 BIT(2), 0);
231 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE,
232 BIT(3), 0);
233 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE,
234 BIT(4), 0);
235
236 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE,
237 BIT(5), 0);
238 clk_register_clkdev(clk, "apb_pclk", "sdi0");
239
240 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE,
241 BIT(6), 0);
242
243 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE,
244 BIT(7), 0);
245 clk_register_clkdev(clk, NULL, "spi3");
246
247 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE,
248 BIT(8), 0);
249
250 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE,
251 BIT(9), 0);
252 clk_register_clkdev(clk, NULL, "gpio.0");
253 clk_register_clkdev(clk, NULL, "gpio.1");
254 clk_register_clkdev(clk, NULL, "gpioblock0");
255
256 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE,
257 BIT(10), 0);
258 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE,
259 BIT(11), 0);
260
261 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE,
262 BIT(0), 0);
263
264 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE,
265 BIT(1), 0);
266 clk_register_clkdev(clk, NULL, "spi2");
267
268 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE,
269 BIT(2), 0);
270 clk_register_clkdev(clk, NULL, "spi1");
271
272 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE,
273 BIT(3), 0);
274 clk_register_clkdev(clk, NULL, "pwl");
275
276 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE,
277 BIT(4), 0);
278 clk_register_clkdev(clk, "apb_pclk", "sdi4");
279
280 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE,
281 BIT(5), 0);
282
283 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE,
284 BIT(6), 0);
285 clk_register_clkdev(clk, "apb_pclk", "sdi1");
286
287
288 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE,
289 BIT(7), 0);
290 clk_register_clkdev(clk, "apb_pclk", "sdi3");
291
292 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE,
293 BIT(8), 0);
294 clk_register_clkdev(clk, NULL, "spi0");
295
296 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE,
297 BIT(9), 0);
298 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0");
299
300 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE,
301 BIT(10), 0);
302 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0");
303
304 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE,
305 BIT(11), 0);
306 clk_register_clkdev(clk, NULL, "gpio.6");
307 clk_register_clkdev(clk, NULL, "gpio.7");
308 clk_register_clkdev(clk, NULL, "gpioblock1");
309
310 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
311 BIT(11), 0);
312
313 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
314 BIT(0), 0);
315 clk_register_clkdev(clk, NULL, "fsmc");
316
317 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
318 BIT(1), 0);
319 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE,
320 BIT(2), 0);
321 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE,
322 BIT(3), 0);
323
324 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE,
325 BIT(4), 0);
326 clk_register_clkdev(clk, "apb_pclk", "sdi2");
327
328 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
329 BIT(5), 0);
330
331 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
332 BIT(6), 0);
333 clk_register_clkdev(clk, "apb_pclk", "uart2");
334
335 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE,
336 BIT(7), 0);
337 clk_register_clkdev(clk, "apb_pclk", "sdi5");
338
339 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE,
340 BIT(8), 0);
341 clk_register_clkdev(clk, NULL, "gpio.2");
342 clk_register_clkdev(clk, NULL, "gpio.3");
343 clk_register_clkdev(clk, NULL, "gpio.4");
344 clk_register_clkdev(clk, NULL, "gpio.5");
345 clk_register_clkdev(clk, NULL, "gpioblock2");
346
347 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE,
348 BIT(0), 0);
349 clk_register_clkdev(clk, "usb", "musb-ux500.0");
350
351 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE,
352 BIT(1), 0);
353 clk_register_clkdev(clk, NULL, "gpio.8");
354 clk_register_clkdev(clk, NULL, "gpioblock3");
355
356 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
357 BIT(0), 0);
358
359 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
360 BIT(1), 0);
361 clk_register_clkdev(clk, NULL, "cryp0");
362 clk_register_clkdev(clk, NULL, "cryp1");
363
364 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE,
365 BIT(2), 0);
366 clk_register_clkdev(clk, NULL, "hash0");
367
368 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE,
369 BIT(3), 0);
370 clk_register_clkdev(clk, NULL, "pka");
371
372 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE,
373 BIT(4), 0);
374 clk_register_clkdev(clk, NULL, "hash1");
375
376 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE,
377 BIT(5), 0);
378 clk_register_clkdev(clk, NULL, "cfgreg");
379
380 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE,
381 BIT(6), 0);
382 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE,
383 BIT(7), 0);
384
385 /* PRCC K-clocks
386 *
387 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
388 * by enabling just the K-clock, even if it is not a valid parent to
389 * the K-clock. Until drivers get fixed we might need some kind of
390 * "parent muxed join".
391 */
392
393 /* Periph1 */
394 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
395 U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE);
396 clk_register_clkdev(clk, NULL, "uart0");
397
398 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
399 U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE);
400 clk_register_clkdev(clk, NULL, "uart1");
401
402 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
403 U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE);
404 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
405 U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
406 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
407 U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE);
408
409 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
410 U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE);
411 clk_register_clkdev(clk, NULL, "sdi0");
412
413 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
414 U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE);
415 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
416 U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE);
417 /* FIXME: Redefinition of BIT(3). */
418 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
419 U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE);
420 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
421 U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE);
422
423 /* Periph2 */
424 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
425 U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE);
426
427 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
428 U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE);
429 clk_register_clkdev(clk, NULL, "sdi4");
430
431 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
432 U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE);
433
434 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
435 U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE);
436 clk_register_clkdev(clk, NULL, "sdi1");
437
438 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
439 U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE);
440 clk_register_clkdev(clk, NULL, "sdi3");
441
442 /* Note that rate is received from parent. */
443 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
444 U8500_CLKRST2_BASE, BIT(6),
445 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
446 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
447 U8500_CLKRST2_BASE, BIT(7),
448 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
449
450 /* Periph3 */
451 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
452 U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE);
453 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
454 U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE);
455 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
456 U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE);
457
458 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
459 U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE);
460 clk_register_clkdev(clk, NULL, "sdi2");
461
462 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
463 U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
464
465 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
466 U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
467 clk_register_clkdev(clk, NULL, "uart2");
468
469 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
470 U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE);
471 clk_register_clkdev(clk, NULL, "sdi5");
472
473 /* Periph6 */
474 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
475 U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
476
477}
diff --git a/drivers/clk/ux500/u8540_clk.c b/drivers/clk/ux500/u8540_clk.c
new file mode 100644
index 000000000000..10adfd2ead21
--- /dev/null
+++ b/drivers/clk/ux500/u8540_clk.c
@@ -0,0 +1,21 @@
1/*
2 * Clock definitions for u8540 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/clk-provider.h>
13#include <linux/mfd/dbx500-prcmu.h>
14#include <linux/platform_data/clk-ux500.h>
15
16#include "clk.h"
17
18void u8540_clk_init(void)
19{
20 /* register clocks here */
21}
diff --git a/drivers/clk/ux500/u9540_clk.c b/drivers/clk/ux500/u9540_clk.c
new file mode 100644
index 000000000000..dbc0191e16c8
--- /dev/null
+++ b/drivers/clk/ux500/u9540_clk.c
@@ -0,0 +1,21 @@
1/*
2 * Clock definitions for u9540 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/clk-provider.h>
13#include <linux/mfd/dbx500-prcmu.h>
14#include <linux/platform_data/clk-ux500.h>
15
16#include "clk.h"
17
18void u9540_clk_init(void)
19{
20 /* register clocks here */
21}
diff --git a/drivers/clk/versatile/Makefile b/drivers/clk/versatile/Makefile
index 50cf6a2ee693..c0a0f6478798 100644
--- a/drivers/clk/versatile/Makefile
+++ b/drivers/clk/versatile/Makefile
@@ -1,3 +1,4 @@
1# Makefile for Versatile-specific clocks 1# Makefile for Versatile-specific clocks
2obj-$(CONFIG_ICST) += clk-icst.o 2obj-$(CONFIG_ICST) += clk-icst.o
3obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o 3obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o
4obj-$(CONFIG_ARCH_REALVIEW) += clk-realview.o
diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c
new file mode 100644
index 000000000000..e21a99cef378
--- /dev/null
+++ b/drivers/clk/versatile/clk-realview.c
@@ -0,0 +1,114 @@
1#include <linux/clk.h>
2#include <linux/clkdev.h>
3#include <linux/err.h>
4#include <linux/io.h>
5#include <linux/clk-provider.h>
6
7#include <mach/hardware.h>
8#include <mach/platform.h>
9
10#include "clk-icst.h"
11
12/*
13 * Implementation of the ARM RealView clock trees.
14 */
15
16static void __iomem *sys_lock;
17static void __iomem *sys_vcoreg;
18
19/**
20 * realview_oscvco_get() - get ICST OSC settings for the RealView
21 */
22static struct icst_vco realview_oscvco_get(void)
23{
24 u32 val;
25 struct icst_vco vco;
26
27 val = readl(sys_vcoreg);
28 vco.v = val & 0x1ff;
29 vco.r = (val >> 9) & 0x7f;
30 vco.s = (val >> 16) & 03;
31 return vco;
32}
33
34static void realview_oscvco_set(struct icst_vco vco)
35{
36 u32 val;
37
38 val = readl(sys_vcoreg) & ~0x7ffff;
39 val |= vco.v | (vco.r << 9) | (vco.s << 16);
40
41 /* This magic unlocks the CM VCO so it can be controlled */
42 writel(0xa05f, sys_lock);
43 writel(val, sys_vcoreg);
44 /* This locks the CM again */
45 writel(0, sys_lock);
46}
47
48static const struct icst_params realview_oscvco_params = {
49 .ref = 24000000,
50 .vco_max = ICST307_VCO_MAX,
51 .vco_min = ICST307_VCO_MIN,
52 .vd_min = 4 + 8,
53 .vd_max = 511 + 8,
54 .rd_min = 1 + 2,
55 .rd_max = 127 + 2,
56 .s2div = icst307_s2div,
57 .idx2s = icst307_idx2s,
58};
59
60static const struct clk_icst_desc __initdata realview_icst_desc = {
61 .params = &realview_oscvco_params,
62 .getvco = realview_oscvco_get,
63 .setvco = realview_oscvco_set,
64};
65
66/*
67 * realview_clk_init() - set up the RealView clock tree
68 */
69void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176)
70{
71 struct clk *clk;
72
73 sys_lock = sysbase + REALVIEW_SYS_LOCK_OFFSET;
74 if (is_pb1176)
75 sys_vcoreg = sysbase + REALVIEW_SYS_OSC0_OFFSET;
76 else
77 sys_vcoreg = sysbase + REALVIEW_SYS_OSC4_OFFSET;
78
79
80 /* APB clock dummy */
81 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
82 clk_register_clkdev(clk, "apb_pclk", NULL);
83
84 /* 24 MHz clock */
85 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT,
86 24000000);
87 clk_register_clkdev(clk, NULL, "dev:uart0");
88 clk_register_clkdev(clk, NULL, "dev:uart1");
89 clk_register_clkdev(clk, NULL, "dev:uart2");
90 clk_register_clkdev(clk, NULL, "fpga:kmi0");
91 clk_register_clkdev(clk, NULL, "fpga:kmi1");
92 clk_register_clkdev(clk, NULL, "fpga:mmc0");
93 clk_register_clkdev(clk, NULL, "dev:ssp0");
94 if (is_pb1176) {
95 /*
96 * UART3 is on the dev chip in PB1176
97 * UART4 only exists in PB1176
98 */
99 clk_register_clkdev(clk, NULL, "dev:uart3");
100 clk_register_clkdev(clk, NULL, "dev:uart4");
101 } else
102 clk_register_clkdev(clk, NULL, "fpga:uart3");
103
104
105 /* 1 MHz clock */
106 clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT,
107 1000000);
108 clk_register_clkdev(clk, NULL, "sp804");
109
110 /* ICST VCO clock */
111 clk = icst_clk_register(NULL, &realview_icst_desc);
112 clk_register_clkdev(clk, NULL, "dev:clcd");
113 clk_register_clkdev(clk, NULL, "issp:clcd");
114}
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 9cac88a65f78..9528779ca463 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -26,6 +26,8 @@
26#include <linux/syscore_ops.h> 26#include <linux/syscore_ops.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28 28
29#include <asm/mach/irq.h>
30
29#include <mach/irqs.h> 31#include <mach/irqs.h>
30 32
31/* 33/*
@@ -59,6 +61,7 @@
59#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) 61#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
60 62
61int pxa_last_gpio; 63int pxa_last_gpio;
64static int irq_base;
62 65
63#ifdef CONFIG_OF 66#ifdef CONFIG_OF
64static struct irq_domain *domain; 67static struct irq_domain *domain;
@@ -167,63 +170,14 @@ static inline int __gpio_is_occupied(unsigned gpio)
167 return ret; 170 return ret;
168} 171}
169 172
170#ifdef CONFIG_ARCH_PXA
171static inline int __pxa_gpio_to_irq(int gpio)
172{
173 if (gpio_is_pxa_type(gpio_type))
174 return PXA_GPIO_TO_IRQ(gpio);
175 return -1;
176}
177
178static inline int __pxa_irq_to_gpio(int irq)
179{
180 if (gpio_is_pxa_type(gpio_type))
181 return irq - PXA_GPIO_TO_IRQ(0);
182 return -1;
183}
184#else
185static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
186static inline int __pxa_irq_to_gpio(int irq) { return -1; }
187#endif
188
189#ifdef CONFIG_ARCH_MMP
190static inline int __mmp_gpio_to_irq(int gpio)
191{
192 if (gpio_is_mmp_type(gpio_type))
193 return MMP_GPIO_TO_IRQ(gpio);
194 return -1;
195}
196
197static inline int __mmp_irq_to_gpio(int irq)
198{
199 if (gpio_is_mmp_type(gpio_type))
200 return irq - MMP_GPIO_TO_IRQ(0);
201 return -1;
202}
203#else
204static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
205static inline int __mmp_irq_to_gpio(int irq) { return -1; }
206#endif
207
208static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 173static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
209{ 174{
210 int gpio, ret; 175 return chip->base + offset + irq_base;
211
212 gpio = chip->base + offset;
213 ret = __pxa_gpio_to_irq(gpio);
214 if (ret >= 0)
215 return ret;
216 return __mmp_gpio_to_irq(gpio);
217} 176}
218 177
219int pxa_irq_to_gpio(int irq) 178int pxa_irq_to_gpio(int irq)
220{ 179{
221 int ret; 180 return irq - irq_base;
222
223 ret = __pxa_irq_to_gpio(irq);
224 if (ret >= 0)
225 return ret;
226 return __mmp_irq_to_gpio(irq);
227} 181}
228 182
229static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 183static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -403,6 +357,9 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
403 struct pxa_gpio_chip *c; 357 struct pxa_gpio_chip *c;
404 int loop, gpio, gpio_base, n; 358 int loop, gpio, gpio_base, n;
405 unsigned long gedr; 359 unsigned long gedr;
360 struct irq_chip *chip = irq_desc_get_chip(desc);
361
362 chained_irq_enter(chip, desc);
406 363
407 do { 364 do {
408 loop = 0; 365 loop = 0;
@@ -422,6 +379,8 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
422 } 379 }
423 } 380 }
424 } while (loop); 381 } while (loop);
382
383 chained_irq_exit(chip, desc);
425} 384}
426 385
427static void pxa_ack_muxed_gpio(struct irq_data *d) 386static void pxa_ack_muxed_gpio(struct irq_data *d)
@@ -535,7 +494,7 @@ const struct irq_domain_ops pxa_irq_domain_ops = {
535 494
536static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev) 495static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
537{ 496{
538 int ret, nr_banks, nr_gpios, irq_base; 497 int ret, nr_banks, nr_gpios;
539 struct device_node *prev, *next, *np = pdev->dev.of_node; 498 struct device_node *prev, *next, *np = pdev->dev.of_node;
540 const struct of_device_id *of_id = 499 const struct of_device_id *of_id =
541 of_match_device(pxa_gpio_dt_ids, &pdev->dev); 500 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
@@ -590,10 +549,20 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
590 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; 549 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
591 550
592 ret = pxa_gpio_probe_dt(pdev); 551 ret = pxa_gpio_probe_dt(pdev);
593 if (ret < 0) 552 if (ret < 0) {
594 pxa_last_gpio = pxa_gpio_nums(); 553 pxa_last_gpio = pxa_gpio_nums();
595 else 554#ifdef CONFIG_ARCH_PXA
555 if (gpio_is_pxa_type(gpio_type))
556 irq_base = PXA_GPIO_TO_IRQ(0);
557#endif
558#ifdef CONFIG_ARCH_MMP
559 if (gpio_is_mmp_type(gpio_type))
560 irq_base = MMP_GPIO_TO_IRQ(0);
561#endif
562 } else {
596 use_of = 1; 563 use_of = 1;
564 }
565
597 if (!pxa_last_gpio) 566 if (!pxa_last_gpio)
598 return -EINVAL; 567 return -EINVAL;
599 568
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 1c169324e357..8af4b06e80f7 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
938 s3c_gpiolib_track(chip); 938 s3c_gpiolib_track(chip);
939} 939}
940 940
941#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
942static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
943 const struct of_phandle_args *gpiospec, u32 *flags)
944{
945 unsigned int pin;
946
947 if (WARN_ON(gc->of_gpio_n_cells < 3))
948 return -EINVAL;
949
950 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
951 return -EINVAL;
952
953 if (gpiospec->args[0] > gc->ngpio)
954 return -EINVAL;
955
956 pin = gc->base + gpiospec->args[0];
957
958 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
959 pr_warn("gpio_xlate: failed to set pin function\n");
960 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
961 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
962
963 if (flags)
964 *flags = gpiospec->args[2] >> 16;
965
966 return gpiospec->args[0];
967}
968
969static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
970 { .compatible = "samsung,s3c24xx-gpio", },
971 {}
972};
973
974static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
975 u64 base, u64 offset)
976{
977 struct gpio_chip *gc = &chip->chip;
978 u64 address;
979
980 if (!of_have_populated_dt())
981 return;
982
983 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
984 gc->of_node = of_find_matching_node_by_address(NULL,
985 s3c24xx_gpio_dt_match, address);
986 if (!gc->of_node) {
987 pr_info("gpio: device tree node not found for gpio controller"
988 " with base address %08llx\n", address);
989 return;
990 }
991 gc->of_gpio_n_cells = 3;
992 gc->of_xlate = s3c24xx_gpio_xlate;
993}
994#else
995static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
996 u64 base, u64 offset)
997{
998 return;
999}
1000#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
1001
941static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip, 1002static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
942 int nr_chips, void __iomem *base) 1003 int nr_chips, void __iomem *base)
943{ 1004{
@@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
962 gc->direction_output = samsung_gpiolib_2bit_output; 1023 gc->direction_output = samsung_gpiolib_2bit_output;
963 1024
964 samsung_gpiolib_add(chip); 1025 samsung_gpiolib_add(chip);
1026
1027 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
965 } 1028 }
966} 1029}
967 1030
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index f030880bc9bb..c5f8ca233e1f 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -396,6 +396,29 @@ static int __devinit gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
396 396
397static int gpio_twl4030_remove(struct platform_device *pdev); 397static int gpio_twl4030_remove(struct platform_device *pdev);
398 398
399static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev)
400{
401 struct twl4030_gpio_platform_data *omap_twl_info;
402
403 omap_twl_info = devm_kzalloc(dev, sizeof(*omap_twl_info), GFP_KERNEL);
404 if (!omap_twl_info)
405 return NULL;
406
407 omap_twl_info->use_leds = of_property_read_bool(dev->of_node,
408 "ti,use-leds");
409
410 of_property_read_u32(dev->of_node, "ti,debounce",
411 &omap_twl_info->debounce);
412 of_property_read_u32(dev->of_node, "ti,mmc-cd",
413 (u32 *)&omap_twl_info->mmc_cd);
414 of_property_read_u32(dev->of_node, "ti,pullups",
415 &omap_twl_info->pullups);
416 of_property_read_u32(dev->of_node, "ti,pulldowns",
417 &omap_twl_info->pulldowns);
418
419 return omap_twl_info;
420}
421
399static int __devinit gpio_twl4030_probe(struct platform_device *pdev) 422static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
400{ 423{
401 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data; 424 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
@@ -428,33 +451,37 @@ no_irqs:
428 twl_gpiochip.ngpio = TWL4030_GPIO_MAX; 451 twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
429 twl_gpiochip.dev = &pdev->dev; 452 twl_gpiochip.dev = &pdev->dev;
430 453
431 if (pdata) { 454 if (node)
432 /* 455 pdata = of_gpio_twl4030(&pdev->dev);
433 * NOTE: boards may waste power if they don't set pullups 456
434 * and pulldowns correctly ... default for non-ULPI pins is 457 if (pdata == NULL) {
435 * pulldown, and some other pins may have external pullups 458 dev_err(&pdev->dev, "Platform data is missing\n");
436 * or pulldowns. Careful! 459 return -ENXIO;
437 */
438 ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
439 if (ret)
440 dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
441 pdata->pullups, pdata->pulldowns,
442 ret);
443
444 ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
445 if (ret)
446 dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
447 pdata->debounce, pdata->mmc_cd,
448 ret);
449
450 /*
451 * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
452 * is (still) clear if use_leds is set.
453 */
454 if (pdata->use_leds)
455 twl_gpiochip.ngpio += 2;
456 } 460 }
457 461
462 /*
463 * NOTE: boards may waste power if they don't set pullups
464 * and pulldowns correctly ... default for non-ULPI pins is
465 * pulldown, and some other pins may have external pullups
466 * or pulldowns. Careful!
467 */
468 ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
469 if (ret)
470 dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
471 pdata->pullups, pdata->pulldowns, ret);
472
473 ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
474 if (ret)
475 dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
476 pdata->debounce, pdata->mmc_cd, ret);
477
478 /*
479 * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
480 * is (still) clear if use_leds is set.
481 */
482 if (pdata->use_leds)
483 twl_gpiochip.ngpio += 2;
484
458 ret = gpiochip_add(&twl_gpiochip); 485 ret = gpiochip_add(&twl_gpiochip);
459 if (ret < 0) { 486 if (ret < 0) {
460 dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret); 487 dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 0e63cdd9b52a..6b67edbdbd01 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -418,6 +418,9 @@ static struct {
418 418
419static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 419static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
420 420
421/* Functions definition */
422static void compute_armss_rate(void);
423
421/* Spinlocks */ 424/* Spinlocks */
422static DEFINE_SPINLOCK(prcmu_lock); 425static DEFINE_SPINLOCK(prcmu_lock);
423static DEFINE_SPINLOCK(clkout_lock); 426static DEFINE_SPINLOCK(clkout_lock);
@@ -517,6 +520,7 @@ static struct dsiescclk dsiescclk[3] = {
517 } 520 }
518}; 521};
519 522
523
520/* 524/*
521* Used by MCDE to setup all necessary PRCMU registers 525* Used by MCDE to setup all necessary PRCMU registers
522*/ 526*/
@@ -1013,6 +1017,7 @@ int db8500_prcmu_set_arm_opp(u8 opp)
1013 (mb1_transfer.ack.arm_opp != opp)) 1017 (mb1_transfer.ack.arm_opp != opp))
1014 r = -EIO; 1018 r = -EIO;
1015 1019
1020 compute_armss_rate();
1016 mutex_unlock(&mb1_transfer.lock); 1021 mutex_unlock(&mb1_transfer.lock);
1017 1022
1018 return r; 1023 return r;
@@ -1612,6 +1617,7 @@ static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1612 if ((branch == PLL_FIX) || ((branch == PLL_DIV) && 1617 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1613 (val & PRCM_PLL_FREQ_DIV2EN) && 1618 (val & PRCM_PLL_FREQ_DIV2EN) &&
1614 ((reg == PRCM_PLLSOC0_FREQ) || 1619 ((reg == PRCM_PLLSOC0_FREQ) ||
1620 (reg == PRCM_PLLARM_FREQ) ||
1615 (reg == PRCM_PLLDDR_FREQ)))) 1621 (reg == PRCM_PLLDDR_FREQ))))
1616 div *= 2; 1622 div *= 2;
1617 1623
@@ -1661,6 +1667,39 @@ static unsigned long clock_rate(u8 clock)
1661 else 1667 else
1662 return 0; 1668 return 0;
1663} 1669}
1670static unsigned long latest_armss_rate;
1671static unsigned long armss_rate(void)
1672{
1673 return latest_armss_rate;
1674}
1675
1676static void compute_armss_rate(void)
1677{
1678 u32 r;
1679 unsigned long rate;
1680
1681 r = readl(PRCM_ARM_CHGCLKREQ);
1682
1683 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1684 /* External ARMCLKFIX clock */
1685
1686 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1687
1688 /* Check PRCM_ARM_CHGCLKREQ divider */
1689 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1690 rate /= 2;
1691
1692 /* Check PRCM_ARMCLKFIX_MGT divider */
1693 r = readl(PRCM_ARMCLKFIX_MGT);
1694 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1695 rate /= r;
1696
1697 } else {/* ARM PLL */
1698 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1699 }
1700
1701 latest_armss_rate = rate;
1702}
1664 1703
1665static unsigned long dsiclk_rate(u8 n) 1704static unsigned long dsiclk_rate(u8 n)
1666{ 1705{
@@ -1707,6 +1746,8 @@ unsigned long prcmu_clock_rate(u8 clock)
1707 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1746 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1708 else if (clock == PRCMU_PLLSOC1) 1747 else if (clock == PRCMU_PLLSOC1)
1709 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1748 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1749 else if (clock == PRCMU_ARMSS)
1750 return armss_rate();
1710 else if (clock == PRCMU_PLLDDR) 1751 else if (clock == PRCMU_PLLDDR)
1711 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); 1752 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1712 else if (clock == PRCMU_PLLDSI) 1753 else if (clock == PRCMU_PLLDSI)
@@ -2693,6 +2734,7 @@ void __init db8500_prcmu_early_init(void)
2693 handle_simple_irq); 2734 handle_simple_irq);
2694 set_irq_flags(irq, IRQF_VALID); 2735 set_irq_flags(irq, IRQF_VALID);
2695 } 2736 }
2737 compute_armss_rate();
2696} 2738}
2697 2739
2698static void __init init_prcm_registers(void) 2740static void __init init_prcm_registers(void)
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 23108a6e3167..79c76ebdba52 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -61,7 +61,8 @@
61#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 61#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2
62 62
63#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) 63#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
64#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ 0x1 64#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
65#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16)
65 66
66#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) 67#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
67#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 68#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1
@@ -140,6 +141,7 @@
140/* PRCMU clock/PLL/reset registers */ 141/* PRCMU clock/PLL/reset registers */
141#define PRCM_PLLSOC0_FREQ (_PRCMU_BASE + 0x080) 142#define PRCM_PLLSOC0_FREQ (_PRCMU_BASE + 0x080)
142#define PRCM_PLLSOC1_FREQ (_PRCMU_BASE + 0x084) 143#define PRCM_PLLSOC1_FREQ (_PRCMU_BASE + 0x084)
144#define PRCM_PLLARM_FREQ (_PRCMU_BASE + 0x088)
143#define PRCM_PLLDDR_FREQ (_PRCMU_BASE + 0x08C) 145#define PRCM_PLLDDR_FREQ (_PRCMU_BASE + 0x08C)
144#define PRCM_PLL_FREQ_D_SHIFT 0 146#define PRCM_PLL_FREQ_D_SHIFT 0
145#define PRCM_PLL_FREQ_D_MASK BITS(0, 7) 147#define PRCM_PLL_FREQ_D_MASK BITS(0, 7)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 252aaefcacfa..d944d6ef7da8 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,6 +22,8 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/slab.h> 24#include <linux/slab.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
25 27
26#include <mach/dma.h> 28#include <mach/dma.h>
27#include <plat/pxa3xx_nand.h> 29#include <plat/pxa3xx_nand.h>
@@ -1032,7 +1034,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
1032 struct pxa3xx_nand_platform_data *pdata; 1034 struct pxa3xx_nand_platform_data *pdata;
1033 struct pxa3xx_nand_info *info; 1035 struct pxa3xx_nand_info *info;
1034 struct pxa3xx_nand_host *host; 1036 struct pxa3xx_nand_host *host;
1035 struct nand_chip *chip; 1037 struct nand_chip *chip = NULL;
1036 struct mtd_info *mtd; 1038 struct mtd_info *mtd;
1037 struct resource *r; 1039 struct resource *r;
1038 int ret, irq, cs; 1040 int ret, irq, cs;
@@ -1081,21 +1083,31 @@ static int alloc_nand_resource(struct platform_device *pdev)
1081 } 1083 }
1082 clk_enable(info->clk); 1084 clk_enable(info->clk);
1083 1085
1084 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1086 /*
1085 if (r == NULL) { 1087 * This is a dirty hack to make this driver work from devicetree
1086 dev_err(&pdev->dev, "no resource defined for data DMA\n"); 1088 * bindings. It can be removed once we have a prober DMA controller
1087 ret = -ENXIO; 1089 * framework for DT.
1088 goto fail_put_clk; 1090 */
1089 } 1091 if (pdev->dev.of_node && cpu_is_pxa3xx()) {
1090 info->drcmr_dat = r->start; 1092 info->drcmr_dat = 97;
1093 info->drcmr_cmd = 99;
1094 } else {
1095 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1096 if (r == NULL) {
1097 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1098 ret = -ENXIO;
1099 goto fail_put_clk;
1100 }
1101 info->drcmr_dat = r->start;
1091 1102
1092 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1103 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1093 if (r == NULL) { 1104 if (r == NULL) {
1094 dev_err(&pdev->dev, "no resource defined for command DMA\n"); 1105 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1095 ret = -ENXIO; 1106 ret = -ENXIO;
1096 goto fail_put_clk; 1107 goto fail_put_clk;
1108 }
1109 info->drcmr_cmd = r->start;
1097 } 1110 }
1098 info->drcmr_cmd = r->start;
1099 1111
1100 irq = platform_get_irq(pdev, 0); 1112 irq = platform_get_irq(pdev, 0);
1101 if (irq < 0) { 1113 if (irq < 0) {
@@ -1200,12 +1212,55 @@ static int pxa3xx_nand_remove(struct platform_device *pdev)
1200 return 0; 1212 return 0;
1201} 1213}
1202 1214
1215#ifdef CONFIG_OF
1216static struct of_device_id pxa3xx_nand_dt_ids[] = {
1217 { .compatible = "marvell,pxa3xx-nand" },
1218 {}
1219};
1220MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1221
1222static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1223{
1224 struct pxa3xx_nand_platform_data *pdata;
1225 struct device_node *np = pdev->dev.of_node;
1226 const struct of_device_id *of_id =
1227 of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
1228
1229 if (!of_id)
1230 return 0;
1231
1232 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1233 if (!pdata)
1234 return -ENOMEM;
1235
1236 if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
1237 pdata->enable_arbiter = 1;
1238 if (of_get_property(np, "marvell,nand-keep-config", NULL))
1239 pdata->keep_config = 1;
1240 of_property_read_u32(np, "num-cs", &pdata->num_cs);
1241
1242 pdev->dev.platform_data = pdata;
1243
1244 return 0;
1245}
1246#else
1247static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
1248{
1249 return 0;
1250}
1251#endif
1252
1203static int pxa3xx_nand_probe(struct platform_device *pdev) 1253static int pxa3xx_nand_probe(struct platform_device *pdev)
1204{ 1254{
1205 struct pxa3xx_nand_platform_data *pdata; 1255 struct pxa3xx_nand_platform_data *pdata;
1256 struct mtd_part_parser_data ppdata = {};
1206 struct pxa3xx_nand_info *info; 1257 struct pxa3xx_nand_info *info;
1207 int ret, cs, probe_success; 1258 int ret, cs, probe_success;
1208 1259
1260 ret = pxa3xx_nand_probe_dt(pdev);
1261 if (ret)
1262 return ret;
1263
1209 pdata = pdev->dev.platform_data; 1264 pdata = pdev->dev.platform_data;
1210 if (!pdata) { 1265 if (!pdata) {
1211 dev_err(&pdev->dev, "no platform data defined\n"); 1266 dev_err(&pdev->dev, "no platform data defined\n");
@@ -1229,8 +1284,9 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
1229 continue; 1284 continue;
1230 } 1285 }
1231 1286
1287 ppdata.of_node = pdev->dev.of_node;
1232 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL, 1288 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
1233 NULL, pdata->parts[cs], 1289 &ppdata, pdata->parts[cs],
1234 pdata->nr_parts[cs]); 1290 pdata->nr_parts[cs]);
1235 if (!ret) 1291 if (!ret)
1236 probe_success = 1; 1292 probe_success = 1;
@@ -1306,6 +1362,7 @@ static int pxa3xx_nand_resume(struct platform_device *pdev)
1306static struct platform_driver pxa3xx_nand_driver = { 1362static struct platform_driver pxa3xx_nand_driver = {
1307 .driver = { 1363 .driver = {
1308 .name = "pxa3xx-nand", 1364 .name = "pxa3xx-nand",
1365 .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
1309 }, 1366 },
1310 .probe = pxa3xx_nand_probe, 1367 .probe = pxa3xx_nand_probe,
1311 .remove = pxa3xx_nand_remove, 1368 .remove = pxa3xx_nand_remove,
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 7fca6ce5952b..304360cd213e 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -17,6 +17,7 @@
17#include <linux/pinctrl/pinctrl.h> 17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h> 18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/consumer.h> 19#include <linux/pinctrl/consumer.h>
20#include <linux/pinctrl/machine.h>
20#include <linux/of.h> 21#include <linux/of.h>
21#include <linux/of_address.h> 22#include <linux/of_address.h>
22#include <linux/of_device.h> 23#include <linux/of_device.h>
@@ -916,11 +917,66 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
916 seq_printf(s, " " DRIVER_NAME); 917 seq_printf(s, " " DRIVER_NAME);
917} 918}
918 919
920static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
921 struct device_node *np_config,
922 struct pinctrl_map **map, unsigned *num_maps)
923{
924 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
925 struct device_node *np;
926 struct property *prop;
927 const char *function, *group;
928 int ret, index = 0, count = 0;
929
930 /* calculate number of maps required */
931 for_each_child_of_node(np_config, np) {
932 ret = of_property_read_string(np, "sirf,function", &function);
933 if (ret < 0)
934 return ret;
935
936 ret = of_property_count_strings(np, "sirf,pins");
937 if (ret < 0)
938 return ret;
939
940 count += ret;
941 }
942
943 if (!count) {
944 dev_err(spmx->dev, "No child nodes passed via DT\n");
945 return -ENODEV;
946 }
947
948 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
949 if (!*map)
950 return -ENOMEM;
951
952 for_each_child_of_node(np_config, np) {
953 of_property_read_string(np, "sirf,function", &function);
954 of_property_for_each_string(np, "sirf,pins", prop, group) {
955 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
956 (*map)[index].data.mux.group = group;
957 (*map)[index].data.mux.function = function;
958 index++;
959 }
960 }
961
962 *num_maps = count;
963
964 return 0;
965}
966
967static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
968 struct pinctrl_map *map, unsigned num_maps)
969{
970 kfree(map);
971}
972
919static struct pinctrl_ops sirfsoc_pctrl_ops = { 973static struct pinctrl_ops sirfsoc_pctrl_ops = {
920 .get_groups_count = sirfsoc_get_groups_count, 974 .get_groups_count = sirfsoc_get_groups_count,
921 .get_group_name = sirfsoc_get_group_name, 975 .get_group_name = sirfsoc_get_group_name,
922 .get_group_pins = sirfsoc_get_group_pins, 976 .get_group_pins = sirfsoc_get_group_pins,
923 .pin_dbg_show = sirfsoc_pin_dbg_show, 977 .pin_dbg_show = sirfsoc_pin_dbg_show,
978 .dt_node_to_map = sirfsoc_dt_node_to_map,
979 .dt_free_map = sirfsoc_dt_free_map,
924}; 980};
925 981
926struct sirfsoc_pmx_func { 982struct sirfsoc_pmx_func {
@@ -1221,7 +1277,7 @@ out_no_gpio_remap:
1221} 1277}
1222 1278
1223static const struct of_device_id pinmux_ids[] __devinitconst = { 1279static const struct of_device_id pinmux_ids[] __devinitconst = {
1224 { .compatible = "sirf,prima2-gpio-pinmux" }, 1280 { .compatible = "sirf,prima2-pinctrl" },
1225 {} 1281 {}
1226}; 1282};
1227 1283
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 0075c8fd93d8..f771b2ee4b18 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -27,6 +27,8 @@
27#include <linux/interrupt.h> 27#include <linux/interrupt.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
30 32
31#include <mach/hardware.h> 33#include <mach/hardware.h>
32 34
@@ -396,6 +398,14 @@ static int __exit pxa_rtc_remove(struct platform_device *pdev)
396 return 0; 398 return 0;
397} 399}
398 400
401#ifdef CONFIG_OF
402static struct of_device_id pxa_rtc_dt_ids[] = {
403 { .compatible = "marvell,pxa-rtc" },
404 {}
405};
406MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
407#endif
408
399#ifdef CONFIG_PM 409#ifdef CONFIG_PM
400static int pxa_rtc_suspend(struct device *dev) 410static int pxa_rtc_suspend(struct device *dev)
401{ 411{
@@ -425,6 +435,7 @@ static struct platform_driver pxa_rtc_driver = {
425 .remove = __exit_p(pxa_rtc_remove), 435 .remove = __exit_p(pxa_rtc_remove),
426 .driver = { 436 .driver = {
427 .name = "pxa-rtc", 437 .name = "pxa-rtc",
438 .of_match_table = of_match_ptr(pxa_rtc_dt_ids),
428#ifdef CONFIG_PM 439#ifdef CONFIG_PM
429 .pm = &pxa_rtc_pm_ops, 440 .pm = &pxa_rtc_pm_ops,
430#endif 441#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 13:36:57 -0500