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authorRalph Metzler <rjkm@metzlerbros.de>2011-07-03 12:36:17 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-07-27 16:55:40 -0400
commite8783950f8a3a240c81c0d8d3becbda4b56c1794 (patch)
treecb080618b84d30284637b47a8e12b60c8ef672ce /drivers
parentebee4b589ffeb8dd700c2a3649e31f4e41c1bb6b (diff)
[media] tda18271c2dd: Initial check-in
Driver for the NXP TDA18271c2 silicon tuner. Signed-off-by: Ralph Metzler <rjkm@metzlerbros.de> Signed-off-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/dvb/frontends/tda18271c2dd.c1063
-rw-r--r--drivers/media/dvb/frontends/tda18271c2dd.h5
-rw-r--r--drivers/media/dvb/frontends/tda18271c2dd_maps.h810
3 files changed, 1878 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/tda18271c2dd.c b/drivers/media/dvb/frontends/tda18271c2dd.c
new file mode 100644
index 000000000000..b4a23bf00104
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda18271c2dd.c
@@ -0,0 +1,1063 @@
1/*
2 * tda18271c2dd: Driver for the TDA18271C2 tuner
3 *
4 * Copyright (C) 2010 Digital Devices GmbH
5 *
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 only, as published by the Free Software Foundation.
10 *
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * 02110-1301, USA
22 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/init.h>
29#include <linux/delay.h>
30#include <linux/firmware.h>
31#include <linux/i2c.h>
32#include <linux/version.h>
33#include <asm/div64.h>
34
35#include "dvb_frontend.h"
36
37struct SStandardParam {
38 s32 m_IFFrequency;
39 u32 m_BandWidth;
40 u8 m_EP3_4_0;
41 u8 m_EB22;
42};
43
44struct SMap {
45 u32 m_Frequency;
46 u8 m_Param;
47};
48
49struct SMapI {
50 u32 m_Frequency;
51 s32 m_Param;
52};
53
54struct SMap2 {
55 u32 m_Frequency;
56 u8 m_Param1;
57 u8 m_Param2;
58};
59
60struct SRFBandMap {
61 u32 m_RF_max;
62 u32 m_RF1_Default;
63 u32 m_RF2_Default;
64 u32 m_RF3_Default;
65};
66
67enum ERegister
68{
69 ID = 0,
70 TM,
71 PL,
72 EP1, EP2, EP3, EP4, EP5,
73 CPD, CD1, CD2, CD3,
74 MPD, MD1, MD2, MD3,
75 EB1, EB2, EB3, EB4, EB5, EB6, EB7, EB8, EB9, EB10,
76 EB11, EB12, EB13, EB14, EB15, EB16, EB17, EB18, EB19, EB20,
77 EB21, EB22, EB23,
78 NUM_REGS
79};
80
81struct tda_state {
82 struct i2c_adapter *i2c;
83 u8 adr;
84
85 u32 m_Frequency;
86 u32 IF;
87
88 u8 m_IFLevelAnalog;
89 u8 m_IFLevelDigital;
90 u8 m_IFLevelDVBC;
91 u8 m_IFLevelDVBT;
92
93 u8 m_EP4;
94 u8 m_EP3_Standby;
95
96 bool m_bMaster;
97
98 s32 m_SettlingTime;
99
100 u8 m_Regs[NUM_REGS];
101
102 /* Tracking filter settings for band 0..6 */
103 u32 m_RF1[7];
104 s32 m_RF_A1[7];
105 s32 m_RF_B1[7];
106 u32 m_RF2[7];
107 s32 m_RF_A2[7];
108 s32 m_RF_B2[7];
109 u32 m_RF3[7];
110
111 u8 m_TMValue_RFCal; /* Calibration temperatur */
112
113 bool m_bFMInput; /* true to use Pin 8 for FM Radio */
114
115};
116
117static int PowerScan(struct tda_state *state,
118 u8 RFBand,u32 RF_in,
119 u32 * pRF_Out, bool *pbcal);
120
121static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len)
122{
123 struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD,
124 .buf = data, .len = len}};
125 return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
126}
127
128static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
129{
130 struct i2c_msg msg = {.addr = adr, .flags = 0,
131 .buf = data, .len = len};
132
133 if (i2c_transfer(adap, &msg, 1) != 1) {
134 printk("i2c_write error\n");
135 return -1;
136 }
137 return 0;
138}
139
140static int WriteRegs(struct tda_state *state,
141 u8 SubAddr, u8 *Regs, u16 nRegs)
142{
143 u8 data[nRegs+1];
144
145 data[0] = SubAddr;
146 memcpy(data + 1, Regs, nRegs);
147 return i2c_write(state->i2c, state->adr, data, nRegs+1);
148}
149
150static int WriteReg(struct tda_state *state, u8 SubAddr,u8 Reg)
151{
152 u8 msg[2] = {SubAddr, Reg};
153
154 return i2c_write(state->i2c, state->adr, msg, 2);
155}
156
157static int Read(struct tda_state *state, u8 * Regs)
158{
159 return i2c_readn(state->i2c, state->adr, Regs, 16);
160}
161
162static int ReadExtented(struct tda_state *state, u8 * Regs)
163{
164 return i2c_readn(state->i2c, state->adr, Regs, NUM_REGS);
165}
166
167static int UpdateRegs(struct tda_state *state, u8 RegFrom,u8 RegTo)
168{
169 return WriteRegs(state, RegFrom,
170 &state->m_Regs[RegFrom], RegTo-RegFrom+1);
171}
172static int UpdateReg(struct tda_state *state, u8 Reg)
173{
174 return WriteReg(state, Reg,state->m_Regs[Reg]);
175}
176
177#include "tda18271c2dd_maps.h"
178
179#undef CHK_ERROR
180#define CHK_ERROR(s) if ((status = s) < 0) break
181
182static void reset(struct tda_state *state)
183{
184 u32 ulIFLevelAnalog = 0;
185 u32 ulIFLevelDigital = 2;
186 u32 ulIFLevelDVBC = 7;
187 u32 ulIFLevelDVBT = 6;
188 u32 ulXTOut = 0;
189 u32 ulStandbyMode = 0x06; // Send in stdb, but leave osc on
190 u32 ulSlave = 0;
191 u32 ulFMInput = 0;
192 u32 ulSettlingTime = 100;
193
194 state->m_Frequency = 0;
195 state->m_SettlingTime = 100;
196 state->m_IFLevelAnalog = (ulIFLevelAnalog & 0x07) << 2;
197 state->m_IFLevelDigital = (ulIFLevelDigital & 0x07) << 2;
198 state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07) << 2;
199 state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07) << 2;
200
201 state->m_EP4 = 0x20;
202 if( ulXTOut != 0 ) state->m_EP4 |= 0x40;
203
204 state->m_EP3_Standby = ((ulStandbyMode & 0x07) << 5) | 0x0F;
205 state->m_bMaster = (ulSlave == 0);
206
207 state->m_SettlingTime = ulSettlingTime;
208
209 state->m_bFMInput = (ulFMInput == 2);
210}
211
212static bool SearchMap1(struct SMap Map[],
213 u32 Frequency, u8 *pParam)
214{
215 int i = 0;
216
217 while ((Map[i].m_Frequency != 0) && (Frequency > Map[i].m_Frequency) )
218 i += 1;
219 if (Map[i].m_Frequency == 0)
220 return false;
221 *pParam = Map[i].m_Param;
222 return true;
223}
224
225static bool SearchMap2(struct SMapI Map[],
226 u32 Frequency, s32 *pParam)
227{
228 int i = 0;
229
230 while ((Map[i].m_Frequency != 0) &&
231 (Frequency > Map[i].m_Frequency) )
232 i += 1;
233 if (Map[i].m_Frequency == 0)
234 return false;
235 *pParam = Map[i].m_Param;
236 return true;
237}
238
239static bool SearchMap3(struct SMap2 Map[],u32 Frequency,
240 u8 *pParam1, u8 *pParam2)
241{
242 int i = 0;
243
244 while ((Map[i].m_Frequency != 0) &&
245 (Frequency > Map[i].m_Frequency) )
246 i += 1;
247 if (Map[i].m_Frequency == 0)
248 return false;
249 *pParam1 = Map[i].m_Param1;
250 *pParam2 = Map[i].m_Param2;
251 return true;
252}
253
254static bool SearchMap4(struct SRFBandMap Map[],
255 u32 Frequency, u8 *pRFBand)
256{
257 int i = 0;
258
259 while (i < 7 && (Frequency > Map[i].m_RF_max))
260 i += 1;
261 if (i == 7)
262 return false;
263 *pRFBand = i;
264 return true;
265}
266
267static int ThermometerRead(struct tda_state *state, u8 *pTM_Value)
268{
269 int status = 0;
270
271 do {
272 u8 Regs[16];
273 state->m_Regs[TM] |= 0x10;
274 CHK_ERROR(UpdateReg(state,TM));
275 CHK_ERROR(Read(state,Regs));
276 if( ( (Regs[TM] & 0x0F) == 0 && (Regs[TM] & 0x20) == 0x20 ) ||
277 ( (Regs[TM] & 0x0F) == 8 && (Regs[TM] & 0x20) == 0x00 ) ) {
278 state->m_Regs[TM] ^= 0x20;
279 CHK_ERROR(UpdateReg(state,TM));
280 msleep(10);
281 CHK_ERROR(Read(state,Regs));
282 }
283 *pTM_Value = (Regs[TM] & 0x20 ) ? m_Thermometer_Map_2[Regs[TM] & 0x0F] :
284 m_Thermometer_Map_1[Regs[TM] & 0x0F] ;
285 state->m_Regs[TM] &= ~0x10; // Thermometer off
286 CHK_ERROR(UpdateReg(state,TM));
287 state->m_Regs[EP4] &= ~0x03; // CAL_mode = 0 ?????????
288 CHK_ERROR(UpdateReg(state,EP4));
289 } while(0);
290
291 return status;
292}
293
294static int StandBy(struct tda_state *state)
295{
296 int status = 0;
297 do {
298 state->m_Regs[EB12] &= ~0x20; // PD_AGC1_Det = 0
299 CHK_ERROR(UpdateReg(state,EB12));
300 state->m_Regs[EB18] &= ~0x83; // AGC1_loop_off = 0, AGC1_Gain = 6 dB
301 CHK_ERROR(UpdateReg(state,EB18));
302 state->m_Regs[EB21] |= 0x03; // AGC2_Gain = -6 dB
303 state->m_Regs[EP3] = state->m_EP3_Standby;
304 CHK_ERROR(UpdateReg(state,EP3));
305 state->m_Regs[EB23] &= ~0x06; // ForceLP_Fc2_En = 0, LP_Fc[2] = 0
306 CHK_ERROR(UpdateRegs(state,EB21,EB23));
307 } while(0);
308 return status;
309}
310
311static int CalcMainPLL(struct tda_state *state, u32 freq)
312{
313
314 u8 PostDiv;
315 u8 Div;
316 u64 OscFreq;
317 u32 MainDiv;
318
319 if (!SearchMap3(m_Main_PLL_Map, freq, &PostDiv, &Div)) {
320 return -EINVAL;
321 }
322
323 OscFreq = (u64) freq * (u64) Div;
324 OscFreq *= (u64) 16384;
325 do_div(OscFreq, (u64)16000000);
326 MainDiv = OscFreq;
327
328 state->m_Regs[MPD] = PostDiv & 0x77;
329 state->m_Regs[MD1] = ((MainDiv >> 16) & 0x7F);
330 state->m_Regs[MD2] = ((MainDiv >> 8) & 0xFF);
331 state->m_Regs[MD3] = ((MainDiv ) & 0xFF);
332
333 return UpdateRegs(state, MPD, MD3);
334}
335
336static int CalcCalPLL(struct tda_state *state, u32 freq)
337{
338 //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d)\n",freq));
339
340 u8 PostDiv;
341 u8 Div;
342 u64 OscFreq;
343 u32 CalDiv;
344
345 if( !SearchMap3(m_Cal_PLL_Map,freq,&PostDiv,&Div) )
346 {
347 return -EINVAL;
348 }
349
350 OscFreq = (u64)freq * (u64)Div;
351 //CalDiv = u32( OscFreq * 16384 / 16000000 );
352 OscFreq*=(u64)16384;
353 do_div(OscFreq, (u64)16000000);
354 CalDiv=OscFreq;
355
356 state->m_Regs[CPD] = PostDiv;
357 state->m_Regs[CD1] = ((CalDiv >> 16) & 0xFF);
358 state->m_Regs[CD2] = ((CalDiv >> 8) & 0xFF);
359 state->m_Regs[CD3] = ((CalDiv ) & 0xFF);
360
361 return UpdateRegs(state,CPD,CD3);
362}
363
364static int CalibrateRF(struct tda_state *state,
365 u8 RFBand,u32 freq, s32 * pCprog)
366{
367 //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " ID = %02x\n",state->m_Regs[ID]));
368 int status = 0;
369 u8 Regs[NUM_REGS];
370 do {
371 u8 BP_Filter=0;
372 u8 GainTaper=0;
373 u8 RFC_K=0;
374 u8 RFC_M=0;
375
376 state->m_Regs[EP4] &= ~0x03; // CAL_mode = 0
377 CHK_ERROR(UpdateReg(state,EP4));
378 state->m_Regs[EB18] |= 0x03; // AGC1_Gain = 3
379 CHK_ERROR(UpdateReg(state,EB18));
380
381 // Switching off LT (as datasheet says) causes calibration on C1 to fail
382 // (Readout of Cprog is allways 255)
383 if( state->m_Regs[ID] != 0x83 ) // C1: ID == 83, C2: ID == 84
384 {
385 state->m_Regs[EP3] |= 0x40; // SM_LT = 1
386 }
387
388 if( ! ( SearchMap1(m_BP_Filter_Map,freq,&BP_Filter) &&
389 SearchMap1(m_GainTaper_Map,freq,&GainTaper) &&
390 SearchMap3(m_KM_Map,freq,&RFC_K,&RFC_M)) )
391 {
392 return -EINVAL;
393 }
394
395 state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | BP_Filter;
396 state->m_Regs[EP2] = (RFBand << 5) | GainTaper;
397
398 state->m_Regs[EB13] = (state->m_Regs[EB13] & ~0x7C) | (RFC_K << 4) | (RFC_M << 2);
399
400 CHK_ERROR(UpdateRegs(state,EP1,EP3));
401 CHK_ERROR(UpdateReg(state,EB13));
402
403 state->m_Regs[EB4] |= 0x20; // LO_ForceSrce = 1
404 CHK_ERROR(UpdateReg(state,EB4));
405
406 state->m_Regs[EB7] |= 0x20; // CAL_ForceSrce = 1
407 CHK_ERROR(UpdateReg(state,EB7));
408
409 state->m_Regs[EB14] = 0; // RFC_Cprog = 0
410 CHK_ERROR(UpdateReg(state,EB14));
411
412 state->m_Regs[EB20] &= ~0x20; // ForceLock = 0;
413 CHK_ERROR(UpdateReg(state,EB20));
414
415 state->m_Regs[EP4] |= 0x03; // CAL_Mode = 3
416 CHK_ERROR(UpdateRegs(state,EP4,EP5));
417
418 CHK_ERROR(CalcCalPLL(state,freq));
419 CHK_ERROR(CalcMainPLL(state,freq + 1000000));
420
421 msleep(5);
422 CHK_ERROR(UpdateReg(state,EP2));
423 CHK_ERROR(UpdateReg(state,EP1));
424 CHK_ERROR(UpdateReg(state,EP2));
425 CHK_ERROR(UpdateReg(state,EP1));
426
427 state->m_Regs[EB4] &= ~0x20; // LO_ForceSrce = 0
428 CHK_ERROR(UpdateReg(state,EB4));
429
430 state->m_Regs[EB7] &= ~0x20; // CAL_ForceSrce = 0
431 CHK_ERROR(UpdateReg(state,EB7));
432 msleep(10);
433
434 state->m_Regs[EB20] |= 0x20; // ForceLock = 1;
435 CHK_ERROR(UpdateReg(state,EB20));
436 msleep(60);
437
438 state->m_Regs[EP4] &= ~0x03; // CAL_Mode = 0
439 state->m_Regs[EP3] &= ~0x40; // SM_LT = 0
440 state->m_Regs[EB18] &= ~0x03; // AGC1_Gain = 0
441 CHK_ERROR(UpdateReg(state,EB18));
442 CHK_ERROR(UpdateRegs(state,EP3,EP4));
443 CHK_ERROR(UpdateReg(state,EP1));
444
445 CHK_ERROR(ReadExtented(state,Regs));
446
447 *pCprog = Regs[EB14];
448 //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " Cprog = %d\n",Regs[EB14]));
449
450 } while(0);
451 return status;
452}
453
454static int RFTrackingFiltersInit(struct tda_state *state,
455 u8 RFBand)
456{
457 //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
458 int status = 0;
459
460 u32 RF1 = m_RF_Band_Map[RFBand].m_RF1_Default;
461 u32 RF2 = m_RF_Band_Map[RFBand].m_RF2_Default;
462 u32 RF3 = m_RF_Band_Map[RFBand].m_RF3_Default;
463 bool bcal = false;
464
465 s32 Cprog_cal1 = 0;
466 s32 Cprog_table1 = 0;
467 s32 Cprog_cal2 = 0;
468 s32 Cprog_table2 = 0;
469 s32 Cprog_cal3 = 0;
470 s32 Cprog_table3 = 0;
471
472 state->m_RF_A1[RFBand] = 0;
473 state->m_RF_B1[RFBand] = 0;
474 state->m_RF_A2[RFBand] = 0;
475 state->m_RF_B2[RFBand] = 0;
476
477 do {
478 CHK_ERROR(PowerScan(state,RFBand,RF1,&RF1,&bcal));
479 if( bcal ) {
480 CHK_ERROR(CalibrateRF(state,RFBand,RF1,&Cprog_cal1));
481 }
482 SearchMap2(m_RF_Cal_Map,RF1,&Cprog_table1);
483 if( !bcal ) {
484 Cprog_cal1 = Cprog_table1;
485 }
486 state->m_RF_B1[RFBand] = Cprog_cal1 - Cprog_table1;
487 //state->m_RF_A1[RF_Band] = ????
488
489 if( RF2 == 0 ) break;
490
491 CHK_ERROR(PowerScan(state,RFBand,RF2,&RF2,&bcal));
492 if( bcal ) {
493 CHK_ERROR(CalibrateRF(state,RFBand,RF2,&Cprog_cal2));
494 }
495 SearchMap2(m_RF_Cal_Map,RF2,&Cprog_table2);
496 if( !bcal )
497 {
498 Cprog_cal2 = Cprog_table2;
499 }
500
501 state->m_RF_A1[RFBand] =
502 (Cprog_cal2 - Cprog_table2 - Cprog_cal1 + Cprog_table1) /
503 ((s32)(RF2)-(s32)(RF1));
504
505 if( RF3 == 0 ) break;
506
507 CHK_ERROR(PowerScan(state,RFBand,RF3,&RF3,&bcal));
508 if( bcal )
509 {
510 CHK_ERROR(CalibrateRF(state,RFBand,RF3,&Cprog_cal3));
511 }
512 SearchMap2(m_RF_Cal_Map,RF3,&Cprog_table3);
513 if( !bcal )
514 {
515 Cprog_cal3 = Cprog_table3;
516 }
517 state->m_RF_A2[RFBand] = (Cprog_cal3 - Cprog_table3 - Cprog_cal2 + Cprog_table2) / ((s32)(RF3)-(s32)(RF2));
518 state->m_RF_B2[RFBand] = Cprog_cal2 - Cprog_table2;
519
520 } while(0);
521
522 state->m_RF1[RFBand] = RF1;
523 state->m_RF2[RFBand] = RF2;
524 state->m_RF3[RFBand] = RF3;
525
526#if 0
527 printk("%s %d RF1 = %d A1 = %d B1 = %d RF2 = %d A2 = %d B2 = %d RF3 = %d\n", __FUNCTION__,
528 RFBand,RF1,state->m_RF_A1[RFBand],state->m_RF_B1[RFBand],RF2,
529 state->m_RF_A2[RFBand],state->m_RF_B2[RFBand],RF3);
530#endif
531
532 return status;
533}
534
535static int PowerScan(struct tda_state *state,
536 u8 RFBand,u32 RF_in, u32 * pRF_Out, bool *pbcal)
537{
538 //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "(%d,%d)\n",RFBand,RF_in));
539 int status = 0;
540 do {
541 u8 Gain_Taper=0;
542 s32 RFC_Cprog=0;
543 u8 CID_Target=0;
544 u8 CountLimit=0;
545 u32 freq_MainPLL;
546 u8 Regs[NUM_REGS];
547 u8 CID_Gain;
548 s32 Count = 0;
549 int sign = 1;
550 bool wait = false;
551
552 if( ! (SearchMap2(m_RF_Cal_Map,RF_in,&RFC_Cprog) &&
553 SearchMap1(m_GainTaper_Map,RF_in,&Gain_Taper) &&
554 SearchMap3(m_CID_Target_Map,RF_in,&CID_Target,&CountLimit) )) {
555 printk("%s Search map failed\n", __FUNCTION__);
556 return -EINVAL;
557 }
558
559 state->m_Regs[EP2] = (RFBand << 5) | Gain_Taper;
560 state->m_Regs[EB14] = (RFC_Cprog);
561 CHK_ERROR(UpdateReg(state,EP2));
562 CHK_ERROR(UpdateReg(state,EB14));
563
564 freq_MainPLL = RF_in + 1000000;
565 CHK_ERROR(CalcMainPLL(state,freq_MainPLL));
566 msleep(5);
567 state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; // CAL_mode = 1
568 CHK_ERROR(UpdateReg(state,EP4));
569 CHK_ERROR(UpdateReg(state,EP2)); // Launch power measurement
570 CHK_ERROR(ReadExtented(state,Regs));
571 CID_Gain = Regs[EB10] & 0x3F;
572 state->m_Regs[ID] = Regs[ID]; // Chip version, (needed for C1 workarround in CalibrateRF )
573
574 *pRF_Out = RF_in;
575
576 while( CID_Gain < CID_Target ) {
577 freq_MainPLL = RF_in + sign * Count + 1000000;
578 CHK_ERROR(CalcMainPLL(state,freq_MainPLL));
579 msleep( wait ? 5 : 1 );
580 wait = false;
581 CHK_ERROR(UpdateReg(state,EP2)); // Launch power measurement
582 CHK_ERROR(ReadExtented(state,Regs));
583 CID_Gain = Regs[EB10] & 0x3F;
584 Count += 200000;
585
586 if( Count < CountLimit * 100000 ) continue;
587 if( sign < 0 ) break;
588
589 sign = -sign;
590 Count = 200000;
591 wait = true;
592 }
593 CHK_ERROR(status);
594 if( CID_Gain >= CID_Target )
595 {
596 *pbcal = true;
597 *pRF_Out = freq_MainPLL - 1000000;
598 }
599 else
600 {
601 *pbcal = false;
602 }
603 } while(0);
604 //KdPrintEx((MSG_TRACE " - " __FUNCTION__ " Found = %d RF = %d\n",*pbcal,*pRF_Out));
605 return status;
606}
607
608static int PowerScanInit(struct tda_state *state)
609{
610 //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
611 int status = 0;
612 do
613 {
614 state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | 0x12;
615 state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); // If level = 0, Cal mode = 0
616 CHK_ERROR(UpdateRegs(state,EP3,EP4));
617 state->m_Regs[EB18] = (state->m_Regs[EB18] & ~0x03 ); // AGC 1 Gain = 0
618 CHK_ERROR(UpdateReg(state,EB18));
619 state->m_Regs[EB21] = (state->m_Regs[EB21] & ~0x03 ); // AGC 2 Gain = 0 (Datasheet = 3)
620 state->m_Regs[EB23] = (state->m_Regs[EB23] | 0x06 ); // ForceLP_Fc2_En = 1, LPFc[2] = 1
621 CHK_ERROR(UpdateRegs(state,EB21,EB23));
622 } while(0);
623 return status;
624}
625
626static int CalcRFFilterCurve(struct tda_state *state)
627{
628 //KdPrintEx((MSG_TRACE " - " __FUNCTION__ "\n"));
629 int status = 0;
630 do
631 {
632 msleep(200); // Temperature stabilisation
633 CHK_ERROR(PowerScanInit(state));
634 CHK_ERROR(RFTrackingFiltersInit(state,0));
635 CHK_ERROR(RFTrackingFiltersInit(state,1));
636 CHK_ERROR(RFTrackingFiltersInit(state,2));
637 CHK_ERROR(RFTrackingFiltersInit(state,3));
638 CHK_ERROR(RFTrackingFiltersInit(state,4));
639 CHK_ERROR(RFTrackingFiltersInit(state,5));
640 CHK_ERROR(RFTrackingFiltersInit(state,6));
641 CHK_ERROR(ThermometerRead(state,&state->m_TMValue_RFCal)); // also switches off Cal mode !!!
642 } while(0);
643
644 return status;
645}
646
647static int FixedContentsI2CUpdate(struct tda_state *state)
648{
649 static u8 InitRegs[] = {
650 0x08,0x80,0xC6,
651 0xDF,0x16,0x60,0x80,
652 0x80,0x00,0x00,0x00,
653 0x00,0x00,0x00,0x00,
654 0xFC,0x01,0x84,0x41,
655 0x01,0x84,0x40,0x07,
656 0x00,0x00,0x96,0x3F,
657 0xC1,0x00,0x8F,0x00,
658 0x00,0x8C,0x00,0x20,
659 0xB3,0x48,0xB0,
660 };
661 int status = 0;
662 memcpy(&state->m_Regs[TM],InitRegs,EB23-TM+1);
663 do {
664 CHK_ERROR(UpdateRegs(state,TM,EB23));
665
666 // AGC1 gain setup
667 state->m_Regs[EB17] = 0x00;
668 CHK_ERROR(UpdateReg(state,EB17));
669 state->m_Regs[EB17] = 0x03;
670 CHK_ERROR(UpdateReg(state,EB17));
671 state->m_Regs[EB17] = 0x43;
672 CHK_ERROR(UpdateReg(state,EB17));
673 state->m_Regs[EB17] = 0x4C;
674 CHK_ERROR(UpdateReg(state,EB17));
675
676 // IRC Cal Low band
677 state->m_Regs[EP3] = 0x1F;
678 state->m_Regs[EP4] = 0x66;
679 state->m_Regs[EP5] = 0x81;
680 state->m_Regs[CPD] = 0xCC;
681 state->m_Regs[CD1] = 0x6C;
682 state->m_Regs[CD2] = 0x00;
683 state->m_Regs[CD3] = 0x00;
684 state->m_Regs[MPD] = 0xC5;
685 state->m_Regs[MD1] = 0x77;
686 state->m_Regs[MD2] = 0x08;
687 state->m_Regs[MD3] = 0x00;
688 CHK_ERROR(UpdateRegs(state,EP2,MD3)); // diff between sw and datasheet (ep3-md3)
689
690 //state->m_Regs[EB4] = 0x61; // missing in sw
691 //CHK_ERROR(UpdateReg(state,EB4));
692 //msleep(1);
693 //state->m_Regs[EB4] = 0x41;
694 //CHK_ERROR(UpdateReg(state,EB4));
695
696 msleep(5);
697 CHK_ERROR(UpdateReg(state,EP1));
698 msleep(5);
699
700 state->m_Regs[EP5] = 0x85;
701 state->m_Regs[CPD] = 0xCB;
702 state->m_Regs[CD1] = 0x66;
703 state->m_Regs[CD2] = 0x70;
704 CHK_ERROR(UpdateRegs(state,EP3,CD3));
705 msleep(5);
706 CHK_ERROR(UpdateReg(state,EP2));
707 msleep(30);
708
709 // IRC Cal mid band
710 state->m_Regs[EP5] = 0x82;
711 state->m_Regs[CPD] = 0xA8;
712 state->m_Regs[CD2] = 0x00;
713 state->m_Regs[MPD] = 0xA1; // Datasheet = 0xA9
714 state->m_Regs[MD1] = 0x73;
715 state->m_Regs[MD2] = 0x1A;
716 CHK_ERROR(UpdateRegs(state,EP3,MD3));
717
718 msleep(5);
719 CHK_ERROR(UpdateReg(state,EP1));
720 msleep(5);
721
722 state->m_Regs[EP5] = 0x86;
723 state->m_Regs[CPD] = 0xA8;
724 state->m_Regs[CD1] = 0x66;
725 state->m_Regs[CD2] = 0xA0;
726 CHK_ERROR(UpdateRegs(state,EP3,CD3));
727 msleep(5);
728 CHK_ERROR(UpdateReg(state,EP2));
729 msleep(30);
730
731 // IRC Cal high band
732 state->m_Regs[EP5] = 0x83;
733 state->m_Regs[CPD] = 0x98;
734 state->m_Regs[CD1] = 0x65;
735 state->m_Regs[CD2] = 0x00;
736 state->m_Regs[MPD] = 0x91; // Datasheet = 0x91
737 state->m_Regs[MD1] = 0x71;
738 state->m_Regs[MD2] = 0xCD;
739 CHK_ERROR(UpdateRegs(state,EP3,MD3));
740 msleep(5);
741 CHK_ERROR(UpdateReg(state,EP1));
742 msleep(5);
743 state->m_Regs[EP5] = 0x87;
744 state->m_Regs[CD1] = 0x65;
745 state->m_Regs[CD2] = 0x50;
746 CHK_ERROR(UpdateRegs(state,EP3,CD3));
747 msleep(5);
748 CHK_ERROR(UpdateReg(state,EP2));
749 msleep(30);
750
751 // Back to normal
752 state->m_Regs[EP4] = 0x64;
753 CHK_ERROR(UpdateReg(state,EP4));
754 CHK_ERROR(UpdateReg(state,EP1));
755
756 } while(0);
757 return status;
758}
759
760static int InitCal(struct tda_state *state)
761{
762 int status = 0;
763
764 do
765 {
766 CHK_ERROR(FixedContentsI2CUpdate(state));
767 CHK_ERROR(CalcRFFilterCurve(state));
768 CHK_ERROR(StandBy(state));
769 //m_bInitDone = true;
770 } while(0);
771 return status;
772};
773
774static int RFTrackingFiltersCorrection(struct tda_state *state,
775 u32 Frequency)
776{
777 int status = 0;
778 s32 Cprog_table;
779 u8 RFBand;
780 u8 dCoverdT;
781
782 if( !SearchMap2(m_RF_Cal_Map,Frequency,&Cprog_table) ||
783 !SearchMap4(m_RF_Band_Map,Frequency,&RFBand) ||
784 !SearchMap1(m_RF_Cal_DC_Over_DT_Map,Frequency,&dCoverdT) )
785 {
786 return -EINVAL;
787 }
788
789 do
790 {
791 u8 TMValue_Current;
792 u32 RF1 = state->m_RF1[RFBand];
793 u32 RF2 = state->m_RF1[RFBand];
794 u32 RF3 = state->m_RF1[RFBand];
795 s32 RF_A1 = state->m_RF_A1[RFBand];
796 s32 RF_B1 = state->m_RF_B1[RFBand];
797 s32 RF_A2 = state->m_RF_A2[RFBand];
798 s32 RF_B2 = state->m_RF_B2[RFBand];
799 s32 Capprox = 0;
800 int TComp;
801
802 state->m_Regs[EP3] &= ~0xE0; // Power up
803 CHK_ERROR(UpdateReg(state,EP3));
804
805 CHK_ERROR(ThermometerRead(state,&TMValue_Current));
806
807 if( RF3 == 0 || Frequency < RF2 )
808 {
809 Capprox = RF_A1 * ((s32)(Frequency) - (s32)(RF1)) + RF_B1 + Cprog_table;
810 }
811 else
812 {
813 Capprox = RF_A2 * ((s32)(Frequency) - (s32)(RF2)) + RF_B2 + Cprog_table;
814 }
815
816 TComp = (int)(dCoverdT) * ((int)(TMValue_Current) - (int)(state->m_TMValue_RFCal))/1000;
817
818 Capprox += TComp;
819
820 if( Capprox < 0 ) Capprox = 0;
821 else if( Capprox > 255 ) Capprox = 255;
822
823
824 // TODO Temperature compensation. There is defenitely a scale factor
825 // missing in the datasheet, so leave it out for now.
826 state->m_Regs[EB14] = (Capprox );
827
828 CHK_ERROR(UpdateReg(state,EB14));
829
830 } while(0);
831 return status;
832}
833
834static int ChannelConfiguration(struct tda_state *state,
835 u32 Frequency, int Standard)
836{
837
838 s32 IntermediateFrequency = m_StandardTable[Standard].m_IFFrequency;
839 int status = 0;
840
841 u8 BP_Filter = 0;
842 u8 RF_Band = 0;
843 u8 GainTaper = 0;
844 u8 IR_Meas;
845
846 state->IF=IntermediateFrequency;
847 //printk("%s Freq = %d Standard = %d IF = %d\n",__FUNCTION__,Frequency,Standard,IntermediateFrequency);
848 // get values from tables
849
850 if(! ( SearchMap1(m_BP_Filter_Map,Frequency,&BP_Filter) &&
851 SearchMap1(m_GainTaper_Map,Frequency,&GainTaper) &&
852 SearchMap1(m_IR_Meas_Map,Frequency,&IR_Meas) &&
853 SearchMap4(m_RF_Band_Map,Frequency,&RF_Band) ) )
854 {
855 printk("%s SearchMap failed\n", __FUNCTION__);
856 return -EINVAL;
857 }
858
859 do
860 {
861 state->m_Regs[EP3] = (state->m_Regs[EP3] & ~0x1F) | m_StandardTable[Standard].m_EP3_4_0;
862 state->m_Regs[EP3] &= ~0x04; // switch RFAGC to high speed mode
863
864 // m_EP4 default for XToutOn, CAL_Mode (0)
865 state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax )? state->m_IFLevelDigital : state->m_IFLevelAnalog );
866 //state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
867 if( Standard <= HF_AnalogMax ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
868 else if( Standard <= HF_ATSC ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
869 else if( Standard <= HF_DVBC ) state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
870 else state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
871
872 if( (Standard == HF_FM_Radio) && state->m_bFMInput ) state->m_Regs[EP4] |= 80;
873
874 state->m_Regs[MPD] &= ~0x80;
875 if( Standard > HF_AnalogMax ) state->m_Regs[MPD] |= 0x80; // Add IF_notch for digital
876
877 state->m_Regs[EB22] = m_StandardTable[Standard].m_EB22;
878
879 // Note: This is missing from flowchart in TDA18271 specification ( 1.5 MHz cutoff for FM )
880 if( Standard == HF_FM_Radio ) state->m_Regs[EB23] |= 0x06; // ForceLP_Fc2_En = 1, LPFc[2] = 1
881 else state->m_Regs[EB23] &= ~0x06; // ForceLP_Fc2_En = 0, LPFc[2] = 0
882
883 CHK_ERROR(UpdateRegs(state,EB22,EB23));
884
885 state->m_Regs[EP1] = (state->m_Regs[EP1] & ~0x07) | 0x40 | BP_Filter; // Dis_Power_level = 1, Filter
886 state->m_Regs[EP5] = (state->m_Regs[EP5] & ~0x07) | IR_Meas;
887 state->m_Regs[EP2] = (RF_Band << 5) | GainTaper;
888
889 state->m_Regs[EB1] = (state->m_Regs[EB1] & ~0x07) |
890 (state->m_bMaster ? 0x04 : 0x00); // CALVCO_FortLOn = MS
891 // AGC1_always_master = 0
892 // AGC_firstn = 0
893 CHK_ERROR(UpdateReg(state,EB1));
894
895 if( state->m_bMaster )
896 {
897 CHK_ERROR(CalcMainPLL(state,Frequency + IntermediateFrequency));
898 CHK_ERROR(UpdateRegs(state,TM,EP5));
899 state->m_Regs[EB4] |= 0x20; // LO_forceSrce = 1
900 CHK_ERROR(UpdateReg(state,EB4));
901 msleep(1);
902 state->m_Regs[EB4] &= ~0x20; // LO_forceSrce = 0
903 CHK_ERROR(UpdateReg(state,EB4));
904 }
905 else
906 {
907 u8 PostDiv;
908 u8 Div;
909 CHK_ERROR(CalcCalPLL(state,Frequency + IntermediateFrequency));
910
911 SearchMap3(m_Cal_PLL_Map,Frequency + IntermediateFrequency,&PostDiv,&Div);
912 state->m_Regs[MPD] = (state->m_Regs[MPD] & ~0x7F) | (PostDiv & 0x77);
913 CHK_ERROR(UpdateReg(state,MPD));
914 CHK_ERROR(UpdateRegs(state,TM,EP5));
915
916 state->m_Regs[EB7] |= 0x20; // CAL_forceSrce = 1
917 CHK_ERROR(UpdateReg(state,EB7));
918 msleep(1);
919 state->m_Regs[EB7] &= ~0x20; // CAL_forceSrce = 0
920 CHK_ERROR(UpdateReg(state,EB7));
921 }
922 msleep(20);
923 if( Standard != HF_FM_Radio )
924 {
925 state->m_Regs[EP3] |= 0x04; // RFAGC to normal mode
926 }
927 CHK_ERROR(UpdateReg(state,EP3));
928
929 } while(0);
930 return status;
931}
932
933static int sleep(struct dvb_frontend* fe)
934{
935 struct tda_state *state = fe->tuner_priv;
936
937 StandBy(state);
938 return 0;
939}
940
941static int init(struct dvb_frontend* fe)
942{
943 //struct tda_state *state = fe->tuner_priv;
944 return 0;
945}
946
947static int release(struct dvb_frontend* fe)
948{
949 kfree(fe->tuner_priv);
950 fe->tuner_priv = NULL;
951 return 0;
952}
953
954static int set_params(struct dvb_frontend *fe,
955 struct dvb_frontend_parameters *params)
956{
957 struct tda_state *state = fe->tuner_priv;
958 int status = 0;
959 int Standard;
960
961 state->m_Frequency = params->frequency;
962
963 if (fe->ops.info.type == FE_OFDM)
964 switch (params->u.ofdm.bandwidth) {
965 case BANDWIDTH_6_MHZ:
966 Standard = HF_DVBT_6MHZ;
967 break;
968 case BANDWIDTH_7_MHZ:
969 Standard = HF_DVBT_7MHZ;
970 break;
971 default:
972 case BANDWIDTH_8_MHZ:
973 Standard = HF_DVBT_8MHZ;
974 break;
975 }
976 else if (fe->ops.info.type == FE_QAM) {
977 Standard = HF_DVBC_8MHZ;
978 } else
979 return -EINVAL;
980 do {
981 CHK_ERROR(RFTrackingFiltersCorrection(state,params->frequency));
982 CHK_ERROR(ChannelConfiguration(state,params->frequency,Standard));
983
984 msleep(state->m_SettlingTime); // Allow AGC's to settle down
985 } while(0);
986 return status;
987}
988
989#if 0
990static int GetSignalStrength(s32 * pSignalStrength,u32 RFAgc,u32 IFAgc)
991{
992 if( IFAgc < 500 ) {
993 // Scale this from 0 to 50000
994 *pSignalStrength = IFAgc * 100;
995 } else {
996 // Scale range 500-1500 to 50000-80000
997 *pSignalStrength = 50000 + (IFAgc - 500) * 30;
998 }
999
1000 return 0;
1001}
1002#endif
1003
1004static int get_frequency(struct dvb_frontend *fe, u32 *frequency)
1005{
1006 struct tda_state *state = fe->tuner_priv;
1007
1008 *frequency = state->IF;
1009 return 0;
1010}
1011
1012static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
1013{
1014 //struct tda_state *state = fe->tuner_priv;
1015 //*bandwidth = priv->bandwidth;
1016 return 0;
1017}
1018
1019
1020static struct dvb_tuner_ops tuner_ops = {
1021 .info = {
1022 .name = "NXP TDA18271C2D",
1023 .frequency_min = 47125000,
1024 .frequency_max = 865000000,
1025 .frequency_step = 62500
1026 },
1027 .init = init,
1028 .sleep = sleep,
1029 .set_params = set_params,
1030 .release = release,
1031 .get_frequency = get_frequency,
1032 .get_bandwidth = get_bandwidth,
1033};
1034
1035struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
1036 struct i2c_adapter *i2c, u8 adr)
1037{
1038 struct tda_state *state;
1039
1040 state = kzalloc(sizeof(struct tda_state), GFP_KERNEL);
1041 if (!state)
1042 return NULL;
1043
1044 fe->tuner_priv = state;
1045 state->adr = adr;
1046 state->i2c = i2c;
1047 memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops));
1048 reset(state);
1049 InitCal(state);
1050
1051 return fe;
1052}
1053
1054EXPORT_SYMBOL_GPL(tda18271c2dd_attach);
1055MODULE_DESCRIPTION("TDA18271C2 driver");
1056MODULE_AUTHOR("DD");
1057MODULE_LICENSE("GPL");
1058
1059/*
1060 * Local variables:
1061 * c-basic-offset: 8
1062 * End:
1063 */
diff --git a/drivers/media/dvb/frontends/tda18271c2dd.h b/drivers/media/dvb/frontends/tda18271c2dd.h
new file mode 100644
index 000000000000..492badd50231
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda18271c2dd.h
@@ -0,0 +1,5 @@
1#ifndef _TDA18271C2DD_H_
2#define _TDA18271C2DD_H_
3struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe,
4 struct i2c_adapter *i2c, u8 adr);
5#endif
diff --git a/drivers/media/dvb/frontends/tda18271c2dd_maps.h b/drivers/media/dvb/frontends/tda18271c2dd_maps.h
new file mode 100644
index 000000000000..21fa4e1d9277
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda18271c2dd_maps.h
@@ -0,0 +1,810 @@
1enum HF_S {
2 HF_None=0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
3 HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ,
4 HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ,
5 HF_DVBC_8MHZ, HF_DVBC
6};
7
8struct SStandardParam m_StandardTable[] =
9{
10 { 0, 0, 0x00, 0x00 }, // HF_None
11 { 6000000, 7000000, 0x1D, 0x2C }, // HF_B,
12 { 6900000, 8000000, 0x1E, 0x2C }, // HF_DK,
13 { 7100000, 8000000, 0x1E, 0x2C }, // HF_G,
14 { 7250000, 8000000, 0x1E, 0x2C }, // HF_I,
15 { 6900000, 8000000, 0x1E, 0x2C }, // HF_L,
16 { 1250000, 8000000, 0x1E, 0x2C }, // HF_L1,
17 { 5400000, 6000000, 0x1C, 0x2C }, // HF_MN,
18 { 1250000, 500000, 0x18, 0x2C }, // HF_FM_Radio,
19 { 0, 0, 0x00, 0x00 }, // HF_AnalogMax (Unused)
20 { 3300000, 6000000, 0x1C, 0x58 }, // HF_DVBT_6MHZ
21 { 3500000, 7000000, 0x1C, 0x37 }, // HF_DVBT_7MHZ
22 { 4000000, 8000000, 0x1D, 0x37 }, // HF_DVBT_8MHZ
23 { 0, 0, 0x00, 0x00 }, // HF_DVBT (Unused)
24 { 5000000, 6000000, 0x1C, 0x37 }, // HF_ATSC (center = 3.25 MHz)
25 { 4000000, 6000000, 0x1D, 0x58 }, // HF_DVBC_6MHZ (Chicago)
26 { 4500000, 7000000, 0x1E, 0x37 }, // HF_DVBC_7MHZ (not documented by NXP)
27 { 5000000, 8000000, 0x1F, 0x37 }, // HF_DVBC_8MHZ
28 { 0, 0, 0x00, 0x00 }, // HF_DVBC (Unused)
29};
30
31struct SMap m_BP_Filter_Map[] = {
32 { 62000000, 0x00 },
33 { 84000000, 0x01 },
34 { 100000000, 0x02 },
35 { 140000000, 0x03 },
36 { 170000000, 0x04 },
37 { 180000000, 0x05 },
38 { 865000000, 0x06 },
39 { 0, 0x00 }, // Table End
40};
41
42static struct SMapI m_RF_Cal_Map[] = {
43 { 41000000, 0x0F },
44 { 43000000, 0x1C },
45 { 45000000, 0x2F },
46 { 46000000, 0x39 },
47 { 47000000, 0x40 },
48 { 47900000, 0x50 },
49 { 49100000, 0x16 },
50 { 50000000, 0x18 },
51 { 51000000, 0x20 },
52 { 53000000, 0x28 },
53 { 55000000, 0x2B },
54 { 56000000, 0x32 },
55 { 57000000, 0x35 },
56 { 58000000, 0x3E },
57 { 59000000, 0x43 },
58 { 60000000, 0x4E },
59 { 61100000, 0x55 },
60 { 63000000, 0x0F },
61 { 64000000, 0x11 },
62 { 65000000, 0x12 },
63 { 66000000, 0x15 },
64 { 67000000, 0x16 },
65 { 68000000, 0x17 },
66 { 70000000, 0x19 },
67 { 71000000, 0x1C },
68 { 72000000, 0x1D },
69 { 73000000, 0x1F },
70 { 74000000, 0x20 },
71 { 75000000, 0x21 },
72 { 76000000, 0x24 },
73 { 77000000, 0x25 },
74 { 78000000, 0x27 },
75 { 80000000, 0x28 },
76 { 81000000, 0x29 },
77 { 82000000, 0x2D },
78 { 83000000, 0x2E },
79 { 84000000, 0x2F },
80 { 85000000, 0x31 },
81 { 86000000, 0x33 },
82 { 87000000, 0x34 },
83 { 88000000, 0x35 },
84 { 89000000, 0x37 },
85 { 90000000, 0x38 },
86 { 91000000, 0x39 },
87 { 93000000, 0x3C },
88 { 94000000, 0x3E },
89 { 95000000, 0x3F },
90 { 96000000, 0x40 },
91 { 97000000, 0x42 },
92 { 99000000, 0x45 },
93 { 100000000, 0x46 },
94 { 102000000, 0x48 },
95 { 103000000, 0x4A },
96 { 105000000, 0x4D },
97 { 106000000, 0x4E },
98 { 107000000, 0x50 },
99 { 108000000, 0x51 },
100 { 110000000, 0x54 },
101 { 111000000, 0x56 },
102 { 112000000, 0x57 },
103 { 113000000, 0x58 },
104 { 114000000, 0x59 },
105 { 115000000, 0x5C },
106 { 116000000, 0x5D },
107 { 117000000, 0x5F },
108 { 119000000, 0x60 },
109 { 120000000, 0x64 },
110 { 121000000, 0x65 },
111 { 122000000, 0x66 },
112 { 123000000, 0x68 },
113 { 124000000, 0x69 },
114 { 125000000, 0x6C },
115 { 126000000, 0x6D },
116 { 127000000, 0x6E },
117 { 128000000, 0x70 },
118 { 129000000, 0x71 },
119 { 130000000, 0x75 },
120 { 131000000, 0x77 },
121 { 132000000, 0x78 },
122 { 133000000, 0x7B },
123 { 134000000, 0x7E },
124 { 135000000, 0x81 },
125 { 136000000, 0x82 },
126 { 137000000, 0x87 },
127 { 138000000, 0x88 },
128 { 139000000, 0x8D },
129 { 140000000, 0x8E },
130 { 141000000, 0x91 },
131 { 142000000, 0x95 },
132 { 143000000, 0x9A },
133 { 144000000, 0x9D },
134 { 145000000, 0xA1 },
135 { 146000000, 0xA2 },
136 { 147000000, 0xA4 },
137 { 148000000, 0xA9 },
138 { 149000000, 0xAE },
139 { 150000000, 0xB0 },
140 { 151000000, 0xB1 },
141 { 152000000, 0xB7 },
142 { 152600000, 0xBD },
143 { 154000000, 0x20 },
144 { 155000000, 0x22 },
145 { 156000000, 0x24 },
146 { 157000000, 0x25 },
147 { 158000000, 0x27 },
148 { 159000000, 0x29 },
149 { 160000000, 0x2C },
150 { 161000000, 0x2D },
151 { 163000000, 0x2E },
152 { 164000000, 0x2F },
153 { 164700000, 0x30 },
154 { 166000000, 0x11 },
155 { 167000000, 0x12 },
156 { 168000000, 0x13 },
157 { 169000000, 0x14 },
158 { 170000000, 0x15 },
159 { 172000000, 0x16 },
160 { 173000000, 0x17 },
161 { 174000000, 0x18 },
162 { 175000000, 0x1A },
163 { 176000000, 0x1B },
164 { 178000000, 0x1D },
165 { 179000000, 0x1E },
166 { 180000000, 0x1F },
167 { 181000000, 0x20 },
168 { 182000000, 0x21 },
169 { 183000000, 0x22 },
170 { 184000000, 0x24 },
171 { 185000000, 0x25 },
172 { 186000000, 0x26 },
173 { 187000000, 0x27 },
174 { 188000000, 0x29 },
175 { 189000000, 0x2A },
176 { 190000000, 0x2C },
177 { 191000000, 0x2D },
178 { 192000000, 0x2E },
179 { 193000000, 0x2F },
180 { 194000000, 0x30 },
181 { 195000000, 0x33 },
182 { 196000000, 0x35 },
183 { 198000000, 0x36 },
184 { 200000000, 0x38 },
185 { 201000000, 0x3C },
186 { 202000000, 0x3D },
187 { 203500000, 0x3E },
188 { 206000000, 0x0E },
189 { 208000000, 0x0F },
190 { 212000000, 0x10 },
191 { 216000000, 0x11 },
192 { 217000000, 0x12 },
193 { 218000000, 0x13 },
194 { 220000000, 0x14 },
195 { 222000000, 0x15 },
196 { 225000000, 0x16 },
197 { 228000000, 0x17 },
198 { 231000000, 0x18 },
199 { 234000000, 0x19 },
200 { 235000000, 0x1A },
201 { 236000000, 0x1B },
202 { 237000000, 0x1C },
203 { 240000000, 0x1D },
204 { 242000000, 0x1E },
205 { 244000000, 0x1F },
206 { 247000000, 0x20 },
207 { 249000000, 0x21 },
208 { 252000000, 0x22 },
209 { 253000000, 0x23 },
210 { 254000000, 0x24 },
211 { 256000000, 0x25 },
212 { 259000000, 0x26 },
213 { 262000000, 0x27 },
214 { 264000000, 0x28 },
215 { 267000000, 0x29 },
216 { 269000000, 0x2A },
217 { 271000000, 0x2B },
218 { 273000000, 0x2C },
219 { 275000000, 0x2D },
220 { 277000000, 0x2E },
221 { 279000000, 0x2F },
222 { 282000000, 0x30 },
223 { 284000000, 0x31 },
224 { 286000000, 0x32 },
225 { 287000000, 0x33 },
226 { 290000000, 0x34 },
227 { 293000000, 0x35 },
228 { 295000000, 0x36 },
229 { 297000000, 0x37 },
230 { 300000000, 0x38 },
231 { 303000000, 0x39 },
232 { 305000000, 0x3A },
233 { 306000000, 0x3B },
234 { 307000000, 0x3C },
235 { 310000000, 0x3D },
236 { 312000000, 0x3E },
237 { 315000000, 0x3F },
238 { 318000000, 0x40 },
239 { 320000000, 0x41 },
240 { 323000000, 0x42 },
241 { 324000000, 0x43 },
242 { 325000000, 0x44 },
243 { 327000000, 0x45 },
244 { 331000000, 0x46 },
245 { 334000000, 0x47 },
246 { 337000000, 0x48 },
247 { 339000000, 0x49 },
248 { 340000000, 0x4A },
249 { 341000000, 0x4B },
250 { 343000000, 0x4C },
251 { 345000000, 0x4D },
252 { 349000000, 0x4E },
253 { 352000000, 0x4F },
254 { 353000000, 0x50 },
255 { 355000000, 0x51 },
256 { 357000000, 0x52 },
257 { 359000000, 0x53 },
258 { 361000000, 0x54 },
259 { 362000000, 0x55 },
260 { 364000000, 0x56 },
261 { 368000000, 0x57 },
262 { 370000000, 0x58 },
263 { 372000000, 0x59 },
264 { 375000000, 0x5A },
265 { 376000000, 0x5B },
266 { 377000000, 0x5C },
267 { 379000000, 0x5D },
268 { 382000000, 0x5E },
269 { 384000000, 0x5F },
270 { 385000000, 0x60 },
271 { 386000000, 0x61 },
272 { 388000000, 0x62 },
273 { 390000000, 0x63 },
274 { 393000000, 0x64 },
275 { 394000000, 0x65 },
276 { 396000000, 0x66 },
277 { 397000000, 0x67 },
278 { 398000000, 0x68 },
279 { 400000000, 0x69 },
280 { 402000000, 0x6A },
281 { 403000000, 0x6B },
282 { 407000000, 0x6C },
283 { 408000000, 0x6D },
284 { 409000000, 0x6E },
285 { 410000000, 0x6F },
286 { 411000000, 0x70 },
287 { 412000000, 0x71 },
288 { 413000000, 0x72 },
289 { 414000000, 0x73 },
290 { 417000000, 0x74 },
291 { 418000000, 0x75 },
292 { 420000000, 0x76 },
293 { 422000000, 0x77 },
294 { 423000000, 0x78 },
295 { 424000000, 0x79 },
296 { 427000000, 0x7A },
297 { 428000000, 0x7B },
298 { 429000000, 0x7D },
299 { 432000000, 0x7F },
300 { 434000000, 0x80 },
301 { 435000000, 0x81 },
302 { 436000000, 0x83 },
303 { 437000000, 0x84 },
304 { 438000000, 0x85 },
305 { 439000000, 0x86 },
306 { 440000000, 0x87 },
307 { 441000000, 0x88 },
308 { 442000000, 0x89 },
309 { 445000000, 0x8A },
310 { 446000000, 0x8B },
311 { 447000000, 0x8C },
312 { 448000000, 0x8E },
313 { 449000000, 0x8F },
314 { 450000000, 0x90 },
315 { 452000000, 0x91 },
316 { 453000000, 0x93 },
317 { 454000000, 0x94 },
318 { 456000000, 0x96 },
319 { 457800000, 0x98 },
320 { 461000000, 0x11 },
321 { 468000000, 0x12 },
322 { 472000000, 0x13 },
323 { 473000000, 0x14 },
324 { 474000000, 0x15 },
325 { 481000000, 0x16 },
326 { 486000000, 0x17 },
327 { 491000000, 0x18 },
328 { 498000000, 0x19 },
329 { 499000000, 0x1A },
330 { 501000000, 0x1B },
331 { 506000000, 0x1C },
332 { 511000000, 0x1D },
333 { 516000000, 0x1E },
334 { 520000000, 0x1F },
335 { 521000000, 0x20 },
336 { 525000000, 0x21 },
337 { 529000000, 0x22 },
338 { 533000000, 0x23 },
339 { 539000000, 0x24 },
340 { 541000000, 0x25 },
341 { 547000000, 0x26 },
342 { 549000000, 0x27 },
343 { 551000000, 0x28 },
344 { 556000000, 0x29 },
345 { 561000000, 0x2A },
346 { 563000000, 0x2B },
347 { 565000000, 0x2C },
348 { 569000000, 0x2D },
349 { 571000000, 0x2E },
350 { 577000000, 0x2F },
351 { 580000000, 0x30 },
352 { 582000000, 0x31 },
353 { 584000000, 0x32 },
354 { 588000000, 0x33 },
355 { 591000000, 0x34 },
356 { 596000000, 0x35 },
357 { 598000000, 0x36 },
358 { 603000000, 0x37 },
359 { 604000000, 0x38 },
360 { 606000000, 0x39 },
361 { 612000000, 0x3A },
362 { 615000000, 0x3B },
363 { 617000000, 0x3C },
364 { 621000000, 0x3D },
365 { 622000000, 0x3E },
366 { 625000000, 0x3F },
367 { 632000000, 0x40 },
368 { 633000000, 0x41 },
369 { 634000000, 0x42 },
370 { 642000000, 0x43 },
371 { 643000000, 0x44 },
372 { 647000000, 0x45 },
373 { 650000000, 0x46 },
374 { 652000000, 0x47 },
375 { 657000000, 0x48 },
376 { 661000000, 0x49 },
377 { 662000000, 0x4A },
378 { 665000000, 0x4B },
379 { 667000000, 0x4C },
380 { 670000000, 0x4D },
381 { 673000000, 0x4E },
382 { 676000000, 0x4F },
383 { 677000000, 0x50 },
384 { 681000000, 0x51 },
385 { 683000000, 0x52 },
386 { 686000000, 0x53 },
387 { 688000000, 0x54 },
388 { 689000000, 0x55 },
389 { 691000000, 0x56 },
390 { 695000000, 0x57 },
391 { 698000000, 0x58 },
392 { 703000000, 0x59 },
393 { 704000000, 0x5A },
394 { 705000000, 0x5B },
395 { 707000000, 0x5C },
396 { 710000000, 0x5D },
397 { 712000000, 0x5E },
398 { 717000000, 0x5F },
399 { 718000000, 0x60 },
400 { 721000000, 0x61 },
401 { 722000000, 0x62 },
402 { 723000000, 0x63 },
403 { 725000000, 0x64 },
404 { 727000000, 0x65 },
405 { 730000000, 0x66 },
406 { 732000000, 0x67 },
407 { 735000000, 0x68 },
408 { 740000000, 0x69 },
409 { 741000000, 0x6A },
410 { 742000000, 0x6B },
411 { 743000000, 0x6C },
412 { 745000000, 0x6D },
413 { 747000000, 0x6E },
414 { 748000000, 0x6F },
415 { 750000000, 0x70 },
416 { 752000000, 0x71 },
417 { 754000000, 0x72 },
418 { 757000000, 0x73 },
419 { 758000000, 0x74 },
420 { 760000000, 0x75 },
421 { 763000000, 0x76 },
422 { 764000000, 0x77 },
423 { 766000000, 0x78 },
424 { 767000000, 0x79 },
425 { 768000000, 0x7A },
426 { 773000000, 0x7B },
427 { 774000000, 0x7C },
428 { 776000000, 0x7D },
429 { 777000000, 0x7E },
430 { 778000000, 0x7F },
431 { 779000000, 0x80 },
432 { 781000000, 0x81 },
433 { 783000000, 0x82 },
434 { 784000000, 0x83 },
435 { 785000000, 0x84 },
436 { 786000000, 0x85 },
437 { 793000000, 0x86 },
438 { 794000000, 0x87 },
439 { 795000000, 0x88 },
440 { 797000000, 0x89 },
441 { 799000000, 0x8A },
442 { 801000000, 0x8B },
443 { 802000000, 0x8C },
444 { 803000000, 0x8D },
445 { 804000000, 0x8E },
446 { 810000000, 0x90 },
447 { 811000000, 0x91 },
448 { 812000000, 0x92 },
449 { 814000000, 0x93 },
450 { 816000000, 0x94 },
451 { 817000000, 0x96 },
452 { 818000000, 0x97 },
453 { 820000000, 0x98 },
454 { 821000000, 0x99 },
455 { 822000000, 0x9A },
456 { 828000000, 0x9B },
457 { 829000000, 0x9D },
458 { 830000000, 0x9F },
459 { 831000000, 0xA0 },
460 { 833000000, 0xA1 },
461 { 835000000, 0xA2 },
462 { 836000000, 0xA3 },
463 { 837000000, 0xA4 },
464 { 838000000, 0xA6 },
465 { 840000000, 0xA8 },
466 { 842000000, 0xA9 },
467 { 845000000, 0xAA },
468 { 846000000, 0xAB },
469 { 847000000, 0xAD },
470 { 848000000, 0xAE },
471 { 852000000, 0xAF },
472 { 853000000, 0xB0 },
473 { 858000000, 0xB1 },
474 { 860000000, 0xB2 },
475 { 861000000, 0xB3 },
476 { 862000000, 0xB4 },
477 { 863000000, 0xB6 },
478 { 864000000, 0xB8 },
479 { 865000000, 0xB9 },
480 { 0, 0x00 }, // Table End
481};
482
483
484static struct SMap2 m_KM_Map[] = {
485 { 47900000, 3, 2 },
486 { 61100000, 3, 1 },
487 { 350000000, 3, 0 },
488 { 720000000, 2, 1 },
489 { 865000000, 3, 3 },
490 { 0, 0x00 }, // Table End
491};
492
493static struct SMap2 m_Main_PLL_Map[] = {
494 { 33125000, 0x57, 0xF0 },
495 { 35500000, 0x56, 0xE0 },
496 { 38188000, 0x55, 0xD0 },
497 { 41375000, 0x54, 0xC0 },
498 { 45125000, 0x53, 0xB0 },
499 { 49688000, 0x52, 0xA0 },
500 { 55188000, 0x51, 0x90 },
501 { 62125000, 0x50, 0x80 },
502 { 66250000, 0x47, 0x78 },
503 { 71000000, 0x46, 0x70 },
504 { 76375000, 0x45, 0x68 },
505 { 82750000, 0x44, 0x60 },
506 { 90250000, 0x43, 0x58 },
507 { 99375000, 0x42, 0x50 },
508 { 110375000, 0x41, 0x48 },
509 { 124250000, 0x40, 0x40 },
510 { 132500000, 0x37, 0x3C },
511 { 142000000, 0x36, 0x38 },
512 { 152750000, 0x35, 0x34 },
513 { 165500000, 0x34, 0x30 },
514 { 180500000, 0x33, 0x2C },
515 { 198750000, 0x32, 0x28 },
516 { 220750000, 0x31, 0x24 },
517 { 248500000, 0x30, 0x20 },
518 { 265000000, 0x27, 0x1E },
519 { 284000000, 0x26, 0x1C },
520 { 305500000, 0x25, 0x1A },
521 { 331000000, 0x24, 0x18 },
522 { 361000000, 0x23, 0x16 },
523 { 397500000, 0x22, 0x14 },
524 { 441500000, 0x21, 0x12 },
525 { 497000000, 0x20, 0x10 },
526 { 530000000, 0x17, 0x0F },
527 { 568000000, 0x16, 0x0E },
528 { 611000000, 0x15, 0x0D },
529 { 662000000, 0x14, 0x0C },
530 { 722000000, 0x13, 0x0B },
531 { 795000000, 0x12, 0x0A },
532 { 883000000, 0x11, 0x09 },
533 { 994000000, 0x10, 0x08 },
534 { 0, 0x00, 0x00 }, // Table End
535};
536
537static struct SMap2 m_Cal_PLL_Map[] = {
538 { 33813000, 0xDD, 0xD0 },
539 { 36625000, 0xDC, 0xC0 },
540 { 39938000, 0xDB, 0xB0 },
541 { 43938000, 0xDA, 0xA0 },
542 { 48813000, 0xD9, 0x90 },
543 { 54938000, 0xD8, 0x80 },
544 { 62813000, 0xD3, 0x70 },
545 { 67625000, 0xCD, 0x68 },
546 { 73250000, 0xCC, 0x60 },
547 { 79875000, 0xCB, 0x58 },
548 { 87875000, 0xCA, 0x50 },
549 { 97625000, 0xC9, 0x48 },
550 { 109875000, 0xC8, 0x40 },
551 { 125625000, 0xC3, 0x38 },
552 { 135250000, 0xBD, 0x34 },
553 { 146500000, 0xBC, 0x30 },
554 { 159750000, 0xBB, 0x2C },
555 { 175750000, 0xBA, 0x28 },
556 { 195250000, 0xB9, 0x24 },
557 { 219750000, 0xB8, 0x20 },
558 { 251250000, 0xB3, 0x1C },
559 { 270500000, 0xAD, 0x1A },
560 { 293000000, 0xAC, 0x18 },
561 { 319500000, 0xAB, 0x16 },
562 { 351500000, 0xAA, 0x14 },
563 { 390500000, 0xA9, 0x12 },
564 { 439500000, 0xA8, 0x10 },
565 { 502500000, 0xA3, 0x0E },
566 { 541000000, 0x9D, 0x0D },
567 { 586000000, 0x9C, 0x0C },
568 { 639000000, 0x9B, 0x0B },
569 { 703000000, 0x9A, 0x0A },
570 { 781000000, 0x99, 0x09 },
571 { 879000000, 0x98, 0x08 },
572 { 0, 0x00, 0x00 }, // Table End
573};
574
575static struct SMap m_GainTaper_Map[] = {
576 { 45400000, 0x1F },
577 { 45800000, 0x1E },
578 { 46200000, 0x1D },
579 { 46700000, 0x1C },
580 { 47100000, 0x1B },
581 { 47500000, 0x1A },
582 { 47900000, 0x19 },
583 { 49600000, 0x17 },
584 { 51200000, 0x16 },
585 { 52900000, 0x15 },
586 { 54500000, 0x14 },
587 { 56200000, 0x13 },
588 { 57800000, 0x12 },
589 { 59500000, 0x11 },
590 { 61100000, 0x10 },
591 { 67600000, 0x0D },
592 { 74200000, 0x0C },
593 { 80700000, 0x0B },
594 { 87200000, 0x0A },
595 { 93800000, 0x09 },
596 { 100300000, 0x08 },
597 { 106900000, 0x07 },
598 { 113400000, 0x06 },
599 { 119900000, 0x05 },
600 { 126500000, 0x04 },
601 { 133000000, 0x03 },
602 { 139500000, 0x02 },
603 { 146100000, 0x01 },
604 { 152600000, 0x00 },
605 { 154300000, 0x1F },
606 { 156100000, 0x1E },
607 { 157800000, 0x1D },
608 { 159500000, 0x1C },
609 { 161200000, 0x1B },
610 { 163000000, 0x1A },
611 { 164700000, 0x19 },
612 { 170200000, 0x17 },
613 { 175800000, 0x16 },
614 { 181300000, 0x15 },
615 { 186900000, 0x14 },
616 { 192400000, 0x13 },
617 { 198000000, 0x12 },
618 { 203500000, 0x11 },
619 { 216200000, 0x14 },
620 { 228900000, 0x13 },
621 { 241600000, 0x12 },
622 { 254400000, 0x11 },
623 { 267100000, 0x10 },
624 { 279800000, 0x0F },
625 { 292500000, 0x0E },
626 { 305200000, 0x0D },
627 { 317900000, 0x0C },
628 { 330700000, 0x0B },
629 { 343400000, 0x0A },
630 { 356100000, 0x09 },
631 { 368800000, 0x08 },
632 { 381500000, 0x07 },
633 { 394200000, 0x06 },
634 { 406900000, 0x05 },
635 { 419700000, 0x04 },
636 { 432400000, 0x03 },
637 { 445100000, 0x02 },
638 { 457800000, 0x01 },
639 { 476300000, 0x19 },
640 { 494800000, 0x18 },
641 { 513300000, 0x17 },
642 { 531800000, 0x16 },
643 { 550300000, 0x15 },
644 { 568900000, 0x14 },
645 { 587400000, 0x13 },
646 { 605900000, 0x12 },
647 { 624400000, 0x11 },
648 { 642900000, 0x10 },
649 { 661400000, 0x0F },
650 { 679900000, 0x0E },
651 { 698400000, 0x0D },
652 { 716900000, 0x0C },
653 { 735400000, 0x0B },
654 { 753900000, 0x0A },
655 { 772500000, 0x09 },
656 { 791000000, 0x08 },
657 { 809500000, 0x07 },
658 { 828000000, 0x06 },
659 { 846500000, 0x05 },
660 { 865000000, 0x04 },
661 { 0, 0x00 }, // Table End
662};
663
664static struct SMap m_RF_Cal_DC_Over_DT_Map[] = {
665 { 47900000, 0x00 },
666 { 55000000, 0x00 },
667 { 61100000, 0x0A },
668 { 64000000, 0x0A },
669 { 82000000, 0x14 },
670 { 84000000, 0x19 },
671 { 119000000, 0x1C },
672 { 124000000, 0x20 },
673 { 129000000, 0x2A },
674 { 134000000, 0x32 },
675 { 139000000, 0x39 },
676 { 144000000, 0x3E },
677 { 149000000, 0x3F },
678 { 152600000, 0x40 },
679 { 154000000, 0x40 },
680 { 164700000, 0x41 },
681 { 203500000, 0x32 },
682 { 353000000, 0x19 },
683 { 356000000, 0x1A },
684 { 359000000, 0x1B },
685 { 363000000, 0x1C },
686 { 366000000, 0x1D },
687 { 369000000, 0x1E },
688 { 373000000, 0x1F },
689 { 376000000, 0x20 },
690 { 379000000, 0x21 },
691 { 383000000, 0x22 },
692 { 386000000, 0x23 },
693 { 389000000, 0x24 },
694 { 393000000, 0x25 },
695 { 396000000, 0x26 },
696 { 399000000, 0x27 },
697 { 402000000, 0x28 },
698 { 404000000, 0x29 },
699 { 407000000, 0x2A },
700 { 409000000, 0x2B },
701 { 412000000, 0x2C },
702 { 414000000, 0x2D },
703 { 417000000, 0x2E },
704 { 419000000, 0x2F },
705 { 422000000, 0x30 },
706 { 424000000, 0x31 },
707 { 427000000, 0x32 },
708 { 429000000, 0x33 },
709 { 432000000, 0x34 },
710 { 434000000, 0x35 },
711 { 437000000, 0x36 },
712 { 439000000, 0x37 },
713 { 442000000, 0x38 },
714 { 444000000, 0x39 },
715 { 447000000, 0x3A },
716 { 449000000, 0x3B },
717 { 457800000, 0x3C },
718 { 465000000, 0x0F },
719 { 477000000, 0x12 },
720 { 483000000, 0x14 },
721 { 502000000, 0x19 },
722 { 508000000, 0x1B },
723 { 519000000, 0x1C },
724 { 522000000, 0x1D },
725 { 524000000, 0x1E },
726 { 534000000, 0x1F },
727 { 549000000, 0x20 },
728 { 554000000, 0x22 },
729 { 584000000, 0x24 },
730 { 589000000, 0x26 },
731 { 658000000, 0x27 },
732 { 664000000, 0x2C },
733 { 669000000, 0x2D },
734 { 699000000, 0x2E },
735 { 704000000, 0x30 },
736 { 709000000, 0x31 },
737 { 714000000, 0x32 },
738 { 724000000, 0x33 },
739 { 729000000, 0x36 },
740 { 739000000, 0x38 },
741 { 744000000, 0x39 },
742 { 749000000, 0x3B },
743 { 754000000, 0x3C },
744 { 759000000, 0x3D },
745 { 764000000, 0x3E },
746 { 769000000, 0x3F },
747 { 774000000, 0x40 },
748 { 779000000, 0x41 },
749 { 784000000, 0x43 },
750 { 789000000, 0x46 },
751 { 794000000, 0x48 },
752 { 799000000, 0x4B },
753 { 804000000, 0x4F },
754 { 809000000, 0x54 },
755 { 814000000, 0x59 },
756 { 819000000, 0x5D },
757 { 824000000, 0x61 },
758 { 829000000, 0x68 },
759 { 834000000, 0x6E },
760 { 839000000, 0x75 },
761 { 844000000, 0x7E },
762 { 849000000, 0x82 },
763 { 854000000, 0x84 },
764 { 859000000, 0x8F },
765 { 865000000, 0x9A },
766 { 0, 0x00 }, // Table End
767};
768
769
770static struct SMap m_IR_Meas_Map[] = {
771 { 200000000, 0x05 },
772 { 400000000, 0x06 },
773 { 865000000, 0x07 },
774 { 0, 0x00 }, // Table End
775};
776
777static struct SMap2 m_CID_Target_Map[] = {
778 { 46000000, 0x04, 18 },
779 { 52200000, 0x0A, 15 },
780 { 70100000, 0x01, 40 },
781 { 136800000, 0x18, 40 },
782 { 156700000, 0x18, 40 },
783 { 186250000, 0x0A, 40 },
784 { 230000000, 0x0A, 40 },
785 { 345000000, 0x18, 40 },
786 { 426000000, 0x0E, 40 },
787 { 489500000, 0x1E, 40 },
788 { 697500000, 0x32, 40 },
789 { 842000000, 0x3A, 40 },
790 { 0, 0x00, 0 }, // Table End
791};
792
793static struct SRFBandMap m_RF_Band_Map[7] = {
794 { 47900000, 46000000, 0, 0},
795 { 61100000, 52200000, 0, 0},
796 { 152600000, 70100000, 136800000, 0},
797 { 164700000, 156700000, 0, 0},
798 { 203500000, 186250000, 0, 0},
799 { 457800000, 230000000, 345000000, 426000000},
800 { 865000000, 489500000, 697500000, 842000000},
801};
802
803u8 m_Thermometer_Map_1[16] = {
804 60,62,66,64, 74,72,68,70, 90,88,84,86, 76,78,82,80,
805};
806
807u8 m_Thermometer_Map_2[16] = {
808 92,94,98,96, 106,104,100,102, 122,120,116,118, 108,110,114,112,
809};
810
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 17:51:44 -0500