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authorStephen Warren <swarren@nvidia.com>2014-04-15 13:00:50 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-04-22 10:48:39 -0400
commite53b797474ac61debd6e7c186285c8cc24a3a166 (patch)
treeeda64dc694dc9c840b555b7a5b20b19f144f6e0b /drivers
parenta16b81dcbfc5889c37dac5f8e836136e4740fc18 (diff)
pinctrl: tegra: remove redundant data table fields
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel options has the relevant HW register fields in the same register as the mux function selection. Similarly, the drvtype option is always in the drive register, if it is supported at all. Hence, we don't need to have struct *_reg fields in the pin group table to define which register and bank to use for those options. Delete this to save space in the driver's data tables. However, many of those options are not supported on all SoCs, or not supported on some pingroups. We need a way to detect when they are supported. Previously, this was indicated by setting the struct *_reg field to -1. With the struct *_reg fields removed, we use the struct *_bit fields for this purpose instead. The struct *_bit fields need to be expanded from 5 to 6 bits in order to store a value outside the valid HW bit range of 0..31. Even without removing the struct *_reg fields, we still need to add code to validate the struct *_bit fields, since some struct *_bit fields were already being set to -1, without an option-specific struct *_reg field to "guard" them. In other words, before this change, the pinmux driver might allow some unsupported options to be written to HW. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c26
-rw-r--r--drivers/pinctrl/pinctrl-tegra.h124
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c53
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c53
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c25
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c48
6 files changed, 132 insertions, 197 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 65458096f41e..22faf5b10bda 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -336,32 +336,32 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
336 *width = 1; 336 *width = 1;
337 break; 337 break;
338 case TEGRA_PINCONF_PARAM_ENABLE_INPUT: 338 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
339 *bank = g->einput_bank; 339 *bank = g->mux_bank;
340 *reg = g->einput_reg; 340 *reg = g->mux_reg;
341 *bit = g->einput_bit; 341 *bit = g->einput_bit;
342 *width = 1; 342 *width = 1;
343 break; 343 break;
344 case TEGRA_PINCONF_PARAM_OPEN_DRAIN: 344 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
345 *bank = g->odrain_bank; 345 *bank = g->mux_bank;
346 *reg = g->odrain_reg; 346 *reg = g->mux_reg;
347 *bit = g->odrain_bit; 347 *bit = g->odrain_bit;
348 *width = 1; 348 *width = 1;
349 break; 349 break;
350 case TEGRA_PINCONF_PARAM_LOCK: 350 case TEGRA_PINCONF_PARAM_LOCK:
351 *bank = g->lock_bank; 351 *bank = g->mux_bank;
352 *reg = g->lock_reg; 352 *reg = g->mux_reg;
353 *bit = g->lock_bit; 353 *bit = g->lock_bit;
354 *width = 1; 354 *width = 1;
355 break; 355 break;
356 case TEGRA_PINCONF_PARAM_IORESET: 356 case TEGRA_PINCONF_PARAM_IORESET:
357 *bank = g->ioreset_bank; 357 *bank = g->mux_bank;
358 *reg = g->ioreset_reg; 358 *reg = g->mux_reg;
359 *bit = g->ioreset_bit; 359 *bit = g->ioreset_bit;
360 *width = 1; 360 *width = 1;
361 break; 361 break;
362 case TEGRA_PINCONF_PARAM_RCV_SEL: 362 case TEGRA_PINCONF_PARAM_RCV_SEL:
363 *bank = g->rcv_sel_bank; 363 *bank = g->mux_bank;
364 *reg = g->rcv_sel_reg; 364 *reg = g->mux_reg;
365 *bit = g->rcv_sel_bit; 365 *bit = g->rcv_sel_bit;
366 *width = 1; 366 *width = 1;
367 break; 367 break;
@@ -408,8 +408,8 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
408 *width = g->slwr_width; 408 *width = g->slwr_width;
409 break; 409 break;
410 case TEGRA_PINCONF_PARAM_DRIVE_TYPE: 410 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
411 *bank = g->drvtype_bank; 411 *bank = g->drv_bank;
412 *reg = g->drvtype_reg; 412 *reg = g->drv_reg;
413 *bit = g->drvtype_bit; 413 *bit = g->drvtype_bit;
414 *width = 2; 414 *width = 2;
415 break; 415 break;
@@ -418,7 +418,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
418 return -ENOTSUPP; 418 return -ENOTSUPP;
419 } 419 }
420 420
421 if (*reg < 0) { 421 if (*reg < 0 || *bit > 31) {
422 if (report_err) 422 if (report_err)
423 dev_err(pmx->dev, 423 dev_err(pmx->dev,
424 "Config param %04x not supported on group %s\n", 424 "Config param %04x not supported on group %s\n",
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 6053832d433e..7262ba8ebade 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -78,55 +78,49 @@ struct tegra_function {
78 78
79/** 79/**
80 * struct tegra_pingroup - Tegra pin group 80 * struct tegra_pingroup - Tegra pin group
81 * @mux_reg: Mux register offset. -1 if unsupported. 81 * @mux_reg: Mux register offset.
82 * @mux_bank: Mux register bank. 0 if unsupported. 82 * This register contains the mux, einput, odrain, lock,
83 * @mux_bit: Mux register bit. 0 if unsupported. 83 * ioreset, rcv_sel parameters.
84 * @pupd_reg: Pull-up/down register offset. -1 if unsupported. 84 * @mux_bank: Mux register bank.
85 * @pupd_bank: Pull-up/down register bank. 0 if unsupported. 85 * @mux_bit: Mux register bit.
86 * @pupd_bit: Pull-up/down register bit. 0 if unsupported. 86 * @pupd_reg: Pull-up/down register offset.
87 * @tri_reg: Tri-state register offset. -1 if unsupported. 87 * @pupd_bank: Pull-up/down register bank.
88 * @tri_bank: Tri-state register bank. 0 if unsupported. 88 * @pupd_bit: Pull-up/down register bit.
89 * @tri_bit: Tri-state register bit. 0 if unsupported. 89 * @tri_reg: Tri-state register offset.
90 * @einput_reg: Enable-input register offset. -1 if unsupported. 90 * @tri_bank: Tri-state register bank.
91 * @einput_bank: Enable-input register bank. 0 if unsupported. 91 * @tri_bit: Tri-state register bit.
92 * @einput_bit: Enable-input register bit. 0 if unsupported. 92 * @einput_bit: Enable-input register bit.
93 * @odrain_reg: Open-drain register offset. -1 if unsupported. 93 * @odrain_bit: Open-drain register bit.
94 * @odrain_bank: Open-drain register bank. 0 if unsupported. 94 * @lock_bit: Lock register bit.
95 * @odrain_bit: Open-drain register bit. 0 if unsupported. 95 * @ioreset_bit: IO reset register bit.
96 * @lock_reg: Lock register offset. -1 if unsupported. 96 * @rcv_sel_bit: Receiver select bit.
97 * @lock_bank: Lock register bank. 0 if unsupported. 97 * @drv_reg: Drive fields register offset.
98 * @lock_bit: Lock register bit. 0 if unsupported. 98 * This register contains hsm, schmitt, lpmd, drvdn,
99 * @ioreset_reg: IO reset register offset. -1 if unsupported. 99 * drvup, slwr, slwf, and drvtype parameters.
100 * @ioreset_bank: IO reset register bank. 0 if unsupported. 100 * @drv_bank: Drive fields register bank.
101 * @ioreset_bit: IO reset register bit. 0 if unsupported. 101 * @hsm_bit: High Speed Mode register bit.
102 * @rcv_sel_reg: Receiver select offset. -1 if unsupported. 102 * @schmitt_bit: Scmitt register bit.
103 * @rcv_sel_bank: Receiver select bank. 0 if unsupported. 103 * @lpmd_bit: Low Power Mode register bit.
104 * @rcv_sel_bit: Receiver select bit. 0 if unsupported. 104 * @drvdn_bit: Drive Down register bit.
105 * @drv_reg: Drive fields register offset. -1 if unsupported. 105 * @drvdn_width: Drive Down field width.
106 * This register contains the hsm, schmitt, lpmd, drvdn, 106 * @drvup_bit: Drive Up register bit.
107 * drvup, slwr, and slwf parameters. 107 * @drvup_width: Drive Up field width.
108 * @drv_bank: Drive fields register bank. 0 if unsupported. 108 * @slwr_bit: Slew Rising register bit.
109 * @hsm_bit: High Speed Mode register bit. 0 if unsupported. 109 * @slwr_width: Slew Rising field width.
110 * @schmitt_bit: Scmitt register bit. 0 if unsupported. 110 * @slwf_bit: Slew Falling register bit.
111 * @lpmd_bit: Low Power Mode register bit. 0 if unsupported. 111 * @slwf_width: Slew Falling field width.
112 * @drvdn_bit: Drive Down register bit. 0 if unsupported. 112 * @drvtype_bit: Drive type register bit.
113 * @drvdn_width: Drive Down field width. 0 if unsupported. 113 *
114 * @drvup_bit: Drive Up register bit. 0 if unsupported. 114 * -1 in a *_reg field means that feature is unsupported for this group.
115 * @drvup_width: Drive Up field width. 0 if unsupported. 115 * *_bank and *_reg values are irrelevant when *_reg is -1.
116 * @slwr_bit: Slew Rising register bit. 0 if unsupported. 116 * When *_reg is valid, *_bit may be -1 to indicate an unsupported feature.
117 * @slwr_width: Slew Rising field width. 0 if unsupported.
118 * @slwf_bit: Slew Falling register bit. 0 if unsupported.
119 * @slwf_width: Slew Falling field width. 0 if unsupported.
120 * @drvtype_reg: Drive type fields register offset. -1 if unsupported.
121 * @drvtype_bank: Drive type fields register bank. 0 if unsupported.
122 * @drvtype_bit: Drive type register bit. 0 if unsupported.
123 * 117 *
124 * A representation of a group of pins (possibly just one pin) in the Tegra 118 * A representation of a group of pins (possibly just one pin) in the Tegra
125 * pin controller. Each group allows some parameter or parameters to be 119 * pin controller. Each group allows some parameter or parameters to be
126 * configured. The most common is mux function selection. Many others exist 120 * configured. The most common is mux function selection. Many others exist
127 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex; 121 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
128 * certain groups may only support configuring certain parameters, hence 122 * certain groups may only support configuring certain parameters, hence
129 * each parameter is optional, represented by a -1 "reg" value. 123 * each parameter is optional.
130 */ 124 */
131struct tegra_pingroup { 125struct tegra_pingroup {
132 const char *name; 126 const char *name;
@@ -137,39 +131,27 @@ struct tegra_pingroup {
137 s16 mux_reg; 131 s16 mux_reg;
138 s16 pupd_reg; 132 s16 pupd_reg;
139 s16 tri_reg; 133 s16 tri_reg;
140 s16 einput_reg;
141 s16 odrain_reg;
142 s16 lock_reg;
143 s16 ioreset_reg;
144 s16 rcv_sel_reg;
145 s16 drv_reg; 134 s16 drv_reg;
146 s16 drvtype_reg;
147 u32 mux_bank:2; 135 u32 mux_bank:2;
148 u32 pupd_bank:2; 136 u32 pupd_bank:2;
149 u32 tri_bank:2; 137 u32 tri_bank:2;
150 u32 einput_bank:2;
151 u32 odrain_bank:2;
152 u32 ioreset_bank:2;
153 u32 rcv_sel_bank:2;
154 u32 lock_bank:2;
155 u32 drv_bank:2; 138 u32 drv_bank:2;
156 u32 drvtype_bank:2; 139 u32 mux_bit:6;
157 u32 mux_bit:5; 140 u32 pupd_bit:6;
158 u32 pupd_bit:5; 141 u32 tri_bit:6;
159 u32 tri_bit:5; 142 u32 einput_bit:6;
160 u32 einput_bit:5; 143 u32 odrain_bit:6;
161 u32 odrain_bit:5; 144 u32 lock_bit:6;
162 u32 lock_bit:5; 145 u32 ioreset_bit:6;
163 u32 ioreset_bit:5; 146 u32 rcv_sel_bit:6;
164 u32 rcv_sel_bit:5; 147 u32 hsm_bit:6;
165 u32 hsm_bit:5; 148 u32 schmitt_bit:6;
166 u32 schmitt_bit:5; 149 u32 lpmd_bit:6;
167 u32 lpmd_bit:5; 150 u32 drvdn_bit:6;
168 u32 drvdn_bit:5; 151 u32 drvup_bit:6;
169 u32 drvup_bit:5; 152 u32 slwr_bit:6;
170 u32 slwr_bit:5; 153 u32 slwf_bit:6;
171 u32 slwf_bit:5; 154 u32 drvtype_bit:6;
172 u32 drvtype_bit:5;
173 u32 drvdn_width:6; 155 u32 drvdn_width:6;
174 u32 drvup_width:6; 156 u32 drvup_width:6;
175 u32 slwr_width:6; 157 u32 slwr_width:6;
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 63fe7619d3ff..6766873669e8 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1547,8 +1547,10 @@ static struct tegra_function tegra114_functions[] = {
1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1548#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1548#define PINGROUP_REG_A 0x3000 /* bank 1 */
1549 1549
1550#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 1550#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1551#define PINGROUP_REG_N(r) -1 1551
1552#define PINGROUP_BIT_Y(b) (b)
1553#define PINGROUP_BIT_N(b) (-1)
1552 1554
1553#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ 1555#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
1554 { \ 1556 { \
@@ -1562,37 +1564,24 @@ static struct tegra_function tegra114_functions[] = {
1562 TEGRA_MUX_##f3, \ 1564 TEGRA_MUX_##f3, \
1563 }, \ 1565 }, \
1564 .func_safe = TEGRA_MUX_##f_safe, \ 1566 .func_safe = TEGRA_MUX_##f_safe, \
1565 .mux_reg = PINGROUP_REG_Y(r), \ 1567 .mux_reg = PINGROUP_REG(r), \
1566 .mux_bank = 1, \ 1568 .mux_bank = 1, \
1567 .mux_bit = 0, \ 1569 .mux_bit = 0, \
1568 .pupd_reg = PINGROUP_REG_Y(r), \ 1570 .pupd_reg = PINGROUP_REG(r), \
1569 .pupd_bank = 1, \ 1571 .pupd_bank = 1, \
1570 .pupd_bit = 2, \ 1572 .pupd_bit = 2, \
1571 .tri_reg = PINGROUP_REG_Y(r), \ 1573 .tri_reg = PINGROUP_REG(r), \
1572 .tri_bank = 1, \ 1574 .tri_bank = 1, \
1573 .tri_bit = 4, \ 1575 .tri_bit = 4, \
1574 .einput_reg = PINGROUP_REG_Y(r), \ 1576 .einput_bit = PINGROUP_BIT_Y(5), \
1575 .einput_bank = 1, \ 1577 .odrain_bit = PINGROUP_BIT_##od(6), \
1576 .einput_bit = 5, \ 1578 .lock_bit = PINGROUP_BIT_Y(7), \
1577 .odrain_reg = PINGROUP_REG_##od(r), \ 1579 .ioreset_bit = PINGROUP_BIT_##ior(8), \
1578 .odrain_bank = 1, \ 1580 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1579 .odrain_bit = 6, \
1580 .lock_reg = PINGROUP_REG_Y(r), \
1581 .lock_bank = 1, \
1582 .lock_bit = 7, \
1583 .ioreset_reg = PINGROUP_REG_##ior(r), \
1584 .ioreset_bank = 1, \
1585 .ioreset_bit = 8, \
1586 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \
1587 .rcv_sel_bank = 1, \
1588 .rcv_sel_bit = 9, \
1589 .drv_reg = -1, \ 1581 .drv_reg = -1, \
1590 .drvtype_reg = -1, \
1591 } 1582 }
1592 1583
1593#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A) 1584#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1594#define DRV_PINGROUP_REG_N(r) -1
1595
1596 1585
1597#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1586#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
1598 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 1587 drvdn_b, drvdn_w, drvup_b, drvup_w, \
@@ -1605,12 +1594,12 @@ static struct tegra_function tegra114_functions[] = {
1605 .mux_reg = -1, \ 1594 .mux_reg = -1, \
1606 .pupd_reg = -1, \ 1595 .pupd_reg = -1, \
1607 .tri_reg = -1, \ 1596 .tri_reg = -1, \
1608 .einput_reg = -1, \ 1597 .einput_bit = -1, \
1609 .odrain_reg = -1, \ 1598 .odrain_bit = -1, \
1610 .lock_reg = -1, \ 1599 .lock_bit = -1, \
1611 .ioreset_reg = -1, \ 1600 .ioreset_bit = -1, \
1612 .rcv_sel_reg = -1, \ 1601 .rcv_sel_bit = -1, \
1613 .drv_reg = DRV_PINGROUP_REG_Y(r), \ 1602 .drv_reg = DRV_PINGROUP_REG(r), \
1614 .drv_bank = 0, \ 1603 .drv_bank = 0, \
1615 .hsm_bit = hsm_b, \ 1604 .hsm_bit = hsm_b, \
1616 .schmitt_bit = schmitt_b, \ 1605 .schmitt_bit = schmitt_b, \
@@ -1623,9 +1612,7 @@ static struct tegra_function tegra114_functions[] = {
1623 .slwr_width = slwr_w, \ 1612 .slwr_width = slwr_w, \
1624 .slwf_bit = slwf_b, \ 1613 .slwf_bit = slwf_b, \
1625 .slwf_width = slwf_w, \ 1614 .slwf_width = slwf_w, \
1626 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \ 1615 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1627 .drvtype_bank = 0, \
1628 .drvtype_bit = 6, \
1629 } 1616 }
1630 1617
1631static const struct tegra_pingroup tegra114_groups[] = { 1618static const struct tegra_pingroup tegra114_groups[] = {
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index 73773706755b..03e4918b5ade 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -1677,8 +1677,10 @@ static struct tegra_function tegra124_functions[] = {
1677#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1677#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1678#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1678#define PINGROUP_REG_A 0x3000 /* bank 1 */
1679 1679
1680#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 1680#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1681#define PINGROUP_REG_N(r) -1 1681
1682#define PINGROUP_BIT_Y(b) (b)
1683#define PINGROUP_BIT_N(b) (-1)
1682 1684
1683#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \ 1685#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
1684 { \ 1686 { \
@@ -1692,37 +1694,24 @@ static struct tegra_function tegra124_functions[] = {
1692 TEGRA_MUX_##f3, \ 1694 TEGRA_MUX_##f3, \
1693 }, \ 1695 }, \
1694 .func_safe = TEGRA_MUX_##f_safe, \ 1696 .func_safe = TEGRA_MUX_##f_safe, \
1695 .mux_reg = PINGROUP_REG_Y(r), \ 1697 .mux_reg = PINGROUP_REG(r), \
1696 .mux_bank = 1, \ 1698 .mux_bank = 1, \
1697 .mux_bit = 0, \ 1699 .mux_bit = 0, \
1698 .pupd_reg = PINGROUP_REG_Y(r), \ 1700 .pupd_reg = PINGROUP_REG(r), \
1699 .pupd_bank = 1, \ 1701 .pupd_bank = 1, \
1700 .pupd_bit = 2, \ 1702 .pupd_bit = 2, \
1701 .tri_reg = PINGROUP_REG_Y(r), \ 1703 .tri_reg = PINGROUP_REG(r), \
1702 .tri_bank = 1, \ 1704 .tri_bank = 1, \
1703 .tri_bit = 4, \ 1705 .tri_bit = 4, \
1704 .einput_reg = PINGROUP_REG_Y(r), \ 1706 .einput_bit = PINGROUP_BIT_Y(5), \
1705 .einput_bank = 1, \ 1707 .odrain_bit = PINGROUP_BIT_##od(6), \
1706 .einput_bit = 5, \ 1708 .lock_bit = PINGROUP_BIT_Y(7), \
1707 .odrain_reg = PINGROUP_REG_##od(r), \ 1709 .ioreset_bit = PINGROUP_BIT_##ior(8), \
1708 .odrain_bank = 1, \ 1710 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1709 .odrain_bit = 6, \
1710 .lock_reg = PINGROUP_REG_Y(r), \
1711 .lock_bank = 1, \
1712 .lock_bit = 7, \
1713 .ioreset_reg = PINGROUP_REG_##ior(r), \
1714 .ioreset_bank = 1, \
1715 .ioreset_bit = 8, \
1716 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \
1717 .rcv_sel_bank = 1, \
1718 .rcv_sel_bit = 9, \
1719 .drv_reg = -1, \ 1711 .drv_reg = -1, \
1720 .drvtype_reg = -1, \
1721 } 1712 }
1722 1713
1723#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A) 1714#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1724#define DRV_PINGROUP_REG_N(r) -1
1725
1726 1715
1727#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1716#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
1728 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 1717 drvdn_b, drvdn_w, drvup_b, drvup_w, \
@@ -1735,12 +1724,12 @@ static struct tegra_function tegra124_functions[] = {
1735 .mux_reg = -1, \ 1724 .mux_reg = -1, \
1736 .pupd_reg = -1, \ 1725 .pupd_reg = -1, \
1737 .tri_reg = -1, \ 1726 .tri_reg = -1, \
1738 .einput_reg = -1, \ 1727 .einput_bit = -1, \
1739 .odrain_reg = -1, \ 1728 .odrain_bit = -1, \
1740 .lock_reg = -1, \ 1729 .lock_bit = -1, \
1741 .ioreset_reg = -1, \ 1730 .ioreset_bit = -1, \
1742 .rcv_sel_reg = -1, \ 1731 .rcv_sel_bit = -1, \
1743 .drv_reg = DRV_PINGROUP_REG_Y(r), \ 1732 .drv_reg = DRV_PINGROUP_REG(r), \
1744 .drv_bank = 0, \ 1733 .drv_bank = 0, \
1745 .hsm_bit = hsm_b, \ 1734 .hsm_bit = hsm_b, \
1746 .schmitt_bit = schmitt_b, \ 1735 .schmitt_bit = schmitt_b, \
@@ -1753,9 +1742,7 @@ static struct tegra_function tegra124_functions[] = {
1753 .slwr_width = slwr_w, \ 1742 .slwr_width = slwr_w, \
1754 .slwf_bit = slwf_b, \ 1743 .slwf_bit = slwf_b, \
1755 .slwf_width = slwf_w, \ 1744 .slwf_width = slwf_w, \
1756 .drvtype_reg = DRV_PINGROUP_REG_##drvtype(r), \ 1745 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1757 .drvtype_bank = 0, \
1758 .drvtype_bit = 6, \
1759 } 1746 }
1760 1747
1761static const struct tegra_pingroup tegra124_groups[] = { 1748static const struct tegra_pingroup tegra124_groups[] = {
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index e0b504088387..8d3b34a97ef5 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -1995,13 +1995,12 @@ static struct tegra_function tegra20_functions[] = {
1995 .tri_reg = ((tri_r) - TRISTATE_REG_A), \ 1995 .tri_reg = ((tri_r) - TRISTATE_REG_A), \
1996 .tri_bank = 0, \ 1996 .tri_bank = 0, \
1997 .tri_bit = tri_b, \ 1997 .tri_bit = tri_b, \
1998 .einput_reg = -1, \ 1998 .einput_bit = -1, \
1999 .odrain_reg = -1, \ 1999 .odrain_bit = -1, \
2000 .lock_reg = -1, \ 2000 .lock_bit = -1, \
2001 .ioreset_reg = -1, \ 2001 .ioreset_bit = -1, \
2002 .rcv_sel_reg = -1, \ 2002 .rcv_sel_bit = -1, \
2003 .drv_reg = -1, \ 2003 .drv_reg = -1, \
2004 .drvtype_reg = -1, \
2005 } 2004 }
2006 2005
2007/* Pin groups with only pull up and pull down control */ 2006/* Pin groups with only pull up and pull down control */
@@ -2014,14 +2013,7 @@ static struct tegra_function tegra20_functions[] = {
2014 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ 2013 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
2015 .pupd_bank = 2, \ 2014 .pupd_bank = 2, \
2016 .pupd_bit = pupd_b, \ 2015 .pupd_bit = pupd_b, \
2017 .tri_reg = -1, \
2018 .einput_reg = -1, \
2019 .odrain_reg = -1, \
2020 .lock_reg = -1, \
2021 .ioreset_reg = -1, \
2022 .rcv_sel_reg = -1, \
2023 .drv_reg = -1, \ 2016 .drv_reg = -1, \
2024 .drvtype_reg = -1, \
2025 } 2017 }
2026 2018
2027/* Pin groups for drive strength registers (configurable version) */ 2019/* Pin groups for drive strength registers (configurable version) */
@@ -2035,11 +2027,6 @@ static struct tegra_function tegra20_functions[] = {
2035 .mux_reg = -1, \ 2027 .mux_reg = -1, \
2036 .pupd_reg = -1, \ 2028 .pupd_reg = -1, \
2037 .tri_reg = -1, \ 2029 .tri_reg = -1, \
2038 .einput_reg = -1, \
2039 .odrain_reg = -1, \
2040 .lock_reg = -1, \
2041 .ioreset_reg = -1, \
2042 .rcv_sel_reg = -1, \
2043 .drv_reg = ((r) - PINGROUP_REG_A), \ 2030 .drv_reg = ((r) - PINGROUP_REG_A), \
2044 .drv_bank = 3, \ 2031 .drv_bank = 3, \
2045 .hsm_bit = hsm_b, \ 2032 .hsm_bit = hsm_b, \
@@ -2053,7 +2040,7 @@ static struct tegra_function tegra20_functions[] = {
2053 .slwr_width = slwr_w, \ 2040 .slwr_width = slwr_w, \
2054 .slwf_bit = slwf_b, \ 2041 .slwf_bit = slwf_b, \
2055 .slwf_width = slwf_w, \ 2042 .slwf_width = slwf_w, \
2056 .drvtype_reg = -1, \ 2043 .drvtype_bit = -1, \
2057 } 2044 }
2058 2045
2059/* Pin groups for drive strength registers (simple version) */ 2046/* Pin groups for drive strength registers (simple version) */
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 41d24f5c2854..6492adaa0575 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -2108,8 +2108,10 @@ static struct tegra_function tegra30_functions[] = {
2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2109#define PINGROUP_REG_A 0x3000 /* bank 1 */ 2109#define PINGROUP_REG_A 0x3000 /* bank 1 */
2110 2110
2111#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A) 2111#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
2112#define PINGROUP_REG_N(r) -1 2112
2113#define PINGROUP_BIT_Y(b) (b)
2114#define PINGROUP_BIT_N(b) (-1)
2113 2115
2114#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \ 2116#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior) \
2115 { \ 2117 { \
@@ -2123,34 +2125,24 @@ static struct tegra_function tegra30_functions[] = {
2123 TEGRA_MUX_##f3, \ 2125 TEGRA_MUX_##f3, \
2124 }, \ 2126 }, \
2125 .func_safe = TEGRA_MUX_##f_safe, \ 2127 .func_safe = TEGRA_MUX_##f_safe, \
2126 .mux_reg = PINGROUP_REG_Y(r), \ 2128 .mux_reg = PINGROUP_REG(r), \
2127 .mux_bank = 1, \ 2129 .mux_bank = 1, \
2128 .mux_bit = 0, \ 2130 .mux_bit = 0, \
2129 .pupd_reg = PINGROUP_REG_Y(r), \ 2131 .pupd_reg = PINGROUP_REG(r), \
2130 .pupd_bank = 1, \ 2132 .pupd_bank = 1, \
2131 .pupd_bit = 2, \ 2133 .pupd_bit = 2, \
2132 .tri_reg = PINGROUP_REG_Y(r), \ 2134 .tri_reg = PINGROUP_REG(r), \
2133 .tri_bank = 1, \ 2135 .tri_bank = 1, \
2134 .tri_bit = 4, \ 2136 .tri_bit = 4, \
2135 .einput_reg = PINGROUP_REG_Y(r), \ 2137 .einput_bit = PINGROUP_BIT_Y(5), \
2136 .einput_bank = 1, \ 2138 .odrain_bit = PINGROUP_BIT_##od(6), \
2137 .einput_bit = 5, \ 2139 .lock_bit = PINGROUP_BIT_Y(7), \
2138 .odrain_reg = PINGROUP_REG_##od(r), \ 2140 .ioreset_bit = PINGROUP_BIT_##ior(8), \
2139 .odrain_bank = 1, \ 2141 .rcv_sel_bit = -1, \
2140 .odrain_bit = 6, \
2141 .lock_reg = PINGROUP_REG_Y(r), \
2142 .lock_bank = 1, \
2143 .lock_bit = 7, \
2144 .ioreset_reg = PINGROUP_REG_##ior(r), \
2145 .ioreset_bank = 1, \
2146 .ioreset_bit = 8, \
2147 .rcv_sel_reg = -1, \
2148 .drv_reg = -1, \ 2142 .drv_reg = -1, \
2149 .drvtype_reg = -1, \
2150 } 2143 }
2151 2144
2152#define DRV_PINGROUP_REG_Y(r) ((r) - DRV_PINGROUP_REG_A) 2145#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
2153#define DRV_PINGROUP_REG_N(r) -1
2154 2146
2155#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 2147#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2156 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 2148 drvdn_b, drvdn_w, drvup_b, drvup_w, \
@@ -2162,12 +2154,12 @@ static struct tegra_function tegra30_functions[] = {
2162 .mux_reg = -1, \ 2154 .mux_reg = -1, \
2163 .pupd_reg = -1, \ 2155 .pupd_reg = -1, \
2164 .tri_reg = -1, \ 2156 .tri_reg = -1, \
2165 .einput_reg = -1, \ 2157 .einput_bit = -1, \
2166 .odrain_reg = -1, \ 2158 .odrain_bit = -1, \
2167 .lock_reg = -1, \ 2159 .lock_bit = -1, \
2168 .ioreset_reg = -1, \ 2160 .ioreset_bit = -1, \
2169 .rcv_sel_reg = -1, \ 2161 .rcv_sel_bit = -1, \
2170 .drv_reg = DRV_PINGROUP_REG_Y(r), \ 2162 .drv_reg = DRV_PINGROUP_REG(r), \
2171 .drv_bank = 0, \ 2163 .drv_bank = 0, \
2172 .hsm_bit = hsm_b, \ 2164 .hsm_bit = hsm_b, \
2173 .schmitt_bit = schmitt_b, \ 2165 .schmitt_bit = schmitt_b, \
@@ -2180,7 +2172,7 @@ static struct tegra_function tegra30_functions[] = {
2180 .slwr_width = slwr_w, \ 2172 .slwr_width = slwr_w, \
2181 .slwf_bit = slwf_b, \ 2173 .slwf_bit = slwf_b, \
2182 .slwf_width = slwf_w, \ 2174 .slwf_width = slwf_w, \
2183 .drvtype_reg = -1, \ 2175 .drvtype_bit = -1, \
2184 } 2176 }
2185 2177
2186static const struct tegra_pingroup tegra30_groups[] = { 2178static const struct tegra_pingroup tegra30_groups[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 10:00:02 -0500