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authorwwang <wei_wang@realsil.com.cn>2011-03-15 04:22:06 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-04-05 00:33:26 -0400
commite0007c0c87f02b357a4f97f792c96f1264d09ea9 (patch)
treeb9a4eaea8193e9e0325988d6d2b84c98704b0629 /drivers
parent07e195fde6dd553f30fb287fc169d64895425f5e (diff)
staging: rts_pstor: modify initial card clock
Modify initial card clock to avoid over spec Signed-off-by: wwang <wei_wang@realsil.com.cn> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/rts_pstor/rtsx.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/staging/rts_pstor/rtsx.c b/drivers/staging/rts_pstor/rtsx.c
index 4514419a5fb8..02525d57ba83 100644
--- a/drivers/staging/rts_pstor/rtsx.c
+++ b/drivers/staging/rts_pstor/rtsx.c
@@ -824,13 +824,13 @@ static void rtsx_init_options(struct rtsx_chip *chip)
824 chip->fpga_ms_hg_clk = CLK_80; 824 chip->fpga_ms_hg_clk = CLK_80;
825 chip->fpga_ms_4bit_clk = CLK_80; 825 chip->fpga_ms_4bit_clk = CLK_80;
826 chip->fpga_ms_1bit_clk = CLK_40; 826 chip->fpga_ms_1bit_clk = CLK_40;
827 chip->asic_sd_sdr104_clk = 207; 827 chip->asic_sd_sdr104_clk = 203;
828 chip->asic_sd_sdr50_clk = 99; 828 chip->asic_sd_sdr50_clk = 98;
829 chip->asic_sd_ddr50_clk = 99; 829 chip->asic_sd_ddr50_clk = 98;
830 chip->asic_sd_hs_clk = 99; 830 chip->asic_sd_hs_clk = 98;
831 chip->asic_mmc_52m_clk = 99; 831 chip->asic_mmc_52m_clk = 98;
832 chip->asic_ms_hg_clk = 119; 832 chip->asic_ms_hg_clk = 117;
833 chip->asic_ms_4bit_clk = 79; 833 chip->asic_ms_4bit_clk = 78;
834 chip->asic_ms_1bit_clk = 39; 834 chip->asic_ms_1bit_clk = 39;
835 chip->ssc_depth_sd_sdr104 = SSC_DEPTH_2M; 835 chip->ssc_depth_sd_sdr104 = SSC_DEPTH_2M;
836 chip->ssc_depth_sd_sdr50 = SSC_DEPTH_2M; 836 chip->ssc_depth_sd_sdr50 = SSC_DEPTH_2M;