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authorAlex Deucher <alexander.deucher@amd.com>2013-04-18 09:36:42 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-04-22 10:39:15 -0400
commitdcb852905772416e322536ced5cb3c796d176af5 (patch)
tree800a1764755c36a61c69d02b42d7613d3ed71ee4 /drivers
parentf93e3fc37e1e9959a4f3102f075bfb180ce8a72f (diff)
drm/radeon: fix hdmi mode enable on RS600/RS690/RS740
These chips were previously skipped since they are pre-R600. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 91582a534f77..e419b98b0c47 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -433,7 +433,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
433 offset = dig->afmt->offset; 433 offset = dig->afmt->offset;
434 434
435 /* Older chipsets require setting HDMI and routing manually */ 435 /* Older chipsets require setting HDMI and routing manually */
436 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 436 if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) {
437 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; 437 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
438 switch (radeon_encoder->encoder_id) { 438 switch (radeon_encoder->encoder_id) {
439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
@@ -499,7 +499,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
499 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 499 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
500 500
501 /* Older chipsets not handled by AtomBIOS */ 501 /* Older chipsets not handled by AtomBIOS */
502 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 502 if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) {
503 switch (radeon_encoder->encoder_id) { 503 switch (radeon_encoder->encoder_id) {
504 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 504 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
505 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); 505 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);