drm/radeon: fix bank tiling parameters on SI

The sixteen bank case wasn't handled here, leading to GPU
crashes because of userspace miscalculation.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 12 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index c053f8193771..c153a7f359c8 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1639,11 +1639,19 @@ static void si_gpu_init(struct radeon_device *rdev)
                 /* XXX what about 12? */
                 rdev->config.si.tile_config |= (3 << 0);
                 break;
-        }
-        if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
-                rdev->config.si.tile_config |= 1 << 4;
-        else
+        }       
+        switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
+        case 0: /* four banks */
                 rdev->config.si.tile_config |= 0 << 4;
+                break;
+        case 1: /* eight banks */
+                rdev->config.si.tile_config |= 1 << 4;
+                break;
+        case 2: /* sixteen banks */
+        default:
+                rdev->config.si.tile_config |= 2 << 4;
+                break;
+        }
         rdev->config.si.tile_config |=
                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
         rdev->config.si.tile_config |=