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authorDave Airlie <airlied@redhat.com>2010-03-30 23:41:35 -0400
committerDave Airlie <airlied@redhat.com>2010-03-31 22:50:46 -0400
commitd668046c13024d74af7d04a124ba55f406380fe7 (patch)
tree41ef48d72324f88211e279a56bd7f43563a3e366 /drivers
parent08a370fa758fae7e387274ca3571ce625d7f829b (diff)
drm/radeon/kms: enable ACPI powermanagement mode on radeon gpus.
Some GPUs have an APM/ACPI PM mode selection switch and some BIOSes set this to APM. We really want this in ACPI mode for Linux. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/r100.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h1
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index c8f4b0300b70..3ae51ada1abf 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1809,6 +1809,7 @@ void r100_set_common_regs(struct radeon_device *rdev)
1809{ 1809{
1810 struct drm_device *dev = rdev->ddev; 1810 struct drm_device *dev = rdev->ddev;
1811 bool force_dac2 = false; 1811 bool force_dac2 = false;
1812 u32 tmp;
1812 1813
1813 /* set these so they don't interfere with anything */ 1814 /* set these so they don't interfere with anything */
1814 WREG32(RADEON_OV0_SCALE_CNTL, 0); 1815 WREG32(RADEON_OV0_SCALE_CNTL, 0);
@@ -1880,6 +1881,12 @@ void r100_set_common_regs(struct radeon_device *rdev)
1880 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1881 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1881 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1882 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1882 } 1883 }
1884
1885 /* switch PM block to ACPI mode */
1886 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
1887 tmp &= ~RADEON_PM_MODE_SEL;
1888 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
1889
1883} 1890}
1884 1891
1885/* 1892/*
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 5c0dc082d330..eabbc9cf30a7 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -346,6 +346,7 @@
346# define RADEON_TVPLL_PWRMGT_OFF (1 << 30) 346# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
347# define RADEON_TVCLK_TURNOFF (1 << 31) 347# define RADEON_TVCLK_TURNOFF (1 << 31)
348#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ 348#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
349# define RADEON_PM_MODE_SEL (1 << 13)
349# define RADEON_TCL_BYPASS_DISABLE (1 << 20) 350# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
350#define RADEON_CLR_CMP_CLR_3D 0x1a24 351#define RADEON_CLR_CMP_CLR_3D 0x1a24
351#define RADEON_CLR_CMP_CLR_DST 0x15c8 352#define RADEON_CLR_CMP_CLR_DST 0x15c8