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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2012-11-20 10:27:35 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-21 11:46:45 -0500
commitd63fa0dc1a3636816260bc507e59e168e423f150 (patch)
tree43d9681beebd6436c67e83c1bc9b45e05230f8d1 /drivers
parentb4a98e57fc27854b5938fc8b08b68e5e68b91e1f (diff)
drm/i915: don't limit Haswell CRT encoder to pipe A
This is a full revert of 59c859d6f2e78344945e8a8406a194156176bc4e: drm/i915: account for only one PCH receiver on Haswell Now that the PCH code is fixed to be able use the only PCH transcoder independently of the pipe and CPU transcoder, we can revert this. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Resolve conflict due to the rebasing of dinq on top of drm-next.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c15
2 files changed, 4 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 62a5b1154762..5c7774396e10 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -751,7 +751,7 @@ void intel_crt_init(struct drm_device *dev)
751 751
752 crt->base.type = INTEL_OUTPUT_ANALOG; 752 crt->base.type = INTEL_OUTPUT_ANALOG;
753 crt->base.cloneable = true; 753 crt->base.cloneable = true;
754 if (IS_HASWELL(dev) || IS_I830(dev)) 754 if (IS_I830(dev))
755 crt->base.crtc_mask = (1 << 0); 755 crt->base.crtc_mask = (1 << 0);
756 else 756 else
757 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 757 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 797953376954..82ab55af52fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1149,14 +1149,9 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1149 u32 val; 1149 u32 val;
1150 bool cur_state; 1150 bool cur_state;
1151 1151
1152 if (IS_HASWELL(dev_priv->dev) && pipe > 0) { 1152 reg = FDI_RX_CTL(pipe);
1153 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n"); 1153 val = I915_READ(reg);
1154 return; 1154 cur_state = !!(val & FDI_RX_ENABLE);
1155 } else {
1156 reg = FDI_RX_CTL(pipe);
1157 val = I915_READ(reg);
1158 cur_state = !!(val & FDI_RX_ENABLE);
1159 }
1160 WARN(cur_state != state, 1155 WARN(cur_state != state,
1161 "FDI RX state assertion failure (expected %s, current %s)\n", 1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1162 state_string(state), state_string(cur_state)); 1157 state_string(state), state_string(cur_state));
@@ -1189,10 +1184,6 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 int reg; 1184 int reg;
1190 u32 val; 1185 u32 val;
1191 1186
1192 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1193 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1194 return;
1195 }
1196 reg = FDI_RX_CTL(pipe); 1187 reg = FDI_RX_CTL(pipe);
1197 val = I915_READ(reg); 1188 val = I915_READ(reg);
1198 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); 1189 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");