diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-03-28 16:39:24 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-03-28 18:09:44 -0400 |
commit | c46ce4d7e69d129c02640c118f45a86a4412774b (patch) | |
tree | c3a1ecf611288c2b11e1cf172996a7cf87f21fed /drivers | |
parent | 575155a9af9ba5e384caa6979cd918387d712221 (diff) |
drm/i915: interrupt bit definitions for VLV
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3aadace73ddb..0bcad74de7be 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -2485,23 +2485,30 @@ | |||
2485 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) | 2485 | #define PIPECONF_DITHER_TYPE_TEMP (3<<2) |
2486 | #define _PIPEASTAT 0x70024 | 2486 | #define _PIPEASTAT 0x70024 |
2487 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) | 2487 | #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) |
2488 | #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) | ||
2488 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) | 2489 | #define PIPE_CRC_ERROR_ENABLE (1UL<<29) |
2489 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) | 2490 | #define PIPE_CRC_DONE_ENABLE (1UL<<28) |
2490 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) | 2491 | #define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) |
2492 | #define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) | ||
2491 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) | 2493 | #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) |
2492 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) | 2494 | #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) |
2493 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | 2495 | #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) |
2494 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) | 2496 | #define PIPE_DPST_EVENT_ENABLE (1UL<<23) |
2497 | #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26) | ||
2495 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | 2498 | #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) |
2496 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | 2499 | #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) |
2497 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | 2500 | #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) |
2498 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ | 2501 | #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ |
2499 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | 2502 | #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ |
2500 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) | 2503 | #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) |
2504 | #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) | ||
2501 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) | 2505 | #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) |
2506 | #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15) | ||
2507 | #define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15) | ||
2502 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | 2508 | #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) |
2503 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | 2509 | #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) |
2504 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) | 2510 | #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) |
2511 | #define PLANE_FLIPDONE_INT_STATUS_VLV (1UL<<10) | ||
2505 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) | 2512 | #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) |
2506 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) | 2513 | #define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) |
2507 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | 2514 | #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) |
@@ -2526,6 +2533,40 @@ | |||
2526 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) | 2533 | #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) |
2527 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) | 2534 | #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) |
2528 | 2535 | ||
2536 | #define DPFLIPSTAT_VLV 0x70028 | ||
2537 | #define PIPEB_LINE_COMPARE_STATUS (1<<29) | ||
2538 | #define PIPEB_HLINE_INT_EN (1<<28) | ||
2539 | #define PIPEB_VBLANK_INT_EN (1<<27) | ||
2540 | #define SPRITED_FLIPDONE_INT_EN (1<<26) | ||
2541 | #define SPRITEC_FLIPDONE_INT_EN (1<<25) | ||
2542 | #define PLANEB_FLIPDONE_INT_EN (1<<24) | ||
2543 | #define PIPEA_LINE_COMPARE_STATUS (1<<21) | ||
2544 | #define PIPEA_HLINE_INT_EN (1<<20) | ||
2545 | #define PIPEA_VBLANK_INT_EN (1<<19) | ||
2546 | #define SPRITEB_FLIPDONE_INT_EN (1<<18) | ||
2547 | #define SPRITEA_FLIPDONE_INT_EN (1<<17) | ||
2548 | #define PLANEA_FLIPDONE_INT_EN (1<<16) | ||
2549 | |||
2550 | #define DPINVGTT 0x7002c /* VLV only */ | ||
2551 | #define CURSORB_INVALID_GTT_INT_EN (1<<23) | ||
2552 | #define CURSORA_INVALID_GTT_INT_EN (1<<22) | ||
2553 | #define SPRITED_INVALID_GTT_INT_EN (1<<21) | ||
2554 | #define SPRITEC_INVALID_GTT_INT_EN (1<<20) | ||
2555 | #define PLANEB_INVALID_GTT_INT_EN (1<<19) | ||
2556 | #define SPRITEB_INVALID_GTT_INT_EN (1<<18) | ||
2557 | #define SPRITEA_INVALID_GTT_INT_EN (1<<17) | ||
2558 | #define PLANEA_INVALID_GTT_INT_EN (1<<16) | ||
2559 | #define DPINVGTT_EN_MASK 0xff0000 | ||
2560 | #define CURSORB_INVALID_GTT_STATUS (1<<7) | ||
2561 | #define CURSORA_INVALID_GTT_STATUS (1<<6) | ||
2562 | #define SPRITED_INVALID_GTT_STATUS (1<<5) | ||
2563 | #define SPRITEC_INVALID_GTT_STATUS (1<<4) | ||
2564 | #define PLANEB_INVALID_GTT_STATUS (1<<3) | ||
2565 | #define SPRITEB_INVALID_GTT_STATUS (1<<2) | ||
2566 | #define SPRITEA_INVALID_GTT_STATUS (1<<1) | ||
2567 | #define PLANEA_INVALID_GTT_STATUS (1<<0) | ||
2568 | #define DPINVGTT_STATUS_MASK 0xff | ||
2569 | |||
2529 | #define DSPARB 0x70030 | 2570 | #define DSPARB 0x70030 |
2530 | #define DSPARB_CSTART_MASK (0x7f << 7) | 2571 | #define DSPARB_CSTART_MASK (0x7f << 7) |
2531 | #define DSPARB_CSTART_SHIFT 7 | 2572 | #define DSPARB_CSTART_SHIFT 7 |