ath9k_hw: Restore ANI registers to default during partial reset for AR9271

For AR9271 chips, if partial reset is done while scanning, the cycpwrThr1
will be set to maximum. This causes the degrade in DL throughput.
So restore the ANI registers to default during the partial reset.

Signed-off-by: Rajkumar Manoharan <rmanoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

3 files changed, 53 insertions, 0 deletions

diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 303c63da5ea3..94392daebaa0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -580,3 +580,53 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
         else
                 ath9k_hw_attach_ani_ops_old(ah);
 }
+
+void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
+{
+        u32 modesIndex;
+        int i;
+
+        switch (chan->chanmode) {
+        case CHANNEL_A:
+        case CHANNEL_A_HT20:
+                modesIndex = 1;
+                break;
+        case CHANNEL_A_HT40PLUS:
+        case CHANNEL_A_HT40MINUS:
+                modesIndex = 2;
+                break;
+        case CHANNEL_G:
+        case CHANNEL_G_HT20:
+        case CHANNEL_B:
+                modesIndex = 4;
+                break;
+        case CHANNEL_G_HT40PLUS:
+        case CHANNEL_G_HT40MINUS:
+                modesIndex = 3;
+                break;
+
+        default:
+                return;
+        }
+
+        ENABLE_REGWRITE_BUFFER(ah);
+
+        for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) {
+                u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0);
+                u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex);
+                u32 val_orig;
+
+                if (reg == AR_PHY_CCK_DETECT) {
+                        val_orig = REG_READ(ah, reg);
+                        val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
+                        val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK;
+
+                        REG_WRITE(ah, reg, val|val_orig);
+                } else
+                        REG_WRITE(ah, reg, val);
+        }
+
+        REGWRITE_BUFFER_FLUSH(ah);
+        DISABLE_REGWRITE_BUFFER(ah);
+
+}
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 68940a8864e0..afadade2a67e 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1263,6 +1263,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                 if (ath9k_hw_channel_change(ah, chan)) {
                         ath9k_hw_loadnf(ah, ah->curchan);
                         ath9k_hw_start_nfcal(ah, true);
+                        if (AR_SREV_9271(ah))
+                                ar9002_hw_load_ani_reg(ah, chan);
                         return 0;
                 }
         }
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 197c717286e7..1724b17bfc73 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -996,6 +996,7 @@ void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
 void ar9002_hw_attach_ops(struct ath_hw *ah);
 void ar9003_hw_attach_ops(struct ath_hw *ah);
 
+void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
 /*
  * ANI work can be shared between all families but a next
  * generation implementation of ANI will be used only for AR9003 only