ARM: at91: make watchdog drivers soc independent

switch the watchdog drivers to resource and pass it via platform_device

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>

2 files changed, 22 insertions, 6 deletions

diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index 87445b2d72a7..00562566ef5f 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -35,6 +35,11 @@
 
 #define DRV_NAME "AT91SAM9 Watchdog"
 
+#define wdt_read(field) \
+        __raw_readl(at91wdt_private.base + field)
+#define wdt_write(field, val) \
+        __raw_writel((val), at91wdt_private.base + field)
+
 /* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
  * use this to convert a watchdog
  * value from/to milliseconds.
@@ -63,6 +68,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
 static void at91_ping(unsigned long data);
 
 static struct {
+        void __iomem *base;
         unsigned long next_heartbeat;   /* the next_heartbeat for the timer */
         unsigned long open;
         char expect_close;
@@ -77,7 +83,7 @@ static struct {
  */
 static inline void at91_wdt_reset(void)
 {
-        at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
+        wdt_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
 }
 
 /*
@@ -132,7 +138,7 @@ static int at91_wdt_settimeout(unsigned int timeout)
         unsigned int mr;
 
         /* Check if disabled */
-        mr = at91_sys_read(AT91_WDT_MR);
+        mr = wdt_read(AT91_WDT_MR);
         if (mr & AT91_WDT_WDDIS) {
                 printk(KERN_ERR DRV_NAME": sorry, watchdog is disabled\n");
                 return -EIO;
@@ -149,7 +155,7 @@ static int at91_wdt_settimeout(unsigned int timeout)
                 | AT91_WDT_WDDBGHLT     /* disabled in debug mode */
                 | AT91_WDT_WDD          /* restart at any time */
                 | (timeout & AT91_WDT_WDV);  /* timer value */
-        at91_sys_write(AT91_WDT_MR, reg);
+        wdt_write(AT91_WDT_MR, reg);
 
         return 0;
 }
@@ -248,12 +254,22 @@ static struct miscdevice at91wdt_miscdev = {
 
 static int __init at91wdt_probe(struct platform_device *pdev)
 {
+        struct resource *r;
         int res;
 
         if (at91wdt_miscdev.parent)
                 return -EBUSY;
         at91wdt_miscdev.parent = &pdev->dev;
 
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r)
+                return -ENODEV;
+        at91wdt_private.base = ioremap(r->start, resource_size(r));
+        if (!at91wdt_private.base) {
+                dev_err(&pdev->dev, "failed to map registers, aborting.\n");
+                return -ENOMEM;
+        }
+
         /* Set watchdog */
         res = at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
         if (res)
diff --git a/drivers/watchdog/at91sam9_wdt.h b/drivers/watchdog/at91sam9_wdt.h
index 757f9cab5c82..c6fbb2e6c41b 100644
--- a/drivers/watchdog/at91sam9_wdt.h
+++ b/drivers/watchdog/at91sam9_wdt.h
@@ -16,11 +16,11 @@
 #ifndef AT91_WDT_H
 #define AT91_WDT_H
 
-#define AT91_WDT_CR             (AT91_WDT + 0x00)       /* Watchdog Control Register */
+#define AT91_WDT_CR             0x00                    /* Watchdog Control Register */
 #define         AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
 #define         AT91_WDT_KEY            (0xa5 << 24)            /* KEY Password */
 
-#define AT91_WDT_MR             (AT91_WDT + 0x04)       /* Watchdog Mode Register */
+#define AT91_WDT_MR             0x04                    /* Watchdog Mode Register */
 #define         AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
 #define         AT91_WDT_WDFIEN         (1     << 12)           /* Fault Interrupt Enable */
 #define         AT91_WDT_WDRSTEN        (1     << 13)           /* Reset Processor */
@@ -30,7 +30,7 @@
 #define         AT91_WDT_WDDBGHLT       (1     << 28)           /* Debug Halt */
 #define         AT91_WDT_WDIDLEHLT      (1     << 29)           /* Idle Halt */
 
-#define AT91_WDT_SR             (AT91_WDT + 0x08)       /* Watchdog Status Register */
+#define AT91_WDT_SR             0x08                    /* Watchdog Status Register */
 #define         AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
 #define         AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */