diff options
author | Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | 2009-08-21 03:30:28 -0400 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-21 04:25:47 -0400 |
commit | c01f0f1a4a96eb3acc5850e18cc43f24366966d0 (patch) | |
tree | 402c307afc1af3023e1e1528f0abd190e94ae4e7 /drivers | |
parent | 9e7291c1124655980ab05fc89930de8e218c7d64 (diff) |
sh: Add initial support for SH7757 CPU subtype
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/serial/sh-sci.c | 3 | ||||
-rw-r--r-- | drivers/serial/sh-sci.h | 17 |
2 files changed, 19 insertions, 1 deletions
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c index 4cbb87ad070a..32dc2fc50e6b 100644 --- a/drivers/serial/sh-sci.c +++ b/drivers/serial/sh-sci.c | |||
@@ -272,7 +272,8 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag) | |||
272 | __raw_writew(data, PSCR); | 272 | __raw_writew(data, PSCR); |
273 | } | 273 | } |
274 | } | 274 | } |
275 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ | 275 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \ |
276 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ | ||
276 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | 277 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
277 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | 278 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
278 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ | 279 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ |
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 38072c15b845..3e2fcf93b42e 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -112,6 +112,13 @@ | |||
112 | #elif defined(CONFIG_H8S2678) | 112 | #elif defined(CONFIG_H8S2678) |
113 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | 113 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
114 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | 114 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
115 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) | ||
116 | # define SCSPTR0 0xfe4b0020 | ||
117 | # define SCSPTR1 0xfe4b0020 | ||
118 | # define SCSPTR2 0xfe4b0020 | ||
119 | # define SCIF_ORER 0x0001 | ||
120 | # define SCSCR_INIT(port) 0x38 | ||
121 | # define SCIF_ONLY | ||
115 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | 122 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
116 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | 123 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
117 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | 124 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ |
@@ -562,6 +569,16 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
562 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | 569 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ |
563 | return 1; | 570 | return 1; |
564 | } | 571 | } |
572 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) | ||
573 | static inline int sci_rxd_in(struct uart_port *port) | ||
574 | { | ||
575 | if (port->mapbase == 0xfe4b0000) | ||
576 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; | ||
577 | if (port->mapbase == 0xfe4c0000) | ||
578 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; | ||
579 | if (port->mapbase == 0xfe4d0000) | ||
580 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; | ||
581 | } | ||
565 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | 582 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
566 | static inline int sci_rxd_in(struct uart_port *port) | 583 | static inline int sci_rxd_in(struct uart_port *port) |
567 | { | 584 | { |