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authorOlof Johansson <olof@lixom.net>2013-04-13 02:04:54 -0400
committerOlof Johansson <olof@lixom.net>2013-04-13 02:05:08 -0400
commitbf049ded36b2178e80bb9f227d4490714d838c11 (patch)
tree39b81f33a56bb96551d3d2f24bf075af839f994d /drivers
parent4f779ad9939038821202ac5632bbb9610fbac124 (diff)
parent58a7bbf75442ea439a4d3b7993ad87023e406063 (diff)
Merge tag 'dt-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt2
update device tree for exynos4 and exynos5 * tag 'dt-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (125 commits) ARM: dts: add PDMA0 changes for exynos5440 ARM: dts: Add cpufreq controller node for Exynos5440 SoC ARM: dts: Fix gmac clock ids due to changes in Exynos5440 ARM: dts: add device tree file for SD5v1 board ARM: dts: update bootargs to boot from sda2 for exynos5440-ssdk5440 ARM: dts: add PMU support in exynos5440 ARM: dts: Add node for GMAC for exynos5440 ARM: dts: list the interrupts generated by pin-controller on Exynos5440 ARM: dts: Add FIMD DT binding Documentation ARM: dts: Add FIMD node and display timing node to exynos4412-origen.dts ARM: dts: Add FIMD node to exynos4 ARM: dts: Add SYSREG block node for S5P/Exynos4 SoC series ARM: dts: Add display timing node to exynos5250-smdk5250.dts ARM: dts: Add FIMD node to exynos5 ARM: dts: Add virtual GIC DT bindings for exynos5440 ARM: dts: Document usb clocks in samsung,exynos4210-ehci/ohci bindings ARM: dts: add usb 2.0 clock references to exynos5250 device tree ARM: dts: Add architected timer nodes for exynos5250 ARM: dts: Declare the gic as a15 compatible for exynos5250 ARM: dts: Add HDMI HPD and regulator node for Arndale board ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/samsung/Makefile8
-rw-r--r--drivers/clk/samsung/clk-exynos4.c1091
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c523
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c139
-rw-r--r--drivers/clk/samsung/clk-pll.c419
-rw-r--r--drivers/clk/samsung/clk-pll.h41
-rw-r--r--drivers/clk/samsung/clk.c320
-rw-r--r--drivers/clk/samsung/clk.h289
-rw-r--r--drivers/clocksource/Kconfig5
-rw-r--r--drivers/clocksource/Makefile1
-rw-r--r--drivers/clocksource/exynos_mct.c558
-rw-r--r--drivers/mmc/host/s3cmci.c83
13 files changed, 3476 insertions, 2 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 79e98e416724..17e8dc4e417c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
29obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 29obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
30obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o 30obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
31obj-$(CONFIG_ARCH_TEGRA) += tegra/ 31obj-$(CONFIG_ARCH_TEGRA) += tegra/
32obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
32 33
33obj-$(CONFIG_X86) += x86/ 34obj-$(CONFIG_X86) += x86/
34 35
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
new file mode 100644
index 000000000000..b7c232e67425
--- /dev/null
+++ b/drivers/clk/samsung/Makefile
@@ -0,0 +1,8 @@
1#
2# Samsung Clock specific Makefile
3#
4
5obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
6obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
7obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
8obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
new file mode 100644
index 000000000000..71046694d9dd
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -0,0 +1,1091 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Exynos4 SoCs.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <plat/cpu.h>
20#include "clk.h"
21#include "clk-pll.h"
22
23/* Exynos4 clock controller register offsets */
24#define SRC_LEFTBUS 0x4200
25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800
27#define E4X12_GATE_IP_IMAGE 0x4930
28#define SRC_RIGHTBUS 0x8200
29#define DIV_RIGHTBUS 0x8500
30#define GATE_IP_RIGHTBUS 0x8800
31#define E4X12_GATE_IP_PERIR 0x8960
32#define EPLL_LOCK 0xc010
33#define VPLL_LOCK 0xc020
34#define EPLL_CON0 0xc110
35#define EPLL_CON1 0xc114
36#define EPLL_CON2 0xc118
37#define VPLL_CON0 0xc120
38#define VPLL_CON1 0xc124
39#define VPLL_CON2 0xc128
40#define SRC_TOP0 0xc210
41#define SRC_TOP1 0xc214
42#define SRC_CAM 0xc220
43#define SRC_TV 0xc224
44#define SRC_MFC 0xcc28
45#define SRC_G3D 0xc22c
46#define E4210_SRC_IMAGE 0xc230
47#define SRC_LCD0 0xc234
48#define E4210_SRC_LCD1 0xc238
49#define E4X12_SRC_ISP 0xc238
50#define SRC_MAUDIO 0xc23c
51#define SRC_FSYS 0xc240
52#define SRC_PERIL0 0xc250
53#define SRC_PERIL1 0xc254
54#define E4X12_SRC_CAM1 0xc258
55#define SRC_MASK_TOP 0xc310
56#define SRC_MASK_CAM 0xc320
57#define SRC_MASK_TV 0xc324
58#define SRC_MASK_LCD0 0xc334
59#define E4210_SRC_MASK_LCD1 0xc338
60#define E4X12_SRC_MASK_ISP 0xc338
61#define SRC_MASK_MAUDIO 0xc33c
62#define SRC_MASK_FSYS 0xc340
63#define SRC_MASK_PERIL0 0xc350
64#define SRC_MASK_PERIL1 0xc354
65#define DIV_TOP 0xc510
66#define DIV_CAM 0xc520
67#define DIV_TV 0xc524
68#define DIV_MFC 0xc528
69#define DIV_G3D 0xc52c
70#define DIV_IMAGE 0xc530
71#define DIV_LCD0 0xc534
72#define E4210_DIV_LCD1 0xc538
73#define E4X12_DIV_ISP 0xc538
74#define DIV_MAUDIO 0xc53c
75#define DIV_FSYS0 0xc540
76#define DIV_FSYS1 0xc544
77#define DIV_FSYS2 0xc548
78#define DIV_FSYS3 0xc54c
79#define DIV_PERIL0 0xc550
80#define DIV_PERIL1 0xc554
81#define DIV_PERIL2 0xc558
82#define DIV_PERIL3 0xc55c
83#define DIV_PERIL4 0xc560
84#define DIV_PERIL5 0xc564
85#define E4X12_DIV_CAM1 0xc568
86#define GATE_SCLK_CAM 0xc820
87#define GATE_IP_CAM 0xc920
88#define GATE_IP_TV 0xc924
89#define GATE_IP_MFC 0xc928
90#define GATE_IP_G3D 0xc92c
91#define E4210_GATE_IP_IMAGE 0xc930
92#define GATE_IP_LCD0 0xc934
93#define E4210_GATE_IP_LCD1 0xc938
94#define E4X12_GATE_IP_ISP 0xc938
95#define E4X12_GATE_IP_MAUDIO 0xc93c
96#define GATE_IP_FSYS 0xc940
97#define GATE_IP_GPS 0xc94c
98#define GATE_IP_PERIL 0xc950
99#define E4210_GATE_IP_PERIR 0xc960
100#define GATE_BLOCK 0xc970
101#define E4X12_MPLL_CON0 0x10108
102#define SRC_DMC 0x10200
103#define SRC_MASK_DMC 0x10300
104#define DIV_DMC0 0x10500
105#define DIV_DMC1 0x10504
106#define GATE_IP_DMC 0x10900
107#define APLL_CON0 0x14100
108#define E4210_MPLL_CON0 0x14108
109#define SRC_CPU 0x14200
110#define DIV_CPU0 0x14500
111#define DIV_CPU1 0x14504
112#define GATE_SCLK_CPU 0x14800
113#define GATE_IP_CPU 0x14900
114#define E4X12_DIV_ISP0 0x18300
115#define E4X12_DIV_ISP1 0x18304
116#define E4X12_GATE_ISP0 0x18800
117#define E4X12_GATE_ISP1 0x18804
118
119/* the exynos4 soc type */
120enum exynos4_soc {
121 EXYNOS4210,
122 EXYNOS4X12,
123};
124
125/*
126 * Let each supported clock get a unique id. This id is used to lookup the clock
127 * for device tree based platforms. The clocks are categorized into three
128 * sections: core, sclk gate and bus interface gate clocks.
129 *
130 * When adding a new clock to this list, it is advised to choose a clock
131 * category and add it to the end of that category. That is because the the
132 * device tree source file is referring to these ids and any change in the
133 * sequence number of existing clocks will require corresponding change in the
134 * device tree files. This limitation would go away when pre-processor support
135 * for dtc would be available.
136 */
137enum exynos4_clks {
138 none,
139
140 /* core clocks */
141 xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll,
142 sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100,
143 aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core,
144 mout_apll, /* 20 */
145
146 /* gate for special clocks (sclk) */
147 sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0,
148 sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac,
149 sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0,
150 sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4,
151 sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4,
152 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
153 sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
154 sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
155 sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
156
157 /* gate clocks */
158 fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
159 smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi,
160 smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d,
161 smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1,
162 mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0,
163 sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie,
164 onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3,
165 uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc,
166 spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus,
167 spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif,
168 audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0,
169 fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp,
170 gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp,
171 mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp,
172 asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk,
173 spi1_isp_sclk, uart_isp_sclk,
174
175 /* mux clocks */
176 mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0,
177 mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d,
178 aclk400_mcuisp,
179
180 /* div clocks */
181 div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200,
182 div_aclk400_mcuisp,
183
184 nr_clks,
185};
186
187/*
188 * list of controller registers to be saved and restored during a
189 * suspend/resume cycle.
190 */
191static __initdata unsigned long exynos4210_clk_save[] = {
192 E4210_SRC_IMAGE,
193 E4210_SRC_LCD1,
194 E4210_SRC_MASK_LCD1,
195 E4210_DIV_LCD1,
196 E4210_GATE_IP_IMAGE,
197 E4210_GATE_IP_LCD1,
198 E4210_GATE_IP_PERIR,
199 E4210_MPLL_CON0,
200};
201
202static __initdata unsigned long exynos4x12_clk_save[] = {
203 E4X12_GATE_IP_IMAGE,
204 E4X12_GATE_IP_PERIR,
205 E4X12_SRC_CAM1,
206 E4X12_DIV_ISP,
207 E4X12_DIV_CAM1,
208 E4X12_MPLL_CON0,
209};
210
211static __initdata unsigned long exynos4_clk_regs[] = {
212 SRC_LEFTBUS,
213 DIV_LEFTBUS,
214 GATE_IP_LEFTBUS,
215 SRC_RIGHTBUS,
216 DIV_RIGHTBUS,
217 GATE_IP_RIGHTBUS,
218 EPLL_CON0,
219 EPLL_CON1,
220 EPLL_CON2,
221 VPLL_CON0,
222 VPLL_CON1,
223 VPLL_CON2,
224 SRC_TOP0,
225 SRC_TOP1,
226 SRC_CAM,
227 SRC_TV,
228 SRC_MFC,
229 SRC_G3D,
230 SRC_LCD0,
231 SRC_MAUDIO,
232 SRC_FSYS,
233 SRC_PERIL0,
234 SRC_PERIL1,
235 SRC_MASK_TOP,
236 SRC_MASK_CAM,
237 SRC_MASK_TV,
238 SRC_MASK_LCD0,
239 SRC_MASK_MAUDIO,
240 SRC_MASK_FSYS,
241 SRC_MASK_PERIL0,
242 SRC_MASK_PERIL1,
243 DIV_TOP,
244 DIV_CAM,
245 DIV_TV,
246 DIV_MFC,
247 DIV_G3D,
248 DIV_IMAGE,
249 DIV_LCD0,
250 DIV_MAUDIO,
251 DIV_FSYS0,
252 DIV_FSYS1,
253 DIV_FSYS2,
254 DIV_FSYS3,
255 DIV_PERIL0,
256 DIV_PERIL1,
257 DIV_PERIL2,
258 DIV_PERIL3,
259 DIV_PERIL4,
260 DIV_PERIL5,
261 GATE_SCLK_CAM,
262 GATE_IP_CAM,
263 GATE_IP_TV,
264 GATE_IP_MFC,
265 GATE_IP_G3D,
266 GATE_IP_LCD0,
267 GATE_IP_FSYS,
268 GATE_IP_GPS,
269 GATE_IP_PERIL,
270 GATE_BLOCK,
271 SRC_MASK_DMC,
272 SRC_DMC,
273 DIV_DMC0,
274 DIV_DMC1,
275 GATE_IP_DMC,
276 APLL_CON0,
277 SRC_CPU,
278 DIV_CPU0,
279 DIV_CPU1,
280 GATE_SCLK_CPU,
281 GATE_IP_CPU,
282};
283
284/* list of all parent clock list */
285PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
286PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
287PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
288PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
289PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
290PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
291PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
292PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
293PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
294PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
295PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", };
296PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
297 "spdif_extclk", };
298PNAME(mout_onenand_p) = {"aclk133", "aclk160", };
299PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
300
301/* Exynos 4210-specific parent groups */
302PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", };
303PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", };
304PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", };
305PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m",
306 "sclk_usbphy0", "none", "sclk_hdmiphy",
307 "sclk_mpll", "sclk_epll", "sclk_vpll", };
308PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
309 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
310 "sclk_epll", "sclk_vpll" };
311PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
312 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
313 "sclk_epll", "sclk_vpll", };
314PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
315 "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
316 "sclk_epll", "sclk_vpll", };
317PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
318PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
319
320/* Exynos 4x12-specific parent groups */
321PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
322PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
323PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
324PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
325 "none", "sclk_hdmiphy", "mout_mpll_user_t",
326 "sclk_epll", "sclk_vpll", };
327PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
328 "sclk_usbphy0", "xxti", "xusbxti",
329 "mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
330PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
331 "sclk_usbphy0", "xxti", "xusbxti",
332 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
333PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
334 "sclk_usbphy0", "xxti", "xusbxti",
335 "mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
336PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
337PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
338PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
339PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
340
341/* fixed rate clocks generated outside the soc */
342struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
343 FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0),
344 FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0),
345};
346
347/* fixed rate clocks generated inside the soc */
348struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
349 FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
350 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
351 FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
352};
353
354struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = {
355 FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
356};
357
358/* list of mux clocks supported in all exynos4 soc's */
359struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
360 MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
361 CLK_SET_RATE_PARENT, 0),
362 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
363 MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
364 MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
365 MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
366 CLK_SET_RATE_PARENT, 0),
367 MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
368 CLK_SET_RATE_PARENT, 0),
369 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
370 MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
371 MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"),
372 MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
373};
374
375/* list of mux clocks supported in exynos4210 soc */
376struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
377 MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
378 MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
379 MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
380 MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
381 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
382 MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
383 MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
384 MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
385 MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
386 MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
387 MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
388 MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
389 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
390 MUX_A(mout_core, "mout_core", mout_core_p4210,
391 SRC_CPU, 16, 1, "mout_core"),
392 MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
393 SRC_TOP0, 8, 1, "sclk_vpll"),
394 MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
395 MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
396 MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
397 MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
398 MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
399 MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
400 MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
401 MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
402 MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
403 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
404 CLK_SET_RATE_PARENT, 0),
405 MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
406 MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
407 MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
408 MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
409 MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
410 MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
411 MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
412 MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
413 MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
414 MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
415 MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
416 MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
417 MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
418 MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
419 MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
420 MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
421 MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
422 MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
423 MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
424};
425
426/* list of mux clocks supported in exynos4x12 soc */
427struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
428 MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12,
429 SRC_CPU, 24, 1),
430 MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
431 MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
432 MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12,
433 SRC_TOP1, 12, 1),
434 MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
435 SRC_TOP1, 16, 1),
436 MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
437 MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12,
438 SRC_TOP1, 24, 1),
439 MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
440 MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
441 MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
442 MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
443 MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
444 MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
445 MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
446 MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
447 MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
448 MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
449 MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p,
450 SRC_DMC, 12, 1, "sclk_mpll"),
451 MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p,
452 SRC_TOP0, 8, 1, "sclk_vpll"),
453 MUX(mout_core, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
454 MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
455 MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
456 MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
457 MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
458 MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
459 MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
460 MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
461 MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
462 MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
463 MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
464 CLK_SET_RATE_PARENT, 0),
465 MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
466 MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
467 MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
468 MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
469 MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
470 MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
471 MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
472 MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
473 MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
474 MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
475 MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
476 MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
477 MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
478 MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
479 MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
480 MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
481 MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
482 MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
483 MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
484 MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
485 MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
486 MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
487 MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
488};
489
490/* list of divider clocks supported in all exynos4 soc's */
491struct samsung_div_clock exynos4_div_clks[] __initdata = {
492 DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3),
493 DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3),
494 DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
495 DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
496 DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
497 DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
498 DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
499 DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
500 DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
501 DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
502 DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
503 DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4,
504 CLK_SET_RATE_PARENT, 0),
505 DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
506 DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
507 DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
508 DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
509 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
510 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
511 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
512 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
513 DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
514 DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
515 DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
516 DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
517 DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
518 DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
519 DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
520 DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
521 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
522 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
523 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
524 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8),
525 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
526 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
527 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
528 DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
529 DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
530 DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
531 DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
532 DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
533 DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
534 DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
535 DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
536 DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
537 DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
538 DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"),
539 DIV_A(sclk_apll, "sclk_apll", "mout_apll",
540 DIV_CPU0, 24, 3, "sclk_apll"),
541 DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
542 CLK_SET_RATE_PARENT, 0),
543 DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
544 CLK_SET_RATE_PARENT, 0),
545 DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
546 CLK_SET_RATE_PARENT, 0),
547 DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
548 CLK_SET_RATE_PARENT, 0),
549 DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
550 CLK_SET_RATE_PARENT, 0),
551};
552
553/* list of divider clocks supported in exynos4210 soc */
554struct samsung_div_clock exynos4210_div_clks[] __initdata = {
555 DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
556 DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
557 DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
558 DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
559 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
560 DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
561 CLK_SET_RATE_PARENT, 0),
562};
563
564/* list of divider clocks supported in exynos4x12 soc */
565struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
566 DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
567 DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
568 DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
569 DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
570 DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
571 DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
572 DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
573 DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
574 DIV_TOP, 24, 3),
575 DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
576 DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
577 DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
578 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
579 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
580 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
581 DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
582 DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
583 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
584 DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
585 DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
586};
587
588/* list of gate clocks supported in all exynos4 soc's */
589struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
590 /*
591 * After all Exynos4 based platforms are migrated to use device tree,
592 * the device name and clock alias names specified below for some
593 * of the clocks can be removed.
594 */
595 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
596 GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0),
597 GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
598 GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
599 GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
600 GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
601 GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
602 GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
603 GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0),
604 GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
605 GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
606 GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
607 CLK_SET_RATE_PARENT, 0),
608 GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
609 GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
610 GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
611 GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
612 GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
613 GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
614 GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
615 CLK_SET_RATE_PARENT, 0),
616 GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
617 CLK_SET_RATE_PARENT, 0),
618 GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0",
619 SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
620 GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
621 CLK_SET_RATE_PARENT, 0),
622 GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
623 CLK_SET_RATE_PARENT, 0),
624 GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
625 GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
626 GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
627 GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"),
628 GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"),
629 GATE_A(usb_host, "usb_host", "aclk133",
630 GATE_IP_FSYS, 12, 0, 0, "usbhost"),
631 GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0",
632 SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
633 GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1",
634 SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
635 GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2",
636 SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
637 GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3",
638 SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"),
639 GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0",
640 SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
641 GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1",
642 SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"),
643 GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0",
644 SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
645 GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0",
646 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0,
647 "mmc_busclk.2"),
648 GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1",
649 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0,
650 "mmc_busclk.2"),
651 GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2",
652 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0,
653 "mmc_busclk.2"),
654 GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3",
655 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0,
656 "mmc_busclk.2"),
657 GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4",
658 SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"),
659 GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0",
660 SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT,
661 0, "clk_uart_baud0"),
662 GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1",
663 SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT,
664 0, "clk_uart_baud0"),
665 GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2",
666 SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT,
667 0, "clk_uart_baud0"),
668 GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3",
669 SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT,
670 0, "clk_uart_baud0"),
671 GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4",
672 SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT,
673 0, "clk_uart_baud0"),
674 GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
675 CLK_SET_RATE_PARENT, 0),
676 GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0",
677 SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT,
678 0, "spi_busclk0"),
679 GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1",
680 SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT,
681 0, "spi_busclk0"),
682 GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2",
683 SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT,
684 0, "spi_busclk0"),
685 GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160",
686 GATE_IP_CAM, 0, 0, 0, "fimc"),
687 GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",
688 GATE_IP_CAM, 1, 0, 0, "fimc"),
689 GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160",
690 GATE_IP_CAM, 2, 0, 0, "fimc"),
691 GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160",
692 GATE_IP_CAM, 3, 0, 0, "fimc"),
693 GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160",
694 GATE_IP_CAM, 4, 0, 0, "fimc"),
695 GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160",
696 GATE_IP_CAM, 5, 0, 0, "fimc"),
697 GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160",
698 GATE_IP_CAM, 7, 0, 0, "sysmmu"),
699 GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160",
700 GATE_IP_CAM, 8, 0, 0, "sysmmu"),
701 GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160",
702 GATE_IP_CAM, 9, 0, 0, "sysmmu"),
703 GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160",
704 GATE_IP_CAM, 10, 0, 0, "sysmmu"),
705 GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160",
706 GATE_IP_CAM, 11, 0, 0, "sysmmu"),
707 GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
708 GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
709 GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160",
710 GATE_IP_TV, 4, 0, 0, "sysmmu"),
711 GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"),
712 GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100",
713 GATE_IP_MFC, 1, 0, 0, "sysmmu"),
714 GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100",
715 GATE_IP_MFC, 2, 0, 0, "sysmmu"),
716 GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160",
717 GATE_IP_LCD0, 0, 0, 0, "fimd"),
718 GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160",
719 GATE_IP_LCD0, 4, 0, 0, "sysmmu"),
720 GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133",
721 GATE_IP_FSYS, 0, 0, 0, "dma"),
722 GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133",
723 GATE_IP_FSYS, 1, 0, 0, "dma"),
724 GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133",
725 GATE_IP_FSYS, 5, 0, 0, "hsmmc"),
726 GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133",
727 GATE_IP_FSYS, 6, 0, 0, "hsmmc"),
728 GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133",
729 GATE_IP_FSYS, 7, 0, 0, "hsmmc"),
730 GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133",
731 GATE_IP_FSYS, 8, 0, 0, "hsmmc"),
732 GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100",
733 GATE_IP_PERIL, 0, 0, 0, "uart"),
734 GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100",
735 GATE_IP_PERIL, 1, 0, 0, "uart"),
736 GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100",
737 GATE_IP_PERIL, 2, 0, 0, "uart"),
738 GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100",
739 GATE_IP_PERIL, 3, 0, 0, "uart"),
740 GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100",
741 GATE_IP_PERIL, 4, 0, 0, "uart"),
742 GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100",
743 GATE_IP_PERIL, 6, 0, 0, "i2c"),
744 GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100",
745 GATE_IP_PERIL, 7, 0, 0, "i2c"),
746 GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100",
747 GATE_IP_PERIL, 8, 0, 0, "i2c"),
748 GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100",
749 GATE_IP_PERIL, 9, 0, 0, "i2c"),
750 GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100",
751 GATE_IP_PERIL, 10, 0, 0, "i2c"),
752 GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100",
753 GATE_IP_PERIL, 11, 0, 0, "i2c"),
754 GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100",
755 GATE_IP_PERIL, 12, 0, 0, "i2c"),
756 GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100",
757 GATE_IP_PERIL, 13, 0, 0, "i2c"),
758 GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100",
759 GATE_IP_PERIL, 14, 0, 0, "i2c"),
760 GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100",
761 GATE_IP_PERIL, 16, 0, 0, "spi"),
762 GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100",
763 GATE_IP_PERIL, 17, 0, 0, "spi"),
764 GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100",
765 GATE_IP_PERIL, 18, 0, 0, "spi"),
766 GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100",
767 GATE_IP_PERIL, 20, 0, 0, "iis"),
768 GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100",
769 GATE_IP_PERIL, 21, 0, 0, "iis"),
770 GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100",
771 GATE_IP_PERIL, 22, 0, 0, "pcm"),
772 GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100",
773 GATE_IP_PERIL, 23, 0, 0, "pcm"),
774 GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100",
775 GATE_IP_PERIL, 26, 0, 0, "spdif"),
776 GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100",
777 GATE_IP_PERIL, 27, 0, 0, "ac97"),
778};
779
780/* list of gate clocks supported in exynos4210 soc */
781struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
782 GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
783 GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
784 GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
785 GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
786 GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
787 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0),
788 GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
789 GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
790 GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
791 GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
792 GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
793 GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
794 GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
795 GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
796 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
797 GATE(smmu_rotator, "smmu_rotator", "aclk200",
798 E4210_GATE_IP_IMAGE, 4, 0, 0),
799 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1",
800 E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
801 GATE(sclk_sata, "sclk_sata", "div_sata",
802 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
803 GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
804 GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
805 GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"),
806 GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"),
807 GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
808 GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"),
809 GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"),
810 GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1",
811 E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"),
812};
813
814/* list of gate clocks supported in exynos4x12 soc */
815struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
816 GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
817 GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
818 GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
819 GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
820 GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
821 GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
822 GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
823 GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
824 GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
825 GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
826 SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
827 GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
828 SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
829 GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi",
830 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
831 GATE(smmu_rotator, "smmu_rotator", "aclk200",
832 E4X12_GATE_IP_IMAGE, 4, 0, 0),
833 GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"),
834 GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"),
835 GATE_A(keyif, "keyif", "aclk100",
836 E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"),
837 GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp",
838 E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
839 GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",
840 E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
841 GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre",
842 E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
843 GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp",
844 E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
845 GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp",
846 E4X12_GATE_IP_ISP, 0, 0, 0),
847 GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp",
848 E4X12_GATE_IP_ISP, 1, 0, 0),
849 GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp",
850 E4X12_GATE_IP_ISP, 2, 0, 0),
851 GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp",
852 E4X12_GATE_IP_ISP, 3, 0, 0),
853 GATE_A(wdt, "watchdog", "aclk100",
854 E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"),
855 GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100",
856 E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"),
857 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100",
858 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"),
859 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0,
860 CLK_IGNORE_UNUSED, 0),
861 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1,
862 CLK_IGNORE_UNUSED, 0),
863 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2,
864 CLK_IGNORE_UNUSED, 0),
865 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
866 CLK_IGNORE_UNUSED, 0),
867 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
868 CLK_IGNORE_UNUSED, 0),
869 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
870 CLK_IGNORE_UNUSED, 0),
871 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
872 CLK_IGNORE_UNUSED, 0),
873 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
874 CLK_IGNORE_UNUSED, 0),
875 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
876 CLK_IGNORE_UNUSED, 0),
877 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
878 CLK_IGNORE_UNUSED, 0),
879 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
880 CLK_IGNORE_UNUSED, 0),
881 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
882 CLK_IGNORE_UNUSED, 0),
883 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
884 CLK_IGNORE_UNUSED, 0),
885 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
886 CLK_IGNORE_UNUSED, 0),
887 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
888 CLK_IGNORE_UNUSED, 0),
889 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
890 CLK_IGNORE_UNUSED, 0),
891 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
892 CLK_IGNORE_UNUSED, 0),
893 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
894 CLK_IGNORE_UNUSED, 0),
895 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
896 CLK_IGNORE_UNUSED, 0),
897 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
898 CLK_IGNORE_UNUSED, 0),
899 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
900 CLK_IGNORE_UNUSED, 0),
901 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
902 CLK_IGNORE_UNUSED, 0),
903 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
904 CLK_IGNORE_UNUSED, 0),
905 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
906 CLK_IGNORE_UNUSED, 0),
907 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
908 CLK_IGNORE_UNUSED, 0),
909 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
910 CLK_IGNORE_UNUSED, 0),
911};
912
913#ifdef CONFIG_OF
914static struct of_device_id exynos4_clk_ids[] __initdata = {
915 { .compatible = "samsung,exynos4210-clock",
916 .data = (void *)EXYNOS4210, },
917 { .compatible = "samsung,exynos4412-clock",
918 .data = (void *)EXYNOS4X12, },
919 { },
920};
921#endif
922
923/*
924 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
925 * resides in chipid register space, outside of the clock controller memory
926 * mapped space. So to determine the parent of fin_pll clock, the chipid
927 * controller is first remapped and the value of XOM[0] bit is read to
928 * determine the parent clock.
929 */
930static void __init exynos4_clk_register_finpll(void)
931{
932 struct samsung_fixed_rate_clock fclk;
933 struct device_node *np;
934 struct clk *clk;
935 void __iomem *chipid_base = S5P_VA_CHIPID;
936 unsigned long xom, finpll_f = 24000000;
937 char *parent_name;
938
939 np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
940 if (np)
941 chipid_base = of_iomap(np, 0);
942
943 if (chipid_base) {
944 xom = readl(chipid_base + 8);
945 parent_name = xom & 1 ? "xusbxti" : "xxti";
946 clk = clk_get(NULL, parent_name);
947 if (IS_ERR(clk)) {
948 pr_err("%s: failed to lookup parent clock %s, assuming "
949 "fin_pll clock frequency is 24MHz\n", __func__,
950 parent_name);
951 } else {
952 finpll_f = clk_get_rate(clk);
953 }
954 } else {
955 pr_err("%s: failed to map chipid registers, assuming "
956 "fin_pll clock frequency is 24MHz\n", __func__);
957 }
958
959 fclk.id = fin_pll;
960 fclk.name = "fin_pll";
961 fclk.parent_name = NULL;
962 fclk.flags = CLK_IS_ROOT;
963 fclk.fixed_rate = finpll_f;
964 samsung_clk_register_fixed_rate(&fclk, 1);
965
966 if (np)
967 iounmap(chipid_base);
968}
969
970/*
971 * This function allows non-dt platforms to specify the clock speed of the
972 * xxti and xusbxti clocks. These clocks are then registered with the specified
973 * clock speed.
974 */
975void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f,
976 unsigned long xusbxti_f)
977{
978 exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f;
979 exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f;
980 samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks,
981 ARRAY_SIZE(exynos4_fixed_rate_ext_clks));
982}
983
984static __initdata struct of_device_id ext_clk_match[] = {
985 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
986 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
987 {},
988};
989
990/* register exynos4 clocks */
991void __init exynos4_clk_init(struct device_node *np)
992{
993 void __iomem *reg_base;
994 struct clk *apll, *mpll, *epll, *vpll;
995 u32 exynos4_soc;
996
997 if (np) {
998 const struct of_device_id *match;
999 match = of_match_node(exynos4_clk_ids, np);
1000 exynos4_soc = (u32)match->data;
1001
1002 reg_base = of_iomap(np, 0);
1003 if (!reg_base)
1004 panic("%s: failed to map registers\n", __func__);
1005 } else {
1006 reg_base = S5P_VA_CMU;
1007 if (soc_is_exynos4210())
1008 exynos4_soc = EXYNOS4210;
1009 else if (soc_is_exynos4212() || soc_is_exynos4412())
1010 exynos4_soc = EXYNOS4X12;
1011 else
1012 panic("%s: unable to determine soc\n", __func__);
1013 }
1014
1015 if (exynos4_soc == EXYNOS4210)
1016 samsung_clk_init(np, reg_base, nr_clks,
1017 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1018 exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save));
1019 else
1020 samsung_clk_init(np, reg_base, nr_clks,
1021 exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs),
1022 exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save));
1023
1024 if (np)
1025 samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks,
1026 ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1027 ext_clk_match);
1028
1029 exynos4_clk_register_finpll();
1030
1031 if (exynos4_soc == EXYNOS4210) {
1032 apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
1033 reg_base + APLL_CON0, pll_4508);
1034 mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll",
1035 reg_base + E4210_MPLL_CON0, pll_4508);
1036 epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
1037 reg_base + EPLL_CON0, pll_4600);
1038 vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
1039 reg_base + VPLL_CON0, pll_4650c);
1040 } else {
1041 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
1042 reg_base + APLL_CON0);
1043 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
1044 reg_base + E4X12_MPLL_CON0);
1045 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
1046 reg_base + EPLL_CON0);
1047 vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll",
1048 reg_base + VPLL_CON0);
1049 }
1050
1051 samsung_clk_add_lookup(apll, fout_apll);
1052 samsung_clk_add_lookup(mpll, fout_mpll);
1053 samsung_clk_add_lookup(epll, fout_epll);
1054 samsung_clk_add_lookup(vpll, fout_vpll);
1055
1056 samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks,
1057 ARRAY_SIZE(exynos4_fixed_rate_clks));
1058 samsung_clk_register_mux(exynos4_mux_clks,
1059 ARRAY_SIZE(exynos4_mux_clks));
1060 samsung_clk_register_div(exynos4_div_clks,
1061 ARRAY_SIZE(exynos4_div_clks));
1062 samsung_clk_register_gate(exynos4_gate_clks,
1063 ARRAY_SIZE(exynos4_gate_clks));
1064
1065 if (exynos4_soc == EXYNOS4210) {
1066 samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks,
1067 ARRAY_SIZE(exynos4210_fixed_rate_clks));
1068 samsung_clk_register_mux(exynos4210_mux_clks,
1069 ARRAY_SIZE(exynos4210_mux_clks));
1070 samsung_clk_register_div(exynos4210_div_clks,
1071 ARRAY_SIZE(exynos4210_div_clks));
1072 samsung_clk_register_gate(exynos4210_gate_clks,
1073 ARRAY_SIZE(exynos4210_gate_clks));
1074 } else {
1075 samsung_clk_register_mux(exynos4x12_mux_clks,
1076 ARRAY_SIZE(exynos4x12_mux_clks));
1077 samsung_clk_register_div(exynos4x12_div_clks,
1078 ARRAY_SIZE(exynos4x12_div_clks));
1079 samsung_clk_register_gate(exynos4x12_gate_clks,
1080 ARRAY_SIZE(exynos4x12_gate_clks));
1081 }
1082
1083 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1084 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1085 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1086 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
1087 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1088 _get_rate("arm_clk"));
1089}
1090CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
1091CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
new file mode 100644
index 000000000000..7290faa518d2
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -0,0 +1,523 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5250 SoC.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
19#include <plat/cpu.h>
20#include "clk.h"
21#include "clk-pll.h"
22
23#define SRC_CPU 0x200
24#define DIV_CPU0 0x500
25#define SRC_CORE1 0x4204
26#define SRC_TOP0 0x10210
27#define SRC_TOP2 0x10218
28#define SRC_GSCL 0x10220
29#define SRC_DISP1_0 0x1022c
30#define SRC_MAU 0x10240
31#define SRC_FSYS 0x10244
32#define SRC_GEN 0x10248
33#define SRC_PERIC0 0x10250
34#define SRC_PERIC1 0x10254
35#define SRC_MASK_GSCL 0x10320
36#define SRC_MASK_DISP1_0 0x1032c
37#define SRC_MASK_MAU 0x10334
38#define SRC_MASK_FSYS 0x10340
39#define SRC_MASK_GEN 0x10344
40#define SRC_MASK_PERIC0 0x10350
41#define SRC_MASK_PERIC1 0x10354
42#define DIV_TOP0 0x10510
43#define DIV_TOP1 0x10514
44#define DIV_GSCL 0x10520
45#define DIV_DISP1_0 0x1052c
46#define DIV_GEN 0x1053c
47#define DIV_MAU 0x10544
48#define DIV_FSYS0 0x10548
49#define DIV_FSYS1 0x1054c
50#define DIV_FSYS2 0x10550
51#define DIV_PERIC0 0x10558
52#define DIV_PERIC1 0x1055c
53#define DIV_PERIC2 0x10560
54#define DIV_PERIC3 0x10564
55#define DIV_PERIC4 0x10568
56#define DIV_PERIC5 0x1056c
57#define GATE_IP_GSCL 0x10920
58#define GATE_IP_MFC 0x1092c
59#define GATE_IP_GEN 0x10934
60#define GATE_IP_FSYS 0x10944
61#define GATE_IP_PERIC 0x10950
62#define GATE_IP_PERIS 0x10960
63#define SRC_CDREX 0x20200
64#define PLL_DIV2_SEL 0x20a24
65#define GATE_IP_DISP1 0x10928
66
67/*
68 * Let each supported clock get a unique id. This id is used to lookup the clock
69 * for device tree based platforms. The clocks are categorized into three
70 * sections: core, sclk gate and bus interface gate clocks.
71 *
72 * When adding a new clock to this list, it is advised to choose a clock
73 * category and add it to the end of that category. That is because the the
74 * device tree source file is referring to these ids and any change in the
75 * sequence number of existing clocks will require corresponding change in the
76 * device tree files. This limitation would go away when pre-processor support
77 * for dtc would be available.
78 */
79enum exynos5250_clks {
80 none,
81
82 /* core clocks */
83 fin_pll,
84
85 /* gate for special clocks (sclk) */
86 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
87 sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
88 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
89 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
90 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
91
92 /* gate clocks */
93 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
94 smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
95 jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
96 usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
97 sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
98 i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
99 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
100 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
101 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
102 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi,
103
104 nr_clks,
105};
106
107/*
108 * list of controller registers to be saved and restored during a
109 * suspend/resume cycle.
110 */
111static __initdata unsigned long exynos5250_clk_regs[] = {
112 SRC_CPU,
113 DIV_CPU0,
114 SRC_CORE1,
115 SRC_TOP0,
116 SRC_TOP2,
117 SRC_GSCL,
118 SRC_DISP1_0,
119 SRC_MAU,
120 SRC_FSYS,
121 SRC_GEN,
122 SRC_PERIC0,
123 SRC_PERIC1,
124 SRC_MASK_GSCL,
125 SRC_MASK_DISP1_0,
126 SRC_MASK_MAU,
127 SRC_MASK_FSYS,
128 SRC_MASK_GEN,
129 SRC_MASK_PERIC0,
130 SRC_MASK_PERIC1,
131 DIV_TOP0,
132 DIV_TOP1,
133 DIV_GSCL,
134 DIV_DISP1_0,
135 DIV_GEN,
136 DIV_MAU,
137 DIV_FSYS0,
138 DIV_FSYS1,
139 DIV_FSYS2,
140 DIV_PERIC0,
141 DIV_PERIC1,
142 DIV_PERIC2,
143 DIV_PERIC3,
144 DIV_PERIC4,
145 DIV_PERIC5,
146 GATE_IP_GSCL,
147 GATE_IP_MFC,
148 GATE_IP_GEN,
149 GATE_IP_FSYS,
150 GATE_IP_PERIC,
151 GATE_IP_PERIS,
152 SRC_CDREX,
153 PLL_DIV2_SEL,
154 GATE_IP_DISP1,
155};
156
157/* list of all parent clock list */
158PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
159PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
160PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
161PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
162PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
163PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
164PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
165PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
166PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
167PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
168PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
169PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
170PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" };
171PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" };
172PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
173PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
174PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
175 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
176 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
177 "sclk_cpll" };
178PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
179 "sclk_uhostphy", "sclk_hdmiphy",
180 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
181 "sclk_cpll" };
182PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
183 "sclk_uhostphy", "sclk_hdmiphy",
184 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
185 "sclk_cpll" };
186PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
187 "sclk_uhostphy", "sclk_hdmiphy",
188 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
189 "sclk_cpll" };
190PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
191 "spdif_extclk" };
192
193/* fixed rate clocks generated outside the soc */
194struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
195 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
196};
197
198/* fixed rate clocks generated inside the soc */
199struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
200 FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
201 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
202 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
203 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
204};
205
206struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
207 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
208 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
209};
210
211struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
212 MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
213 MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
214 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
215 MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
216 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
217 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
218 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
219 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
220 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
221 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
222 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
223 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
224 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
225 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
226 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
227 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
228 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
229 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
230 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
231 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
232 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
233 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
234 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
235 MUX(none, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
236 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
237 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
238 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
239 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
240 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
241 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
242 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
243 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
244 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
245 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
246 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
247 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
248 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
249 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
250 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
251 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
252 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
253 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
254 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
255};
256
257struct samsung_div_clock exynos5250_div_clks[] __initdata = {
258 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
259 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
260 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
261 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
262 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
263 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
264 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
265 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
266 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
267 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
268 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
269 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
270 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
271 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
272 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
273 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
274 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
275 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
276 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
277 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
278 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
279 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 8, 8),
280 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 24, 8),
281 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 8, 8),
282 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 24, 8),
283 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
284 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
285 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
286 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
287 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
288 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
289 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
290 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
291 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
292 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
293 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
294 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
295 DIV(none, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
296 DIV(none, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
297 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
298 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
299 DIV_F(none, "div_mipi1_pre", "div_mipi1",
300 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
301 DIV_F(none, "div_mmc_pre0", "div_mmc0",
302 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
303 DIV_F(none, "div_mmc_pre1", "div_mmc1",
304 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
305 DIV_F(none, "div_mmc_pre2", "div_mmc2",
306 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
307 DIV_F(none, "div_mmc_pre3", "div_mmc3",
308 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
309 DIV_F(none, "div_spi_pre0", "div_spi0",
310 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
311 DIV_F(none, "div_spi_pre1", "div_spi1",
312 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
313 DIV_F(none, "div_spi_pre2", "div_spi2",
314 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
315};
316
317struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
318 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
319 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
320 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
321 GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
322 GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
323 GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
324 GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
325 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
326 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
327 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
328 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
329 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0),
330 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),
331 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
332 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
333 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
334 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
335 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
336 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
337 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
338 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
339 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
340 GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
341 GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
342 GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
343 GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
344 GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
345 GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
346 GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
347 GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
348 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
349 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
350 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
351 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
352 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
353 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
354 GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
355 GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
356 GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
357 GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
358 GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
359 GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
360 GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
361 GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
362 GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
363 GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
364 GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
365 GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
366 GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
367 GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
368 GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
369 GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
370 GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
371 GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
372 GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
373 GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
374 GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
375 GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
376 GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
377 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
378 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
379 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
380 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
381 GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0),
382 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, 0, 0),
383 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
384 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
385 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
386 GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
387 GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
388 GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
389 GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
390 GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
391 GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
392 GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
393 GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
394 GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
395 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
396 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
397 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
398 GATE(cmu_top, "cmu_top", "aclk66",
399 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
400 GATE(cmu_core, "cmu_core", "aclk66",
401 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
402 GATE(cmu_mem, "cmu_mem", "aclk66",
403 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
404 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
405 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
406 GATE(sclk_cam0, "sclk_cam0", "div_cam0",
407 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
408 GATE(sclk_cam1, "sclk_cam1", "div_cam1",
409 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
410 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
411 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
412 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
413 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
414 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
415 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
416 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
417 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
418 GATE(sclk_dp, "sclk_dp", "div_dp",
419 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
420 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
421 SRC_MASK_DISP1_0, 20, 0, 0),
422 GATE(sclk_audio0, "sclk_audio0", "div_audio0",
423 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
424 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc0",
425 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
426 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc1",
427 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
428 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc2",
429 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
430 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc3",
431 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
432 GATE(sclk_sata, "sclk_sata", "div_sata",
433 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
434 GATE(sclk_usb3, "sclk_usb3", "div_usb3",
435 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
436 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
437 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
438 GATE(sclk_uart0, "sclk_uart0", "div_uart0",
439 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
440 GATE(sclk_uart1, "sclk_uart1", "div_uart1",
441 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
442 GATE(sclk_uart2, "sclk_uart2", "div_uart2",
443 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
444 GATE(sclk_uart3, "sclk_uart3", "div_uart3",
445 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
446 GATE(sclk_pwm, "sclk_pwm", "div_pwm",
447 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
448 GATE(sclk_audio1, "sclk_audio1", "div_audio1",
449 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
450 GATE(sclk_audio2, "sclk_audio2", "div_audio2",
451 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
452 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
453 SRC_MASK_PERIC1, 4, 0, 0),
454 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
455 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
457 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
458 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
459 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
460 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
461 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
462 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
463 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
464 GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
465 GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
466};
467
468static __initdata struct of_device_id ext_clk_match[] = {
469 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
470 { },
471};
472
473/* register exynox5250 clocks */
474void __init exynos5250_clk_init(struct device_node *np)
475{
476 void __iomem *reg_base;
477 struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll;
478
479 if (np) {
480 reg_base = of_iomap(np, 0);
481 if (!reg_base)
482 panic("%s: failed to map registers\n", __func__);
483 } else {
484 panic("%s: unable to determine soc\n", __func__);
485 }
486
487 samsung_clk_init(np, reg_base, nr_clks,
488 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
489 NULL, 0);
490 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
491 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
492 ext_clk_match);
493
494 apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll",
495 reg_base + 0x100);
496 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",
497 reg_base + 0x4100);
498 bpll = samsung_clk_register_pll35xx("fout_bpll", "fin_pll",
499 reg_base + 0x20110);
500 gpll = samsung_clk_register_pll35xx("fout_gpll", "fin_pll",
501 reg_base + 0x10150);
502 cpll = samsung_clk_register_pll35xx("fout_cpll", "fin_pll",
503 reg_base + 0x10120);
504 epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll",
505 reg_base + 0x10130);
506 vpll = samsung_clk_register_pll36xx("fout_vpll", "mout_vpllsrc",
507 reg_base + 0x10140);
508
509 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
510 ARRAY_SIZE(exynos5250_fixed_rate_clks));
511 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
512 ARRAY_SIZE(exynos5250_fixed_factor_clks));
513 samsung_clk_register_mux(exynos5250_mux_clks,
514 ARRAY_SIZE(exynos5250_mux_clks));
515 samsung_clk_register_div(exynos5250_div_clks,
516 ARRAY_SIZE(exynos5250_div_clks));
517 samsung_clk_register_gate(exynos5250_gate_clks,
518 ARRAY_SIZE(exynos5250_gate_clks));
519
520 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
521 _get_rate("armclk"));
522}
523CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
new file mode 100644
index 000000000000..a0a094c06f19
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -0,0 +1,139 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Thomas Abraham <thomas.ab@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5440 SoC.
10*/
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17
18#include <plat/cpu.h>
19#include "clk.h"
20#include "clk-pll.h"
21
22#define CLKEN_OV_VAL 0xf8
23#define CPU_CLK_STATUS 0xfc
24#define MISC_DOUT1 0x558
25
26/*
27 * Let each supported clock get a unique id. This id is used to lookup the clock
28 * for device tree based platforms.
29 */
30enum exynos5440_clks {
31 none, xtal, arm_clk,
32
33 spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata,
34 usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o,
35 b_200_o, sata_o, usb_o, gmac0_o, cs250_o,
36
37 nr_clks,
38};
39
40/* parent clock name list */
41PNAME(mout_armclk_p) = { "cplla", "cpllb" };
42PNAME(mout_spi_p) = { "div125", "div200" };
43
44/* fixed rate clocks generated outside the soc */
45struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = {
46 FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0),
47};
48
49/* fixed rate clocks */
50struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = {
51 FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000),
52 FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000),
53 FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000),
54 FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000),
55 FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000),
56};
57
58/* fixed factor clocks */
59struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = {
60 FFACTOR(none, "div250", "ppll", 1, 4, 0),
61 FFACTOR(none, "div200", "ppll", 1, 5, 0),
62 FFACTOR(none, "div125", "div250", 1, 2, 0),
63};
64
65/* mux clocks */
66struct samsung_mux_clock exynos5440_mux_clks[] __initdata = {
67 MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
68 MUX_A(arm_clk, "arm_clk", mout_armclk_p,
69 CPU_CLK_STATUS, 0, 1, "armclk"),
70};
71
72/* divider clocks */
73struct samsung_div_clock exynos5440_div_clks[] __initdata = {
74 DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2),
75};
76
77/* gate clocks */
78struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
79 GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
80 GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
81 GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
82 GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
83 GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
84 GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
85 GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
86 GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
87 GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
88 GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
89 GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0),
90 GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0),
91 GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0),
92 GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0),
93 GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0),
94 GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0),
95 GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0),
96 GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0),
97 GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0),
98 GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
99};
100
101static __initdata struct of_device_id ext_clk_match[] = {
102 { .compatible = "samsung,clock-xtal", .data = (void *)0, },
103 {},
104};
105
106/* register exynos5440 clocks */
107void __init exynos5440_clk_init(struct device_node *np)
108{
109 void __iomem *reg_base;
110
111 reg_base = of_iomap(np, 0);
112 if (!reg_base) {
113 pr_err("%s: failed to map clock controller registers,"
114 " aborting clock initialization\n", __func__);
115 return;
116 }
117
118 samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0);
119 samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks,
120 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);
121
122 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
123 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);
124
125 samsung_clk_register_fixed_rate(exynos5440_fixed_rate_clks,
126 ARRAY_SIZE(exynos5440_fixed_rate_clks));
127 samsung_clk_register_fixed_factor(exynos5440_fixed_factor_clks,
128 ARRAY_SIZE(exynos5440_fixed_factor_clks));
129 samsung_clk_register_mux(exynos5440_mux_clks,
130 ARRAY_SIZE(exynos5440_mux_clks));
131 samsung_clk_register_div(exynos5440_div_clks,
132 ARRAY_SIZE(exynos5440_div_clks));
133 samsung_clk_register_gate(exynos5440_gate_clks,
134 ARRAY_SIZE(exynos5440_gate_clks));
135
136 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("armclk"));
137 pr_info("exynos5440 clock initialization complete\n");
138}
139CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
new file mode 100644
index 000000000000..89135f6be116
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.c
@@ -0,0 +1,419 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This file contains the utility functions to register the pll clocks.
10*/
11
12#include <linux/errno.h>
13#include "clk.h"
14#include "clk-pll.h"
15
16/*
17 * PLL35xx Clock Type
18 */
19
20#define PLL35XX_MDIV_MASK (0x3FF)
21#define PLL35XX_PDIV_MASK (0x3F)
22#define PLL35XX_SDIV_MASK (0x7)
23#define PLL35XX_MDIV_SHIFT (16)
24#define PLL35XX_PDIV_SHIFT (8)
25#define PLL35XX_SDIV_SHIFT (0)
26
27struct samsung_clk_pll35xx {
28 struct clk_hw hw;
29 const void __iomem *con_reg;
30};
31
32#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
33
34static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate)
36{
37 struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
38 u32 mdiv, pdiv, sdiv, pll_con;
39 u64 fvco = parent_rate;
40
41 pll_con = __raw_readl(pll->con_reg);
42 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
43 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
44 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
45
46 fvco *= mdiv;
47 do_div(fvco, (pdiv << sdiv));
48
49 return (unsigned long)fvco;
50}
51
52static const struct clk_ops samsung_pll35xx_clk_ops = {
53 .recalc_rate = samsung_pll35xx_recalc_rate,
54};
55
56struct clk * __init samsung_clk_register_pll35xx(const char *name,
57 const char *pname, const void __iomem *con_reg)
58{
59 struct samsung_clk_pll35xx *pll;
60 struct clk *clk;
61 struct clk_init_data init;
62
63 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
64 if (!pll) {
65 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
66 return NULL;
67 }
68
69 init.name = name;
70 init.ops = &samsung_pll35xx_clk_ops;
71 init.flags = CLK_GET_RATE_NOCACHE;
72 init.parent_names = &pname;
73 init.num_parents = 1;
74
75 pll->hw.init = &init;
76 pll->con_reg = con_reg;
77
78 clk = clk_register(NULL, &pll->hw);
79 if (IS_ERR(clk)) {
80 pr_err("%s: failed to register pll clock %s\n", __func__,
81 name);
82 kfree(pll);
83 }
84
85 if (clk_register_clkdev(clk, name, NULL))
86 pr_err("%s: failed to register lookup for %s", __func__, name);
87
88 return clk;
89}
90
91/*
92 * PLL36xx Clock Type
93 */
94
95#define PLL36XX_KDIV_MASK (0xFFFF)
96#define PLL36XX_MDIV_MASK (0x1FF)
97#define PLL36XX_PDIV_MASK (0x3F)
98#define PLL36XX_SDIV_MASK (0x7)
99#define PLL36XX_MDIV_SHIFT (16)
100#define PLL36XX_PDIV_SHIFT (8)
101#define PLL36XX_SDIV_SHIFT (0)
102
103struct samsung_clk_pll36xx {
104 struct clk_hw hw;
105 const void __iomem *con_reg;
106};
107
108#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
109
110static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
111 unsigned long parent_rate)
112{
113 struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
114 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
115 u64 fvco = parent_rate;
116
117 pll_con0 = __raw_readl(pll->con_reg);
118 pll_con1 = __raw_readl(pll->con_reg + 4);
119 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
120 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
121 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
122 kdiv = pll_con1 & PLL36XX_KDIV_MASK;
123
124 fvco *= (mdiv << 16) + kdiv;
125 do_div(fvco, (pdiv << sdiv));
126 fvco >>= 16;
127
128 return (unsigned long)fvco;
129}
130
131static const struct clk_ops samsung_pll36xx_clk_ops = {
132 .recalc_rate = samsung_pll36xx_recalc_rate,
133};
134
135struct clk * __init samsung_clk_register_pll36xx(const char *name,
136 const char *pname, const void __iomem *con_reg)
137{
138 struct samsung_clk_pll36xx *pll;
139 struct clk *clk;
140 struct clk_init_data init;
141
142 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
143 if (!pll) {
144 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
145 return NULL;
146 }
147
148 init.name = name;
149 init.ops = &samsung_pll36xx_clk_ops;
150 init.flags = CLK_GET_RATE_NOCACHE;
151 init.parent_names = &pname;
152 init.num_parents = 1;
153
154 pll->hw.init = &init;
155 pll->con_reg = con_reg;
156
157 clk = clk_register(NULL, &pll->hw);
158 if (IS_ERR(clk)) {
159 pr_err("%s: failed to register pll clock %s\n", __func__,
160 name);
161 kfree(pll);
162 }
163
164 if (clk_register_clkdev(clk, name, NULL))
165 pr_err("%s: failed to register lookup for %s", __func__, name);
166
167 return clk;
168}
169
170/*
171 * PLL45xx Clock Type
172 */
173
174#define PLL45XX_MDIV_MASK (0x3FF)
175#define PLL45XX_PDIV_MASK (0x3F)
176#define PLL45XX_SDIV_MASK (0x7)
177#define PLL45XX_MDIV_SHIFT (16)
178#define PLL45XX_PDIV_SHIFT (8)
179#define PLL45XX_SDIV_SHIFT (0)
180
181struct samsung_clk_pll45xx {
182 struct clk_hw hw;
183 enum pll45xx_type type;
184 const void __iomem *con_reg;
185};
186
187#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
188
189static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
190 unsigned long parent_rate)
191{
192 struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
193 u32 mdiv, pdiv, sdiv, pll_con;
194 u64 fvco = parent_rate;
195
196 pll_con = __raw_readl(pll->con_reg);
197 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
198 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
199 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
200
201 if (pll->type == pll_4508)
202 sdiv = sdiv - 1;
203
204 fvco *= mdiv;
205 do_div(fvco, (pdiv << sdiv));
206
207 return (unsigned long)fvco;
208}
209
210static const struct clk_ops samsung_pll45xx_clk_ops = {
211 .recalc_rate = samsung_pll45xx_recalc_rate,
212};
213
214struct clk * __init samsung_clk_register_pll45xx(const char *name,
215 const char *pname, const void __iomem *con_reg,
216 enum pll45xx_type type)
217{
218 struct samsung_clk_pll45xx *pll;
219 struct clk *clk;
220 struct clk_init_data init;
221
222 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
223 if (!pll) {
224 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
225 return NULL;
226 }
227
228 init.name = name;
229 init.ops = &samsung_pll45xx_clk_ops;
230 init.flags = CLK_GET_RATE_NOCACHE;
231 init.parent_names = &pname;
232 init.num_parents = 1;
233
234 pll->hw.init = &init;
235 pll->con_reg = con_reg;
236 pll->type = type;
237
238 clk = clk_register(NULL, &pll->hw);
239 if (IS_ERR(clk)) {
240 pr_err("%s: failed to register pll clock %s\n", __func__,
241 name);
242 kfree(pll);
243 }
244
245 if (clk_register_clkdev(clk, name, NULL))
246 pr_err("%s: failed to register lookup for %s", __func__, name);
247
248 return clk;
249}
250
251/*
252 * PLL46xx Clock Type
253 */
254
255#define PLL46XX_MDIV_MASK (0x1FF)
256#define PLL46XX_PDIV_MASK (0x3F)
257#define PLL46XX_SDIV_MASK (0x7)
258#define PLL46XX_MDIV_SHIFT (16)
259#define PLL46XX_PDIV_SHIFT (8)
260#define PLL46XX_SDIV_SHIFT (0)
261
262#define PLL46XX_KDIV_MASK (0xFFFF)
263#define PLL4650C_KDIV_MASK (0xFFF)
264#define PLL46XX_KDIV_SHIFT (0)
265
266struct samsung_clk_pll46xx {
267 struct clk_hw hw;
268 enum pll46xx_type type;
269 const void __iomem *con_reg;
270};
271
272#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
273
274static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
275 unsigned long parent_rate)
276{
277 struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
278 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
279 u64 fvco = parent_rate;
280
281 pll_con0 = __raw_readl(pll->con_reg);
282 pll_con1 = __raw_readl(pll->con_reg + 4);
283 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
284 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
285 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
286 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
287 pll_con1 & PLL46XX_KDIV_MASK;
288
289 shift = pll->type == pll_4600 ? 16 : 10;
290 fvco *= (mdiv << shift) + kdiv;
291 do_div(fvco, (pdiv << sdiv));
292 fvco >>= shift;
293
294 return (unsigned long)fvco;
295}
296
297static const struct clk_ops samsung_pll46xx_clk_ops = {
298 .recalc_rate = samsung_pll46xx_recalc_rate,
299};
300
301struct clk * __init samsung_clk_register_pll46xx(const char *name,
302 const char *pname, const void __iomem *con_reg,
303 enum pll46xx_type type)
304{
305 struct samsung_clk_pll46xx *pll;
306 struct clk *clk;
307 struct clk_init_data init;
308
309 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
310 if (!pll) {
311 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
312 return NULL;
313 }
314
315 init.name = name;
316 init.ops = &samsung_pll46xx_clk_ops;
317 init.flags = CLK_GET_RATE_NOCACHE;
318 init.parent_names = &pname;
319 init.num_parents = 1;
320
321 pll->hw.init = &init;
322 pll->con_reg = con_reg;
323 pll->type = type;
324
325 clk = clk_register(NULL, &pll->hw);
326 if (IS_ERR(clk)) {
327 pr_err("%s: failed to register pll clock %s\n", __func__,
328 name);
329 kfree(pll);
330 }
331
332 if (clk_register_clkdev(clk, name, NULL))
333 pr_err("%s: failed to register lookup for %s", __func__, name);
334
335 return clk;
336}
337
338/*
339 * PLL2550x Clock Type
340 */
341
342#define PLL2550X_R_MASK (0x1)
343#define PLL2550X_P_MASK (0x3F)
344#define PLL2550X_M_MASK (0x3FF)
345#define PLL2550X_S_MASK (0x7)
346#define PLL2550X_R_SHIFT (20)
347#define PLL2550X_P_SHIFT (14)
348#define PLL2550X_M_SHIFT (4)
349#define PLL2550X_S_SHIFT (0)
350
351struct samsung_clk_pll2550x {
352 struct clk_hw hw;
353 const void __iomem *reg_base;
354 unsigned long offset;
355};
356
357#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
358
359static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
360 unsigned long parent_rate)
361{
362 struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
363 u32 r, p, m, s, pll_stat;
364 u64 fvco = parent_rate;
365
366 pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
367 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
368 if (!r)
369 return 0;
370 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
371 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
372 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
373
374 fvco *= m;
375 do_div(fvco, (p << s));
376
377 return (unsigned long)fvco;
378}
379
380static const struct clk_ops samsung_pll2550x_clk_ops = {
381 .recalc_rate = samsung_pll2550x_recalc_rate,
382};
383
384struct clk * __init samsung_clk_register_pll2550x(const char *name,
385 const char *pname, const void __iomem *reg_base,
386 const unsigned long offset)
387{
388 struct samsung_clk_pll2550x *pll;
389 struct clk *clk;
390 struct clk_init_data init;
391
392 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
393 if (!pll) {
394 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
395 return NULL;
396 }
397
398 init.name = name;
399 init.ops = &samsung_pll2550x_clk_ops;
400 init.flags = CLK_GET_RATE_NOCACHE;
401 init.parent_names = &pname;
402 init.num_parents = 1;
403
404 pll->hw.init = &init;
405 pll->reg_base = reg_base;
406 pll->offset = offset;
407
408 clk = clk_register(NULL, &pll->hw);
409 if (IS_ERR(clk)) {
410 pr_err("%s: failed to register pll clock %s\n", __func__,
411 name);
412 kfree(pll);
413 }
414
415 if (clk_register_clkdev(clk, name, NULL))
416 pr_err("%s: failed to register lookup for %s", __func__, name);
417
418 return clk;
419}
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
new file mode 100644
index 000000000000..f33786e9a78b
--- /dev/null
+++ b/drivers/clk/samsung/clk-pll.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for all PLL's in Samsung platforms
10*/
11
12#ifndef __SAMSUNG_CLK_PLL_H
13#define __SAMSUNG_CLK_PLL_H
14
15enum pll45xx_type {
16 pll_4500,
17 pll_4502,
18 pll_4508
19};
20
21enum pll46xx_type {
22 pll_4600,
23 pll_4650,
24 pll_4650c,
25};
26
27extern struct clk * __init samsung_clk_register_pll35xx(const char *name,
28 const char *pname, const void __iomem *con_reg);
29extern struct clk * __init samsung_clk_register_pll36xx(const char *name,
30 const char *pname, const void __iomem *con_reg);
31extern struct clk * __init samsung_clk_register_pll45xx(const char *name,
32 const char *pname, const void __iomem *con_reg,
33 enum pll45xx_type type);
34extern struct clk * __init samsung_clk_register_pll46xx(const char *name,
35 const char *pname, const void __iomem *con_reg,
36 enum pll46xx_type type);
37extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
38 const char *pname, const void __iomem *reg_base,
39 const unsigned long offset);
40
41#endif /* __SAMSUNG_CLK_PLL_H */
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
new file mode 100644
index 000000000000..cd3c40ab50f3
--- /dev/null
+++ b/drivers/clk/samsung/clk.c
@@ -0,0 +1,320 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file includes utility functions to register clocks to common
11 * clock framework for Samsung platforms.
12*/
13
14#include <linux/syscore_ops.h>
15#include "clk.h"
16
17static DEFINE_SPINLOCK(lock);
18static struct clk **clk_table;
19static void __iomem *reg_base;
20#ifdef CONFIG_OF
21static struct clk_onecell_data clk_data;
22#endif
23
24#ifdef CONFIG_PM_SLEEP
25static struct samsung_clk_reg_dump *reg_dump;
26static unsigned long nr_reg_dump;
27
28static int samsung_clk_suspend(void)
29{
30 struct samsung_clk_reg_dump *rd = reg_dump;
31 unsigned long i;
32
33 for (i = 0; i < nr_reg_dump; i++, rd++)
34 rd->value = __raw_readl(reg_base + rd->offset);
35
36 return 0;
37}
38
39static void samsung_clk_resume(void)
40{
41 struct samsung_clk_reg_dump *rd = reg_dump;
42 unsigned long i;
43
44 for (i = 0; i < nr_reg_dump; i++, rd++)
45 __raw_writel(rd->value, reg_base + rd->offset);
46}
47
48static struct syscore_ops samsung_clk_syscore_ops = {
49 .suspend = samsung_clk_suspend,
50 .resume = samsung_clk_resume,
51};
52#endif /* CONFIG_PM_SLEEP */
53
54/* setup the essentials required to support clock lookup using ccf */
55void __init samsung_clk_init(struct device_node *np, void __iomem *base,
56 unsigned long nr_clks, unsigned long *rdump,
57 unsigned long nr_rdump, unsigned long *soc_rdump,
58 unsigned long nr_soc_rdump)
59{
60 reg_base = base;
61
62#ifdef CONFIG_PM_SLEEP
63 if (rdump && nr_rdump) {
64 unsigned int idx;
65 reg_dump = kzalloc(sizeof(struct samsung_clk_reg_dump)
66 * (nr_rdump + nr_soc_rdump), GFP_KERNEL);
67 if (!reg_dump) {
68 pr_err("%s: memory alloc for register dump failed\n",
69 __func__);
70 return;
71 }
72
73 for (idx = 0; idx < nr_rdump; idx++)
74 reg_dump[idx].offset = rdump[idx];
75 for (idx = 0; idx < nr_soc_rdump; idx++)
76 reg_dump[nr_rdump + idx].offset = soc_rdump[idx];
77 nr_reg_dump = nr_rdump + nr_soc_rdump;
78 register_syscore_ops(&samsung_clk_syscore_ops);
79 }
80#endif
81
82 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
83 if (!clk_table)
84 panic("could not allocate clock lookup table\n");
85
86 if (!np)
87 return;
88
89#ifdef CONFIG_OF
90 clk_data.clks = clk_table;
91 clk_data.clk_num = nr_clks;
92 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
93#endif
94}
95
96/* add a clock instance to the clock lookup table used for dt based lookup */
97void samsung_clk_add_lookup(struct clk *clk, unsigned int id)
98{
99 if (clk_table && id)
100 clk_table[id] = clk;
101}
102
103/* register a list of aliases */
104void __init samsung_clk_register_alias(struct samsung_clock_alias *list,
105 unsigned int nr_clk)
106{
107 struct clk *clk;
108 unsigned int idx, ret;
109
110 if (!clk_table) {
111 pr_err("%s: clock table missing\n", __func__);
112 return;
113 }
114
115 for (idx = 0; idx < nr_clk; idx++, list++) {
116 if (!list->id) {
117 pr_err("%s: clock id missing for index %d\n", __func__,
118 idx);
119 continue;
120 }
121
122 clk = clk_table[list->id];
123 if (!clk) {
124 pr_err("%s: failed to find clock %d\n", __func__,
125 list->id);
126 continue;
127 }
128
129 ret = clk_register_clkdev(clk, list->alias, list->dev_name);
130 if (ret)
131 pr_err("%s: failed to register lookup %s\n",
132 __func__, list->alias);
133 }
134}
135
136/* register a list of fixed clocks */
137void __init samsung_clk_register_fixed_rate(
138 struct samsung_fixed_rate_clock *list, unsigned int nr_clk)
139{
140 struct clk *clk;
141 unsigned int idx, ret;
142
143 for (idx = 0; idx < nr_clk; idx++, list++) {
144 clk = clk_register_fixed_rate(NULL, list->name,
145 list->parent_name, list->flags, list->fixed_rate);
146 if (IS_ERR(clk)) {
147 pr_err("%s: failed to register clock %s\n", __func__,
148 list->name);
149 continue;
150 }
151
152 samsung_clk_add_lookup(clk, list->id);
153
154 /*
155 * Unconditionally add a clock lookup for the fixed rate clocks.
156 * There are not many of these on any of Samsung platforms.
157 */
158 ret = clk_register_clkdev(clk, list->name, NULL);
159 if (ret)
160 pr_err("%s: failed to register clock lookup for %s",
161 __func__, list->name);
162 }
163}
164
165/* register a list of fixed factor clocks */
166void __init samsung_clk_register_fixed_factor(
167 struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
168{
169 struct clk *clk;
170 unsigned int idx;
171
172 for (idx = 0; idx < nr_clk; idx++, list++) {
173 clk = clk_register_fixed_factor(NULL, list->name,
174 list->parent_name, list->flags, list->mult, list->div);
175 if (IS_ERR(clk)) {
176 pr_err("%s: failed to register clock %s\n", __func__,
177 list->name);
178 continue;
179 }
180
181 samsung_clk_add_lookup(clk, list->id);
182 }
183}
184
185/* register a list of mux clocks */
186void __init samsung_clk_register_mux(struct samsung_mux_clock *list,
187 unsigned int nr_clk)
188{
189 struct clk *clk;
190 unsigned int idx, ret;
191
192 for (idx = 0; idx < nr_clk; idx++, list++) {
193 clk = clk_register_mux(NULL, list->name, list->parent_names,
194 list->num_parents, list->flags, reg_base + list->offset,
195 list->shift, list->width, list->mux_flags, &lock);
196 if (IS_ERR(clk)) {
197 pr_err("%s: failed to register clock %s\n", __func__,
198 list->name);
199 continue;
200 }
201
202 samsung_clk_add_lookup(clk, list->id);
203
204 /* register a clock lookup only if a clock alias is specified */
205 if (list->alias) {
206 ret = clk_register_clkdev(clk, list->alias,
207 list->dev_name);
208 if (ret)
209 pr_err("%s: failed to register lookup %s\n",
210 __func__, list->alias);
211 }
212 }
213}
214
215/* register a list of div clocks */
216void __init samsung_clk_register_div(struct samsung_div_clock *list,
217 unsigned int nr_clk)
218{
219 struct clk *clk;
220 unsigned int idx, ret;
221
222 for (idx = 0; idx < nr_clk; idx++, list++) {
223 if (list->table)
224 clk = clk_register_divider_table(NULL, list->name,
225 list->parent_name, list->flags,
226 reg_base + list->offset, list->shift,
227 list->width, list->div_flags,
228 list->table, &lock);
229 else
230 clk = clk_register_divider(NULL, list->name,
231 list->parent_name, list->flags,
232 reg_base + list->offset, list->shift,
233 list->width, list->div_flags, &lock);
234 if (IS_ERR(clk)) {
235 pr_err("%s: failed to register clock %s\n", __func__,
236 list->name);
237 continue;
238 }
239
240 samsung_clk_add_lookup(clk, list->id);
241
242 /* register a clock lookup only if a clock alias is specified */
243 if (list->alias) {
244 ret = clk_register_clkdev(clk, list->alias,
245 list->dev_name);
246 if (ret)
247 pr_err("%s: failed to register lookup %s\n",
248 __func__, list->alias);
249 }
250 }
251}
252
253/* register a list of gate clocks */
254void __init samsung_clk_register_gate(struct samsung_gate_clock *list,
255 unsigned int nr_clk)
256{
257 struct clk *clk;
258 unsigned int idx, ret;
259
260 for (idx = 0; idx < nr_clk; idx++, list++) {
261 clk = clk_register_gate(NULL, list->name, list->parent_name,
262 list->flags, reg_base + list->offset,
263 list->bit_idx, list->gate_flags, &lock);
264 if (IS_ERR(clk)) {
265 pr_err("%s: failed to register clock %s\n", __func__,
266 list->name);
267 continue;
268 }
269
270 /* register a clock lookup only if a clock alias is specified */
271 if (list->alias) {
272 ret = clk_register_clkdev(clk, list->alias,
273 list->dev_name);
274 if (ret)
275 pr_err("%s: failed to register lookup %s\n",
276 __func__, list->alias);
277 }
278
279 samsung_clk_add_lookup(clk, list->id);
280 }
281}
282
283/*
284 * obtain the clock speed of all external fixed clock sources from device
285 * tree and register it
286 */
287#ifdef CONFIG_OF
288void __init samsung_clk_of_register_fixed_ext(
289 struct samsung_fixed_rate_clock *fixed_rate_clk,
290 unsigned int nr_fixed_rate_clk,
291 struct of_device_id *clk_matches)
292{
293 const struct of_device_id *match;
294 struct device_node *np;
295 u32 freq;
296
297 for_each_matching_node_and_match(np, clk_matches, &match) {
298 if (of_property_read_u32(np, "clock-frequency", &freq))
299 continue;
300 fixed_rate_clk[(u32)match->data].fixed_rate = freq;
301 }
302 samsung_clk_register_fixed_rate(fixed_rate_clk, nr_fixed_rate_clk);
303}
304#endif
305
306/* utility function to get the rate of a specified clock */
307unsigned long _get_rate(const char *clk_name)
308{
309 struct clk *clk;
310 unsigned long rate;
311
312 clk = clk_get(NULL, clk_name);
313 if (IS_ERR(clk)) {
314 pr_err("%s: could not find clock %s\n", __func__, clk_name);
315 return 0;
316 }
317 rate = clk_get_rate(clk);
318 clk_put(clk);
319 return rate;
320}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
new file mode 100644
index 000000000000..10b2111f0c0f
--- /dev/null
+++ b/drivers/clk/samsung/clk.h
@@ -0,0 +1,289 @@
1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for all Samsung platforms
11*/
12
13#ifndef __SAMSUNG_CLK_H
14#define __SAMSUNG_CLK_H
15
16#include <linux/clk.h>
17#include <linux/clkdev.h>
18#include <linux/io.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22
23#include <mach/map.h>
24
25/**
26 * struct samsung_clock_alias: information about mux clock
27 * @id: platform specific id of the clock.
28 * @dev_name: name of the device to which this clock belongs.
29 * @alias: optional clock alias name to be assigned to this clock.
30 */
31struct samsung_clock_alias {
32 unsigned int id;
33 const char *dev_name;
34 const char *alias;
35};
36
37#define ALIAS(_id, dname, a) \
38 { \
39 .id = _id, \
40 .dev_name = dname, \
41 .alias = a, \
42 }
43
44/**
45 * struct samsung_fixed_rate_clock: information about fixed-rate clock
46 * @id: platform specific id of the clock.
47 * @name: name of this fixed-rate clock.
48 * @parent_name: optional parent clock name.
49 * @flags: optional fixed-rate clock flags.
50 * @fixed-rate: fixed clock rate of this clock.
51 */
52struct samsung_fixed_rate_clock {
53 unsigned int id;
54 char *name;
55 const char *parent_name;
56 unsigned long flags;
57 unsigned long fixed_rate;
58};
59
60#define FRATE(_id, cname, pname, f, frate) \
61 { \
62 .id = _id, \
63 .name = cname, \
64 .parent_name = pname, \
65 .flags = f, \
66 .fixed_rate = frate, \
67 }
68
69/*
70 * struct samsung_fixed_factor_clock: information about fixed-factor clock
71 * @id: platform specific id of the clock.
72 * @name: name of this fixed-factor clock.
73 * @parent_name: parent clock name.
74 * @mult: fixed multiplication factor.
75 * @div: fixed division factor.
76 * @flags: optional fixed-factor clock flags.
77 */
78struct samsung_fixed_factor_clock {
79 unsigned int id;
80 char *name;
81 const char *parent_name;
82 unsigned long mult;
83 unsigned long div;
84 unsigned long flags;
85};
86
87#define FFACTOR(_id, cname, pname, m, d, f) \
88 { \
89 .id = _id, \
90 .name = cname, \
91 .parent_name = pname, \
92 .mult = m, \
93 .div = d, \
94 .flags = f, \
95 }
96
97/**
98 * struct samsung_mux_clock: information about mux clock
99 * @id: platform specific id of the clock.
100 * @dev_name: name of the device to which this clock belongs.
101 * @name: name of this mux clock.
102 * @parent_names: array of pointer to parent clock names.
103 * @num_parents: number of parents listed in @parent_names.
104 * @flags: optional flags for basic clock.
105 * @offset: offset of the register for configuring the mux.
106 * @shift: starting bit location of the mux control bit-field in @reg.
107 * @width: width of the mux control bit-field in @reg.
108 * @mux_flags: flags for mux-type clock.
109 * @alias: optional clock alias name to be assigned to this clock.
110 */
111struct samsung_mux_clock {
112 unsigned int id;
113 const char *dev_name;
114 const char *name;
115 const char **parent_names;
116 u8 num_parents;
117 unsigned long flags;
118 unsigned long offset;
119 u8 shift;
120 u8 width;
121 u8 mux_flags;
122 const char *alias;
123};
124
125#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
126 { \
127 .id = _id, \
128 .dev_name = dname, \
129 .name = cname, \
130 .parent_names = pnames, \
131 .num_parents = ARRAY_SIZE(pnames), \
132 .flags = f, \
133 .offset = o, \
134 .shift = s, \
135 .width = w, \
136 .mux_flags = mf, \
137 .alias = a, \
138 }
139
140#define MUX(_id, cname, pnames, o, s, w) \
141 __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
142
143#define MUX_A(_id, cname, pnames, o, s, w, a) \
144 __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
145
146#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
147 __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
148
149/**
150 * @id: platform specific id of the clock.
151 * struct samsung_div_clock: information about div clock
152 * @dev_name: name of the device to which this clock belongs.
153 * @name: name of this div clock.
154 * @parent_name: name of the parent clock.
155 * @flags: optional flags for basic clock.
156 * @offset: offset of the register for configuring the div.
157 * @shift: starting bit location of the div control bit-field in @reg.
158 * @div_flags: flags for div-type clock.
159 * @alias: optional clock alias name to be assigned to this clock.
160 */
161struct samsung_div_clock {
162 unsigned int id;
163 const char *dev_name;
164 const char *name;
165 const char *parent_name;
166 unsigned long flags;
167 unsigned long offset;
168 u8 shift;
169 u8 width;
170 u8 div_flags;
171 const char *alias;
172 struct clk_div_table *table;
173};
174
175#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \
176 { \
177 .id = _id, \
178 .dev_name = dname, \
179 .name = cname, \
180 .parent_name = pname, \
181 .flags = f, \
182 .offset = o, \
183 .shift = s, \
184 .width = w, \
185 .div_flags = df, \
186 .alias = a, \
187 .table = t, \
188 }
189
190#define DIV(_id, cname, pname, o, s, w) \
191 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
192
193#define DIV_A(_id, cname, pname, o, s, w, a) \
194 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
195
196#define DIV_F(_id, cname, pname, o, s, w, f, df) \
197 __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
198
199#define DIV_T(_id, cname, pname, o, s, w, t) \
200 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
201
202/**
203 * struct samsung_gate_clock: information about gate clock
204 * @id: platform specific id of the clock.
205 * @dev_name: name of the device to which this clock belongs.
206 * @name: name of this gate clock.
207 * @parent_name: name of the parent clock.
208 * @flags: optional flags for basic clock.
209 * @offset: offset of the register for configuring the gate.
210 * @bit_idx: bit index of the gate control bit-field in @reg.
211 * @gate_flags: flags for gate-type clock.
212 * @alias: optional clock alias name to be assigned to this clock.
213 */
214struct samsung_gate_clock {
215 unsigned int id;
216 const char *dev_name;
217 const char *name;
218 const char *parent_name;
219 unsigned long flags;
220 unsigned long offset;
221 u8 bit_idx;
222 u8 gate_flags;
223 const char *alias;
224};
225
226#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
227 { \
228 .id = _id, \
229 .dev_name = dname, \
230 .name = cname, \
231 .parent_name = pname, \
232 .flags = f, \
233 .offset = o, \
234 .bit_idx = b, \
235 .gate_flags = gf, \
236 .alias = a, \
237 }
238
239#define GATE(_id, cname, pname, o, b, f, gf) \
240 __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
241
242#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
243 __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
244
245#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
246 __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
247
248#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
249 __GATE(_id, dname, cname, pname, o, b, f, gf, a)
250
251#define PNAME(x) static const char *x[] __initdata
252
253/**
254 * struct samsung_clk_reg_dump: register dump of clock controller registers.
255 * @offset: clock register offset from the controller base address.
256 * @value: the value to be register at offset.
257 */
258struct samsung_clk_reg_dump {
259 u32 offset;
260 u32 value;
261};
262
263extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
264 unsigned long nr_clks, unsigned long *rdump,
265 unsigned long nr_rdump, unsigned long *soc_rdump,
266 unsigned long nr_soc_rdump);
267extern void __init samsung_clk_of_register_fixed_ext(
268 struct samsung_fixed_rate_clock *fixed_rate_clk,
269 unsigned int nr_fixed_rate_clk,
270 struct of_device_id *clk_matches);
271
272extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
273
274extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
275 unsigned int nr_clk);
276extern void __init samsung_clk_register_fixed_rate(
277 struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
278extern void __init samsung_clk_register_fixed_factor(
279 struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
280extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
281 unsigned int nr_clk);
282extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
283 unsigned int nr_clk);
284extern void __init samsung_clk_register_gate(
285 struct samsung_gate_clock *clk_list, unsigned int nr_clk);
286
287extern unsigned long _get_rate(const char *clk_name);
288
289#endif /* __SAMSUNG_CLK_H */
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e507ab7df60b..e8c453285151 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -67,3 +67,8 @@ config CLKSRC_METAG_GENERIC
67 def_bool y if METAG 67 def_bool y if METAG
68 help 68 help
69 This option enables support for the Meta per-thread timers. 69 This option enables support for the Meta per-thread timers.
70
71config CLKSRC_EXYNOS_MCT
72 def_bool y if ARCH_EXYNOS
73 help
74 Support for Multi Core Timer controller on Exynos SoCs.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 89c5adc498b3..7c88173295aa 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
20obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o 20obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
21obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o 21obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
22obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o 22obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
23obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
23 24
24obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o 25obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
25obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o 26obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
new file mode 100644
index 000000000000..203ac05e2b3d
--- /dev/null
+++ b/drivers/clocksource/exynos_mct.c
@@ -0,0 +1,558 @@
1/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/percpu.h>
22#include <linux/of.h>
23#include <linux/of_irq.h>
24#include <linux/of_address.h>
25#include <linux/clocksource.h>
26
27#include <asm/arch_timer.h>
28#include <asm/localtimer.h>
29
30#include <plat/cpu.h>
31
32#include <mach/map.h>
33#include <mach/irqs.h>
34#include <asm/mach/time.h>
35
36#define EXYNOS4_MCTREG(x) (x)
37#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
38#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
39#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
40#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
41#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
42#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
43#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
44#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
45#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
46#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
47#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
48#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
49#define EXYNOS4_MCT_L_MASK (0xffffff00)
50
51#define MCT_L_TCNTB_OFFSET (0x00)
52#define MCT_L_ICNTB_OFFSET (0x08)
53#define MCT_L_TCON_OFFSET (0x20)
54#define MCT_L_INT_CSTAT_OFFSET (0x30)
55#define MCT_L_INT_ENB_OFFSET (0x34)
56#define MCT_L_WSTAT_OFFSET (0x40)
57#define MCT_G_TCON_START (1 << 8)
58#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
59#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
60#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
61#define MCT_L_TCON_INT_START (1 << 1)
62#define MCT_L_TCON_TIMER_START (1 << 0)
63
64#define TICK_BASE_CNT 1
65
66enum {
67 MCT_INT_SPI,
68 MCT_INT_PPI
69};
70
71enum {
72 MCT_G0_IRQ,
73 MCT_G1_IRQ,
74 MCT_G2_IRQ,
75 MCT_G3_IRQ,
76 MCT_L0_IRQ,
77 MCT_L1_IRQ,
78 MCT_L2_IRQ,
79 MCT_L3_IRQ,
80 MCT_NR_IRQS,
81};
82
83static void __iomem *reg_base;
84static unsigned long clk_rate;
85static unsigned int mct_int_type;
86static int mct_irqs[MCT_NR_IRQS];
87
88struct mct_clock_event_device {
89 struct clock_event_device *evt;
90 unsigned long base;
91 char name[10];
92};
93
94static void exynos4_mct_write(unsigned int value, unsigned long offset)
95{
96 unsigned long stat_addr;
97 u32 mask;
98 u32 i;
99
100 __raw_writel(value, reg_base + offset);
101
102 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
103 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
104 switch (offset & EXYNOS4_MCT_L_MASK) {
105 case MCT_L_TCON_OFFSET:
106 mask = 1 << 3; /* L_TCON write status */
107 break;
108 case MCT_L_ICNTB_OFFSET:
109 mask = 1 << 1; /* L_ICNTB write status */
110 break;
111 case MCT_L_TCNTB_OFFSET:
112 mask = 1 << 0; /* L_TCNTB write status */
113 break;
114 default:
115 return;
116 }
117 } else {
118 switch (offset) {
119 case EXYNOS4_MCT_G_TCON:
120 stat_addr = EXYNOS4_MCT_G_WSTAT;
121 mask = 1 << 16; /* G_TCON write status */
122 break;
123 case EXYNOS4_MCT_G_COMP0_L:
124 stat_addr = EXYNOS4_MCT_G_WSTAT;
125 mask = 1 << 0; /* G_COMP0_L write status */
126 break;
127 case EXYNOS4_MCT_G_COMP0_U:
128 stat_addr = EXYNOS4_MCT_G_WSTAT;
129 mask = 1 << 1; /* G_COMP0_U write status */
130 break;
131 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
132 stat_addr = EXYNOS4_MCT_G_WSTAT;
133 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
134 break;
135 case EXYNOS4_MCT_G_CNT_L:
136 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
137 mask = 1 << 0; /* G_CNT_L write status */
138 break;
139 case EXYNOS4_MCT_G_CNT_U:
140 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
141 mask = 1 << 1; /* G_CNT_U write status */
142 break;
143 default:
144 return;
145 }
146 }
147
148 /* Wait maximum 1 ms until written values are applied */
149 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
150 if (__raw_readl(reg_base + stat_addr) & mask) {
151 __raw_writel(mask, reg_base + stat_addr);
152 return;
153 }
154
155 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
156}
157
158/* Clocksource handling */
159static void exynos4_mct_frc_start(u32 hi, u32 lo)
160{
161 u32 reg;
162
163 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
164 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
165
166 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
167 reg |= MCT_G_TCON_START;
168 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
169}
170
171static cycle_t exynos4_frc_read(struct clocksource *cs)
172{
173 unsigned int lo, hi;
174 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
175
176 do {
177 hi = hi2;
178 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
179 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
180 } while (hi != hi2);
181
182 return ((cycle_t)hi << 32) | lo;
183}
184
185static void exynos4_frc_resume(struct clocksource *cs)
186{
187 exynos4_mct_frc_start(0, 0);
188}
189
190struct clocksource mct_frc = {
191 .name = "mct-frc",
192 .rating = 400,
193 .read = exynos4_frc_read,
194 .mask = CLOCKSOURCE_MASK(64),
195 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
196 .resume = exynos4_frc_resume,
197};
198
199static void __init exynos4_clocksource_init(void)
200{
201 exynos4_mct_frc_start(0, 0);
202
203 if (clocksource_register_hz(&mct_frc, clk_rate))
204 panic("%s: can't register clocksource\n", mct_frc.name);
205}
206
207static void exynos4_mct_comp0_stop(void)
208{
209 unsigned int tcon;
210
211 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
212 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
213
214 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
215 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
216}
217
218static void exynos4_mct_comp0_start(enum clock_event_mode mode,
219 unsigned long cycles)
220{
221 unsigned int tcon;
222 cycle_t comp_cycle;
223
224 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
225
226 if (mode == CLOCK_EVT_MODE_PERIODIC) {
227 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
228 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
229 }
230
231 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
232 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
233 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
234
235 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
236
237 tcon |= MCT_G_TCON_COMP0_ENABLE;
238 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
239}
240
241static int exynos4_comp_set_next_event(unsigned long cycles,
242 struct clock_event_device *evt)
243{
244 exynos4_mct_comp0_start(evt->mode, cycles);
245
246 return 0;
247}
248
249static void exynos4_comp_set_mode(enum clock_event_mode mode,
250 struct clock_event_device *evt)
251{
252 unsigned long cycles_per_jiffy;
253 exynos4_mct_comp0_stop();
254
255 switch (mode) {
256 case CLOCK_EVT_MODE_PERIODIC:
257 cycles_per_jiffy =
258 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
259 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
260 break;
261
262 case CLOCK_EVT_MODE_ONESHOT:
263 case CLOCK_EVT_MODE_UNUSED:
264 case CLOCK_EVT_MODE_SHUTDOWN:
265 case CLOCK_EVT_MODE_RESUME:
266 break;
267 }
268}
269
270static struct clock_event_device mct_comp_device = {
271 .name = "mct-comp",
272 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
273 .rating = 250,
274 .set_next_event = exynos4_comp_set_next_event,
275 .set_mode = exynos4_comp_set_mode,
276};
277
278static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
279{
280 struct clock_event_device *evt = dev_id;
281
282 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
283
284 evt->event_handler(evt);
285
286 return IRQ_HANDLED;
287}
288
289static struct irqaction mct_comp_event_irq = {
290 .name = "mct_comp_irq",
291 .flags = IRQF_TIMER | IRQF_IRQPOLL,
292 .handler = exynos4_mct_comp_isr,
293 .dev_id = &mct_comp_device,
294};
295
296static void exynos4_clockevent_init(void)
297{
298 mct_comp_device.cpumask = cpumask_of(0);
299 clockevents_config_and_register(&mct_comp_device, clk_rate,
300 0xf, 0xffffffff);
301 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
302}
303
304#ifdef CONFIG_LOCAL_TIMERS
305
306static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
307
308/* Clock event handling */
309static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
310{
311 unsigned long tmp;
312 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
313 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
314
315 tmp = __raw_readl(reg_base + offset);
316 if (tmp & mask) {
317 tmp &= ~mask;
318 exynos4_mct_write(tmp, offset);
319 }
320}
321
322static void exynos4_mct_tick_start(unsigned long cycles,
323 struct mct_clock_event_device *mevt)
324{
325 unsigned long tmp;
326
327 exynos4_mct_tick_stop(mevt);
328
329 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
330
331 /* update interrupt count buffer */
332 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
333
334 /* enable MCT tick interrupt */
335 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
336
337 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
338 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
339 MCT_L_TCON_INTERVAL_MODE;
340 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
341}
342
343static int exynos4_tick_set_next_event(unsigned long cycles,
344 struct clock_event_device *evt)
345{
346 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
347
348 exynos4_mct_tick_start(cycles, mevt);
349
350 return 0;
351}
352
353static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
354 struct clock_event_device *evt)
355{
356 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
357 unsigned long cycles_per_jiffy;
358
359 exynos4_mct_tick_stop(mevt);
360
361 switch (mode) {
362 case CLOCK_EVT_MODE_PERIODIC:
363 cycles_per_jiffy =
364 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
365 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
366 break;
367
368 case CLOCK_EVT_MODE_ONESHOT:
369 case CLOCK_EVT_MODE_UNUSED:
370 case CLOCK_EVT_MODE_SHUTDOWN:
371 case CLOCK_EVT_MODE_RESUME:
372 break;
373 }
374}
375
376static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
377{
378 struct clock_event_device *evt = mevt->evt;
379
380 /*
381 * This is for supporting oneshot mode.
382 * Mct would generate interrupt periodically
383 * without explicit stopping.
384 */
385 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
386 exynos4_mct_tick_stop(mevt);
387
388 /* Clear the MCT tick interrupt */
389 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
390 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
391 return 1;
392 } else {
393 return 0;
394 }
395}
396
397static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
398{
399 struct mct_clock_event_device *mevt = dev_id;
400 struct clock_event_device *evt = mevt->evt;
401
402 exynos4_mct_tick_clear(mevt);
403
404 evt->event_handler(evt);
405
406 return IRQ_HANDLED;
407}
408
409static struct irqaction mct_tick0_event_irq = {
410 .name = "mct_tick0_irq",
411 .flags = IRQF_TIMER | IRQF_NOBALANCING,
412 .handler = exynos4_mct_tick_isr,
413};
414
415static struct irqaction mct_tick1_event_irq = {
416 .name = "mct_tick1_irq",
417 .flags = IRQF_TIMER | IRQF_NOBALANCING,
418 .handler = exynos4_mct_tick_isr,
419};
420
421static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
422{
423 struct mct_clock_event_device *mevt;
424 unsigned int cpu = smp_processor_id();
425
426 mevt = this_cpu_ptr(&percpu_mct_tick);
427 mevt->evt = evt;
428
429 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
430 sprintf(mevt->name, "mct_tick%d", cpu);
431
432 evt->name = mevt->name;
433 evt->cpumask = cpumask_of(cpu);
434 evt->set_next_event = exynos4_tick_set_next_event;
435 evt->set_mode = exynos4_tick_set_mode;
436 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
437 evt->rating = 450;
438 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
439 0xf, 0x7fffffff);
440
441 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
442
443 if (mct_int_type == MCT_INT_SPI) {
444 if (cpu == 0) {
445 mct_tick0_event_irq.dev_id = mevt;
446 evt->irq = mct_irqs[MCT_L0_IRQ];
447 setup_irq(evt->irq, &mct_tick0_event_irq);
448 } else {
449 mct_tick1_event_irq.dev_id = mevt;
450 evt->irq = mct_irqs[MCT_L1_IRQ];
451 setup_irq(evt->irq, &mct_tick1_event_irq);
452 irq_set_affinity(evt->irq, cpumask_of(1));
453 }
454 } else {
455 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
456 }
457
458 return 0;
459}
460
461static void exynos4_local_timer_stop(struct clock_event_device *evt)
462{
463 unsigned int cpu = smp_processor_id();
464 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
465 if (mct_int_type == MCT_INT_SPI)
466 if (cpu == 0)
467 remove_irq(evt->irq, &mct_tick0_event_irq);
468 else
469 remove_irq(evt->irq, &mct_tick1_event_irq);
470 else
471 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
472}
473
474static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
475 .setup = exynos4_local_timer_setup,
476 .stop = exynos4_local_timer_stop,
477};
478#endif /* CONFIG_LOCAL_TIMERS */
479
480static void __init exynos4_timer_resources(struct device_node *np)
481{
482 struct clk *mct_clk, *tick_clk;
483
484 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
485 clk_get(NULL, "fin_pll");
486 if (IS_ERR(tick_clk))
487 panic("%s: unable to determine tick clock rate\n", __func__);
488 clk_rate = clk_get_rate(tick_clk);
489
490 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
491 if (IS_ERR(mct_clk))
492 panic("%s: unable to retrieve mct clock instance\n", __func__);
493 clk_prepare_enable(mct_clk);
494
495 reg_base = np ? of_iomap(np, 0) : S5P_VA_SYSTIMER;
496 if (!reg_base)
497 panic("%s: unable to ioremap mct address space\n", __func__);
498
499#ifdef CONFIG_LOCAL_TIMERS
500 if (mct_int_type == MCT_INT_PPI) {
501 int err;
502
503 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
504 exynos4_mct_tick_isr, "MCT",
505 &percpu_mct_tick);
506 WARN(err, "MCT: can't request IRQ %d (%d)\n",
507 mct_irqs[MCT_L0_IRQ], err);
508 }
509
510 local_timer_register(&exynos4_mct_tick_ops);
511#endif /* CONFIG_LOCAL_TIMERS */
512}
513
514static const struct of_device_id exynos_mct_ids[] = {
515 { .compatible = "samsung,exynos4210-mct", .data = (void *)MCT_INT_SPI },
516 { .compatible = "samsung,exynos4412-mct", .data = (void *)MCT_INT_PPI },
517};
518
519void __init mct_init(void)
520{
521 struct device_node *np = NULL;
522 const struct of_device_id *match;
523 u32 nr_irqs, i;
524
525#ifdef CONFIG_OF
526 np = of_find_matching_node_and_match(NULL, exynos_mct_ids, &match);
527#endif
528 if (np) {
529 mct_int_type = (u32)(match->data);
530
531 /* This driver uses only one global timer interrupt */
532 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
533
534 /*
535 * Find out the number of local irqs specified. The local
536 * timer irqs are specified after the four global timer
537 * irqs are specified.
538 */
539#ifdef CONFIG_OF
540 nr_irqs = of_irq_count(np);
541#endif
542 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
543 mct_irqs[i] = irq_of_parse_and_map(np, i);
544 } else if (soc_is_exynos4210()) {
545 mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
546 mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
547 mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
548 mct_int_type = MCT_INT_SPI;
549 } else {
550 panic("unable to determine mct controller type\n");
551 }
552
553 exynos4_timer_resources(np);
554 exynos4_clocksource_init();
555 exynos4_clockevent_init();
556}
557CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init)
558CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init)
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 63fb265e0da6..8d6794cdf899 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -25,14 +25,93 @@
25 25
26#include <mach/dma.h> 26#include <mach/dma.h>
27 27
28#include <mach/regs-sdi.h>
29
30#include <linux/platform_data/mmc-s3cmci.h> 28#include <linux/platform_data/mmc-s3cmci.h>
31 29
32#include "s3cmci.h" 30#include "s3cmci.h"
33 31
34#define DRIVER_NAME "s3c-mci" 32#define DRIVER_NAME "s3c-mci"
35 33
34#define S3C2410_SDICON (0x00)
35#define S3C2410_SDIPRE (0x04)
36#define S3C2410_SDICMDARG (0x08)
37#define S3C2410_SDICMDCON (0x0C)
38#define S3C2410_SDICMDSTAT (0x10)
39#define S3C2410_SDIRSP0 (0x14)
40#define S3C2410_SDIRSP1 (0x18)
41#define S3C2410_SDIRSP2 (0x1C)
42#define S3C2410_SDIRSP3 (0x20)
43#define S3C2410_SDITIMER (0x24)
44#define S3C2410_SDIBSIZE (0x28)
45#define S3C2410_SDIDCON (0x2C)
46#define S3C2410_SDIDCNT (0x30)
47#define S3C2410_SDIDSTA (0x34)
48#define S3C2410_SDIFSTA (0x38)
49
50#define S3C2410_SDIDATA (0x3C)
51#define S3C2410_SDIIMSK (0x40)
52
53#define S3C2440_SDIDATA (0x40)
54#define S3C2440_SDIIMSK (0x3C)
55
56#define S3C2440_SDICON_SDRESET (1 << 8)
57#define S3C2410_SDICON_SDIOIRQ (1 << 3)
58#define S3C2410_SDICON_FIFORESET (1 << 1)
59#define S3C2410_SDICON_CLOCKTYPE (1 << 0)
60
61#define S3C2410_SDICMDCON_LONGRSP (1 << 10)
62#define S3C2410_SDICMDCON_WAITRSP (1 << 9)
63#define S3C2410_SDICMDCON_CMDSTART (1 << 8)
64#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
65#define S3C2410_SDICMDCON_INDEX (0x3f)
66
67#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
68#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
69#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
70#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
71
72#define S3C2440_SDIDCON_DS_WORD (2 << 22)
73#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
74#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
75#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
76#define S3C2410_SDIDCON_WIDEBUS (1 << 16)
77#define S3C2410_SDIDCON_DMAEN (1 << 15)
78#define S3C2410_SDIDCON_STOP (1 << 14)
79#define S3C2440_SDIDCON_DATSTART (1 << 14)
80
81#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
82#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
83
84#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
85
86#define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
87#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
88#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
89#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
90#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
91#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
92#define S3C2410_SDIDSTA_TXDATAON (1 << 1)
93#define S3C2410_SDIDSTA_RXDATAON (1 << 0)
94
95#define S3C2440_SDIFSTA_FIFORESET (1 << 16)
96#define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
97#define S3C2410_SDIFSTA_TFDET (1 << 13)
98#define S3C2410_SDIFSTA_RFDET (1 << 12)
99#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
100
101#define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
102#define S3C2410_SDIIMSK_CMDSENT (1 << 16)
103#define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
104#define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
105#define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
106#define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
107#define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
108#define S3C2410_SDIIMSK_DATACRC (1 << 9)
109#define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
110#define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
111#define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
112#define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
113#define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
114
36enum dbg_channels { 115enum dbg_channels {
37 dbg_err = (1 << 0), 116 dbg_err = (1 << 0),
38 dbg_debug = (1 << 1), 117 dbg_debug = (1 << 1),
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-29 16:32:58 -0400