diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 14:10:25 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 15:28:04 -0400 |
commit | bbf8906b2cad17cf9530b06db7509d0e39b02d16 (patch) | |
tree | 8b0ac662278cd6ea528c619d4ebd932f67a29fe3 /drivers | |
parent | a532da976f17234375d3b34633ff5d48f71f62bc (diff) |
drm/nouveau/fifo: audit and version fifo channel classes
The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers')
19 files changed, 323 insertions, 199 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c index a1e722ad31ad..3e14f46cfbd2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c | |||
@@ -52,10 +52,10 @@ nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj, | |||
52 | 52 | ||
53 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { | 53 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { |
54 | switch (nv_mclass(parent->parent)) { | 54 | switch (nv_mclass(parent->parent)) { |
55 | case NV03_CHANNEL_DMA_CLASS: | 55 | case NV03_CHANNEL_DMA: |
56 | case NV10_CHANNEL_DMA_CLASS: | 56 | case NV10_CHANNEL_DMA: |
57 | case NV17_CHANNEL_DMA_CLASS: | 57 | case NV17_CHANNEL_DMA: |
58 | case NV40_CHANNEL_DMA_CLASS: | 58 | case NV40_CHANNEL_DMA: |
59 | break; | 59 | break; |
60 | default: | 60 | default: |
61 | return -EINVAL; | 61 | return -EINVAL; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c index 71387c4c55b1..7495f7d363bb 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c | |||
@@ -48,10 +48,9 @@ nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj, | |||
48 | 48 | ||
49 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { | 49 | if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { |
50 | switch (nv_mclass(parent->parent)) { | 50 | switch (nv_mclass(parent->parent)) { |
51 | case NV50_CHANNEL_DMA_CLASS: | 51 | case NV40_CHANNEL_DMA: |
52 | case NV84_CHANNEL_DMA_CLASS: | 52 | case NV50_CHANNEL_GPFIFO: |
53 | case NV50_CHANNEL_IND_CLASS: | 53 | case G82_CHANNEL_GPFIFO: |
54 | case NV84_CHANNEL_IND_CLASS: | ||
55 | case NV50_DISP_MAST_CLASS: | 54 | case NV50_DISP_MAST_CLASS: |
56 | case NV84_DISP_MAST_CLASS: | 55 | case NV84_DISP_MAST_CLASS: |
57 | case NV94_DISP_MAST_CLASS: | 56 | case NV94_DISP_MAST_CLASS: |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c index 4f0e3d1b6ffd..f825def16ffa 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c | |||
@@ -26,7 +26,8 @@ | |||
26 | #include <core/object.h> | 26 | #include <core/object.h> |
27 | #include <core/handle.h> | 27 | #include <core/handle.h> |
28 | #include <core/event.h> | 28 | #include <core/event.h> |
29 | #include <core/class.h> | 29 | #include <nvif/unpack.h> |
30 | #include <nvif/class.h> | ||
30 | 31 | ||
31 | #include <engine/dmaobj.h> | 32 | #include <engine/dmaobj.h> |
32 | #include <engine/fifo.h> | 33 | #include <engine/fifo.h> |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c index 921062c7e5e4..5b4a9a56d630 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c | |||
@@ -22,8 +22,9 @@ | |||
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <core/os.h> | 25 | #include <core/client.h> |
26 | #include <core/class.h> | 26 | #include <nvif/unpack.h> |
27 | #include <nvif/class.h> | ||
27 | #include <core/engctx.h> | 28 | #include <core/engctx.h> |
28 | #include <core/namedb.h> | 29 | #include <core/namedb.h> |
29 | #include <core/handle.h> | 30 | #include <core/handle.h> |
@@ -117,16 +118,23 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, | |||
117 | struct nouveau_oclass *oclass, void *data, u32 size, | 118 | struct nouveau_oclass *oclass, void *data, u32 size, |
118 | struct nouveau_object **pobject) | 119 | struct nouveau_object **pobject) |
119 | { | 120 | { |
121 | union { | ||
122 | struct nv03_channel_dma_v0 v0; | ||
123 | } *args = data; | ||
120 | struct nv04_fifo_priv *priv = (void *)engine; | 124 | struct nv04_fifo_priv *priv = (void *)engine; |
121 | struct nv04_fifo_chan *chan; | 125 | struct nv04_fifo_chan *chan; |
122 | struct nv03_channel_dma_class *args = data; | ||
123 | int ret; | 126 | int ret; |
124 | 127 | ||
125 | if (size < sizeof(*args)) | 128 | nv_ioctl(parent, "create channel dma size %d\n", size); |
126 | return -EINVAL; | 129 | if (nvif_unpack(args->v0, 0, 0, false)) { |
130 | nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " | ||
131 | "offset %016llx\n", args->v0.version, | ||
132 | args->v0.pushbuf, args->v0.offset); | ||
133 | } else | ||
134 | return ret; | ||
127 | 135 | ||
128 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, | 136 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, |
129 | 0x10000, args->pushbuf, | 137 | 0x10000, args->v0.pushbuf, |
130 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | 138 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
131 | (1ULL << NVDEV_ENGINE_SW) | | 139 | (1ULL << NVDEV_ENGINE_SW) | |
132 | (1ULL << NVDEV_ENGINE_GR), &chan); | 140 | (1ULL << NVDEV_ENGINE_GR), &chan); |
@@ -134,13 +142,15 @@ nv04_fifo_chan_ctor(struct nouveau_object *parent, | |||
134 | if (ret) | 142 | if (ret) |
135 | return ret; | 143 | return ret; |
136 | 144 | ||
145 | args->v0.chid = chan->base.chid; | ||
146 | |||
137 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; | 147 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
138 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | 148 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
139 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; | 149 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; |
140 | chan->ramfc = chan->base.chid * 32; | 150 | chan->ramfc = chan->base.chid * 32; |
141 | 151 | ||
142 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); | 152 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); |
143 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); | 153 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); |
144 | nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); | 154 | nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); |
145 | nv_wo32(priv->ramfc, chan->ramfc + 0x10, | 155 | nv_wo32(priv->ramfc, chan->ramfc + 0x10, |
146 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | | 156 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
@@ -248,7 +258,7 @@ nv04_fifo_ofuncs = { | |||
248 | 258 | ||
249 | static struct nouveau_oclass | 259 | static struct nouveau_oclass |
250 | nv04_fifo_sclass[] = { | 260 | nv04_fifo_sclass[] = { |
251 | { NV03_CHANNEL_DMA_CLASS, &nv04_fifo_ofuncs }, | 261 | { NV03_CHANNEL_DMA, &nv04_fifo_ofuncs }, |
252 | {} | 262 | {} |
253 | }; | 263 | }; |
254 | 264 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c index 571a22aa1ae5..90713fdef662 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c | |||
@@ -22,8 +22,9 @@ | |||
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <core/os.h> | 25 | #include <core/client.h> |
26 | #include <core/class.h> | 26 | #include <nvif/unpack.h> |
27 | #include <nvif/class.h> | ||
27 | #include <core/engctx.h> | 28 | #include <core/engctx.h> |
28 | #include <core/ramht.h> | 29 | #include <core/ramht.h> |
29 | 30 | ||
@@ -59,16 +60,23 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, | |||
59 | struct nouveau_oclass *oclass, void *data, u32 size, | 60 | struct nouveau_oclass *oclass, void *data, u32 size, |
60 | struct nouveau_object **pobject) | 61 | struct nouveau_object **pobject) |
61 | { | 62 | { |
63 | union { | ||
64 | struct nv03_channel_dma_v0 v0; | ||
65 | } *args = data; | ||
62 | struct nv04_fifo_priv *priv = (void *)engine; | 66 | struct nv04_fifo_priv *priv = (void *)engine; |
63 | struct nv04_fifo_chan *chan; | 67 | struct nv04_fifo_chan *chan; |
64 | struct nv03_channel_dma_class *args = data; | ||
65 | int ret; | 68 | int ret; |
66 | 69 | ||
67 | if (size < sizeof(*args)) | 70 | nv_ioctl(parent, "create channel dma size %d\n", size); |
68 | return -EINVAL; | 71 | if (nvif_unpack(args->v0, 0, 0, false)) { |
72 | nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " | ||
73 | "offset %016llx\n", args->v0.version, | ||
74 | args->v0.pushbuf, args->v0.offset); | ||
75 | } else | ||
76 | return ret; | ||
69 | 77 | ||
70 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, | 78 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, |
71 | 0x10000, args->pushbuf, | 79 | 0x10000, args->v0.pushbuf, |
72 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | 80 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
73 | (1ULL << NVDEV_ENGINE_SW) | | 81 | (1ULL << NVDEV_ENGINE_SW) | |
74 | (1ULL << NVDEV_ENGINE_GR), &chan); | 82 | (1ULL << NVDEV_ENGINE_GR), &chan); |
@@ -76,13 +84,15 @@ nv10_fifo_chan_ctor(struct nouveau_object *parent, | |||
76 | if (ret) | 84 | if (ret) |
77 | return ret; | 85 | return ret; |
78 | 86 | ||
87 | args->v0.chid = chan->base.chid; | ||
88 | |||
79 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; | 89 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
80 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | 90 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
81 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; | 91 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; |
82 | chan->ramfc = chan->base.chid * 32; | 92 | chan->ramfc = chan->base.chid * 32; |
83 | 93 | ||
84 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); | 94 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); |
85 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); | 95 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); |
86 | nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); | 96 | nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); |
87 | nv_wo32(priv->ramfc, chan->ramfc + 0x14, | 97 | nv_wo32(priv->ramfc, chan->ramfc + 0x14, |
88 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | | 98 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
@@ -106,7 +116,7 @@ nv10_fifo_ofuncs = { | |||
106 | 116 | ||
107 | static struct nouveau_oclass | 117 | static struct nouveau_oclass |
108 | nv10_fifo_sclass[] = { | 118 | nv10_fifo_sclass[] = { |
109 | { NV10_CHANNEL_DMA_CLASS, &nv10_fifo_ofuncs }, | 119 | { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs }, |
110 | {} | 120 | {} |
111 | }; | 121 | }; |
112 | 122 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c index f25760209316..07b4b2d33bd2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c | |||
@@ -22,8 +22,9 @@ | |||
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <core/os.h> | 25 | #include <core/client.h> |
26 | #include <core/class.h> | 26 | #include <nvif/unpack.h> |
27 | #include <nvif/class.h> | ||
27 | #include <core/engctx.h> | 28 | #include <core/engctx.h> |
28 | #include <core/ramht.h> | 29 | #include <core/ramht.h> |
29 | 30 | ||
@@ -64,16 +65,23 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent, | |||
64 | struct nouveau_oclass *oclass, void *data, u32 size, | 65 | struct nouveau_oclass *oclass, void *data, u32 size, |
65 | struct nouveau_object **pobject) | 66 | struct nouveau_object **pobject) |
66 | { | 67 | { |
68 | union { | ||
69 | struct nv03_channel_dma_v0 v0; | ||
70 | } *args = data; | ||
67 | struct nv04_fifo_priv *priv = (void *)engine; | 71 | struct nv04_fifo_priv *priv = (void *)engine; |
68 | struct nv04_fifo_chan *chan; | 72 | struct nv04_fifo_chan *chan; |
69 | struct nv03_channel_dma_class *args = data; | ||
70 | int ret; | 73 | int ret; |
71 | 74 | ||
72 | if (size < sizeof(*args)) | 75 | nv_ioctl(parent, "create channel dma size %d\n", size); |
73 | return -EINVAL; | 76 | if (nvif_unpack(args->v0, 0, 0, false)) { |
77 | nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " | ||
78 | "offset %016llx\n", args->v0.version, | ||
79 | args->v0.pushbuf, args->v0.offset); | ||
80 | } else | ||
81 | return ret; | ||
74 | 82 | ||
75 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, | 83 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, |
76 | 0x10000, args->pushbuf, | 84 | 0x10000, args->v0.pushbuf, |
77 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | 85 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
78 | (1ULL << NVDEV_ENGINE_SW) | | 86 | (1ULL << NVDEV_ENGINE_SW) | |
79 | (1ULL << NVDEV_ENGINE_GR) | | 87 | (1ULL << NVDEV_ENGINE_GR) | |
@@ -83,13 +91,15 @@ nv17_fifo_chan_ctor(struct nouveau_object *parent, | |||
83 | if (ret) | 91 | if (ret) |
84 | return ret; | 92 | return ret; |
85 | 93 | ||
94 | args->v0.chid = chan->base.chid; | ||
95 | |||
86 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; | 96 | nv_parent(chan)->object_attach = nv04_fifo_object_attach; |
87 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | 97 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
88 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; | 98 | nv_parent(chan)->context_attach = nv04_fifo_context_attach; |
89 | chan->ramfc = chan->base.chid * 64; | 99 | chan->ramfc = chan->base.chid * 64; |
90 | 100 | ||
91 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); | 101 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); |
92 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); | 102 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); |
93 | nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); | 103 | nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); |
94 | nv_wo32(priv->ramfc, chan->ramfc + 0x14, | 104 | nv_wo32(priv->ramfc, chan->ramfc + 0x14, |
95 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | | 105 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
@@ -113,7 +123,7 @@ nv17_fifo_ofuncs = { | |||
113 | 123 | ||
114 | static struct nouveau_oclass | 124 | static struct nouveau_oclass |
115 | nv17_fifo_sclass[] = { | 125 | nv17_fifo_sclass[] = { |
116 | { NV17_CHANNEL_DMA_CLASS, &nv17_fifo_ofuncs }, | 126 | { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, |
117 | {} | 127 | {} |
118 | }; | 128 | }; |
119 | 129 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c index 343487ed2238..0aa3a1387742 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c | |||
@@ -22,8 +22,9 @@ | |||
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <core/os.h> | 25 | #include <core/client.h> |
26 | #include <core/class.h> | 26 | #include <nvif/unpack.h> |
27 | #include <nvif/class.h> | ||
27 | #include <core/engctx.h> | 28 | #include <core/engctx.h> |
28 | #include <core/ramht.h> | 29 | #include <core/ramht.h> |
29 | 30 | ||
@@ -182,16 +183,23 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent, | |||
182 | struct nouveau_oclass *oclass, void *data, u32 size, | 183 | struct nouveau_oclass *oclass, void *data, u32 size, |
183 | struct nouveau_object **pobject) | 184 | struct nouveau_object **pobject) |
184 | { | 185 | { |
186 | union { | ||
187 | struct nv03_channel_dma_v0 v0; | ||
188 | } *args = data; | ||
185 | struct nv04_fifo_priv *priv = (void *)engine; | 189 | struct nv04_fifo_priv *priv = (void *)engine; |
186 | struct nv04_fifo_chan *chan; | 190 | struct nv04_fifo_chan *chan; |
187 | struct nv03_channel_dma_class *args = data; | ||
188 | int ret; | 191 | int ret; |
189 | 192 | ||
190 | if (size < sizeof(*args)) | 193 | nv_ioctl(parent, "create channel dma size %d\n", size); |
191 | return -EINVAL; | 194 | if (nvif_unpack(args->v0, 0, 0, false)) { |
195 | nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " | ||
196 | "offset %016llx\n", args->v0.version, | ||
197 | args->v0.pushbuf, args->v0.offset); | ||
198 | } else | ||
199 | return ret; | ||
192 | 200 | ||
193 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, | 201 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, |
194 | 0x1000, args->pushbuf, | 202 | 0x1000, args->v0.pushbuf, |
195 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | 203 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
196 | (1ULL << NVDEV_ENGINE_SW) | | 204 | (1ULL << NVDEV_ENGINE_SW) | |
197 | (1ULL << NVDEV_ENGINE_GR) | | 205 | (1ULL << NVDEV_ENGINE_GR) | |
@@ -200,14 +208,16 @@ nv40_fifo_chan_ctor(struct nouveau_object *parent, | |||
200 | if (ret) | 208 | if (ret) |
201 | return ret; | 209 | return ret; |
202 | 210 | ||
211 | args->v0.chid = chan->base.chid; | ||
212 | |||
203 | nv_parent(chan)->context_attach = nv40_fifo_context_attach; | 213 | nv_parent(chan)->context_attach = nv40_fifo_context_attach; |
204 | nv_parent(chan)->context_detach = nv40_fifo_context_detach; | 214 | nv_parent(chan)->context_detach = nv40_fifo_context_detach; |
205 | nv_parent(chan)->object_attach = nv40_fifo_object_attach; | 215 | nv_parent(chan)->object_attach = nv40_fifo_object_attach; |
206 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; | 216 | nv_parent(chan)->object_detach = nv04_fifo_object_detach; |
207 | chan->ramfc = chan->base.chid * 128; | 217 | chan->ramfc = chan->base.chid * 128; |
208 | 218 | ||
209 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); | 219 | nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); |
210 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); | 220 | nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); |
211 | nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); | 221 | nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); |
212 | nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 | | 222 | nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 | |
213 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | | 223 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
@@ -232,7 +242,7 @@ nv40_fifo_ofuncs = { | |||
232 | 242 | ||
233 | static struct nouveau_oclass | 243 | static struct nouveau_oclass |
234 | nv40_fifo_sclass[] = { | 244 | nv40_fifo_sclass[] = { |
235 | { NV40_CHANNEL_DMA_CLASS, &nv40_fifo_ofuncs }, | 245 | { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs }, |
236 | {} | 246 | {} |
237 | }; | 247 | }; |
238 | 248 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c index e6352bd5b4ff..ffc74f1ea30f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | |||
@@ -25,7 +25,8 @@ | |||
25 | #include <core/client.h> | 25 | #include <core/client.h> |
26 | #include <core/engctx.h> | 26 | #include <core/engctx.h> |
27 | #include <core/ramht.h> | 27 | #include <core/ramht.h> |
28 | #include <core/class.h> | 28 | #include <nvif/unpack.h> |
29 | #include <nvif/class.h> | ||
29 | 30 | ||
30 | #include <subdev/timer.h> | 31 | #include <subdev/timer.h> |
31 | #include <subdev/bar.h> | 32 | #include <subdev/bar.h> |
@@ -194,17 +195,24 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, | |||
194 | struct nouveau_oclass *oclass, void *data, u32 size, | 195 | struct nouveau_oclass *oclass, void *data, u32 size, |
195 | struct nouveau_object **pobject) | 196 | struct nouveau_object **pobject) |
196 | { | 197 | { |
198 | union { | ||
199 | struct nv03_channel_dma_v0 v0; | ||
200 | } *args = data; | ||
197 | struct nouveau_bar *bar = nouveau_bar(parent); | 201 | struct nouveau_bar *bar = nouveau_bar(parent); |
198 | struct nv50_fifo_base *base = (void *)parent; | 202 | struct nv50_fifo_base *base = (void *)parent; |
199 | struct nv50_fifo_chan *chan; | 203 | struct nv50_fifo_chan *chan; |
200 | struct nv03_channel_dma_class *args = data; | ||
201 | int ret; | 204 | int ret; |
202 | 205 | ||
203 | if (size < sizeof(*args)) | 206 | nv_ioctl(parent, "create channel dma size %d\n", size); |
204 | return -EINVAL; | 207 | if (nvif_unpack(args->v0, 0, 0, false)) { |
208 | nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " | ||
209 | "offset %016llx\n", args->v0.version, | ||
210 | args->v0.pushbuf, args->v0.offset); | ||
211 | } else | ||
212 | return ret; | ||
205 | 213 | ||
206 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, | 214 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, |
207 | 0x2000, args->pushbuf, | 215 | 0x2000, args->v0.pushbuf, |
208 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | 216 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
209 | (1ULL << NVDEV_ENGINE_SW) | | 217 | (1ULL << NVDEV_ENGINE_SW) | |
210 | (1ULL << NVDEV_ENGINE_GR) | | 218 | (1ULL << NVDEV_ENGINE_GR) | |
@@ -213,6 +221,8 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, | |||
213 | if (ret) | 221 | if (ret) |
214 | return ret; | 222 | return ret; |
215 | 223 | ||
224 | args->v0.chid = chan->base.chid; | ||
225 | |||
216 | nv_parent(chan)->context_attach = nv50_fifo_context_attach; | 226 | nv_parent(chan)->context_attach = nv50_fifo_context_attach; |
217 | nv_parent(chan)->context_detach = nv50_fifo_context_detach; | 227 | nv_parent(chan)->context_detach = nv50_fifo_context_detach; |
218 | nv_parent(chan)->object_attach = nv50_fifo_object_attach; | 228 | nv_parent(chan)->object_attach = nv50_fifo_object_attach; |
@@ -223,10 +233,10 @@ nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, | |||
223 | if (ret) | 233 | if (ret) |
224 | return ret; | 234 | return ret; |
225 | 235 | ||
226 | nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset)); | 236 | nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); |
227 | nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset)); | 237 | nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); |
228 | nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset)); | 238 | nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); |
229 | nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset)); | 239 | nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); |
230 | nv_wo32(base->ramfc, 0x3c, 0x003f6078); | 240 | nv_wo32(base->ramfc, 0x3c, 0x003f6078); |
231 | nv_wo32(base->ramfc, 0x44, 0x01003fff); | 241 | nv_wo32(base->ramfc, 0x44, 0x01003fff); |
232 | nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); | 242 | nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); |
@@ -247,18 +257,26 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, | |||
247 | struct nouveau_oclass *oclass, void *data, u32 size, | 257 | struct nouveau_oclass *oclass, void *data, u32 size, |
248 | struct nouveau_object **pobject) | 258 | struct nouveau_object **pobject) |
249 | { | 259 | { |
250 | struct nv50_channel_ind_class *args = data; | 260 | union { |
261 | struct nv50_channel_gpfifo_v0 v0; | ||
262 | } *args = data; | ||
251 | struct nouveau_bar *bar = nouveau_bar(parent); | 263 | struct nouveau_bar *bar = nouveau_bar(parent); |
252 | struct nv50_fifo_base *base = (void *)parent; | 264 | struct nv50_fifo_base *base = (void *)parent; |
253 | struct nv50_fifo_chan *chan; | 265 | struct nv50_fifo_chan *chan; |
254 | u64 ioffset, ilength; | 266 | u64 ioffset, ilength; |
255 | int ret; | 267 | int ret; |
256 | 268 | ||
257 | if (size < sizeof(*args)) | 269 | nv_ioctl(parent, "create channel gpfifo size %d\n", size); |
258 | return -EINVAL; | 270 | if (nvif_unpack(args->v0, 0, 0, false)) { |
271 | nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " | ||
272 | "ioffset %016llx ilength %08x\n", | ||
273 | args->v0.version, args->v0.pushbuf, args->v0.ioffset, | ||
274 | args->v0.ilength); | ||
275 | } else | ||
276 | return ret; | ||
259 | 277 | ||
260 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, | 278 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, |
261 | 0x2000, args->pushbuf, | 279 | 0x2000, args->v0.pushbuf, |
262 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | 280 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
263 | (1ULL << NVDEV_ENGINE_SW) | | 281 | (1ULL << NVDEV_ENGINE_SW) | |
264 | (1ULL << NVDEV_ENGINE_GR) | | 282 | (1ULL << NVDEV_ENGINE_GR) | |
@@ -267,6 +285,8 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, | |||
267 | if (ret) | 285 | if (ret) |
268 | return ret; | 286 | return ret; |
269 | 287 | ||
288 | args->v0.chid = chan->base.chid; | ||
289 | |||
270 | nv_parent(chan)->context_attach = nv50_fifo_context_attach; | 290 | nv_parent(chan)->context_attach = nv50_fifo_context_attach; |
271 | nv_parent(chan)->context_detach = nv50_fifo_context_detach; | 291 | nv_parent(chan)->context_detach = nv50_fifo_context_detach; |
272 | nv_parent(chan)->object_attach = nv50_fifo_object_attach; | 292 | nv_parent(chan)->object_attach = nv50_fifo_object_attach; |
@@ -277,8 +297,8 @@ nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, | |||
277 | if (ret) | 297 | if (ret) |
278 | return ret; | 298 | return ret; |
279 | 299 | ||
280 | ioffset = args->ioffset; | 300 | ioffset = args->v0.ioffset; |
281 | ilength = order_base_2(args->ilength / 8); | 301 | ilength = order_base_2(args->v0.ilength / 8); |
282 | 302 | ||
283 | nv_wo32(base->ramfc, 0x3c, 0x403f6078); | 303 | nv_wo32(base->ramfc, 0x3c, 0x403f6078); |
284 | nv_wo32(base->ramfc, 0x44, 0x01003fff); | 304 | nv_wo32(base->ramfc, 0x44, 0x01003fff); |
@@ -359,8 +379,8 @@ nv50_fifo_ofuncs_ind = { | |||
359 | 379 | ||
360 | static struct nouveau_oclass | 380 | static struct nouveau_oclass |
361 | nv50_fifo_sclass[] = { | 381 | nv50_fifo_sclass[] = { |
362 | { NV50_CHANNEL_DMA_CLASS, &nv50_fifo_ofuncs_dma }, | 382 | { NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma }, |
363 | { NV50_CHANNEL_IND_CLASS, &nv50_fifo_ofuncs_ind }, | 383 | { NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind }, |
364 | {} | 384 | {} |
365 | }; | 385 | }; |
366 | 386 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c index 0bf844d6db8a..bb9017377889 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c | |||
@@ -27,7 +27,8 @@ | |||
27 | #include <core/engctx.h> | 27 | #include <core/engctx.h> |
28 | #include <core/ramht.h> | 28 | #include <core/ramht.h> |
29 | #include <core/event.h> | 29 | #include <core/event.h> |
30 | #include <core/class.h> | 30 | #include <nvif/unpack.h> |
31 | #include <nvif/class.h> | ||
31 | 32 | ||
32 | #include <subdev/timer.h> | 33 | #include <subdev/timer.h> |
33 | #include <subdev/bar.h> | 34 | #include <subdev/bar.h> |
@@ -160,17 +161,24 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, | |||
160 | struct nouveau_oclass *oclass, void *data, u32 size, | 161 | struct nouveau_oclass *oclass, void *data, u32 size, |
161 | struct nouveau_object **pobject) | 162 | struct nouveau_object **pobject) |
162 | { | 163 | { |
164 | union { | ||
165 | struct nv03_channel_dma_v0 v0; | ||
166 | } *args = data; | ||
163 | struct nouveau_bar *bar = nouveau_bar(parent); | 167 | struct nouveau_bar *bar = nouveau_bar(parent); |
164 | struct nv50_fifo_base *base = (void *)parent; | 168 | struct nv50_fifo_base *base = (void *)parent; |
165 | struct nv50_fifo_chan *chan; | 169 | struct nv50_fifo_chan *chan; |
166 | struct nv03_channel_dma_class *args = data; | ||
167 | int ret; | 170 | int ret; |
168 | 171 | ||
169 | if (size < sizeof(*args)) | 172 | nv_ioctl(parent, "create channel dma size %d\n", size); |
170 | return -EINVAL; | 173 | if (nvif_unpack(args->v0, 0, 0, false)) { |
174 | nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " | ||
175 | "offset %016llx\n", args->v0.version, | ||
176 | args->v0.pushbuf, args->v0.offset); | ||
177 | } else | ||
178 | return ret; | ||
171 | 179 | ||
172 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, | 180 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, |
173 | 0x2000, args->pushbuf, | 181 | 0x2000, args->v0.pushbuf, |
174 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | 182 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
175 | (1ULL << NVDEV_ENGINE_SW) | | 183 | (1ULL << NVDEV_ENGINE_SW) | |
176 | (1ULL << NVDEV_ENGINE_GR) | | 184 | (1ULL << NVDEV_ENGINE_GR) | |
@@ -186,6 +194,8 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, | |||
186 | if (ret) | 194 | if (ret) |
187 | return ret; | 195 | return ret; |
188 | 196 | ||
197 | args->v0.chid = chan->base.chid; | ||
198 | |||
189 | ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, | 199 | ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, |
190 | &chan->ramht); | 200 | &chan->ramht); |
191 | if (ret) | 201 | if (ret) |
@@ -196,10 +206,10 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, | |||
196 | nv_parent(chan)->object_attach = nv84_fifo_object_attach; | 206 | nv_parent(chan)->object_attach = nv84_fifo_object_attach; |
197 | nv_parent(chan)->object_detach = nv50_fifo_object_detach; | 207 | nv_parent(chan)->object_detach = nv50_fifo_object_detach; |
198 | 208 | ||
199 | nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset)); | 209 | nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); |
200 | nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset)); | 210 | nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); |
201 | nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset)); | 211 | nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); |
202 | nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset)); | 212 | nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); |
203 | nv_wo32(base->ramfc, 0x3c, 0x003f6078); | 213 | nv_wo32(base->ramfc, 0x3c, 0x003f6078); |
204 | nv_wo32(base->ramfc, 0x44, 0x01003fff); | 214 | nv_wo32(base->ramfc, 0x44, 0x01003fff); |
205 | nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); | 215 | nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); |
@@ -222,18 +232,26 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, | |||
222 | struct nouveau_oclass *oclass, void *data, u32 size, | 232 | struct nouveau_oclass *oclass, void *data, u32 size, |
223 | struct nouveau_object **pobject) | 233 | struct nouveau_object **pobject) |
224 | { | 234 | { |
235 | union { | ||
236 | struct nv50_channel_gpfifo_v0 v0; | ||
237 | } *args = data; | ||
225 | struct nouveau_bar *bar = nouveau_bar(parent); | 238 | struct nouveau_bar *bar = nouveau_bar(parent); |
226 | struct nv50_fifo_base *base = (void *)parent; | 239 | struct nv50_fifo_base *base = (void *)parent; |
227 | struct nv50_fifo_chan *chan; | 240 | struct nv50_fifo_chan *chan; |
228 | struct nv50_channel_ind_class *args = data; | ||
229 | u64 ioffset, ilength; | 241 | u64 ioffset, ilength; |
230 | int ret; | 242 | int ret; |
231 | 243 | ||
232 | if (size < sizeof(*args)) | 244 | nv_ioctl(parent, "create channel gpfifo size %d\n", size); |
233 | return -EINVAL; | 245 | if (nvif_unpack(args->v0, 0, 0, false)) { |
246 | nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " | ||
247 | "ioffset %016llx ilength %08x\n", | ||
248 | args->v0.version, args->v0.pushbuf, args->v0.ioffset, | ||
249 | args->v0.ilength); | ||
250 | } else | ||
251 | return ret; | ||
234 | 252 | ||
235 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, | 253 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, |
236 | 0x2000, args->pushbuf, | 254 | 0x2000, args->v0.pushbuf, |
237 | (1ULL << NVDEV_ENGINE_DMAOBJ) | | 255 | (1ULL << NVDEV_ENGINE_DMAOBJ) | |
238 | (1ULL << NVDEV_ENGINE_SW) | | 256 | (1ULL << NVDEV_ENGINE_SW) | |
239 | (1ULL << NVDEV_ENGINE_GR) | | 257 | (1ULL << NVDEV_ENGINE_GR) | |
@@ -249,6 +267,8 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, | |||
249 | if (ret) | 267 | if (ret) |
250 | return ret; | 268 | return ret; |
251 | 269 | ||
270 | args->v0.chid = chan->base.chid; | ||
271 | |||
252 | ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, | 272 | ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, |
253 | &chan->ramht); | 273 | &chan->ramht); |
254 | if (ret) | 274 | if (ret) |
@@ -259,8 +279,8 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, | |||
259 | nv_parent(chan)->object_attach = nv84_fifo_object_attach; | 279 | nv_parent(chan)->object_attach = nv84_fifo_object_attach; |
260 | nv_parent(chan)->object_detach = nv50_fifo_object_detach; | 280 | nv_parent(chan)->object_detach = nv50_fifo_object_detach; |
261 | 281 | ||
262 | ioffset = args->ioffset; | 282 | ioffset = args->v0.ioffset; |
263 | ilength = order_base_2(args->ilength / 8); | 283 | ilength = order_base_2(args->v0.ilength / 8); |
264 | 284 | ||
265 | nv_wo32(base->ramfc, 0x3c, 0x403f6078); | 285 | nv_wo32(base->ramfc, 0x3c, 0x403f6078); |
266 | nv_wo32(base->ramfc, 0x44, 0x01003fff); | 286 | nv_wo32(base->ramfc, 0x44, 0x01003fff); |
@@ -320,8 +340,8 @@ nv84_fifo_ofuncs_ind = { | |||
320 | 340 | ||
321 | static struct nouveau_oclass | 341 | static struct nouveau_oclass |
322 | nv84_fifo_sclass[] = { | 342 | nv84_fifo_sclass[] = { |
323 | { NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma }, | 343 | { G82_CHANNEL_DMA, &nv84_fifo_ofuncs_dma }, |
324 | { NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind }, | 344 | { G82_CHANNEL_GPFIFO, &nv84_fifo_ofuncs_ind }, |
325 | {} | 345 | {} |
326 | }; | 346 | }; |
327 | 347 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c index bd7bf3c65bc6..c4a1e1122c93 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | |||
@@ -28,7 +28,8 @@ | |||
28 | #include <core/gpuobj.h> | 28 | #include <core/gpuobj.h> |
29 | #include <core/engctx.h> | 29 | #include <core/engctx.h> |
30 | #include <core/event.h> | 30 | #include <core/event.h> |
31 | #include <core/class.h> | 31 | #include <nvif/unpack.h> |
32 | #include <nvif/class.h> | ||
32 | #include <core/enum.h> | 33 | #include <core/enum.h> |
33 | 34 | ||
34 | #include <subdev/timer.h> | 35 | #include <subdev/timer.h> |
@@ -187,20 +188,28 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent, | |||
187 | struct nouveau_oclass *oclass, void *data, u32 size, | 188 | struct nouveau_oclass *oclass, void *data, u32 size, |
188 | struct nouveau_object **pobject) | 189 | struct nouveau_object **pobject) |
189 | { | 190 | { |
191 | union { | ||
192 | struct nv50_channel_gpfifo_v0 v0; | ||
193 | } *args = data; | ||
190 | struct nouveau_bar *bar = nouveau_bar(parent); | 194 | struct nouveau_bar *bar = nouveau_bar(parent); |
191 | struct nvc0_fifo_priv *priv = (void *)engine; | 195 | struct nvc0_fifo_priv *priv = (void *)engine; |
192 | struct nvc0_fifo_base *base = (void *)parent; | 196 | struct nvc0_fifo_base *base = (void *)parent; |
193 | struct nvc0_fifo_chan *chan; | 197 | struct nvc0_fifo_chan *chan; |
194 | struct nv50_channel_ind_class *args = data; | ||
195 | u64 usermem, ioffset, ilength; | 198 | u64 usermem, ioffset, ilength; |
196 | int ret, i; | 199 | int ret, i; |
197 | 200 | ||
198 | if (size < sizeof(*args)) | 201 | nv_ioctl(parent, "create channel gpfifo size %d\n", size); |
199 | return -EINVAL; | 202 | if (nvif_unpack(args->v0, 0, 0, false)) { |
203 | nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " | ||
204 | "ioffset %016llx ilength %08x\n", | ||
205 | args->v0.version, args->v0.pushbuf, args->v0.ioffset, | ||
206 | args->v0.ilength); | ||
207 | } else | ||
208 | return ret; | ||
200 | 209 | ||
201 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, | 210 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, |
202 | priv->user.bar.offset, 0x1000, | 211 | priv->user.bar.offset, 0x1000, |
203 | args->pushbuf, | 212 | args->v0.pushbuf, |
204 | (1ULL << NVDEV_ENGINE_SW) | | 213 | (1ULL << NVDEV_ENGINE_SW) | |
205 | (1ULL << NVDEV_ENGINE_GR) | | 214 | (1ULL << NVDEV_ENGINE_GR) | |
206 | (1ULL << NVDEV_ENGINE_COPY0) | | 215 | (1ULL << NVDEV_ENGINE_COPY0) | |
@@ -212,12 +221,14 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent, | |||
212 | if (ret) | 221 | if (ret) |
213 | return ret; | 222 | return ret; |
214 | 223 | ||
224 | args->v0.chid = chan->base.chid; | ||
225 | |||
215 | nv_parent(chan)->context_attach = nvc0_fifo_context_attach; | 226 | nv_parent(chan)->context_attach = nvc0_fifo_context_attach; |
216 | nv_parent(chan)->context_detach = nvc0_fifo_context_detach; | 227 | nv_parent(chan)->context_detach = nvc0_fifo_context_detach; |
217 | 228 | ||
218 | usermem = chan->base.chid * 0x1000; | 229 | usermem = chan->base.chid * 0x1000; |
219 | ioffset = args->ioffset; | 230 | ioffset = args->v0.ioffset; |
220 | ilength = order_base_2(args->ilength / 8); | 231 | ilength = order_base_2(args->v0.ilength / 8); |
221 | 232 | ||
222 | for (i = 0; i < 0x1000; i += 4) | 233 | for (i = 0; i < 0x1000; i += 4) |
223 | nv_wo32(priv->user.mem, usermem + i, 0x00000000); | 234 | nv_wo32(priv->user.mem, usermem + i, 0x00000000); |
@@ -297,7 +308,7 @@ nvc0_fifo_ofuncs = { | |||
297 | 308 | ||
298 | static struct nouveau_oclass | 309 | static struct nouveau_oclass |
299 | nvc0_fifo_sclass[] = { | 310 | nvc0_fifo_sclass[] = { |
300 | { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs }, | 311 | { FERMI_CHANNEL_GPFIFO, &nvc0_fifo_ofuncs }, |
301 | {} | 312 | {} |
302 | }; | 313 | }; |
303 | 314 | ||
@@ -654,7 +665,7 @@ nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) | |||
654 | object = engctx; | 665 | object = engctx; |
655 | while (object) { | 666 | while (object) { |
656 | switch (nv_mclass(object)) { | 667 | switch (nv_mclass(object)) { |
657 | case NVC0_CHANNEL_IND_CLASS: | 668 | case FERMI_CHANNEL_GPFIFO: |
658 | nvc0_fifo_recover(priv, engine, (void *)object); | 669 | nvc0_fifo_recover(priv, engine, (void *)object); |
659 | break; | 670 | break; |
660 | } | 671 | } |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index 3e7f03dc822f..96b14b7873f1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | |||
@@ -28,7 +28,8 @@ | |||
28 | #include <core/gpuobj.h> | 28 | #include <core/gpuobj.h> |
29 | #include <core/engctx.h> | 29 | #include <core/engctx.h> |
30 | #include <core/event.h> | 30 | #include <core/event.h> |
31 | #include <core/class.h> | 31 | #include <nvif/unpack.h> |
32 | #include <nvif/class.h> | ||
32 | #include <core/enum.h> | 33 | #include <core/enum.h> |
33 | 34 | ||
34 | #include <subdev/timer.h> | 35 | #include <subdev/timer.h> |
@@ -216,46 +217,56 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent, | |||
216 | struct nouveau_oclass *oclass, void *data, u32 size, | 217 | struct nouveau_oclass *oclass, void *data, u32 size, |
217 | struct nouveau_object **pobject) | 218 | struct nouveau_object **pobject) |
218 | { | 219 | { |
220 | union { | ||
221 | struct kepler_channel_gpfifo_a_v0 v0; | ||
222 | } *args = data; | ||
219 | struct nouveau_bar *bar = nouveau_bar(parent); | 223 | struct nouveau_bar *bar = nouveau_bar(parent); |
220 | struct nve0_fifo_priv *priv = (void *)engine; | 224 | struct nve0_fifo_priv *priv = (void *)engine; |
221 | struct nve0_fifo_base *base = (void *)parent; | 225 | struct nve0_fifo_base *base = (void *)parent; |
222 | struct nve0_fifo_chan *chan; | 226 | struct nve0_fifo_chan *chan; |
223 | struct nve0_channel_ind_class *args = data; | ||
224 | u64 usermem, ioffset, ilength; | 227 | u64 usermem, ioffset, ilength; |
225 | int ret, i; | 228 | int ret, i; |
226 | 229 | ||
227 | if (size < sizeof(*args)) | 230 | nv_ioctl(parent, "create channel gpfifo size %d\n", size); |
228 | return -EINVAL; | 231 | if (nvif_unpack(args->v0, 0, 0, false)) { |
232 | nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " | ||
233 | "ioffset %016llx ilength %08x engine %08x\n", | ||
234 | args->v0.version, args->v0.pushbuf, args->v0.ioffset, | ||
235 | args->v0.ilength, args->v0.engine); | ||
236 | } else | ||
237 | return ret; | ||
229 | 238 | ||
230 | for (i = 0; i < FIFO_ENGINE_NR; i++) { | 239 | for (i = 0; i < FIFO_ENGINE_NR; i++) { |
231 | if (args->engine & (1 << i)) { | 240 | if (args->v0.engine & (1 << i)) { |
232 | if (nouveau_engine(parent, fifo_engine[i].subdev)) { | 241 | if (nouveau_engine(parent, fifo_engine[i].subdev)) { |
233 | args->engine = (1 << i); | 242 | args->v0.engine = (1 << i); |
234 | break; | 243 | break; |
235 | } | 244 | } |
236 | } | 245 | } |
237 | } | 246 | } |
238 | 247 | ||
239 | if (i == FIFO_ENGINE_NR) { | 248 | if (i == FIFO_ENGINE_NR) { |
240 | nv_error(priv, "unsupported engines 0x%08x\n", args->engine); | 249 | nv_error(priv, "unsupported engines 0x%08x\n", args->v0.engine); |
241 | return -ENODEV; | 250 | return -ENODEV; |
242 | } | 251 | } |
243 | 252 | ||
244 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, | 253 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, |
245 | priv->user.bar.offset, 0x200, | 254 | priv->user.bar.offset, 0x200, |
246 | args->pushbuf, | 255 | args->v0.pushbuf, |
247 | fifo_engine[i].mask, &chan); | 256 | fifo_engine[i].mask, &chan); |
248 | *pobject = nv_object(chan); | 257 | *pobject = nv_object(chan); |
249 | if (ret) | 258 | if (ret) |
250 | return ret; | 259 | return ret; |
251 | 260 | ||
261 | args->v0.chid = chan->base.chid; | ||
262 | |||
252 | nv_parent(chan)->context_attach = nve0_fifo_context_attach; | 263 | nv_parent(chan)->context_attach = nve0_fifo_context_attach; |
253 | nv_parent(chan)->context_detach = nve0_fifo_context_detach; | 264 | nv_parent(chan)->context_detach = nve0_fifo_context_detach; |
254 | chan->engine = i; | 265 | chan->engine = i; |
255 | 266 | ||
256 | usermem = chan->base.chid * 0x200; | 267 | usermem = chan->base.chid * 0x200; |
257 | ioffset = args->ioffset; | 268 | ioffset = args->v0.ioffset; |
258 | ilength = order_base_2(args->ilength / 8); | 269 | ilength = order_base_2(args->v0.ilength / 8); |
259 | 270 | ||
260 | for (i = 0; i < 0x200; i += 4) | 271 | for (i = 0; i < 0x200; i += 4) |
261 | nv_wo32(priv->user.mem, usermem + i, 0x00000000); | 272 | nv_wo32(priv->user.mem, usermem + i, 0x00000000); |
@@ -331,7 +342,7 @@ nve0_fifo_ofuncs = { | |||
331 | 342 | ||
332 | static struct nouveau_oclass | 343 | static struct nouveau_oclass |
333 | nve0_fifo_sclass[] = { | 344 | nve0_fifo_sclass[] = { |
334 | { NVE0_CHANNEL_IND_CLASS, &nve0_fifo_ofuncs }, | 345 | { KEPLER_CHANNEL_GPFIFO_A, &nve0_fifo_ofuncs }, |
335 | {} | 346 | {} |
336 | }; | 347 | }; |
337 | 348 | ||
@@ -769,7 +780,7 @@ nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) | |||
769 | object = engctx; | 780 | object = engctx; |
770 | while (object) { | 781 | while (object) { |
771 | switch (nv_mclass(object)) { | 782 | switch (nv_mclass(object)) { |
772 | case NVE0_CHANNEL_IND_CLASS: | 783 | case KEPLER_CHANNEL_GPFIFO_A: |
773 | nve0_fifo_recover(priv, engine, (void *)object); | 784 | nve0_fifo_recover(priv, engine, (void *)object); |
774 | break; | 785 | break; |
775 | } | 786 | } |
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h index 79de03bdff96..d3180e51ce62 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/class.h +++ b/drivers/gpu/drm/nouveau/core/include/core/class.h | |||
@@ -3,62 +3,6 @@ | |||
3 | 3 | ||
4 | #include <nvif/class.h> | 4 | #include <nvif/class.h> |
5 | 5 | ||
6 | /* DMA FIFO channel classes | ||
7 | * | ||
8 | * 006b: NV03_CHANNEL_DMA | ||
9 | * 006e: NV10_CHANNEL_DMA | ||
10 | * 176e: NV17_CHANNEL_DMA | ||
11 | * 406e: NV40_CHANNEL_DMA | ||
12 | * 506e: NV50_CHANNEL_DMA | ||
13 | * 826e: NV84_CHANNEL_DMA | ||
14 | */ | ||
15 | #define NV03_CHANNEL_DMA_CLASS 0x0000006b | ||
16 | #define NV10_CHANNEL_DMA_CLASS 0x0000006e | ||
17 | #define NV17_CHANNEL_DMA_CLASS 0x0000176e | ||
18 | #define NV40_CHANNEL_DMA_CLASS 0x0000406e | ||
19 | #define NV50_CHANNEL_DMA_CLASS 0x0000506e | ||
20 | #define NV84_CHANNEL_DMA_CLASS 0x0000826e | ||
21 | |||
22 | struct nv03_channel_dma_class { | ||
23 | u32 pushbuf; | ||
24 | u32 pad0; | ||
25 | u64 offset; | ||
26 | }; | ||
27 | |||
28 | /* Indirect FIFO channel classes | ||
29 | * | ||
30 | * 506f: NV50_CHANNEL_IND | ||
31 | * 826f: NV84_CHANNEL_IND | ||
32 | * 906f: NVC0_CHANNEL_IND | ||
33 | * a06f: NVE0_CHANNEL_IND | ||
34 | */ | ||
35 | |||
36 | #define NV50_CHANNEL_IND_CLASS 0x0000506f | ||
37 | #define NV84_CHANNEL_IND_CLASS 0x0000826f | ||
38 | #define NVC0_CHANNEL_IND_CLASS 0x0000906f | ||
39 | #define NVE0_CHANNEL_IND_CLASS 0x0000a06f | ||
40 | |||
41 | struct nv50_channel_ind_class { | ||
42 | u32 pushbuf; | ||
43 | u32 ilength; | ||
44 | u64 ioffset; | ||
45 | }; | ||
46 | |||
47 | #define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001 | ||
48 | #define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002 | ||
49 | #define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004 | ||
50 | #define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008 | ||
51 | #define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010 | ||
52 | #define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020 | ||
53 | #define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040 | ||
54 | |||
55 | struct nve0_channel_ind_class { | ||
56 | u32 pushbuf; | ||
57 | u32 ilength; | ||
58 | u64 ioffset; | ||
59 | u32 engine; | ||
60 | }; | ||
61 | |||
62 | /* 0046: NV04_DISP | 6 | /* 0046: NV04_DISP |
63 | */ | 7 | */ |
64 | 8 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 0325db93a7d5..43dfc3e83409 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c | |||
@@ -257,13 +257,13 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) | |||
257 | /* hack to allow channel engine type specification on kepler */ | 257 | /* hack to allow channel engine type specification on kepler */ |
258 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { | 258 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { |
259 | if (init->fb_ctxdma_handle != ~0) | 259 | if (init->fb_ctxdma_handle != ~0) |
260 | init->fb_ctxdma_handle = NVE0_CHANNEL_IND_ENGINE_GR; | 260 | init->fb_ctxdma_handle = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR; |
261 | else | 261 | else |
262 | init->fb_ctxdma_handle = init->tt_ctxdma_handle; | 262 | init->fb_ctxdma_handle = init->tt_ctxdma_handle; |
263 | 263 | ||
264 | /* allow flips to be executed if this is a graphics channel */ | 264 | /* allow flips to be executed if this is a graphics channel */ |
265 | init->tt_ctxdma_handle = 0; | 265 | init->tt_ctxdma_handle = 0; |
266 | if (init->fb_ctxdma_handle == NVE0_CHANNEL_IND_ENGINE_GR) | 266 | if (init->fb_ctxdma_handle == KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR) |
267 | init->tt_ctxdma_handle = 1; | 267 | init->tt_ctxdma_handle = 1; |
268 | } | 268 | } |
269 | 269 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 5ce2110b31f3..ab2d9ff45a44 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c | |||
@@ -187,14 +187,18 @@ static int | |||
187 | nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, | 187 | nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, |
188 | u32 handle, u32 engine, struct nouveau_channel **pchan) | 188 | u32 handle, u32 engine, struct nouveau_channel **pchan) |
189 | { | 189 | { |
190 | static const u16 oclasses[] = { NVE0_CHANNEL_IND_CLASS, | 190 | static const u16 oclasses[] = { KEPLER_CHANNEL_GPFIFO_A, |
191 | NVC0_CHANNEL_IND_CLASS, | 191 | FERMI_CHANNEL_GPFIFO, |
192 | NV84_CHANNEL_IND_CLASS, | 192 | G82_CHANNEL_GPFIFO, |
193 | NV50_CHANNEL_IND_CLASS, | 193 | NV50_CHANNEL_GPFIFO, |
194 | 0 }; | 194 | 0 }; |
195 | const u16 *oclass = oclasses; | 195 | const u16 *oclass = oclasses; |
196 | struct nve0_channel_ind_class args; | 196 | union { |
197 | struct nv50_channel_gpfifo_v0 nv50; | ||
198 | struct kepler_channel_gpfifo_a_v0 kepler; | ||
199 | } args, *retn; | ||
197 | struct nouveau_channel *chan; | 200 | struct nouveau_channel *chan; |
201 | u32 size; | ||
198 | int ret; | 202 | int ret; |
199 | 203 | ||
200 | /* allocate dma push buffer */ | 204 | /* allocate dma push buffer */ |
@@ -204,16 +208,32 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, | |||
204 | return ret; | 208 | return ret; |
205 | 209 | ||
206 | /* create channel object */ | 210 | /* create channel object */ |
207 | args.pushbuf = chan->push.ctxdma.handle; | ||
208 | args.ioffset = 0x10000 + chan->push.vma.offset; | ||
209 | args.ilength = 0x02000; | ||
210 | args.engine = engine; | ||
211 | |||
212 | do { | 211 | do { |
212 | if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { | ||
213 | args.kepler.version = 0; | ||
214 | args.kepler.engine = engine; | ||
215 | args.kepler.pushbuf = chan->push.ctxdma.handle; | ||
216 | args.kepler.ilength = 0x02000; | ||
217 | args.kepler.ioffset = 0x10000 + chan->push.vma.offset; | ||
218 | size = sizeof(args.kepler); | ||
219 | } else { | ||
220 | args.nv50.version = 0; | ||
221 | args.nv50.pushbuf = chan->push.ctxdma.handle; | ||
222 | args.nv50.ilength = 0x02000; | ||
223 | args.nv50.ioffset = 0x10000 + chan->push.vma.offset; | ||
224 | size = sizeof(args.nv50); | ||
225 | } | ||
226 | |||
213 | ret = nvif_object_new(nvif_object(device), handle, *oclass++, | 227 | ret = nvif_object_new(nvif_object(device), handle, *oclass++, |
214 | &args, sizeof(args), &chan->object); | 228 | &args, size, &chan->object); |
215 | if (ret == 0) | 229 | if (ret == 0) { |
230 | retn = chan->object->data; | ||
231 | if (chan->object->oclass >= KEPLER_CHANNEL_GPFIFO_A) | ||
232 | chan->chid = retn->kepler.chid; | ||
233 | else | ||
234 | chan->chid = retn->nv50.chid; | ||
216 | return ret; | 235 | return ret; |
236 | } | ||
217 | } while (*oclass); | 237 | } while (*oclass); |
218 | 238 | ||
219 | nouveau_channel_del(pchan); | 239 | nouveau_channel_del(pchan); |
@@ -224,13 +244,13 @@ static int | |||
224 | nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, | 244 | nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, |
225 | u32 handle, struct nouveau_channel **pchan) | 245 | u32 handle, struct nouveau_channel **pchan) |
226 | { | 246 | { |
227 | static const u16 oclasses[] = { NV40_CHANNEL_DMA_CLASS, | 247 | static const u16 oclasses[] = { NV40_CHANNEL_DMA, |
228 | NV17_CHANNEL_DMA_CLASS, | 248 | NV17_CHANNEL_DMA, |
229 | NV10_CHANNEL_DMA_CLASS, | 249 | NV10_CHANNEL_DMA, |
230 | NV03_CHANNEL_DMA_CLASS, | 250 | NV03_CHANNEL_DMA, |
231 | 0 }; | 251 | 0 }; |
232 | const u16 *oclass = oclasses; | 252 | const u16 *oclass = oclasses; |
233 | struct nv03_channel_dma_class args; | 253 | struct nv03_channel_dma_v0 args, *retn; |
234 | struct nouveau_channel *chan; | 254 | struct nouveau_channel *chan; |
235 | int ret; | 255 | int ret; |
236 | 256 | ||
@@ -241,14 +261,18 @@ nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, | |||
241 | return ret; | 261 | return ret; |
242 | 262 | ||
243 | /* create channel object */ | 263 | /* create channel object */ |
264 | args.version = 0; | ||
244 | args.pushbuf = chan->push.ctxdma.handle; | 265 | args.pushbuf = chan->push.ctxdma.handle; |
245 | args.offset = chan->push.vma.offset; | 266 | args.offset = chan->push.vma.offset; |
246 | 267 | ||
247 | do { | 268 | do { |
248 | ret = nvif_object_new(nvif_object(device), handle, *oclass++, | 269 | ret = nvif_object_new(nvif_object(device), handle, *oclass++, |
249 | &args, sizeof(args), &chan->object); | 270 | &args, sizeof(args), &chan->object); |
250 | if (ret == 0) | 271 | if (ret == 0) { |
272 | retn = chan->object->data; | ||
273 | chan->chid = retn->chid; | ||
251 | return ret; | 274 | return ret; |
275 | } | ||
252 | } while (ret && *oclass); | 276 | } while (ret && *oclass); |
253 | 277 | ||
254 | nouveau_channel_del(pchan); | 278 | nouveau_channel_del(pchan); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h index 2a02fd56cf18..20163709d608 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.h +++ b/drivers/gpu/drm/nouveau/nouveau_chan.h | |||
@@ -8,6 +8,8 @@ struct nouveau_channel { | |||
8 | struct nvif_device *device; | 8 | struct nvif_device *device; |
9 | struct nouveau_drm *drm; | 9 | struct nouveau_drm *drm; |
10 | 10 | ||
11 | int chid; | ||
12 | |||
11 | struct nvif_object vram; | 13 | struct nvif_object vram; |
12 | struct nvif_object gart; | 14 | struct nvif_object gart; |
13 | struct nvif_object nvsw; | 15 | struct nvif_object nvsw; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 44f168c356ca..f11b65195337 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c | |||
@@ -156,24 +156,24 @@ nouveau_accel_init(struct nouveau_drm *drm) | |||
156 | 156 | ||
157 | for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) { | 157 | for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) { |
158 | switch (sclass[i]) { | 158 | switch (sclass[i]) { |
159 | case NV03_CHANNEL_DMA_CLASS: | 159 | case NV03_CHANNEL_DMA: |
160 | ret = nv04_fence_create(drm); | 160 | ret = nv04_fence_create(drm); |
161 | break; | 161 | break; |
162 | case NV10_CHANNEL_DMA_CLASS: | 162 | case NV10_CHANNEL_DMA: |
163 | ret = nv10_fence_create(drm); | 163 | ret = nv10_fence_create(drm); |
164 | break; | 164 | break; |
165 | case NV17_CHANNEL_DMA_CLASS: | 165 | case NV17_CHANNEL_DMA: |
166 | case NV40_CHANNEL_DMA_CLASS: | 166 | case NV40_CHANNEL_DMA: |
167 | ret = nv17_fence_create(drm); | 167 | ret = nv17_fence_create(drm); |
168 | break; | 168 | break; |
169 | case NV50_CHANNEL_IND_CLASS: | 169 | case NV50_CHANNEL_GPFIFO: |
170 | ret = nv50_fence_create(drm); | 170 | ret = nv50_fence_create(drm); |
171 | break; | 171 | break; |
172 | case NV84_CHANNEL_IND_CLASS: | 172 | case G82_CHANNEL_GPFIFO: |
173 | ret = nv84_fence_create(drm); | 173 | ret = nv84_fence_create(drm); |
174 | break; | 174 | break; |
175 | case NVC0_CHANNEL_IND_CLASS: | 175 | case FERMI_CHANNEL_GPFIFO: |
176 | case NVE0_CHANNEL_IND_CLASS: | 176 | case KEPLER_CHANNEL_GPFIFO_A: |
177 | ret = nvc0_fence_create(drm); | 177 | ret = nvc0_fence_create(drm); |
178 | break; | 178 | break; |
179 | default: | 179 | default: |
@@ -189,13 +189,13 @@ nouveau_accel_init(struct nouveau_drm *drm) | |||
189 | 189 | ||
190 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { | 190 | if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { |
191 | ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1, | 191 | ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1, |
192 | NVE0_CHANNEL_IND_ENGINE_CE0 | | 192 | KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0| |
193 | NVE0_CHANNEL_IND_ENGINE_CE1, 0, | 193 | KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1, |
194 | &drm->cechan); | 194 | 0, &drm->cechan); |
195 | if (ret) | 195 | if (ret) |
196 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); | 196 | NV_ERROR(drm, "failed to create ce channel, %d\n", ret); |
197 | 197 | ||
198 | arg0 = NVE0_CHANNEL_IND_ENGINE_GR; | 198 | arg0 = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR; |
199 | arg1 = 1; | 199 | arg1 = 1; |
200 | } else | 200 | } else |
201 | if (device->info.chipset >= 0xa3 && | 201 | if (device->info.chipset >= 0xa3 && |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 5e033b603806..4f50add8e6dd 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -410,7 +410,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
410 | if (unlikely(push == NULL)) | 410 | if (unlikely(push == NULL)) |
411 | return -EBUSY; | 411 | return -EBUSY; |
412 | 412 | ||
413 | if (chan && chan->object->oclass < NV84_CHANNEL_IND_CLASS) { | 413 | if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) { |
414 | ret = RING_SPACE(chan, 8); | 414 | ret = RING_SPACE(chan, 8); |
415 | if (ret) | 415 | if (ret) |
416 | return ret; | 416 | return ret; |
@@ -424,7 +424,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
424 | OUT_RING (chan, sync->addr); | 424 | OUT_RING (chan, sync->addr); |
425 | OUT_RING (chan, sync->data); | 425 | OUT_RING (chan, sync->data); |
426 | } else | 426 | } else |
427 | if (chan && chan->object->oclass < NVC0_CHANNEL_IND_CLASS) { | 427 | if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) { |
428 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; | 428 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
429 | ret = RING_SPACE(chan, 12); | 429 | ret = RING_SPACE(chan, 12); |
430 | if (ret) | 430 | if (ret) |
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index c40fb29f9ea8..933a779c93ab 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c | |||
@@ -75,8 +75,7 @@ nv84_fence_emit(struct nouveau_fence *fence) | |||
75 | { | 75 | { |
76 | struct nouveau_channel *chan = fence->channel; | 76 | struct nouveau_channel *chan = fence->channel; |
77 | struct nv84_fence_chan *fctx = chan->fence; | 77 | struct nv84_fence_chan *fctx = chan->fence; |
78 | struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan); | 78 | u64 addr = chan->chid * 16; |
79 | u64 addr = fifo->chid * 16; | ||
80 | 79 | ||
81 | if (fence->sysmem) | 80 | if (fence->sysmem) |
82 | addr += fctx->vma_gart.offset; | 81 | addr += fctx->vma_gart.offset; |
@@ -91,8 +90,7 @@ nv84_fence_sync(struct nouveau_fence *fence, | |||
91 | struct nouveau_channel *prev, struct nouveau_channel *chan) | 90 | struct nouveau_channel *prev, struct nouveau_channel *chan) |
92 | { | 91 | { |
93 | struct nv84_fence_chan *fctx = chan->fence; | 92 | struct nv84_fence_chan *fctx = chan->fence; |
94 | struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(prev); | 93 | u64 addr = prev->chid * 16; |
95 | u64 addr = fifo->chid * 16; | ||
96 | 94 | ||
97 | if (fence->sysmem) | 95 | if (fence->sysmem) |
98 | addr += fctx->vma_gart.offset; | 96 | addr += fctx->vma_gart.offset; |
@@ -105,9 +103,8 @@ nv84_fence_sync(struct nouveau_fence *fence, | |||
105 | static u32 | 103 | static u32 |
106 | nv84_fence_read(struct nouveau_channel *chan) | 104 | nv84_fence_read(struct nouveau_channel *chan) |
107 | { | 105 | { |
108 | struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan); | ||
109 | struct nv84_fence_priv *priv = chan->drm->fence; | 106 | struct nv84_fence_priv *priv = chan->drm->fence; |
110 | return nouveau_bo_rd32(priv->bo, fifo->chid * 16/4); | 107 | return nouveau_bo_rd32(priv->bo, chan->chid * 16/4); |
111 | } | 108 | } |
112 | 109 | ||
113 | static void | 110 | static void |
@@ -133,7 +130,6 @@ nv84_fence_context_del(struct nouveau_channel *chan) | |||
133 | int | 130 | int |
134 | nv84_fence_context_new(struct nouveau_channel *chan) | 131 | nv84_fence_context_new(struct nouveau_channel *chan) |
135 | { | 132 | { |
136 | struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan); | ||
137 | struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base); | 133 | struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base); |
138 | struct nv84_fence_priv *priv = chan->drm->fence; | 134 | struct nv84_fence_priv *priv = chan->drm->fence; |
139 | struct nv84_fence_chan *fctx; | 135 | struct nv84_fence_chan *fctx; |
@@ -162,7 +158,7 @@ nv84_fence_context_new(struct nouveau_channel *chan) | |||
162 | ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]); | 158 | ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]); |
163 | } | 159 | } |
164 | 160 | ||
165 | nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, 0x00000000); | 161 | nouveau_bo_wr32(priv->bo, chan->chid * 16/4, 0x00000000); |
166 | 162 | ||
167 | if (ret) | 163 | if (ret) |
168 | nv84_fence_context_del(chan); | 164 | nv84_fence_context_del(chan); |
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h index 7d6c13026855..476d57a1ed6e 100644 --- a/drivers/gpu/drm/nouveau/nvif/class.h +++ b/drivers/gpu/drm/nouveau/nvif/class.h | |||
@@ -12,6 +12,18 @@ | |||
12 | #define NV_DMA_TO_MEMORY 0x00000003 | 12 | #define NV_DMA_TO_MEMORY 0x00000003 |
13 | #define NV_DMA_IN_MEMORY 0x0000003d | 13 | #define NV_DMA_IN_MEMORY 0x0000003d |
14 | 14 | ||
15 | #define NV03_CHANNEL_DMA 0x0000006b | ||
16 | #define NV10_CHANNEL_DMA 0x0000006e | ||
17 | #define NV17_CHANNEL_DMA 0x0000176e | ||
18 | #define NV40_CHANNEL_DMA 0x0000406e | ||
19 | #define NV50_CHANNEL_DMA 0x0000506e | ||
20 | #define G82_CHANNEL_DMA 0x0000826e | ||
21 | |||
22 | #define NV50_CHANNEL_GPFIFO 0x0000506f | ||
23 | #define G82_CHANNEL_GPFIFO 0x0000826f | ||
24 | #define FERMI_CHANNEL_GPFIFO 0x0000906f | ||
25 | #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f | ||
26 | |||
15 | 27 | ||
16 | /******************************************************************************* | 28 | /******************************************************************************* |
17 | * client | 29 | * client |
@@ -233,4 +245,48 @@ struct nvif_control_pstate_user_v0 { | |||
233 | __u8 pad03[5]; | 245 | __u8 pad03[5]; |
234 | }; | 246 | }; |
235 | 247 | ||
248 | |||
249 | /******************************************************************************* | ||
250 | * DMA FIFO channels | ||
251 | ******************************************************************************/ | ||
252 | |||
253 | struct nv03_channel_dma_v0 { | ||
254 | __u8 version; | ||
255 | __u8 chid; | ||
256 | __u8 pad02[2]; | ||
257 | __u32 pushbuf; | ||
258 | __u64 offset; | ||
259 | }; | ||
260 | |||
261 | |||
262 | /******************************************************************************* | ||
263 | * GPFIFO channels | ||
264 | ******************************************************************************/ | ||
265 | |||
266 | struct nv50_channel_gpfifo_v0 { | ||
267 | __u8 version; | ||
268 | __u8 chid; | ||
269 | __u8 pad01[6]; | ||
270 | __u32 pushbuf; | ||
271 | __u32 ilength; | ||
272 | __u64 ioffset; | ||
273 | }; | ||
274 | |||
275 | struct kepler_channel_gpfifo_a_v0 { | ||
276 | __u8 version; | ||
277 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 | ||
278 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02 | ||
279 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04 | ||
280 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08 | ||
281 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 | ||
282 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 | ||
283 | #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 | ||
284 | __u8 engine; | ||
285 | __u16 chid; | ||
286 | __u8 pad04[4]; | ||
287 | __u32 pushbuf; | ||
288 | __u32 ilength; | ||
289 | __u64 ioffset; | ||
290 | }; | ||
291 | |||
236 | #endif | 292 | #endif |