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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-06-04 05:18:15 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-06-04 14:25:29 -0400
commitb7884eb45ec98c0d34c7f49005ae9d4b4b4e38f6 (patch)
treef7e2366bbf08fd9af1cb6fc48d4cd6e5ba2b8d77 /drivers
parent3eef8918ff440837f6af791942d8dd07e1a268ee (diff)
drm/i915: hold forcewake around ring hw init
Empirical evidence suggests that we need to: On at least one ivb machine when running the hangman i-g-t test, the rings don't properly initialize properly - the RING_START registers seems to be stuck at all zeros. Holding forcewake around this register init sequences makes chip reset reliable again. Note that this is not the first such issue: commit f01db988ef6f6c70a6cc36ee71e4a98a68901229 Author: Sean Paul <seanpaul@chromium.org> Date: Fri Mar 16 12:43:22 2012 -0400 drm/i915: Add wait_for in init_ring_common added delay loops to make RING_START and RING_CTL initialization reliable on the blt ring at boot-up. So I guess it won't hurt if we do this unconditionally for all force_wake needing gpus. To avoid copy&pasting of the HAS_FORCE_WAKE check I've added a new intel_info bit for that. v2: Fixup missing commas in static struct and properly handling the error case in init_ring_common, both noticed by Jani Nikula. Cc: stable@vger.kernel.org Reported-and-tested-by: Yang Guang <guang.a.yang@intel.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522 Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c13
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c16
3 files changed, 25 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 238a52165833..9fe9ebe52a7a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -233,6 +233,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
233 .has_blt_ring = 1, 233 .has_blt_ring = 1,
234 .has_llc = 1, 234 .has_llc = 1,
235 .has_pch_split = 1, 235 .has_pch_split = 1,
236 .has_force_wake = 1,
236}; 237};
237 238
238static const struct intel_device_info intel_sandybridge_m_info = { 239static const struct intel_device_info intel_sandybridge_m_info = {
@@ -243,6 +244,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
243 .has_blt_ring = 1, 244 .has_blt_ring = 1,
244 .has_llc = 1, 245 .has_llc = 1,
245 .has_pch_split = 1, 246 .has_pch_split = 1,
247 .has_force_wake = 1,
246}; 248};
247 249
248static const struct intel_device_info intel_ivybridge_d_info = { 250static const struct intel_device_info intel_ivybridge_d_info = {
@@ -252,6 +254,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
252 .has_blt_ring = 1, 254 .has_blt_ring = 1,
253 .has_llc = 1, 255 .has_llc = 1,
254 .has_pch_split = 1, 256 .has_pch_split = 1,
257 .has_force_wake = 1,
255}; 258};
256 259
257static const struct intel_device_info intel_ivybridge_m_info = { 260static const struct intel_device_info intel_ivybridge_m_info = {
@@ -262,6 +265,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
262 .has_blt_ring = 1, 265 .has_blt_ring = 1,
263 .has_llc = 1, 266 .has_llc = 1,
264 .has_pch_split = 1, 267 .has_pch_split = 1,
268 .has_force_wake = 1,
265}; 269};
266 270
267static const struct intel_device_info intel_valleyview_m_info = { 271static const struct intel_device_info intel_valleyview_m_info = {
@@ -289,6 +293,7 @@ static const struct intel_device_info intel_haswell_d_info = {
289 .has_blt_ring = 1, 293 .has_blt_ring = 1,
290 .has_llc = 1, 294 .has_llc = 1,
291 .has_pch_split = 1, 295 .has_pch_split = 1,
296 .has_force_wake = 1,
292}; 297};
293 298
294static const struct intel_device_info intel_haswell_m_info = { 299static const struct intel_device_info intel_haswell_m_info = {
@@ -298,6 +303,7 @@ static const struct intel_device_info intel_haswell_m_info = {
298 .has_blt_ring = 1, 303 .has_blt_ring = 1,
299 .has_llc = 1, 304 .has_llc = 1,
300 .has_pch_split = 1, 305 .has_pch_split = 1,
306 .has_force_wake = 1,
301}; 307};
302 308
303static const struct pci_device_id pciidlist[] = { /* aka */ 309static const struct pci_device_id pciidlist[] = { /* aka */
@@ -1139,10 +1145,9 @@ MODULE_LICENSE("GPL and additional rights");
1139 1145
1140/* We give fast paths for the really cool registers */ 1146/* We give fast paths for the really cool registers */
1141#define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1147#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1142 (((dev_priv)->info->gen >= 6) && \ 1148 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1143 ((reg) < 0x40000) && \ 1149 ((reg) < 0x40000) && \
1144 ((reg) != FORCEWAKE)) && \ 1150 ((reg) != FORCEWAKE))
1145 (!IS_VALLEYVIEW((dev_priv)->dev))
1146 1151
1147#define __i915_read(x, y) \ 1152#define __i915_read(x, y) \
1148u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 1153u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 377c21f531e4..cff630757650 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -285,6 +285,7 @@ struct intel_device_info {
285 u8 is_ivybridge:1; 285 u8 is_ivybridge:1;
286 u8 is_valleyview:1; 286 u8 is_valleyview:1;
287 u8 has_pch_split:1; 287 u8 has_pch_split:1;
288 u8 has_force_wake:1;
288 u8 is_haswell:1; 289 u8 is_haswell:1;
289 u8 has_fbc:1; 290 u8 has_fbc:1;
290 u8 has_pipe_cxsr:1; 291 u8 has_pipe_cxsr:1;
@@ -1098,6 +1099,8 @@ struct drm_i915_file_private {
1098#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1099#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1099#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1100#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1100 1101
1102#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1103
1101#include "i915_trace.h" 1104#include "i915_trace.h"
1102 1105
1103/** 1106/**
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9fbad086cb4b..e5b84ff89ca5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -266,10 +266,15 @@ u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
266 266
267static int init_ring_common(struct intel_ring_buffer *ring) 267static int init_ring_common(struct intel_ring_buffer *ring)
268{ 268{
269 drm_i915_private_t *dev_priv = ring->dev->dev_private; 269 struct drm_device *dev = ring->dev;
270 drm_i915_private_t *dev_priv = dev->dev_private;
270 struct drm_i915_gem_object *obj = ring->obj; 271 struct drm_i915_gem_object *obj = ring->obj;
272 int ret = 0;
271 u32 head; 273 u32 head;
272 274
275 if (HAS_FORCE_WAKE(dev))
276 gen6_gt_force_wake_get(dev_priv);
277
273 /* Stop the ring if it's running. */ 278 /* Stop the ring if it's running. */
274 I915_WRITE_CTL(ring, 0); 279 I915_WRITE_CTL(ring, 0);
275 I915_WRITE_HEAD(ring, 0); 280 I915_WRITE_HEAD(ring, 0);
@@ -317,7 +322,8 @@ static int init_ring_common(struct intel_ring_buffer *ring)
317 I915_READ_HEAD(ring), 322 I915_READ_HEAD(ring),
318 I915_READ_TAIL(ring), 323 I915_READ_TAIL(ring),
319 I915_READ_START(ring)); 324 I915_READ_START(ring));
320 return -EIO; 325 ret = -EIO;
326 goto out;
321 } 327 }
322 328
323 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) 329 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
@@ -329,7 +335,11 @@ static int init_ring_common(struct intel_ring_buffer *ring)
329 ring->last_retired_head = -1; 335 ring->last_retired_head = -1;
330 } 336 }
331 337
332 return 0; 338out:
339 if (HAS_FORCE_WAKE(dev))
340 gen6_gt_force_wake_put(dev_priv);
341
342 return ret;
333} 343}
334 344
335static int 345static int