diff options
author | Felix Fietkau <nbd@openwrt.org> | 2011-04-10 12:32:16 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-04-12 16:59:19 -0400 |
commit | b2fd97d0190a400b49a2f910109a4a492bfea319 (patch) | |
tree | 053033c6e892ce375abf08f421a68edf1e32bcae /drivers | |
parent | b161b89fb97b30233526d31c5f94397ed94ffea6 (diff) |
ath5k: optimize rx status processing
Use ACCESS_ONCE to reduce the number of redundant loads on uncached memory
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/wireless/ath/ath5k/desc.c | 41 |
1 files changed, 18 insertions, 23 deletions
diff --git a/drivers/net/wireless/ath/ath5k/desc.c b/drivers/net/wireless/ath/ath5k/desc.c index 3758b967029a..e366d30ef039 100644 --- a/drivers/net/wireless/ath/ath5k/desc.c +++ b/drivers/net/wireless/ath/ath5k/desc.c | |||
@@ -603,37 +603,37 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, | |||
603 | struct ath5k_rx_status *rs) | 603 | struct ath5k_rx_status *rs) |
604 | { | 604 | { |
605 | struct ath5k_hw_rx_status *rx_status; | 605 | struct ath5k_hw_rx_status *rx_status; |
606 | u32 rxstat0, rxstat1; | ||
606 | 607 | ||
607 | rx_status = &desc->ud.ds_rx.rx_stat; | 608 | rx_status = &desc->ud.ds_rx.rx_stat; |
609 | rxstat1 = ACCESS_ONCE(rx_status->rx_status_1); | ||
608 | 610 | ||
609 | /* No frame received / not ready */ | 611 | /* No frame received / not ready */ |
610 | if (unlikely(!(rx_status->rx_status_1 & | 612 | if (unlikely(!(rxstat1 & AR5K_5212_RX_DESC_STATUS1_DONE))) |
611 | AR5K_5212_RX_DESC_STATUS1_DONE))) | ||
612 | return -EINPROGRESS; | 613 | return -EINPROGRESS; |
613 | 614 | ||
614 | memset(rs, 0, sizeof(struct ath5k_rx_status)); | 615 | memset(rs, 0, sizeof(struct ath5k_rx_status)); |
616 | rxstat0 = ACCESS_ONCE(rx_status->rx_status_0); | ||
615 | 617 | ||
616 | /* | 618 | /* |
617 | * Frame receive status | 619 | * Frame receive status |
618 | */ | 620 | */ |
619 | rs->rs_datalen = rx_status->rx_status_0 & | 621 | rs->rs_datalen = rxstat0 & AR5K_5212_RX_DESC_STATUS0_DATA_LEN; |
620 | AR5K_5212_RX_DESC_STATUS0_DATA_LEN; | 622 | rs->rs_rssi = AR5K_REG_MS(rxstat0, |
621 | rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, | ||
622 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL); | 623 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL); |
623 | rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, | 624 | rs->rs_rate = AR5K_REG_MS(rxstat0, |
624 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE); | 625 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE); |
625 | rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0, | 626 | rs->rs_antenna = AR5K_REG_MS(rxstat0, |
626 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA); | 627 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA); |
627 | rs->rs_more = !!(rx_status->rx_status_0 & | 628 | rs->rs_more = !!(rxstat0 & AR5K_5212_RX_DESC_STATUS0_MORE); |
628 | AR5K_5212_RX_DESC_STATUS0_MORE); | 629 | rs->rs_tstamp = AR5K_REG_MS(rxstat1, |
629 | rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, | ||
630 | AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); | 630 | AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); |
631 | 631 | ||
632 | /* | 632 | /* |
633 | * Key table status | 633 | * Key table status |
634 | */ | 634 | */ |
635 | if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID) | 635 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID) |
636 | rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, | 636 | rs->rs_keyix = AR5K_REG_MS(rxstat1, |
637 | AR5K_5212_RX_DESC_STATUS1_KEY_INDEX); | 637 | AR5K_5212_RX_DESC_STATUS1_KEY_INDEX); |
638 | else | 638 | else |
639 | rs->rs_keyix = AR5K_RXKEYIX_INVALID; | 639 | rs->rs_keyix = AR5K_RXKEYIX_INVALID; |
@@ -641,27 +641,22 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, | |||
641 | /* | 641 | /* |
642 | * Receive/descriptor errors | 642 | * Receive/descriptor errors |
643 | */ | 643 | */ |
644 | if (!(rx_status->rx_status_1 & | 644 | if (!(rxstat1 & AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) { |
645 | AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) { | 645 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_CRC_ERROR) |
646 | if (rx_status->rx_status_1 & | ||
647 | AR5K_5212_RX_DESC_STATUS1_CRC_ERROR) | ||
648 | rs->rs_status |= AR5K_RXERR_CRC; | 646 | rs->rs_status |= AR5K_RXERR_CRC; |
649 | 647 | ||
650 | if (rx_status->rx_status_1 & | 648 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) { |
651 | AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) { | ||
652 | rs->rs_status |= AR5K_RXERR_PHY; | 649 | rs->rs_status |= AR5K_RXERR_PHY; |
653 | rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1, | 650 | rs->rs_phyerr = AR5K_REG_MS(rxstat1, |
654 | AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE); | 651 | AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE); |
655 | if (!ah->ah_capabilities.cap_has_phyerr_counters) | 652 | if (!ah->ah_capabilities.cap_has_phyerr_counters) |
656 | ath5k_ani_phy_error_report(ah, rs->rs_phyerr); | 653 | ath5k_ani_phy_error_report(ah, rs->rs_phyerr); |
657 | } | 654 | } |
658 | 655 | ||
659 | if (rx_status->rx_status_1 & | 656 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) |
660 | AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) | ||
661 | rs->rs_status |= AR5K_RXERR_DECRYPT; | 657 | rs->rs_status |= AR5K_RXERR_DECRYPT; |
662 | 658 | ||
663 | if (rx_status->rx_status_1 & | 659 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_MIC_ERROR) |
664 | AR5K_5212_RX_DESC_STATUS1_MIC_ERROR) | ||
665 | rs->rs_status |= AR5K_RXERR_MIC; | 660 | rs->rs_status |= AR5K_RXERR_MIC; |
666 | } | 661 | } |
667 | return 0; | 662 | return 0; |