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authorChris Leech <christopher.leech@intel.com>2010-03-24 08:45:21 -0400
committerDavid S. Miller <davem@davemloft.net>2010-03-26 14:56:04 -0400
commitaf06393bbde6e8d474622a0517cffc662676e3fe (patch)
treeabbb33f645a67280ef6b4bec1af619f36e90d6b0 /drivers
parentca77cd59d28456b4061afa5254972ec47fa8baf5 (diff)
ixgbe: filter FIP frames into the FCoE offload queues
During FCF solicitation, the switch is supposed to pad the solicited advertisement out to the endpoints specified maximum FCoE frame size. That means that we need to receive FIP frames that are larger than the standard MTU. To make sure the receive queue is configured correctly, we should be filtering FIP traffic into the FCoE queues. Signed-off-by: Chris Leech <christopher.leech@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ixgbe/ixgbe_fcoe.c15
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h1
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_fcoe.c b/drivers/net/ixgbe/ixgbe_fcoe.c
index e1978da49e5b..9276d5965b0d 100644
--- a/drivers/net/ixgbe/ixgbe_fcoe.c
+++ b/drivers/net/ixgbe/ixgbe_fcoe.c
@@ -522,6 +522,9 @@ void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
522 /* Enable L2 eth type filter for FCoE */ 522 /* Enable L2 eth type filter for FCoE */
523 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE), 523 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FCOE),
524 (ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN)); 524 (ETH_P_FCOE | IXGBE_ETQF_FCOE | IXGBE_ETQF_FILTER_EN));
525 /* Enable L2 eth type filter for FIP */
526 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FIP),
527 (ETH_P_FIP | IXGBE_ETQF_FILTER_EN));
525 if (adapter->ring_feature[RING_F_FCOE].indices) { 528 if (adapter->ring_feature[RING_F_FCOE].indices) {
526 /* Use multiple rx queues for FCoE by redirection table */ 529 /* Use multiple rx queues for FCoE by redirection table */
527 for (i = 0; i < IXGBE_FCRETA_SIZE; i++) { 530 for (i = 0; i < IXGBE_FCRETA_SIZE; i++) {
@@ -532,6 +535,12 @@ void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
532 } 535 }
533 IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA); 536 IXGBE_WRITE_REG(hw, IXGBE_FCRECTL, IXGBE_FCRECTL_ENA);
534 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0); 537 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FCOE), 0);
538 fcoe_i = f->mask;
539 fcoe_i &= IXGBE_FCRETA_ENTRY_MASK;
540 fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
541 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FIP),
542 IXGBE_ETQS_QUEUE_EN |
543 (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
535 } else { 544 } else {
536 /* Use single rx queue for FCoE */ 545 /* Use single rx queue for FCoE */
537 fcoe_i = f->mask; 546 fcoe_i = f->mask;
@@ -541,6 +550,12 @@ void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter)
541 IXGBE_ETQS_QUEUE_EN | 550 IXGBE_ETQS_QUEUE_EN |
542 (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT)); 551 (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
543 } 552 }
553 /* send FIP frames to the first FCoE queue */
554 fcoe_i = f->mask;
555 fcoe_q = adapter->rx_ring[fcoe_i]->reg_idx;
556 IXGBE_WRITE_REG(hw, IXGBE_ETQS(IXGBE_ETQF_FILTER_FIP),
557 IXGBE_ETQS_QUEUE_EN |
558 (fcoe_q << IXGBE_ETQS_RX_QUEUE_SHIFT));
544 559
545 IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL, 560 IXGBE_WRITE_REG(hw, IXGBE_FCRXCTRL,
546 IXGBE_FCRXCTRL_FCOELLI | 561 IXGBE_FCRXCTRL_FCOELLI |
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 0ed5ab37cc53..4ec6dc1a5b75 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -1298,6 +1298,7 @@
1298#define IXGBE_ETQF_FILTER_BCN 1 1298#define IXGBE_ETQF_FILTER_BCN 1
1299#define IXGBE_ETQF_FILTER_FCOE 2 1299#define IXGBE_ETQF_FILTER_FCOE 2
1300#define IXGBE_ETQF_FILTER_1588 3 1300#define IXGBE_ETQF_FILTER_1588 3
1301#define IXGBE_ETQF_FILTER_FIP 4
1301/* VLAN Control Bit Masks */ 1302/* VLAN Control Bit Masks */
1302#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1303#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1303#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1304#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */