diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-01 12:15:15 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-01 12:15:15 -0500 |
| commit | ac0f6f927db539e03e1f3f61bcd4ed57d5cde7a9 (patch) | |
| tree | 816e5ac643b15c2050c64a7075f0f7e13d86ea09 /drivers | |
| parent | b1bf9368407ae7e89d8a005bb40beb70a41df539 (diff) | |
| parent | 9f33be2c3a80bdc2cc08342dd77fac87652e0548 (diff) | |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (100 commits)
ARM: Eliminate decompressor -Dstatic= PIC hack
ARM: 5958/1: ARM: U300: fix inverted clk round rate
ARM: 5956/1: misplaced parentheses
ARM: 5955/1: ep93xx: move timer defines into core.c and document
ARM: 5954/1: ep93xx: move gpio interrupt support to gpio.c
ARM: 5953/1: ep93xx: fix broken build of clock.c
ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig
ARM: 5949/1: NUC900 add gpio virtual memory map
ARM: 5948/1: Enable timer0 to time4 clock support for nuc910
ARM: 5940/2: ARM: MMCI: remove custom DBG macro and printk
ARM: make_coherent(): fix problems with highpte, part 2
MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
ARM: 5945/1: ep93xx: include correct irq.h in core.c
ARM: 5933/1: amba-pl011: support hardware flow control
ARM: 5930/1: Add PKMAP area description to memory.txt.
ARM: 5929/1: Add checks to detect overlap of memory regions.
ARM: 5928/1: Change type of VMALLOC_END to unsigned long.
ARM: 5927/1: Make delimiters of DMA area globally visibly.
ARM: 5926/1: Add "Virtual kernel memory..." printout.
ARM: 5920/1: OMAP4: Enable L2 Cache
...
Fix up trivial conflict in arch/arm/mach-mx25/clock.c
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/i2c/busses/i2c-pnx.c | 285 | ||||
| -rw-r--r-- | drivers/mmc/host/mmci.c | 41 | ||||
| -rw-r--r-- | drivers/rtc/rtc-pl031.c | 365 | ||||
| -rw-r--r-- | drivers/serial/amba-pl011.c | 19 | ||||
| -rw-r--r-- | drivers/spi/amba-pl022.c | 18 | ||||
| -rw-r--r-- | drivers/watchdog/pnx4008_wdt.c | 39 |
6 files changed, 565 insertions, 202 deletions
diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c index 5d1c2603a130..2b0bd0b042d6 100644 --- a/drivers/i2c/busses/i2c-pnx.c +++ b/drivers/i2c/busses/i2c-pnx.c | |||
| @@ -20,15 +20,15 @@ | |||
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/i2c-pnx.h> | 21 | #include <linux/i2c-pnx.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/err.h> | ||
| 24 | #include <linux/clk.h> | ||
| 25 | |||
| 23 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 24 | #include <mach/i2c.h> | 27 | #include <mach/i2c.h> |
| 25 | #include <asm/irq.h> | ||
| 26 | #include <asm/uaccess.h> | ||
| 27 | 28 | ||
| 28 | #define I2C_PNX_TIMEOUT 10 /* msec */ | 29 | #define I2C_PNX_TIMEOUT 10 /* msec */ |
| 29 | #define I2C_PNX_SPEED_KHZ 100 | 30 | #define I2C_PNX_SPEED_KHZ 100 |
| 30 | #define I2C_PNX_REGION_SIZE 0x100 | 31 | #define I2C_PNX_REGION_SIZE 0x100 |
| 31 | #define PNX_DEFAULT_FREQ 13 /* MHz */ | ||
| 32 | 32 | ||
| 33 | static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data) | 33 | static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data) |
| 34 | { | 34 | { |
| @@ -50,22 +50,21 @@ static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data) | |||
| 50 | return (timeout <= 0); | 50 | return (timeout <= 0); |
| 51 | } | 51 | } |
| 52 | 52 | ||
| 53 | static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap) | 53 | static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data) |
| 54 | { | 54 | { |
| 55 | struct i2c_pnx_algo_data *data = adap->algo_data; | 55 | struct timer_list *timer = &alg_data->mif.timer; |
| 56 | struct timer_list *timer = &data->mif.timer; | 56 | unsigned long expires = msecs_to_jiffies(I2C_PNX_TIMEOUT); |
| 57 | int expires = I2C_PNX_TIMEOUT / (1000 / HZ); | ||
| 58 | 57 | ||
| 59 | if (expires <= 1) | 58 | if (expires <= 1) |
| 60 | expires = 2; | 59 | expires = 2; |
| 61 | 60 | ||
| 62 | del_timer_sync(timer); | 61 | del_timer_sync(timer); |
| 63 | 62 | ||
| 64 | dev_dbg(&adap->dev, "Timer armed at %lu plus %u jiffies.\n", | 63 | dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n", |
| 65 | jiffies, expires); | 64 | jiffies, expires); |
| 66 | 65 | ||
| 67 | timer->expires = jiffies + expires; | 66 | timer->expires = jiffies + expires; |
| 68 | timer->data = (unsigned long)adap; | 67 | timer->data = (unsigned long)&alg_data; |
| 69 | 68 | ||
| 70 | add_timer(timer); | 69 | add_timer(timer); |
| 71 | } | 70 | } |
| @@ -77,34 +76,34 @@ static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap) | |||
| 77 | * | 76 | * |
| 78 | * Generate a START signal in the desired mode. | 77 | * Generate a START signal in the desired mode. |
| 79 | */ | 78 | */ |
| 80 | static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap) | 79 | static int i2c_pnx_start(unsigned char slave_addr, |
| 80 | struct i2c_pnx_algo_data *alg_data) | ||
| 81 | { | 81 | { |
| 82 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | 82 | dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__, |
| 83 | |||
| 84 | dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __func__, | ||
| 85 | slave_addr, alg_data->mif.mode); | 83 | slave_addr, alg_data->mif.mode); |
| 86 | 84 | ||
| 87 | /* Check for 7 bit slave addresses only */ | 85 | /* Check for 7 bit slave addresses only */ |
| 88 | if (slave_addr & ~0x7f) { | 86 | if (slave_addr & ~0x7f) { |
| 89 | dev_err(&adap->dev, "%s: Invalid slave address %x. " | 87 | dev_err(&alg_data->adapter.dev, |
| 90 | "Only 7-bit addresses are supported\n", | 88 | "%s: Invalid slave address %x. Only 7-bit addresses are supported\n", |
| 91 | adap->name, slave_addr); | 89 | alg_data->adapter.name, slave_addr); |
| 92 | return -EINVAL; | 90 | return -EINVAL; |
| 93 | } | 91 | } |
| 94 | 92 | ||
| 95 | /* First, make sure bus is idle */ | 93 | /* First, make sure bus is idle */ |
| 96 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) { | 94 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) { |
| 97 | /* Somebody else is monopolizing the bus */ | 95 | /* Somebody else is monopolizing the bus */ |
| 98 | dev_err(&adap->dev, "%s: Bus busy. Slave addr = %02x, " | 96 | dev_err(&alg_data->adapter.dev, |
| 99 | "cntrl = %x, stat = %x\n", | 97 | "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n", |
| 100 | adap->name, slave_addr, | 98 | alg_data->adapter.name, slave_addr, |
| 101 | ioread32(I2C_REG_CTL(alg_data)), | 99 | ioread32(I2C_REG_CTL(alg_data)), |
| 102 | ioread32(I2C_REG_STS(alg_data))); | 100 | ioread32(I2C_REG_STS(alg_data))); |
| 103 | return -EBUSY; | 101 | return -EBUSY; |
| 104 | } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { | 102 | } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { |
| 105 | /* Sorry, we lost the bus */ | 103 | /* Sorry, we lost the bus */ |
| 106 | dev_err(&adap->dev, "%s: Arbitration failure. " | 104 | dev_err(&alg_data->adapter.dev, |
| 107 | "Slave addr = %02x\n", adap->name, slave_addr); | 105 | "%s: Arbitration failure. Slave addr = %02x\n", |
| 106 | alg_data->adapter.name, slave_addr); | ||
| 108 | return -EIO; | 107 | return -EIO; |
| 109 | } | 108 | } |
| 110 | 109 | ||
| @@ -115,14 +114,14 @@ static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap) | |||
| 115 | iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, | 114 | iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, |
| 116 | I2C_REG_STS(alg_data)); | 115 | I2C_REG_STS(alg_data)); |
| 117 | 116 | ||
| 118 | dev_dbg(&adap->dev, "%s(): sending %#x\n", __func__, | 117 | dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__, |
| 119 | (slave_addr << 1) | start_bit | alg_data->mif.mode); | 118 | (slave_addr << 1) | start_bit | alg_data->mif.mode); |
| 120 | 119 | ||
| 121 | /* Write the slave address, START bit and R/W bit */ | 120 | /* Write the slave address, START bit and R/W bit */ |
| 122 | iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, | 121 | iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, |
| 123 | I2C_REG_TX(alg_data)); | 122 | I2C_REG_TX(alg_data)); |
| 124 | 123 | ||
| 125 | dev_dbg(&adap->dev, "%s(): exit\n", __func__); | 124 | dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__); |
| 126 | 125 | ||
| 127 | return 0; | 126 | return 0; |
| 128 | } | 127 | } |
| @@ -133,13 +132,12 @@ static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap) | |||
| 133 | * | 132 | * |
| 134 | * Generate a STOP signal to terminate the master transaction. | 133 | * Generate a STOP signal to terminate the master transaction. |
| 135 | */ | 134 | */ |
| 136 | static void i2c_pnx_stop(struct i2c_adapter *adap) | 135 | static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data) |
| 137 | { | 136 | { |
| 138 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | ||
| 139 | /* Only 1 msec max timeout due to interrupt context */ | 137 | /* Only 1 msec max timeout due to interrupt context */ |
| 140 | long timeout = 1000; | 138 | long timeout = 1000; |
| 141 | 139 | ||
| 142 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | 140 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
| 143 | __func__, ioread32(I2C_REG_STS(alg_data))); | 141 | __func__, ioread32(I2C_REG_STS(alg_data))); |
| 144 | 142 | ||
| 145 | /* Write a STOP bit to TX FIFO */ | 143 | /* Write a STOP bit to TX FIFO */ |
| @@ -153,7 +151,7 @@ static void i2c_pnx_stop(struct i2c_adapter *adap) | |||
| 153 | timeout--; | 151 | timeout--; |
| 154 | } | 152 | } |
| 155 | 153 | ||
| 156 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | 154 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
| 157 | __func__, ioread32(I2C_REG_STS(alg_data))); | 155 | __func__, ioread32(I2C_REG_STS(alg_data))); |
| 158 | } | 156 | } |
| 159 | 157 | ||
| @@ -163,12 +161,11 @@ static void i2c_pnx_stop(struct i2c_adapter *adap) | |||
| 163 | * | 161 | * |
| 164 | * Sends one byte of data to the slave | 162 | * Sends one byte of data to the slave |
| 165 | */ | 163 | */ |
| 166 | static int i2c_pnx_master_xmit(struct i2c_adapter *adap) | 164 | static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data) |
| 167 | { | 165 | { |
| 168 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | ||
| 169 | u32 val; | 166 | u32 val; |
| 170 | 167 | ||
| 171 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | 168 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
| 172 | __func__, ioread32(I2C_REG_STS(alg_data))); | 169 | __func__, ioread32(I2C_REG_STS(alg_data))); |
| 173 | 170 | ||
| 174 | if (alg_data->mif.len > 0) { | 171 | if (alg_data->mif.len > 0) { |
| @@ -184,15 +181,15 @@ static int i2c_pnx_master_xmit(struct i2c_adapter *adap) | |||
| 184 | alg_data->mif.len--; | 181 | alg_data->mif.len--; |
| 185 | iowrite32(val, I2C_REG_TX(alg_data)); | 182 | iowrite32(val, I2C_REG_TX(alg_data)); |
| 186 | 183 | ||
| 187 | dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __func__, | 184 | dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n", |
| 188 | val, alg_data->mif.len + 1); | 185 | __func__, val, alg_data->mif.len + 1); |
| 189 | 186 | ||
| 190 | if (alg_data->mif.len == 0) { | 187 | if (alg_data->mif.len == 0) { |
| 191 | if (alg_data->last) { | 188 | if (alg_data->last) { |
| 192 | /* Wait until the STOP is seen. */ | 189 | /* Wait until the STOP is seen. */ |
| 193 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | 190 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) |
| 194 | dev_err(&adap->dev, "The bus is still " | 191 | dev_err(&alg_data->adapter.dev, |
| 195 | "active after timeout\n"); | 192 | "The bus is still active after timeout\n"); |
| 196 | } | 193 | } |
| 197 | /* Disable master interrupts */ | 194 | /* Disable master interrupts */ |
| 198 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | 195 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & |
| @@ -201,14 +198,15 @@ static int i2c_pnx_master_xmit(struct i2c_adapter *adap) | |||
| 201 | 198 | ||
| 202 | del_timer_sync(&alg_data->mif.timer); | 199 | del_timer_sync(&alg_data->mif.timer); |
| 203 | 200 | ||
| 204 | dev_dbg(&adap->dev, "%s(): Waking up xfer routine.\n", | 201 | dev_dbg(&alg_data->adapter.dev, |
| 202 | "%s(): Waking up xfer routine.\n", | ||
| 205 | __func__); | 203 | __func__); |
| 206 | 204 | ||
| 207 | complete(&alg_data->mif.complete); | 205 | complete(&alg_data->mif.complete); |
| 208 | } | 206 | } |
| 209 | } else if (alg_data->mif.len == 0) { | 207 | } else if (alg_data->mif.len == 0) { |
| 210 | /* zero-sized transfer */ | 208 | /* zero-sized transfer */ |
| 211 | i2c_pnx_stop(adap); | 209 | i2c_pnx_stop(alg_data); |
| 212 | 210 | ||
| 213 | /* Disable master interrupts. */ | 211 | /* Disable master interrupts. */ |
| 214 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & | 212 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) & |
| @@ -217,13 +215,14 @@ static int i2c_pnx_master_xmit(struct i2c_adapter *adap) | |||
| 217 | 215 | ||
| 218 | /* Stop timer. */ | 216 | /* Stop timer. */ |
| 219 | del_timer_sync(&alg_data->mif.timer); | 217 | del_timer_sync(&alg_data->mif.timer); |
| 220 | dev_dbg(&adap->dev, "%s(): Waking up xfer routine after " | 218 | dev_dbg(&alg_data->adapter.dev, |
| 221 | "zero-xfer.\n", __func__); | 219 | "%s(): Waking up xfer routine after zero-xfer.\n", |
| 220 | __func__); | ||
| 222 | 221 | ||
| 223 | complete(&alg_data->mif.complete); | 222 | complete(&alg_data->mif.complete); |
| 224 | } | 223 | } |
| 225 | 224 | ||
| 226 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | 225 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
| 227 | __func__, ioread32(I2C_REG_STS(alg_data))); | 226 | __func__, ioread32(I2C_REG_STS(alg_data))); |
| 228 | 227 | ||
| 229 | return 0; | 228 | return 0; |
| @@ -235,21 +234,21 @@ static int i2c_pnx_master_xmit(struct i2c_adapter *adap) | |||
| 235 | * | 234 | * |
| 236 | * Reads one byte data from the slave | 235 | * Reads one byte data from the slave |
| 237 | */ | 236 | */ |
| 238 | static int i2c_pnx_master_rcv(struct i2c_adapter *adap) | 237 | static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data) |
| 239 | { | 238 | { |
| 240 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | ||
| 241 | unsigned int val = 0; | 239 | unsigned int val = 0; |
| 242 | u32 ctl = 0; | 240 | u32 ctl = 0; |
| 243 | 241 | ||
| 244 | dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", | 242 | dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
| 245 | __func__, ioread32(I2C_REG_STS(alg_data))); | 243 | __func__, ioread32(I2C_REG_STS(alg_data))); |
| 246 | 244 | ||
| 247 | /* Check, whether there is already data, | 245 | /* Check, whether there is already data, |
| 248 | * or we didn't 'ask' for it yet. | 246 | * or we didn't 'ask' for it yet. |
| 249 | */ | 247 | */ |
| 250 | if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { | 248 | if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { |
| 251 | dev_dbg(&adap->dev, "%s(): Write dummy data to fill " | 249 | dev_dbg(&alg_data->adapter.dev, |
| 252 | "Rx-fifo...\n", __func__); | 250 | "%s(): Write dummy data to fill Rx-fifo...\n", |
| 251 | __func__); | ||
| 253 | 252 | ||
| 254 | if (alg_data->mif.len == 1) { | 253 | if (alg_data->mif.len == 1) { |
| 255 | /* Last byte, do not acknowledge next rcv. */ | 254 | /* Last byte, do not acknowledge next rcv. */ |
| @@ -281,16 +280,16 @@ static int i2c_pnx_master_rcv(struct i2c_adapter *adap) | |||
| 281 | if (alg_data->mif.len > 0) { | 280 | if (alg_data->mif.len > 0) { |
| 282 | val = ioread32(I2C_REG_RX(alg_data)); | 281 | val = ioread32(I2C_REG_RX(alg_data)); |
| 283 | *alg_data->mif.buf++ = (u8) (val & 0xff); | 282 | *alg_data->mif.buf++ = (u8) (val & 0xff); |
| 284 | dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __func__, val, | 283 | dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n", |
| 285 | alg_data->mif.len); | 284 | __func__, val, alg_data->mif.len); |
| 286 | 285 | ||
| 287 | alg_data->mif.len--; | 286 | alg_data->mif.len--; |
| 288 | if (alg_data->mif.len == 0) { | 287 | if (alg_data->mif.len == 0) { |
| 289 | if (alg_data->last) | 288 | if (alg_data->last) |
| 290 | /* Wait until the STOP is seen. */ | 289 | /* Wait until the STOP is seen. */ |
| 291 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) | 290 | if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) |
| 292 | dev_err(&adap->dev, "The bus is still " | 291 | dev_err(&alg_data->adapter.dev, |
| 293 | "active after timeout\n"); | 292 | "The bus is still active after timeout\n"); |
| 294 | 293 | ||
| 295 | /* Disable master interrupts */ | 294 | /* Disable master interrupts */ |
| 296 | ctl = ioread32(I2C_REG_CTL(alg_data)); | 295 | ctl = ioread32(I2C_REG_CTL(alg_data)); |
| @@ -304,7 +303,7 @@ static int i2c_pnx_master_rcv(struct i2c_adapter *adap) | |||
| 304 | } | 303 | } |
| 305 | } | 304 | } |
| 306 | 305 | ||
| 307 | dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", | 306 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
| 308 | __func__, ioread32(I2C_REG_STS(alg_data))); | 307 | __func__, ioread32(I2C_REG_STS(alg_data))); |
| 309 | 308 | ||
| 310 | return 0; | 309 | return 0; |
| @@ -312,11 +311,11 @@ static int i2c_pnx_master_rcv(struct i2c_adapter *adap) | |||
| 312 | 311 | ||
| 313 | static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) | 312 | static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) |
| 314 | { | 313 | { |
| 314 | struct i2c_pnx_algo_data *alg_data = dev_id; | ||
| 315 | u32 stat, ctl; | 315 | u32 stat, ctl; |
| 316 | struct i2c_adapter *adap = dev_id; | ||
| 317 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | ||
| 318 | 316 | ||
| 319 | dev_dbg(&adap->dev, "%s(): mstat = %x mctrl = %x, mode = %d\n", | 317 | dev_dbg(&alg_data->adapter.dev, |
| 318 | "%s(): mstat = %x mctrl = %x, mode = %d\n", | ||
| 320 | __func__, | 319 | __func__, |
| 321 | ioread32(I2C_REG_STS(alg_data)), | 320 | ioread32(I2C_REG_STS(alg_data)), |
| 322 | ioread32(I2C_REG_CTL(alg_data)), | 321 | ioread32(I2C_REG_CTL(alg_data)), |
| @@ -339,10 +338,10 @@ static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) | |||
| 339 | complete(&alg_data->mif.complete); | 338 | complete(&alg_data->mif.complete); |
| 340 | } else if (stat & mstatus_nai) { | 339 | } else if (stat & mstatus_nai) { |
| 341 | /* Slave did not acknowledge, generate a STOP */ | 340 | /* Slave did not acknowledge, generate a STOP */ |
| 342 | dev_dbg(&adap->dev, "%s(): " | 341 | dev_dbg(&alg_data->adapter.dev, |
| 343 | "Slave did not acknowledge, generating a STOP.\n", | 342 | "%s(): Slave did not acknowledge, generating a STOP.\n", |
| 344 | __func__); | 343 | __func__); |
| 345 | i2c_pnx_stop(adap); | 344 | i2c_pnx_stop(alg_data); |
| 346 | 345 | ||
| 347 | /* Disable master interrupts. */ | 346 | /* Disable master interrupts. */ |
| 348 | ctl = ioread32(I2C_REG_CTL(alg_data)); | 347 | ctl = ioread32(I2C_REG_CTL(alg_data)); |
| @@ -368,9 +367,9 @@ static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) | |||
| 368 | */ | 367 | */ |
| 369 | if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { | 368 | if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { |
| 370 | if (alg_data->mif.mode == I2C_SMBUS_WRITE) { | 369 | if (alg_data->mif.mode == I2C_SMBUS_WRITE) { |
| 371 | i2c_pnx_master_xmit(adap); | 370 | i2c_pnx_master_xmit(alg_data); |
| 372 | } else if (alg_data->mif.mode == I2C_SMBUS_READ) { | 371 | } else if (alg_data->mif.mode == I2C_SMBUS_READ) { |
| 373 | i2c_pnx_master_rcv(adap); | 372 | i2c_pnx_master_rcv(alg_data); |
| 374 | } | 373 | } |
| 375 | } | 374 | } |
| 376 | } | 375 | } |
| @@ -379,7 +378,8 @@ static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) | |||
| 379 | stat = ioread32(I2C_REG_STS(alg_data)); | 378 | stat = ioread32(I2C_REG_STS(alg_data)); |
| 380 | iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); | 379 | iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); |
| 381 | 380 | ||
| 382 | dev_dbg(&adap->dev, "%s(): exiting, stat = %x ctrl = %x.\n", | 381 | dev_dbg(&alg_data->adapter.dev, |
| 382 | "%s(): exiting, stat = %x ctrl = %x.\n", | ||
| 383 | __func__, ioread32(I2C_REG_STS(alg_data)), | 383 | __func__, ioread32(I2C_REG_STS(alg_data)), |
| 384 | ioread32(I2C_REG_CTL(alg_data))); | 384 | ioread32(I2C_REG_CTL(alg_data))); |
| 385 | 385 | ||
| @@ -388,14 +388,13 @@ static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) | |||
| 388 | 388 | ||
| 389 | static void i2c_pnx_timeout(unsigned long data) | 389 | static void i2c_pnx_timeout(unsigned long data) |
| 390 | { | 390 | { |
| 391 | struct i2c_adapter *adap = (struct i2c_adapter *)data; | 391 | struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data; |
| 392 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | ||
| 393 | u32 ctl; | 392 | u32 ctl; |
| 394 | 393 | ||
| 395 | dev_err(&adap->dev, "Master timed out. stat = %04x, cntrl = %04x. " | 394 | dev_err(&alg_data->adapter.dev, |
| 396 | "Resetting master...\n", | 395 | "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n", |
| 397 | ioread32(I2C_REG_STS(alg_data)), | 396 | ioread32(I2C_REG_STS(alg_data)), |
| 398 | ioread32(I2C_REG_CTL(alg_data))); | 397 | ioread32(I2C_REG_CTL(alg_data))); |
| 399 | 398 | ||
| 400 | /* Reset master and disable interrupts */ | 399 | /* Reset master and disable interrupts */ |
| 401 | ctl = ioread32(I2C_REG_CTL(alg_data)); | 400 | ctl = ioread32(I2C_REG_CTL(alg_data)); |
| @@ -409,15 +408,14 @@ static void i2c_pnx_timeout(unsigned long data) | |||
| 409 | complete(&alg_data->mif.complete); | 408 | complete(&alg_data->mif.complete); |
| 410 | } | 409 | } |
| 411 | 410 | ||
| 412 | static inline void bus_reset_if_active(struct i2c_adapter *adap) | 411 | static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data) |
| 413 | { | 412 | { |
| 414 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | ||
| 415 | u32 stat; | 413 | u32 stat; |
| 416 | 414 | ||
| 417 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { | 415 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { |
| 418 | dev_err(&adap->dev, | 416 | dev_err(&alg_data->adapter.dev, |
| 419 | "%s: Bus is still active after xfer. Reset it...\n", | 417 | "%s: Bus is still active after xfer. Reset it...\n", |
| 420 | adap->name); | 418 | alg_data->adapter.name); |
| 421 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, | 419 | iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, |
| 422 | I2C_REG_CTL(alg_data)); | 420 | I2C_REG_CTL(alg_data)); |
| 423 | wait_reset(I2C_PNX_TIMEOUT, alg_data); | 421 | wait_reset(I2C_PNX_TIMEOUT, alg_data); |
| @@ -451,10 +449,11 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |||
| 451 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | 449 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; |
| 452 | u32 stat = ioread32(I2C_REG_STS(alg_data)); | 450 | u32 stat = ioread32(I2C_REG_STS(alg_data)); |
| 453 | 451 | ||
| 454 | dev_dbg(&adap->dev, "%s(): entering: %d messages, stat = %04x.\n", | 452 | dev_dbg(&alg_data->adapter.dev, |
| 453 | "%s(): entering: %d messages, stat = %04x.\n", | ||
| 455 | __func__, num, ioread32(I2C_REG_STS(alg_data))); | 454 | __func__, num, ioread32(I2C_REG_STS(alg_data))); |
| 456 | 455 | ||
| 457 | bus_reset_if_active(adap); | 456 | bus_reset_if_active(alg_data); |
| 458 | 457 | ||
| 459 | /* Process transactions in a loop. */ | 458 | /* Process transactions in a loop. */ |
| 460 | for (i = 0; rc >= 0 && i < num; i++) { | 459 | for (i = 0; rc >= 0 && i < num; i++) { |
| @@ -464,9 +463,9 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |||
| 464 | addr = pmsg->addr; | 463 | addr = pmsg->addr; |
| 465 | 464 | ||
| 466 | if (pmsg->flags & I2C_M_TEN) { | 465 | if (pmsg->flags & I2C_M_TEN) { |
| 467 | dev_err(&adap->dev, | 466 | dev_err(&alg_data->adapter.dev, |
| 468 | "%s: 10 bits addr not supported!\n", | 467 | "%s: 10 bits addr not supported!\n", |
| 469 | adap->name); | 468 | alg_data->adapter.name); |
| 470 | rc = -EINVAL; | 469 | rc = -EINVAL; |
| 471 | break; | 470 | break; |
| 472 | } | 471 | } |
| @@ -478,11 +477,10 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |||
| 478 | alg_data->mif.ret = 0; | 477 | alg_data->mif.ret = 0; |
| 479 | alg_data->last = (i == num - 1); | 478 | alg_data->last = (i == num - 1); |
| 480 | 479 | ||
| 481 | dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __func__, | 480 | dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n", |
| 482 | alg_data->mif.mode, | 481 | __func__, alg_data->mif.mode, alg_data->mif.len); |
| 483 | alg_data->mif.len); | ||
| 484 | 482 | ||
| 485 | i2c_pnx_arm_timer(adap); | 483 | i2c_pnx_arm_timer(alg_data); |
| 486 | 484 | ||
| 487 | /* initialize the completion var */ | 485 | /* initialize the completion var */ |
| 488 | init_completion(&alg_data->mif.complete); | 486 | init_completion(&alg_data->mif.complete); |
| @@ -493,7 +491,7 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |||
| 493 | I2C_REG_CTL(alg_data)); | 491 | I2C_REG_CTL(alg_data)); |
| 494 | 492 | ||
| 495 | /* Put start-code and slave-address on the bus. */ | 493 | /* Put start-code and slave-address on the bus. */ |
| 496 | rc = i2c_pnx_start(addr, adap); | 494 | rc = i2c_pnx_start(addr, alg_data); |
| 497 | if (rc < 0) | 495 | if (rc < 0) |
| 498 | break; | 496 | break; |
| 499 | 497 | ||
| @@ -502,31 +500,32 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |||
| 502 | 500 | ||
| 503 | if (!(rc = alg_data->mif.ret)) | 501 | if (!(rc = alg_data->mif.ret)) |
| 504 | completed++; | 502 | completed++; |
| 505 | dev_dbg(&adap->dev, "%s(): Complete, return code = %d.\n", | 503 | dev_dbg(&alg_data->adapter.dev, |
| 504 | "%s(): Complete, return code = %d.\n", | ||
| 506 | __func__, rc); | 505 | __func__, rc); |
| 507 | 506 | ||
| 508 | /* Clear TDI and AFI bits in case they are set. */ | 507 | /* Clear TDI and AFI bits in case they are set. */ |
| 509 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { | 508 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { |
| 510 | dev_dbg(&adap->dev, | 509 | dev_dbg(&alg_data->adapter.dev, |
| 511 | "%s: TDI still set... clearing now.\n", | 510 | "%s: TDI still set... clearing now.\n", |
| 512 | adap->name); | 511 | alg_data->adapter.name); |
| 513 | iowrite32(stat, I2C_REG_STS(alg_data)); | 512 | iowrite32(stat, I2C_REG_STS(alg_data)); |
| 514 | } | 513 | } |
| 515 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { | 514 | if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { |
| 516 | dev_dbg(&adap->dev, | 515 | dev_dbg(&alg_data->adapter.dev, |
| 517 | "%s: AFI still set... clearing now.\n", | 516 | "%s: AFI still set... clearing now.\n", |
| 518 | adap->name); | 517 | alg_data->adapter.name); |
| 519 | iowrite32(stat, I2C_REG_STS(alg_data)); | 518 | iowrite32(stat, I2C_REG_STS(alg_data)); |
| 520 | } | 519 | } |
| 521 | } | 520 | } |
| 522 | 521 | ||
| 523 | bus_reset_if_active(adap); | 522 | bus_reset_if_active(alg_data); |
| 524 | 523 | ||
| 525 | /* Cleanup to be sure... */ | 524 | /* Cleanup to be sure... */ |
| 526 | alg_data->mif.buf = NULL; | 525 | alg_data->mif.buf = NULL; |
| 527 | alg_data->mif.len = 0; | 526 | alg_data->mif.len = 0; |
| 528 | 527 | ||
| 529 | dev_dbg(&adap->dev, "%s(): exiting, stat = %x\n", | 528 | dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n", |
| 530 | __func__, ioread32(I2C_REG_STS(alg_data))); | 529 | __func__, ioread32(I2C_REG_STS(alg_data))); |
| 531 | 530 | ||
| 532 | if (completed != num) | 531 | if (completed != num) |
| @@ -545,69 +544,92 @@ static struct i2c_algorithm pnx_algorithm = { | |||
| 545 | .functionality = i2c_pnx_func, | 544 | .functionality = i2c_pnx_func, |
| 546 | }; | 545 | }; |
| 547 | 546 | ||
| 547 | #ifdef CONFIG_PM | ||
| 548 | static int i2c_pnx_controller_suspend(struct platform_device *pdev, | 548 | static int i2c_pnx_controller_suspend(struct platform_device *pdev, |
| 549 | pm_message_t state) | 549 | pm_message_t state) |
| 550 | { | 550 | { |
| 551 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | 551 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
| 552 | return i2c_pnx->suspend(pdev, state); | 552 | |
| 553 | /* FIXME: shouldn't this be clk_disable? */ | ||
| 554 | clk_enable(alg_data->clk); | ||
| 555 | |||
| 556 | return 0; | ||
| 553 | } | 557 | } |
| 554 | 558 | ||
| 555 | static int i2c_pnx_controller_resume(struct platform_device *pdev) | 559 | static int i2c_pnx_controller_resume(struct platform_device *pdev) |
| 556 | { | 560 | { |
| 557 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | 561 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
| 558 | return i2c_pnx->resume(pdev); | 562 | |
| 563 | return clk_enable(alg_data->clk); | ||
| 559 | } | 564 | } |
| 565 | #else | ||
| 566 | #define i2c_pnx_controller_suspend NULL | ||
| 567 | #define i2c_pnx_controller_resume NULL | ||
| 568 | #endif | ||
| 560 | 569 | ||
| 561 | static int __devinit i2c_pnx_probe(struct platform_device *pdev) | 570 | static int __devinit i2c_pnx_probe(struct platform_device *pdev) |
| 562 | { | 571 | { |
| 563 | unsigned long tmp; | 572 | unsigned long tmp; |
| 564 | int ret = 0; | 573 | int ret = 0; |
| 565 | struct i2c_pnx_algo_data *alg_data; | 574 | struct i2c_pnx_algo_data *alg_data; |
| 566 | int freq_mhz; | 575 | unsigned long freq; |
| 567 | struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data; | 576 | struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data; |
| 568 | 577 | ||
| 569 | if (!i2c_pnx || !i2c_pnx->adapter) { | 578 | if (!i2c_pnx || !i2c_pnx->name) { |
| 570 | dev_err(&pdev->dev, "%s: no platform data supplied\n", | 579 | dev_err(&pdev->dev, "%s: no platform data supplied\n", |
| 571 | __func__); | 580 | __func__); |
| 572 | ret = -EINVAL; | 581 | ret = -EINVAL; |
| 573 | goto out; | 582 | goto out; |
| 574 | } | 583 | } |
| 575 | 584 | ||
| 576 | platform_set_drvdata(pdev, i2c_pnx); | 585 | alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL); |
| 577 | 586 | if (!alg_data) { | |
| 578 | if (i2c_pnx->calculate_input_freq) | 587 | ret = -ENOMEM; |
| 579 | freq_mhz = i2c_pnx->calculate_input_freq(pdev); | 588 | goto err_kzalloc; |
| 580 | else { | ||
| 581 | freq_mhz = PNX_DEFAULT_FREQ; | ||
| 582 | dev_info(&pdev->dev, "Setting bus frequency to default value: " | ||
| 583 | "%d MHz\n", freq_mhz); | ||
| 584 | } | 589 | } |
| 585 | 590 | ||
| 586 | i2c_pnx->adapter->algo = &pnx_algorithm; | 591 | platform_set_drvdata(pdev, alg_data); |
| 592 | |||
| 593 | strlcpy(alg_data->adapter.name, i2c_pnx->name, | ||
| 594 | sizeof(alg_data->adapter.name)); | ||
| 595 | alg_data->adapter.dev.parent = &pdev->dev; | ||
| 596 | alg_data->adapter.algo = &pnx_algorithm; | ||
| 597 | alg_data->adapter.algo_data = alg_data; | ||
| 598 | alg_data->adapter.nr = pdev->id; | ||
| 599 | alg_data->i2c_pnx = i2c_pnx; | ||
| 600 | |||
| 601 | alg_data->clk = clk_get(&pdev->dev, NULL); | ||
| 602 | if (IS_ERR(alg_data->clk)) { | ||
| 603 | ret = PTR_ERR(alg_data->clk); | ||
| 604 | goto out_drvdata; | ||
| 605 | } | ||
| 587 | 606 | ||
| 588 | alg_data = i2c_pnx->adapter->algo_data; | ||
| 589 | init_timer(&alg_data->mif.timer); | 607 | init_timer(&alg_data->mif.timer); |
| 590 | alg_data->mif.timer.function = i2c_pnx_timeout; | 608 | alg_data->mif.timer.function = i2c_pnx_timeout; |
| 591 | alg_data->mif.timer.data = (unsigned long)i2c_pnx->adapter; | 609 | alg_data->mif.timer.data = (unsigned long)alg_data; |
| 592 | 610 | ||
| 593 | /* Register I/O resource */ | 611 | /* Register I/O resource */ |
| 594 | if (!request_mem_region(alg_data->base, I2C_PNX_REGION_SIZE, | 612 | if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE, |
| 595 | pdev->name)) { | 613 | pdev->name)) { |
| 596 | dev_err(&pdev->dev, | 614 | dev_err(&pdev->dev, |
| 597 | "I/O region 0x%08x for I2C already in use.\n", | 615 | "I/O region 0x%08x for I2C already in use.\n", |
| 598 | alg_data->base); | 616 | i2c_pnx->base); |
| 599 | ret = -ENODEV; | 617 | ret = -ENODEV; |
| 600 | goto out_drvdata; | 618 | goto out_clkget; |
| 601 | } | 619 | } |
| 602 | 620 | ||
| 603 | if (!(alg_data->ioaddr = | 621 | alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
| 604 | (u32)ioremap(alg_data->base, I2C_PNX_REGION_SIZE))) { | 622 | if (!alg_data->ioaddr) { |
| 605 | dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n"); | 623 | dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n"); |
| 606 | ret = -ENOMEM; | 624 | ret = -ENOMEM; |
| 607 | goto out_release; | 625 | goto out_release; |
| 608 | } | 626 | } |
| 609 | 627 | ||
| 610 | i2c_pnx->set_clock_run(pdev); | 628 | ret = clk_enable(alg_data->clk); |
| 629 | if (ret) | ||
| 630 | goto out_unmap; | ||
| 631 | |||
| 632 | freq = clk_get_rate(alg_data->clk); | ||
| 611 | 633 | ||
| 612 | /* | 634 | /* |
| 613 | * Clock Divisor High This value is the number of system clocks | 635 | * Clock Divisor High This value is the number of system clocks |
| @@ -620,45 +642,47 @@ static int __devinit i2c_pnx_probe(struct platform_device *pdev) | |||
| 620 | * the deglitching filter length. | 642 | * the deglitching filter length. |
| 621 | */ | 643 | */ |
| 622 | 644 | ||
| 623 | tmp = ((freq_mhz * 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2; | 645 | tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2; |
| 624 | iowrite32(tmp, I2C_REG_CKH(alg_data)); | 646 | iowrite32(tmp, I2C_REG_CKH(alg_data)); |
| 625 | iowrite32(tmp, I2C_REG_CKL(alg_data)); | 647 | iowrite32(tmp, I2C_REG_CKL(alg_data)); |
| 626 | 648 | ||
| 627 | iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); | 649 | iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); |
| 628 | if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) { | 650 | if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) { |
| 629 | ret = -ENODEV; | 651 | ret = -ENODEV; |
| 630 | goto out_unmap; | 652 | goto out_clock; |
| 631 | } | 653 | } |
| 632 | init_completion(&alg_data->mif.complete); | 654 | init_completion(&alg_data->mif.complete); |
| 633 | 655 | ||
| 634 | ret = request_irq(alg_data->irq, i2c_pnx_interrupt, | 656 | ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt, |
| 635 | 0, pdev->name, i2c_pnx->adapter); | 657 | 0, pdev->name, alg_data); |
| 636 | if (ret) | 658 | if (ret) |
| 637 | goto out_clock; | 659 | goto out_clock; |
| 638 | 660 | ||
| 639 | /* Register this adapter with the I2C subsystem */ | 661 | /* Register this adapter with the I2C subsystem */ |
| 640 | i2c_pnx->adapter->dev.parent = &pdev->dev; | 662 | ret = i2c_add_numbered_adapter(&alg_data->adapter); |
| 641 | i2c_pnx->adapter->nr = pdev->id; | ||
| 642 | ret = i2c_add_numbered_adapter(i2c_pnx->adapter); | ||
| 643 | if (ret < 0) { | 663 | if (ret < 0) { |
| 644 | dev_err(&pdev->dev, "I2C: Failed to add bus\n"); | 664 | dev_err(&pdev->dev, "I2C: Failed to add bus\n"); |
| 645 | goto out_irq; | 665 | goto out_irq; |
| 646 | } | 666 | } |
| 647 | 667 | ||
| 648 | dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n", | 668 | dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n", |
| 649 | i2c_pnx->adapter->name, alg_data->base, alg_data->irq); | 669 | alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq); |
| 650 | 670 | ||
| 651 | return 0; | 671 | return 0; |
| 652 | 672 | ||
| 653 | out_irq: | 673 | out_irq: |
| 654 | free_irq(alg_data->irq, i2c_pnx->adapter); | 674 | free_irq(i2c_pnx->irq, alg_data); |
| 655 | out_clock: | 675 | out_clock: |
| 656 | i2c_pnx->set_clock_stop(pdev); | 676 | clk_disable(alg_data->clk); |
| 657 | out_unmap: | 677 | out_unmap: |
| 658 | iounmap((void *)alg_data->ioaddr); | 678 | iounmap(alg_data->ioaddr); |
| 659 | out_release: | 679 | out_release: |
| 660 | release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE); | 680 | release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
| 681 | out_clkget: | ||
| 682 | clk_put(alg_data->clk); | ||
| 661 | out_drvdata: | 683 | out_drvdata: |
| 684 | kfree(alg_data); | ||
| 685 | err_kzalloc: | ||
| 662 | platform_set_drvdata(pdev, NULL); | 686 | platform_set_drvdata(pdev, NULL); |
| 663 | out: | 687 | out: |
| 664 | return ret; | 688 | return ret; |
| @@ -666,15 +690,16 @@ out: | |||
| 666 | 690 | ||
| 667 | static int __devexit i2c_pnx_remove(struct platform_device *pdev) | 691 | static int __devexit i2c_pnx_remove(struct platform_device *pdev) |
| 668 | { | 692 | { |
| 669 | struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); | 693 | struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
| 670 | struct i2c_adapter *adap = i2c_pnx->adapter; | 694 | struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx; |
| 671 | struct i2c_pnx_algo_data *alg_data = adap->algo_data; | 695 | |
| 672 | 696 | free_irq(i2c_pnx->irq, alg_data); | |
| 673 | free_irq(alg_data->irq, i2c_pnx->adapter); | 697 | i2c_del_adapter(&alg_data->adapter); |
| 674 | i2c_del_adapter(adap); | 698 | clk_disable(alg_data->clk); |
| 675 | i2c_pnx->set_clock_stop(pdev); | 699 | iounmap(alg_data->ioaddr); |
| 676 | iounmap((void *)alg_data->ioaddr); | 700 | release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE); |
| 677 | release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE); | 701 | clk_put(alg_data->clk); |
| 702 | kfree(alg_data); | ||
| 678 | platform_set_drvdata(pdev, NULL); | 703 | platform_set_drvdata(pdev, NULL); |
| 679 | 704 | ||
| 680 | return 0; | 705 | return 0; |
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 90d168ad03b6..84c103a7ee13 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
| 5 | * Copyright (C) 2010 ST-Ericsson AB. | ||
| 5 | * | 6 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
| @@ -34,9 +35,6 @@ | |||
| 34 | 35 | ||
| 35 | #define DRIVER_NAME "mmci-pl18x" | 36 | #define DRIVER_NAME "mmci-pl18x" |
| 36 | 37 | ||
| 37 | #define DBG(host,fmt,args...) \ | ||
| 38 | pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args) | ||
| 39 | |||
| 40 | static unsigned int fmax = 515633; | 38 | static unsigned int fmax = 515633; |
| 41 | 39 | ||
| 42 | /* | 40 | /* |
| @@ -105,8 +103,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) | |||
| 105 | void __iomem *base; | 103 | void __iomem *base; |
| 106 | int blksz_bits; | 104 | int blksz_bits; |
| 107 | 105 | ||
| 108 | DBG(host, "blksz %04x blks %04x flags %08x\n", | 106 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
| 109 | data->blksz, data->blocks, data->flags); | 107 | data->blksz, data->blocks, data->flags); |
| 110 | 108 | ||
| 111 | host->data = data; | 109 | host->data = data; |
| 112 | host->size = data->blksz; | 110 | host->size = data->blksz; |
| @@ -155,7 +153,7 @@ mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |||
| 155 | { | 153 | { |
| 156 | void __iomem *base = host->base; | 154 | void __iomem *base = host->base; |
| 157 | 155 | ||
| 158 | DBG(host, "op %02x arg %08x flags %08x\n", | 156 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
| 159 | cmd->opcode, cmd->arg, cmd->flags); | 157 | cmd->opcode, cmd->arg, cmd->flags); |
| 160 | 158 | ||
| 161 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | 159 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { |
| @@ -184,8 +182,20 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |||
| 184 | { | 182 | { |
| 185 | if (status & MCI_DATABLOCKEND) { | 183 | if (status & MCI_DATABLOCKEND) { |
| 186 | host->data_xfered += data->blksz; | 184 | host->data_xfered += data->blksz; |
| 185 | #ifdef CONFIG_ARCH_U300 | ||
| 186 | /* | ||
| 187 | * On the U300 some signal or other is | ||
| 188 | * badly routed so that a data write does | ||
| 189 | * not properly terminate with a MCI_DATAEND | ||
| 190 | * status flag. This quirk will make writes | ||
| 191 | * work again. | ||
| 192 | */ | ||
| 193 | if (data->flags & MMC_DATA_WRITE) | ||
| 194 | status |= MCI_DATAEND; | ||
| 195 | #endif | ||
| 187 | } | 196 | } |
| 188 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | 197 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { |
| 198 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); | ||
| 189 | if (status & MCI_DATACRCFAIL) | 199 | if (status & MCI_DATACRCFAIL) |
| 190 | data->error = -EILSEQ; | 200 | data->error = -EILSEQ; |
| 191 | else if (status & MCI_DATATIMEOUT) | 201 | else if (status & MCI_DATATIMEOUT) |
| @@ -307,7 +317,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id) | |||
| 307 | 317 | ||
| 308 | status = readl(base + MMCISTATUS); | 318 | status = readl(base + MMCISTATUS); |
| 309 | 319 | ||
| 310 | DBG(host, "irq1 %08x\n", status); | 320 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
| 311 | 321 | ||
| 312 | do { | 322 | do { |
| 313 | unsigned long flags; | 323 | unsigned long flags; |
| @@ -401,7 +411,7 @@ static irqreturn_t mmci_irq(int irq, void *dev_id) | |||
| 401 | status &= readl(host->base + MMCIMASK0); | 411 | status &= readl(host->base + MMCIMASK0); |
| 402 | writel(status, host->base + MMCICLEAR); | 412 | writel(status, host->base + MMCICLEAR); |
| 403 | 413 | ||
| 404 | DBG(host, "irq0 %08x\n", status); | 414 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
| 405 | 415 | ||
| 406 | data = host->data; | 416 | data = host->data; |
| 407 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | 417 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| |
| @@ -428,8 +438,8 @@ static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |||
| 428 | WARN_ON(host->mrq != NULL); | 438 | WARN_ON(host->mrq != NULL); |
| 429 | 439 | ||
| 430 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { | 440 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
| 431 | printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n", | 441 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
| 432 | mmc_hostname(mmc), mrq->data->blksz); | 442 | mrq->data->blksz); |
| 433 | mrq->cmd->error = -EINVAL; | 443 | mrq->cmd->error = -EINVAL; |
| 434 | mmc_request_done(mmc, mrq); | 444 | mmc_request_done(mmc, mrq); |
| 435 | return; | 445 | return; |
| @@ -582,8 +592,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
| 582 | 592 | ||
| 583 | host->hw_designer = amba_manf(dev); | 593 | host->hw_designer = amba_manf(dev); |
| 584 | host->hw_revision = amba_rev(dev); | 594 | host->hw_revision = amba_rev(dev); |
| 585 | DBG(host, "designer ID = 0x%02x\n", host->hw_designer); | 595 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
| 586 | DBG(host, "revision = 0x%01x\n", host->hw_revision); | 596 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); |
| 587 | 597 | ||
| 588 | host->clk = clk_get(&dev->dev, NULL); | 598 | host->clk = clk_get(&dev->dev, NULL); |
| 589 | if (IS_ERR(host->clk)) { | 599 | if (IS_ERR(host->clk)) { |
| @@ -608,7 +618,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
| 608 | if (ret < 0) | 618 | if (ret < 0) |
| 609 | goto clk_disable; | 619 | goto clk_disable; |
| 610 | host->mclk = clk_get_rate(host->clk); | 620 | host->mclk = clk_get_rate(host->clk); |
| 611 | DBG(host, "eventual mclk rate: %u Hz\n", host->mclk); | 621 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
| 622 | host->mclk); | ||
| 612 | } | 623 | } |
| 613 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); | 624 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
| 614 | if (!host->base) { | 625 | if (!host->base) { |
| @@ -619,6 +630,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
| 619 | mmc->ops = &mmci_ops; | 630 | mmc->ops = &mmci_ops; |
| 620 | mmc->f_min = (host->mclk + 511) / 512; | 631 | mmc->f_min = (host->mclk + 511) / 512; |
| 621 | mmc->f_max = min(host->mclk, fmax); | 632 | mmc->f_max = min(host->mclk, fmax); |
| 633 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); | ||
| 634 | |||
| 622 | #ifdef CONFIG_REGULATOR | 635 | #ifdef CONFIG_REGULATOR |
| 623 | /* If we're using the regulator framework, try to fetch a regulator */ | 636 | /* If we're using the regulator framework, try to fetch a regulator */ |
| 624 | host->vcc = regulator_get(&dev->dev, "vmmc"); | 637 | host->vcc = regulator_get(&dev->dev, "vmmc"); |
| @@ -712,7 +725,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) | |||
| 712 | 725 | ||
| 713 | mmc_add_host(mmc); | 726 | mmc_add_host(mmc); |
| 714 | 727 | ||
| 715 | printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", | 728 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
| 716 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), | 729 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
| 717 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); | 730 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
| 718 | 731 | ||
diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c index 0264b117893b..c256aacfa954 100644 --- a/drivers/rtc/rtc-pl031.c +++ b/drivers/rtc/rtc-pl031.c | |||
| @@ -7,6 +7,9 @@ | |||
| 7 | * | 7 | * |
| 8 | * Copyright 2006 (c) MontaVista Software, Inc. | 8 | * Copyright 2006 (c) MontaVista Software, Inc. |
| 9 | * | 9 | * |
| 10 | * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> | ||
| 11 | * Copyright 2010 (c) ST-Ericsson AB | ||
| 12 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | 13 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License | 14 | * modify it under the terms of the GNU General Public License |
| 12 | * as published by the Free Software Foundation; either version | 15 | * as published by the Free Software Foundation; either version |
| @@ -18,6 +21,9 @@ | |||
| 18 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
| 19 | #include <linux/amba/bus.h> | 22 | #include <linux/amba/bus.h> |
| 20 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/bcd.h> | ||
| 25 | #include <linux/delay.h> | ||
| 26 | #include <linux/version.h> | ||
| 21 | 27 | ||
| 22 | /* | 28 | /* |
| 23 | * Register definitions | 29 | * Register definitions |
| @@ -30,35 +36,207 @@ | |||
| 30 | #define RTC_RIS 0x14 /* Raw interrupt status register */ | 36 | #define RTC_RIS 0x14 /* Raw interrupt status register */ |
| 31 | #define RTC_MIS 0x18 /* Masked interrupt status register */ | 37 | #define RTC_MIS 0x18 /* Masked interrupt status register */ |
| 32 | #define RTC_ICR 0x1c /* Interrupt clear register */ | 38 | #define RTC_ICR 0x1c /* Interrupt clear register */ |
| 39 | /* ST variants have additional timer functionality */ | ||
| 40 | #define RTC_TDR 0x20 /* Timer data read register */ | ||
| 41 | #define RTC_TLR 0x24 /* Timer data load register */ | ||
| 42 | #define RTC_TCR 0x28 /* Timer control register */ | ||
| 43 | #define RTC_YDR 0x30 /* Year data read register */ | ||
| 44 | #define RTC_YMR 0x34 /* Year match register */ | ||
| 45 | #define RTC_YLR 0x38 /* Year data load register */ | ||
| 46 | |||
| 47 | #define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */ | ||
| 48 | |||
| 49 | #define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */ | ||
| 50 | |||
| 51 | /* Common bit definitions for Interrupt status and control registers */ | ||
| 52 | #define RTC_BIT_AI (1 << 0) /* Alarm interrupt bit */ | ||
| 53 | #define RTC_BIT_PI (1 << 1) /* Periodic interrupt bit. ST variants only. */ | ||
| 54 | |||
| 55 | /* Common bit definations for ST v2 for reading/writing time */ | ||
| 56 | #define RTC_SEC_SHIFT 0 | ||
| 57 | #define RTC_SEC_MASK (0x3F << RTC_SEC_SHIFT) /* Second [0-59] */ | ||
| 58 | #define RTC_MIN_SHIFT 6 | ||
| 59 | #define RTC_MIN_MASK (0x3F << RTC_MIN_SHIFT) /* Minute [0-59] */ | ||
| 60 | #define RTC_HOUR_SHIFT 12 | ||
| 61 | #define RTC_HOUR_MASK (0x1F << RTC_HOUR_SHIFT) /* Hour [0-23] */ | ||
| 62 | #define RTC_WDAY_SHIFT 17 | ||
| 63 | #define RTC_WDAY_MASK (0x7 << RTC_WDAY_SHIFT) /* Day of Week [1-7] 1=Sunday */ | ||
| 64 | #define RTC_MDAY_SHIFT 20 | ||
| 65 | #define RTC_MDAY_MASK (0x1F << RTC_MDAY_SHIFT) /* Day of Month [1-31] */ | ||
| 66 | #define RTC_MON_SHIFT 25 | ||
| 67 | #define RTC_MON_MASK (0xF << RTC_MON_SHIFT) /* Month [1-12] 1=January */ | ||
| 68 | |||
| 69 | #define RTC_TIMER_FREQ 32768 | ||
| 33 | 70 | ||
| 34 | struct pl031_local { | 71 | struct pl031_local { |
| 35 | struct rtc_device *rtc; | 72 | struct rtc_device *rtc; |
| 36 | void __iomem *base; | 73 | void __iomem *base; |
| 74 | u8 hw_designer; | ||
| 75 | u8 hw_revision:4; | ||
| 37 | }; | 76 | }; |
| 38 | 77 | ||
| 39 | static irqreturn_t pl031_interrupt(int irq, void *dev_id) | 78 | static int pl031_alarm_irq_enable(struct device *dev, |
| 79 | unsigned int enabled) | ||
| 80 | { | ||
| 81 | struct pl031_local *ldata = dev_get_drvdata(dev); | ||
| 82 | unsigned long imsc; | ||
| 83 | |||
| 84 | /* Clear any pending alarm interrupts. */ | ||
| 85 | writel(RTC_BIT_AI, ldata->base + RTC_ICR); | ||
| 86 | |||
| 87 | imsc = readl(ldata->base + RTC_IMSC); | ||
| 88 | |||
| 89 | if (enabled == 1) | ||
| 90 | writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC); | ||
| 91 | else | ||
| 92 | writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC); | ||
| 93 | |||
| 94 | return 0; | ||
| 95 | } | ||
| 96 | |||
| 97 | /* | ||
| 98 | * Convert Gregorian date to ST v2 RTC format. | ||
| 99 | */ | ||
| 100 | static int pl031_stv2_tm_to_time(struct device *dev, | ||
| 101 | struct rtc_time *tm, unsigned long *st_time, | ||
| 102 | unsigned long *bcd_year) | ||
| 103 | { | ||
| 104 | int year = tm->tm_year + 1900; | ||
| 105 | int wday = tm->tm_wday; | ||
| 106 | |||
| 107 | /* wday masking is not working in hardware so wday must be valid */ | ||
| 108 | if (wday < -1 || wday > 6) { | ||
| 109 | dev_err(dev, "invalid wday value %d\n", tm->tm_wday); | ||
| 110 | return -EINVAL; | ||
| 111 | } else if (wday == -1) { | ||
| 112 | /* wday is not provided, calculate it here */ | ||
| 113 | unsigned long time; | ||
| 114 | struct rtc_time calc_tm; | ||
| 115 | |||
| 116 | rtc_tm_to_time(tm, &time); | ||
| 117 | rtc_time_to_tm(time, &calc_tm); | ||
| 118 | wday = calc_tm.tm_wday; | ||
| 119 | } | ||
| 120 | |||
| 121 | *bcd_year = (bin2bcd(year % 100) | bin2bcd(year / 100) << 8); | ||
| 122 | |||
| 123 | *st_time = ((tm->tm_mon + 1) << RTC_MON_SHIFT) | ||
| 124 | | (tm->tm_mday << RTC_MDAY_SHIFT) | ||
| 125 | | ((wday + 1) << RTC_WDAY_SHIFT) | ||
| 126 | | (tm->tm_hour << RTC_HOUR_SHIFT) | ||
| 127 | | (tm->tm_min << RTC_MIN_SHIFT) | ||
| 128 | | (tm->tm_sec << RTC_SEC_SHIFT); | ||
| 129 | |||
| 130 | return 0; | ||
| 131 | } | ||
| 132 | |||
| 133 | /* | ||
| 134 | * Convert ST v2 RTC format to Gregorian date. | ||
| 135 | */ | ||
| 136 | static int pl031_stv2_time_to_tm(unsigned long st_time, unsigned long bcd_year, | ||
| 137 | struct rtc_time *tm) | ||
| 138 | { | ||
| 139 | tm->tm_year = bcd2bin(bcd_year) + (bcd2bin(bcd_year >> 8) * 100); | ||
| 140 | tm->tm_mon = ((st_time & RTC_MON_MASK) >> RTC_MON_SHIFT) - 1; | ||
| 141 | tm->tm_mday = ((st_time & RTC_MDAY_MASK) >> RTC_MDAY_SHIFT); | ||
| 142 | tm->tm_wday = ((st_time & RTC_WDAY_MASK) >> RTC_WDAY_SHIFT) - 1; | ||
| 143 | tm->tm_hour = ((st_time & RTC_HOUR_MASK) >> RTC_HOUR_SHIFT); | ||
| 144 | tm->tm_min = ((st_time & RTC_MIN_MASK) >> RTC_MIN_SHIFT); | ||
| 145 | tm->tm_sec = ((st_time & RTC_SEC_MASK) >> RTC_SEC_SHIFT); | ||
| 146 | |||
| 147 | tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year); | ||
| 148 | tm->tm_year -= 1900; | ||
| 149 | |||
| 150 | return 0; | ||
| 151 | } | ||
| 152 | |||
| 153 | static int pl031_stv2_read_time(struct device *dev, struct rtc_time *tm) | ||
| 154 | { | ||
| 155 | struct pl031_local *ldata = dev_get_drvdata(dev); | ||
| 156 | |||
| 157 | pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR), | ||
| 158 | readl(ldata->base + RTC_YDR), tm); | ||
| 159 | |||
| 160 | return 0; | ||
| 161 | } | ||
| 162 | |||
| 163 | static int pl031_stv2_set_time(struct device *dev, struct rtc_time *tm) | ||
| 164 | { | ||
| 165 | unsigned long time; | ||
| 166 | unsigned long bcd_year; | ||
| 167 | struct pl031_local *ldata = dev_get_drvdata(dev); | ||
| 168 | int ret; | ||
| 169 | |||
| 170 | ret = pl031_stv2_tm_to_time(dev, tm, &time, &bcd_year); | ||
| 171 | if (ret == 0) { | ||
| 172 | writel(bcd_year, ldata->base + RTC_YLR); | ||
| 173 | writel(time, ldata->base + RTC_LR); | ||
| 174 | } | ||
| 175 | |||
| 176 | return ret; | ||
| 177 | } | ||
| 178 | |||
| 179 | static int pl031_stv2_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | ||
| 40 | { | 180 | { |
| 41 | struct rtc_device *rtc = dev_id; | 181 | struct pl031_local *ldata = dev_get_drvdata(dev); |
| 182 | int ret; | ||
| 42 | 183 | ||
| 43 | rtc_update_irq(rtc, 1, RTC_AF); | 184 | ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR), |
| 185 | readl(ldata->base + RTC_YMR), &alarm->time); | ||
| 44 | 186 | ||
| 45 | return IRQ_HANDLED; | 187 | alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI; |
| 188 | alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI; | ||
| 189 | |||
| 190 | return ret; | ||
| 46 | } | 191 | } |
| 47 | 192 | ||
| 48 | static int pl031_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | 193 | static int pl031_stv2_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
| 49 | { | 194 | { |
| 50 | struct pl031_local *ldata = dev_get_drvdata(dev); | 195 | struct pl031_local *ldata = dev_get_drvdata(dev); |
| 196 | unsigned long time; | ||
| 197 | unsigned long bcd_year; | ||
| 198 | int ret; | ||
| 199 | |||
| 200 | /* At the moment, we can only deal with non-wildcarded alarm times. */ | ||
| 201 | ret = rtc_valid_tm(&alarm->time); | ||
| 202 | if (ret == 0) { | ||
| 203 | ret = pl031_stv2_tm_to_time(dev, &alarm->time, | ||
| 204 | &time, &bcd_year); | ||
| 205 | if (ret == 0) { | ||
| 206 | writel(bcd_year, ldata->base + RTC_YMR); | ||
| 207 | writel(time, ldata->base + RTC_MR); | ||
| 208 | |||
| 209 | pl031_alarm_irq_enable(dev, alarm->enabled); | ||
| 210 | } | ||
| 211 | } | ||
| 212 | |||
| 213 | return ret; | ||
| 214 | } | ||
| 215 | |||
| 216 | static irqreturn_t pl031_interrupt(int irq, void *dev_id) | ||
| 217 | { | ||
| 218 | struct pl031_local *ldata = dev_id; | ||
| 219 | unsigned long rtcmis; | ||
| 220 | unsigned long events = 0; | ||
| 221 | |||
| 222 | rtcmis = readl(ldata->base + RTC_MIS); | ||
| 223 | if (rtcmis) { | ||
| 224 | writel(rtcmis, ldata->base + RTC_ICR); | ||
| 225 | |||
| 226 | if (rtcmis & RTC_BIT_AI) | ||
| 227 | events |= (RTC_AF | RTC_IRQF); | ||
| 228 | |||
| 229 | /* Timer interrupt is only available in ST variants */ | ||
| 230 | if ((rtcmis & RTC_BIT_PI) && | ||
| 231 | (ldata->hw_designer == AMBA_VENDOR_ST)) | ||
| 232 | events |= (RTC_PF | RTC_IRQF); | ||
| 233 | |||
| 234 | rtc_update_irq(ldata->rtc, 1, events); | ||
| 51 | 235 | ||
| 52 | switch (cmd) { | 236 | return IRQ_HANDLED; |
| 53 | case RTC_AIE_OFF: | ||
| 54 | writel(1, ldata->base + RTC_MIS); | ||
| 55 | return 0; | ||
| 56 | case RTC_AIE_ON: | ||
| 57 | writel(0, ldata->base + RTC_MIS); | ||
| 58 | return 0; | ||
| 59 | } | 237 | } |
| 60 | 238 | ||
| 61 | return -ENOIOCTLCMD; | 239 | return IRQ_NONE; |
| 62 | } | 240 | } |
| 63 | 241 | ||
| 64 | static int pl031_read_time(struct device *dev, struct rtc_time *tm) | 242 | static int pl031_read_time(struct device *dev, struct rtc_time *tm) |
| @@ -74,11 +252,14 @@ static int pl031_set_time(struct device *dev, struct rtc_time *tm) | |||
| 74 | { | 252 | { |
| 75 | unsigned long time; | 253 | unsigned long time; |
| 76 | struct pl031_local *ldata = dev_get_drvdata(dev); | 254 | struct pl031_local *ldata = dev_get_drvdata(dev); |
| 255 | int ret; | ||
| 77 | 256 | ||
| 78 | rtc_tm_to_time(tm, &time); | 257 | ret = rtc_tm_to_time(tm, &time); |
| 79 | writel(time, ldata->base + RTC_LR); | ||
| 80 | 258 | ||
| 81 | return 0; | 259 | if (ret == 0) |
| 260 | writel(time, ldata->base + RTC_LR); | ||
| 261 | |||
| 262 | return ret; | ||
| 82 | } | 263 | } |
| 83 | 264 | ||
| 84 | static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | 265 | static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) |
| @@ -86,8 +267,9 @@ static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |||
| 86 | struct pl031_local *ldata = dev_get_drvdata(dev); | 267 | struct pl031_local *ldata = dev_get_drvdata(dev); |
| 87 | 268 | ||
| 88 | rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time); | 269 | rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time); |
| 89 | alarm->pending = readl(ldata->base + RTC_RIS); | 270 | |
| 90 | alarm->enabled = readl(ldata->base + RTC_IMSC); | 271 | alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI; |
| 272 | alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI; | ||
| 91 | 273 | ||
| 92 | return 0; | 274 | return 0; |
| 93 | } | 275 | } |
| @@ -96,22 +278,71 @@ static int pl031_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) | |||
| 96 | { | 278 | { |
| 97 | struct pl031_local *ldata = dev_get_drvdata(dev); | 279 | struct pl031_local *ldata = dev_get_drvdata(dev); |
| 98 | unsigned long time; | 280 | unsigned long time; |
| 281 | int ret; | ||
| 282 | |||
| 283 | /* At the moment, we can only deal with non-wildcarded alarm times. */ | ||
| 284 | ret = rtc_valid_tm(&alarm->time); | ||
| 285 | if (ret == 0) { | ||
| 286 | ret = rtc_tm_to_time(&alarm->time, &time); | ||
| 287 | if (ret == 0) { | ||
| 288 | writel(time, ldata->base + RTC_MR); | ||
| 289 | pl031_alarm_irq_enable(dev, alarm->enabled); | ||
| 290 | } | ||
| 291 | } | ||
| 292 | |||
| 293 | return ret; | ||
| 294 | } | ||
| 295 | |||
| 296 | /* Periodic interrupt is only available in ST variants. */ | ||
| 297 | static int pl031_irq_set_state(struct device *dev, int enabled) | ||
| 298 | { | ||
| 299 | struct pl031_local *ldata = dev_get_drvdata(dev); | ||
| 300 | |||
| 301 | if (enabled == 1) { | ||
| 302 | /* Clear any pending timer interrupt. */ | ||
| 303 | writel(RTC_BIT_PI, ldata->base + RTC_ICR); | ||
| 304 | |||
| 305 | writel(readl(ldata->base + RTC_IMSC) | RTC_BIT_PI, | ||
| 306 | ldata->base + RTC_IMSC); | ||
| 99 | 307 | ||
| 100 | rtc_tm_to_time(&alarm->time, &time); | 308 | /* Now start the timer */ |
| 309 | writel(readl(ldata->base + RTC_TCR) | RTC_TCR_EN, | ||
| 310 | ldata->base + RTC_TCR); | ||
| 101 | 311 | ||
| 102 | writel(time, ldata->base + RTC_MR); | 312 | } else { |
| 103 | writel(!alarm->enabled, ldata->base + RTC_MIS); | 313 | writel(readl(ldata->base + RTC_IMSC) & (~RTC_BIT_PI), |
| 314 | ldata->base + RTC_IMSC); | ||
| 315 | |||
| 316 | /* Also stop the timer */ | ||
| 317 | writel(readl(ldata->base + RTC_TCR) & (~RTC_TCR_EN), | ||
| 318 | ldata->base + RTC_TCR); | ||
| 319 | } | ||
| 320 | /* Wait at least 1 RTC32 clock cycle to ensure next access | ||
| 321 | * to RTC_TCR will succeed. | ||
| 322 | */ | ||
| 323 | udelay(40); | ||
| 104 | 324 | ||
| 105 | return 0; | 325 | return 0; |
| 106 | } | 326 | } |
| 107 | 327 | ||
| 108 | static const struct rtc_class_ops pl031_ops = { | 328 | static int pl031_irq_set_freq(struct device *dev, int freq) |
| 109 | .ioctl = pl031_ioctl, | 329 | { |
| 110 | .read_time = pl031_read_time, | 330 | struct pl031_local *ldata = dev_get_drvdata(dev); |
| 111 | .set_time = pl031_set_time, | 331 | |
| 112 | .read_alarm = pl031_read_alarm, | 332 | /* Cant set timer if it is already enabled */ |
| 113 | .set_alarm = pl031_set_alarm, | 333 | if (readl(ldata->base + RTC_TCR) & RTC_TCR_EN) { |
| 114 | }; | 334 | dev_err(dev, "can't change frequency while timer enabled\n"); |
| 335 | return -EINVAL; | ||
| 336 | } | ||
| 337 | |||
| 338 | /* If self start bit in RTC_TCR is set timer will start here, | ||
| 339 | * but we never set that bit. Instead we start the timer when | ||
| 340 | * set_state is called with enabled == 1. | ||
| 341 | */ | ||
| 342 | writel(RTC_TIMER_FREQ / freq, ldata->base + RTC_TLR); | ||
| 343 | |||
| 344 | return 0; | ||
| 345 | } | ||
| 115 | 346 | ||
| 116 | static int pl031_remove(struct amba_device *adev) | 347 | static int pl031_remove(struct amba_device *adev) |
| 117 | { | 348 | { |
| @@ -131,18 +362,20 @@ static int pl031_probe(struct amba_device *adev, struct amba_id *id) | |||
| 131 | { | 362 | { |
| 132 | int ret; | 363 | int ret; |
| 133 | struct pl031_local *ldata; | 364 | struct pl031_local *ldata; |
| 365 | struct rtc_class_ops *ops = id->data; | ||
| 134 | 366 | ||
| 135 | ret = amba_request_regions(adev, NULL); | 367 | ret = amba_request_regions(adev, NULL); |
| 136 | if (ret) | 368 | if (ret) |
| 137 | goto err_req; | 369 | goto err_req; |
| 138 | 370 | ||
| 139 | ldata = kmalloc(sizeof(struct pl031_local), GFP_KERNEL); | 371 | ldata = kzalloc(sizeof(struct pl031_local), GFP_KERNEL); |
| 140 | if (!ldata) { | 372 | if (!ldata) { |
| 141 | ret = -ENOMEM; | 373 | ret = -ENOMEM; |
| 142 | goto out; | 374 | goto out; |
| 143 | } | 375 | } |
| 144 | 376 | ||
| 145 | ldata->base = ioremap(adev->res.start, resource_size(&adev->res)); | 377 | ldata->base = ioremap(adev->res.start, resource_size(&adev->res)); |
| 378 | |||
| 146 | if (!ldata->base) { | 379 | if (!ldata->base) { |
| 147 | ret = -ENOMEM; | 380 | ret = -ENOMEM; |
| 148 | goto out_no_remap; | 381 | goto out_no_remap; |
| @@ -150,24 +383,36 @@ static int pl031_probe(struct amba_device *adev, struct amba_id *id) | |||
| 150 | 383 | ||
| 151 | amba_set_drvdata(adev, ldata); | 384 | amba_set_drvdata(adev, ldata); |
| 152 | 385 | ||
| 153 | if (request_irq(adev->irq[0], pl031_interrupt, IRQF_DISABLED, | 386 | ldata->hw_designer = amba_manf(adev); |
| 154 | "rtc-pl031", ldata->rtc)) { | 387 | ldata->hw_revision = amba_rev(adev); |
| 155 | ret = -EIO; | 388 | |
| 156 | goto out_no_irq; | 389 | dev_dbg(&adev->dev, "designer ID = 0x%02x\n", ldata->hw_designer); |
| 157 | } | 390 | dev_dbg(&adev->dev, "revision = 0x%01x\n", ldata->hw_revision); |
| 158 | 391 | ||
| 159 | ldata->rtc = rtc_device_register("pl031", &adev->dev, &pl031_ops, | 392 | /* Enable the clockwatch on ST Variants */ |
| 160 | THIS_MODULE); | 393 | if ((ldata->hw_designer == AMBA_VENDOR_ST) && |
| 394 | (ldata->hw_revision > 1)) | ||
| 395 | writel(readl(ldata->base + RTC_CR) | RTC_CR_CWEN, | ||
| 396 | ldata->base + RTC_CR); | ||
| 397 | |||
| 398 | ldata->rtc = rtc_device_register("pl031", &adev->dev, ops, | ||
| 399 | THIS_MODULE); | ||
| 161 | if (IS_ERR(ldata->rtc)) { | 400 | if (IS_ERR(ldata->rtc)) { |
| 162 | ret = PTR_ERR(ldata->rtc); | 401 | ret = PTR_ERR(ldata->rtc); |
| 163 | goto out_no_rtc; | 402 | goto out_no_rtc; |
| 164 | } | 403 | } |
| 165 | 404 | ||
| 405 | if (request_irq(adev->irq[0], pl031_interrupt, | ||
| 406 | IRQF_DISABLED | IRQF_SHARED, "rtc-pl031", ldata)) { | ||
| 407 | ret = -EIO; | ||
| 408 | goto out_no_irq; | ||
| 409 | } | ||
| 410 | |||
| 166 | return 0; | 411 | return 0; |
| 167 | 412 | ||
| 168 | out_no_rtc: | ||
| 169 | free_irq(adev->irq[0], ldata->rtc); | ||
| 170 | out_no_irq: | 413 | out_no_irq: |
| 414 | rtc_device_unregister(ldata->rtc); | ||
| 415 | out_no_rtc: | ||
| 171 | iounmap(ldata->base); | 416 | iounmap(ldata->base); |
| 172 | amba_set_drvdata(adev, NULL); | 417 | amba_set_drvdata(adev, NULL); |
| 173 | out_no_remap: | 418 | out_no_remap: |
| @@ -175,13 +420,57 @@ out_no_remap: | |||
| 175 | out: | 420 | out: |
| 176 | amba_release_regions(adev); | 421 | amba_release_regions(adev); |
| 177 | err_req: | 422 | err_req: |
| 423 | |||
| 178 | return ret; | 424 | return ret; |
| 179 | } | 425 | } |
| 180 | 426 | ||
| 427 | /* Operations for the original ARM version */ | ||
| 428 | static struct rtc_class_ops arm_pl031_ops = { | ||
| 429 | .read_time = pl031_read_time, | ||
| 430 | .set_time = pl031_set_time, | ||
| 431 | .read_alarm = pl031_read_alarm, | ||
| 432 | .set_alarm = pl031_set_alarm, | ||
| 433 | .alarm_irq_enable = pl031_alarm_irq_enable, | ||
| 434 | }; | ||
| 435 | |||
| 436 | /* The First ST derivative */ | ||
| 437 | static struct rtc_class_ops stv1_pl031_ops = { | ||
| 438 | .read_time = pl031_read_time, | ||
| 439 | .set_time = pl031_set_time, | ||
| 440 | .read_alarm = pl031_read_alarm, | ||
| 441 | .set_alarm = pl031_set_alarm, | ||
| 442 | .alarm_irq_enable = pl031_alarm_irq_enable, | ||
| 443 | .irq_set_state = pl031_irq_set_state, | ||
| 444 | .irq_set_freq = pl031_irq_set_freq, | ||
| 445 | }; | ||
| 446 | |||
| 447 | /* And the second ST derivative */ | ||
| 448 | static struct rtc_class_ops stv2_pl031_ops = { | ||
| 449 | .read_time = pl031_stv2_read_time, | ||
| 450 | .set_time = pl031_stv2_set_time, | ||
| 451 | .read_alarm = pl031_stv2_read_alarm, | ||
| 452 | .set_alarm = pl031_stv2_set_alarm, | ||
| 453 | .alarm_irq_enable = pl031_alarm_irq_enable, | ||
| 454 | .irq_set_state = pl031_irq_set_state, | ||
| 455 | .irq_set_freq = pl031_irq_set_freq, | ||
| 456 | }; | ||
| 457 | |||
| 181 | static struct amba_id pl031_ids[] __initdata = { | 458 | static struct amba_id pl031_ids[] __initdata = { |
| 182 | { | 459 | { |
| 183 | .id = 0x00041031, | 460 | .id = 0x00041031, |
| 184 | .mask = 0x000fffff, | 461 | .mask = 0x000fffff, |
| 462 | .data = &arm_pl031_ops, | ||
| 463 | }, | ||
| 464 | /* ST Micro variants */ | ||
| 465 | { | ||
| 466 | .id = 0x00180031, | ||
| 467 | .mask = 0x00ffffff, | ||
| 468 | .data = &stv1_pl031_ops, | ||
| 469 | }, | ||
| 470 | { | ||
| 471 | .id = 0x00280031, | ||
| 472 | .mask = 0x00ffffff, | ||
| 473 | .data = &stv2_pl031_ops, | ||
| 185 | }, | 474 | }, |
| 186 | {0, 0}, | 475 | {0, 0}, |
| 187 | }; | 476 | }; |
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c index ef7adc8135dd..ce6c35333ff7 100644 --- a/drivers/serial/amba-pl011.c +++ b/drivers/serial/amba-pl011.c | |||
| @@ -71,6 +71,7 @@ struct uart_amba_port { | |||
| 71 | unsigned int im; /* interrupt mask */ | 71 | unsigned int im; /* interrupt mask */ |
| 72 | unsigned int old_status; | 72 | unsigned int old_status; |
| 73 | unsigned int ifls; /* vendor-specific */ | 73 | unsigned int ifls; /* vendor-specific */ |
| 74 | bool autorts; | ||
| 74 | }; | 75 | }; |
| 75 | 76 | ||
| 76 | /* There is by now at least one vendor with differing details, so handle it */ | 77 | /* There is by now at least one vendor with differing details, so handle it */ |
| @@ -308,6 +309,11 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
| 308 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | 309 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); |
| 309 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | 310 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); |
| 310 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | 311 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); |
| 312 | |||
| 313 | if (uap->autorts) { | ||
| 314 | /* We need to disable auto-RTS if we want to turn RTS off */ | ||
| 315 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | ||
| 316 | } | ||
| 311 | #undef TIOCMBIT | 317 | #undef TIOCMBIT |
| 312 | 318 | ||
| 313 | writew(cr, uap->port.membase + UART011_CR); | 319 | writew(cr, uap->port.membase + UART011_CR); |
| @@ -437,6 +443,7 @@ static void pl011_shutdown(struct uart_port *port) | |||
| 437 | /* | 443 | /* |
| 438 | * disable the port | 444 | * disable the port |
| 439 | */ | 445 | */ |
| 446 | uap->autorts = false; | ||
| 440 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); | 447 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); |
| 441 | 448 | ||
| 442 | /* | 449 | /* |
| @@ -456,6 +463,7 @@ static void | |||
| 456 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, | 463 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
| 457 | struct ktermios *old) | 464 | struct ktermios *old) |
| 458 | { | 465 | { |
| 466 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | ||
| 459 | unsigned int lcr_h, old_cr; | 467 | unsigned int lcr_h, old_cr; |
| 460 | unsigned long flags; | 468 | unsigned long flags; |
| 461 | unsigned int baud, quot; | 469 | unsigned int baud, quot; |
| @@ -532,6 +540,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, | |||
| 532 | old_cr = readw(port->membase + UART011_CR); | 540 | old_cr = readw(port->membase + UART011_CR); |
| 533 | writew(0, port->membase + UART011_CR); | 541 | writew(0, port->membase + UART011_CR); |
| 534 | 542 | ||
| 543 | if (termios->c_cflag & CRTSCTS) { | ||
| 544 | if (old_cr & UART011_CR_RTS) | ||
| 545 | old_cr |= UART011_CR_RTSEN; | ||
| 546 | |||
| 547 | old_cr |= UART011_CR_CTSEN; | ||
| 548 | uap->autorts = true; | ||
| 549 | } else { | ||
| 550 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | ||
| 551 | uap->autorts = false; | ||
| 552 | } | ||
| 553 | |||
| 535 | /* Set baud rate */ | 554 | /* Set baud rate */ |
| 536 | writew(quot & 0x3f, port->membase + UART011_FBRD); | 555 | writew(quot & 0x3f, port->membase + UART011_FBRD); |
| 537 | writew(quot >> 6, port->membase + UART011_IBRD); | 556 | writew(quot >> 6, port->membase + UART011_IBRD); |
diff --git a/drivers/spi/amba-pl022.c b/drivers/spi/amba-pl022.c index ff5bbb9c43c9..9aeb68113100 100644 --- a/drivers/spi/amba-pl022.c +++ b/drivers/spi/amba-pl022.c | |||
| @@ -363,6 +363,7 @@ struct pl022 { | |||
| 363 | void *rx_end; | 363 | void *rx_end; |
| 364 | enum ssp_reading read; | 364 | enum ssp_reading read; |
| 365 | enum ssp_writing write; | 365 | enum ssp_writing write; |
| 366 | u32 exp_fifo_level; | ||
| 366 | }; | 367 | }; |
| 367 | 368 | ||
| 368 | /** | 369 | /** |
| @@ -501,6 +502,9 @@ static int flush(struct pl022 *pl022) | |||
| 501 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) | 502 | while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) |
| 502 | readw(SSP_DR(pl022->virtbase)); | 503 | readw(SSP_DR(pl022->virtbase)); |
| 503 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); | 504 | } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); |
| 505 | |||
| 506 | pl022->exp_fifo_level = 0; | ||
| 507 | |||
| 504 | return limit; | 508 | return limit; |
| 505 | } | 509 | } |
| 506 | 510 | ||
| @@ -583,10 +587,9 @@ static void readwriter(struct pl022 *pl022) | |||
| 583 | * errons in 8bit wide transfers on ARM variants (just 8 words | 587 | * errons in 8bit wide transfers on ARM variants (just 8 words |
| 584 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. | 588 | * FIFO, means only 8x8 = 64 bits in FIFO) at least. |
| 585 | * | 589 | * |
| 586 | * FIXME: currently we have no logic to account for this. | 590 | * To prevent this issue, the TX FIFO is only filled to the |
| 587 | * perhaps there is even something broken in HW regarding | 591 | * unused RX FIFO fill length, regardless of what the TX |
| 588 | * 8bit transfers (it doesn't fail on 16bit) so this needs | 592 | * FIFO status flag indicates. |
| 589 | * more investigation... | ||
| 590 | */ | 593 | */ |
| 591 | dev_dbg(&pl022->adev->dev, | 594 | dev_dbg(&pl022->adev->dev, |
| 592 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", | 595 | "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n", |
| @@ -613,11 +616,12 @@ static void readwriter(struct pl022 *pl022) | |||
| 613 | break; | 616 | break; |
| 614 | } | 617 | } |
| 615 | pl022->rx += (pl022->cur_chip->n_bytes); | 618 | pl022->rx += (pl022->cur_chip->n_bytes); |
| 619 | pl022->exp_fifo_level--; | ||
| 616 | } | 620 | } |
| 617 | /* | 621 | /* |
| 618 | * Write as much as you can, while keeping an eye on the RX FIFO! | 622 | * Write as much as possible up to the RX FIFO size |
| 619 | */ | 623 | */ |
| 620 | while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF) | 624 | while ((pl022->exp_fifo_level < pl022->vendor->fifodepth) |
| 621 | && (pl022->tx < pl022->tx_end)) { | 625 | && (pl022->tx < pl022->tx_end)) { |
| 622 | switch (pl022->write) { | 626 | switch (pl022->write) { |
| 623 | case WRITING_NULL: | 627 | case WRITING_NULL: |
| @@ -634,6 +638,7 @@ static void readwriter(struct pl022 *pl022) | |||
| 634 | break; | 638 | break; |
| 635 | } | 639 | } |
| 636 | pl022->tx += (pl022->cur_chip->n_bytes); | 640 | pl022->tx += (pl022->cur_chip->n_bytes); |
| 641 | pl022->exp_fifo_level++; | ||
| 637 | /* | 642 | /* |
| 638 | * This inner reader takes care of things appearing in the RX | 643 | * This inner reader takes care of things appearing in the RX |
| 639 | * FIFO as we're transmitting. This will happen a lot since the | 644 | * FIFO as we're transmitting. This will happen a lot since the |
| @@ -660,6 +665,7 @@ static void readwriter(struct pl022 *pl022) | |||
| 660 | break; | 665 | break; |
| 661 | } | 666 | } |
| 662 | pl022->rx += (pl022->cur_chip->n_bytes); | 667 | pl022->rx += (pl022->cur_chip->n_bytes); |
| 668 | pl022->exp_fifo_level--; | ||
| 663 | } | 669 | } |
| 664 | } | 670 | } |
| 665 | /* | 671 | /* |
diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c index 430a5848a9a5..c7a9479934af 100644 --- a/drivers/watchdog/pnx4008_wdt.c +++ b/drivers/watchdog/pnx4008_wdt.c | |||
| @@ -96,9 +96,6 @@ static void wdt_enable(void) | |||
| 96 | { | 96 | { |
| 97 | spin_lock(&io_lock); | 97 | spin_lock(&io_lock); |
| 98 | 98 | ||
| 99 | if (wdt_clk) | ||
| 100 | clk_set_rate(wdt_clk, 1); | ||
| 101 | |||
| 102 | /* stop counter, initiate counter reset */ | 99 | /* stop counter, initiate counter reset */ |
| 103 | __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); | 100 | __raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); |
| 104 | /*wait for reset to complete. 100% guarantee event */ | 101 | /*wait for reset to complete. 100% guarantee event */ |
| @@ -125,19 +122,25 @@ static void wdt_disable(void) | |||
| 125 | spin_lock(&io_lock); | 122 | spin_lock(&io_lock); |
| 126 | 123 | ||
| 127 | __raw_writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ | 124 | __raw_writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ |
| 128 | if (wdt_clk) | ||
| 129 | clk_set_rate(wdt_clk, 0); | ||
| 130 | 125 | ||
| 131 | spin_unlock(&io_lock); | 126 | spin_unlock(&io_lock); |
| 132 | } | 127 | } |
| 133 | 128 | ||
| 134 | static int pnx4008_wdt_open(struct inode *inode, struct file *file) | 129 | static int pnx4008_wdt_open(struct inode *inode, struct file *file) |
| 135 | { | 130 | { |
| 131 | int ret; | ||
| 132 | |||
| 136 | if (test_and_set_bit(WDT_IN_USE, &wdt_status)) | 133 | if (test_and_set_bit(WDT_IN_USE, &wdt_status)) |
| 137 | return -EBUSY; | 134 | return -EBUSY; |
| 138 | 135 | ||
| 139 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | 136 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); |
| 140 | 137 | ||
| 138 | ret = clk_enable(wdt_clk); | ||
| 139 | if (ret) { | ||
| 140 | clear_bit(WDT_IN_USE, &wdt_status); | ||
| 141 | return ret; | ||
| 142 | } | ||
| 143 | |||
| 141 | wdt_enable(); | 144 | wdt_enable(); |
| 142 | 145 | ||
| 143 | return nonseekable_open(inode, file); | 146 | return nonseekable_open(inode, file); |
| @@ -225,6 +228,7 @@ static int pnx4008_wdt_release(struct inode *inode, struct file *file) | |||
| 225 | printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n"); | 228 | printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n"); |
| 226 | 229 | ||
| 227 | wdt_disable(); | 230 | wdt_disable(); |
| 231 | clk_disable(wdt_clk); | ||
| 228 | clear_bit(WDT_IN_USE, &wdt_status); | 232 | clear_bit(WDT_IN_USE, &wdt_status); |
| 229 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); | 233 | clear_bit(WDT_OK_TO_CLOSE, &wdt_status); |
| 230 | 234 | ||
| @@ -273,25 +277,33 @@ static int __devinit pnx4008_wdt_probe(struct platform_device *pdev) | |||
| 273 | } | 277 | } |
| 274 | wdt_base = (void __iomem *)IO_ADDRESS(res->start); | 278 | wdt_base = (void __iomem *)IO_ADDRESS(res->start); |
| 275 | 279 | ||
| 276 | wdt_clk = clk_get(&pdev->dev, "wdt_ck"); | 280 | wdt_clk = clk_get(&pdev->dev, NULL); |
| 277 | if (IS_ERR(wdt_clk)) { | 281 | if (IS_ERR(wdt_clk)) { |
| 278 | ret = PTR_ERR(wdt_clk); | 282 | ret = PTR_ERR(wdt_clk); |
| 279 | release_resource(wdt_mem); | 283 | release_resource(wdt_mem); |
| 280 | kfree(wdt_mem); | 284 | kfree(wdt_mem); |
| 281 | goto out; | 285 | goto out; |
| 282 | } else | 286 | } |
| 283 | clk_set_rate(wdt_clk, 1); | 287 | |
| 288 | ret = clk_enable(wdt_clk); | ||
| 289 | if (ret) { | ||
| 290 | release_resource(wdt_mem); | ||
| 291 | kfree(wdt_mem); | ||
| 292 | goto out; | ||
| 293 | } | ||
| 284 | 294 | ||
| 285 | ret = misc_register(&pnx4008_wdt_miscdev); | 295 | ret = misc_register(&pnx4008_wdt_miscdev); |
| 286 | if (ret < 0) { | 296 | if (ret < 0) { |
| 287 | printk(KERN_ERR MODULE_NAME "cannot register misc device\n"); | 297 | printk(KERN_ERR MODULE_NAME "cannot register misc device\n"); |
| 288 | release_resource(wdt_mem); | 298 | release_resource(wdt_mem); |
| 289 | kfree(wdt_mem); | 299 | kfree(wdt_mem); |
| 290 | clk_set_rate(wdt_clk, 0); | 300 | clk_disable(wdt_clk); |
| 301 | clk_put(wdt_clk); | ||
| 291 | } else { | 302 | } else { |
| 292 | boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? | 303 | boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ? |
| 293 | WDIOF_CARDRESET : 0; | 304 | WDIOF_CARDRESET : 0; |
| 294 | wdt_disable(); /*disable for now */ | 305 | wdt_disable(); /*disable for now */ |
| 306 | clk_disable(wdt_clk); | ||
| 295 | set_bit(WDT_DEVICE_INITED, &wdt_status); | 307 | set_bit(WDT_DEVICE_INITED, &wdt_status); |
| 296 | } | 308 | } |
| 297 | 309 | ||
| @@ -302,11 +314,10 @@ out: | |||
| 302 | static int __devexit pnx4008_wdt_remove(struct platform_device *pdev) | 314 | static int __devexit pnx4008_wdt_remove(struct platform_device *pdev) |
| 303 | { | 315 | { |
| 304 | misc_deregister(&pnx4008_wdt_miscdev); | 316 | misc_deregister(&pnx4008_wdt_miscdev); |
| 305 | if (wdt_clk) { | 317 | |
| 306 | clk_set_rate(wdt_clk, 0); | 318 | clk_disable(wdt_clk); |
| 307 | clk_put(wdt_clk); | 319 | clk_put(wdt_clk); |
| 308 | wdt_clk = NULL; | 320 | |
| 309 | } | ||
| 310 | if (wdt_mem) { | 321 | if (wdt_mem) { |
| 311 | release_resource(wdt_mem); | 322 | release_resource(wdt_mem); |
| 312 | kfree(wdt_mem); | 323 | kfree(wdt_mem); |
