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authorRafał Miłecki <zajec5@gmail.com>2010-02-18 15:24:28 -0500
committerDave Airlie <airlied@redhat.com>2010-02-22 18:48:56 -0500
commitaa5120d2ef228042416d3023fb7eda9ee487dcf9 (patch)
tree802a097e3d3b18f91113f47f02bbd091b9409698 /drivers
parent08ff2a7a7a13c562e81a406722193f43cbb4e4ef (diff)
drm/radeon/kms: implement reading active PCIE lanes on R600+
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/r300.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h4
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c2
4 files changed, 10 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index b188aae764cc..dc32cd13a837 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -554,7 +554,10 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev)
554 554
555 /* FIXME wait for idle */ 555 /* FIXME wait for idle */
556 556
557 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 557 if (rdev->family < CHIP_R600)
558 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
559 else
560 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
558 561
559 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 562 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
560 case RADEON_PCIE_LC_LINK_WIDTH_X0: 563 case RADEON_PCIE_LC_LINK_WIDTH_X0:
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index fc9044edc0aa..2434d553bbbc 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1014,6 +1014,8 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
1014#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1014#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1015#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1015#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1016#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1016#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1017#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1018#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1017#define WREG32_P(reg, val, mask) \ 1019#define WREG32_P(reg, val, mask) \
1018 do { \ 1020 do { \
1019 uint32_t tmp_ = RREG32(reg); \ 1021 uint32_t tmp_ = RREG32(reg); \
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index b7030d7c0396..4572a6699884 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -626,7 +626,7 @@ static struct radeon_asic r600_asic = {
626 .set_engine_clock = &radeon_atom_set_engine_clock, 626 .set_engine_clock = &radeon_atom_set_engine_clock,
627 .get_memory_clock = &radeon_atom_get_memory_clock, 627 .get_memory_clock = &radeon_atom_get_memory_clock,
628 .set_memory_clock = &radeon_atom_set_memory_clock, 628 .set_memory_clock = &radeon_atom_set_memory_clock,
629 .get_pcie_lanes = NULL, 629 .get_pcie_lanes = &rv370_get_pcie_lanes,
630 .set_pcie_lanes = NULL, 630 .set_pcie_lanes = NULL,
631 .set_clock_gating = NULL, 631 .set_clock_gating = NULL,
632 .set_surface_reg = r600_set_surface_reg, 632 .set_surface_reg = r600_set_surface_reg,
@@ -672,7 +672,7 @@ static struct radeon_asic rv770_asic = {
672 .set_engine_clock = &radeon_atom_set_engine_clock, 672 .set_engine_clock = &radeon_atom_set_engine_clock,
673 .get_memory_clock = &radeon_atom_get_memory_clock, 673 .get_memory_clock = &radeon_atom_get_memory_clock,
674 .set_memory_clock = &radeon_atom_set_memory_clock, 674 .set_memory_clock = &radeon_atom_set_memory_clock,
675 .get_pcie_lanes = NULL, 675 .get_pcie_lanes = &rv370_get_pcie_lanes,
676 .set_pcie_lanes = NULL, 676 .set_pcie_lanes = NULL,
677 .set_clock_gating = &radeon_atom_set_clock_gating, 677 .set_clock_gating = &radeon_atom_set_clock_gating,
678 .set_surface_reg = r600_set_surface_reg, 678 .set_surface_reg = r600_set_surface_reg,
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index d174d93c9386..d4d1c39a0e99 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -442,6 +442,8 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
442 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk); 442 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
443 if (rdev->asic->get_memory_clock) 443 if (rdev->asic->get_memory_clock)
444 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 444 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
445 if (rdev->asic->get_pcie_lanes)
446 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
445 447
446 return 0; 448 return 0;
447} 449}