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authorDaniel Vetter <daniel.vetter@ffwll.ch>2014-09-30 04:56:47 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-10-24 10:33:54 -0400
commita72e4c9f9a11d44458a12928cc776921ae43a616 (patch)
tree4eeff2e4e1db683934d6626dfa745ec5f24ddd81 /drivers
parent47339cd9ff07376df1639260ecc088adf1856bfe (diff)
drm/i915: Use dev_priv in public intel_fifo_underrun.c functions
It's the new rule! Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c35
-rw-r--r--drivers/gpu/drm/i915/intel_display.c35
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h8
-rw-r--r--drivers/gpu/drm/i915/intel_fifo_underrun.c25
4 files changed, 58 insertions, 45 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 536efa277b01..3ee8c4756adb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1750,7 +1750,7 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1750 * handle. 1750 * handle.
1751 */ 1751 */
1752 mask = 0; 1752 mask = 0;
1753 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe)) 1753 if (__cpu_fifo_underrun_reporting_enabled(dev_priv, pipe))
1754 mask |= PIPE_FIFO_UNDERRUN_STATUS; 1754 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1755 1755
1756 switch (pipe) { 1756 switch (pipe) {
@@ -1797,7 +1797,8 @@ static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1797 i9xx_pipe_crc_irq_handler(dev, pipe); 1797 i9xx_pipe_crc_irq_handler(dev, pipe);
1798 1798
1799 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 1799 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1800 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 1800 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
1801 false))
1801 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 1802 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1802 } 1803 }
1803 1804
@@ -1965,12 +1966,14 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1965 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 1966 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1966 1967
1967 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 1968 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1968 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 1969 if (intel_set_pch_fifo_underrun_reporting(dev_priv,
1970 TRANSCODER_A,
1969 false)) 1971 false))
1970 DRM_ERROR("PCH transcoder A FIFO underrun\n"); 1972 DRM_ERROR("PCH transcoder A FIFO underrun\n");
1971 1973
1972 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 1974 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1973 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 1975 if (intel_set_pch_fifo_underrun_reporting(dev_priv,
1976 TRANSCODER_B,
1974 false)) 1977 false))
1975 DRM_ERROR("PCH transcoder B FIFO underrun\n"); 1978 DRM_ERROR("PCH transcoder B FIFO underrun\n");
1976} 1979}
@@ -1986,7 +1989,7 @@ static void ivb_err_int_handler(struct drm_device *dev)
1986 1989
1987 for_each_pipe(dev_priv, pipe) { 1990 for_each_pipe(dev_priv, pipe) {
1988 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { 1991 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1989 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 1992 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
1990 false)) 1993 false))
1991 DRM_ERROR("Pipe %c FIFO underrun\n", 1994 DRM_ERROR("Pipe %c FIFO underrun\n",
1992 pipe_name(pipe)); 1995 pipe_name(pipe));
@@ -2012,17 +2015,17 @@ static void cpt_serr_int_handler(struct drm_device *dev)
2012 DRM_ERROR("PCH poison interrupt\n"); 2015 DRM_ERROR("PCH poison interrupt\n");
2013 2016
2014 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) 2017 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2015 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 2018 if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
2016 false)) 2019 false))
2017 DRM_ERROR("PCH transcoder A FIFO underrun\n"); 2020 DRM_ERROR("PCH transcoder A FIFO underrun\n");
2018 2021
2019 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) 2022 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2020 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 2023 if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_B,
2021 false)) 2024 false))
2022 DRM_ERROR("PCH transcoder B FIFO underrun\n"); 2025 DRM_ERROR("PCH transcoder B FIFO underrun\n");
2023 2026
2024 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) 2027 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2025 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, 2028 if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_C,
2026 false)) 2029 false))
2027 DRM_ERROR("PCH transcoder C FIFO underrun\n"); 2030 DRM_ERROR("PCH transcoder C FIFO underrun\n");
2028 2031
@@ -2090,7 +2093,9 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2090 intel_check_page_flip(dev, pipe); 2093 intel_check_page_flip(dev, pipe);
2091 2094
2092 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 2095 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2093 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 2096 if (intel_set_cpu_fifo_underrun_reporting(dev_priv,
2097 pipe,
2098 false))
2094 DRM_ERROR("Pipe %c FIFO underrun\n", 2099 DRM_ERROR("Pipe %c FIFO underrun\n",
2095 pipe_name(pipe)); 2100 pipe_name(pipe));
2096 2101
@@ -2312,7 +2317,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2312 hsw_pipe_crc_irq_handler(dev, pipe); 2317 hsw_pipe_crc_irq_handler(dev, pipe);
2313 2318
2314 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { 2319 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2315 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 2320 if (intel_set_cpu_fifo_underrun_reporting(dev_priv,
2321 pipe,
2316 false)) 2322 false))
2317 DRM_ERROR("Pipe %c FIFO underrun\n", 2323 DRM_ERROR("Pipe %c FIFO underrun\n",
2318 pipe_name(pipe)); 2324 pipe_name(pipe));
@@ -3834,7 +3840,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3834 i9xx_pipe_crc_irq_handler(dev, pipe); 3840 i9xx_pipe_crc_irq_handler(dev, pipe);
3835 3841
3836 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 3842 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3837 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 3843 intel_set_cpu_fifo_underrun_reporting(dev_priv,
3844 pipe, false))
3838 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 3845 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3839 } 3846 }
3840 3847
@@ -4028,7 +4035,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
4028 i9xx_pipe_crc_irq_handler(dev, pipe); 4035 i9xx_pipe_crc_irq_handler(dev, pipe);
4029 4036
4030 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 4037 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4031 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 4038 intel_set_cpu_fifo_underrun_reporting(dev_priv,
4039 pipe, false))
4032 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 4040 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4033 } 4041 }
4034 4042
@@ -4256,7 +4264,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4256 i9xx_pipe_crc_irq_handler(dev, pipe); 4264 i9xx_pipe_crc_irq_handler(dev, pipe);
4257 4265
4258 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS && 4266 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4259 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 4267 intel_set_cpu_fifo_underrun_reporting(dev_priv,
4268 pipe, false))
4260 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); 4269 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4261 } 4270 }
4262 4271
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1fc05ffc4695..ee8156cf6f61 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4163,8 +4163,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
4163 4163
4164 intel_crtc->active = true; 4164 intel_crtc->active = true;
4165 4165
4166 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4167 intel_set_pch_fifo_underrun_reporting(dev, pipe, true); 4167 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4168 4168
4169 for_each_encoder_on_crtc(dev, crtc, encoder) 4169 for_each_encoder_on_crtc(dev, crtc, encoder)
4170 if (encoder->pre_enable) 4170 if (encoder->pre_enable)
@@ -4278,13 +4278,14 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4278 4278
4279 intel_crtc->active = true; 4279 intel_crtc->active = true;
4280 4280
4281 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4281 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4282 for_each_encoder_on_crtc(dev, crtc, encoder) 4282 for_each_encoder_on_crtc(dev, crtc, encoder)
4283 if (encoder->pre_enable) 4283 if (encoder->pre_enable)
4284 encoder->pre_enable(encoder); 4284 encoder->pre_enable(encoder);
4285 4285
4286 if (intel_crtc->config.has_pch_encoder) { 4286 if (intel_crtc->config.has_pch_encoder) {
4287 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); 4287 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4288 true);
4288 dev_priv->display.fdi_link_train(crtc); 4289 dev_priv->display.fdi_link_train(crtc);
4289 } 4290 }
4290 4291
@@ -4360,7 +4361,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
4360 encoder->disable(encoder); 4361 encoder->disable(encoder);
4361 4362
4362 if (intel_crtc->config.has_pch_encoder) 4363 if (intel_crtc->config.has_pch_encoder)
4363 intel_set_pch_fifo_underrun_reporting(dev, pipe, false); 4364 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4364 4365
4365 intel_disable_pipe(intel_crtc); 4366 intel_disable_pipe(intel_crtc);
4366 4367
@@ -4374,7 +4375,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
4374 ironlake_fdi_disable(crtc); 4375 ironlake_fdi_disable(crtc);
4375 4376
4376 ironlake_disable_pch_transcoder(dev_priv, pipe); 4377 ironlake_disable_pch_transcoder(dev_priv, pipe);
4377 intel_set_pch_fifo_underrun_reporting(dev, pipe, true); 4378 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4378 4379
4379 if (HAS_PCH_CPT(dev)) { 4380 if (HAS_PCH_CPT(dev)) {
4380 /* disable TRANS_DP_CTL */ 4381 /* disable TRANS_DP_CTL */
@@ -4427,7 +4428,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4427 } 4428 }
4428 4429
4429 if (intel_crtc->config.has_pch_encoder) 4430 if (intel_crtc->config.has_pch_encoder)
4430 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); 4431 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4432 false);
4431 intel_disable_pipe(intel_crtc); 4433 intel_disable_pipe(intel_crtc);
4432 4434
4433 if (intel_crtc->config.dp_encoder_is_mst) 4435 if (intel_crtc->config.dp_encoder_is_mst)
@@ -4441,7 +4443,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4441 4443
4442 if (intel_crtc->config.has_pch_encoder) { 4444 if (intel_crtc->config.has_pch_encoder) {
4443 lpt_disable_pch_transcoder(dev_priv); 4445 lpt_disable_pch_transcoder(dev_priv);
4444 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); 4446 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4447 true);
4445 intel_ddi_fdi_disable(crtc); 4448 intel_ddi_fdi_disable(crtc);
4446 } 4449 }
4447 4450
@@ -4818,6 +4821,7 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
4818static void valleyview_crtc_enable(struct drm_crtc *crtc) 4821static void valleyview_crtc_enable(struct drm_crtc *crtc)
4819{ 4822{
4820 struct drm_device *dev = crtc->dev; 4823 struct drm_device *dev = crtc->dev;
4824 struct drm_i915_private *dev_priv = to_i915(dev);
4821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4822 struct intel_encoder *encoder; 4826 struct intel_encoder *encoder;
4823 int pipe = intel_crtc->pipe; 4827 int pipe = intel_crtc->pipe;
@@ -4846,7 +4850,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
4846 4850
4847 intel_crtc->active = true; 4851 intel_crtc->active = true;
4848 4852
4849 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4853 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4850 4854
4851 for_each_encoder_on_crtc(dev, crtc, encoder) 4855 for_each_encoder_on_crtc(dev, crtc, encoder)
4852 if (encoder->pre_pll_enable) 4856 if (encoder->pre_pll_enable)
@@ -4879,7 +4883,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
4879 intel_crtc_enable_planes(crtc); 4883 intel_crtc_enable_planes(crtc);
4880 4884
4881 /* Underruns don't raise interrupts, so check manually. */ 4885 /* Underruns don't raise interrupts, so check manually. */
4882 i9xx_check_fifo_underruns(dev); 4886 i9xx_check_fifo_underruns(dev_priv);
4883} 4887}
4884 4888
4885static void i9xx_set_pll_dividers(struct intel_crtc *crtc) 4889static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
@@ -4894,6 +4898,7 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4894static void i9xx_crtc_enable(struct drm_crtc *crtc) 4898static void i9xx_crtc_enable(struct drm_crtc *crtc)
4895{ 4899{
4896 struct drm_device *dev = crtc->dev; 4900 struct drm_device *dev = crtc->dev;
4901 struct drm_i915_private *dev_priv = to_i915(dev);
4897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4898 struct intel_encoder *encoder; 4903 struct intel_encoder *encoder;
4899 int pipe = intel_crtc->pipe; 4904 int pipe = intel_crtc->pipe;
@@ -4915,7 +4920,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
4915 intel_crtc->active = true; 4920 intel_crtc->active = true;
4916 4921
4917 if (!IS_GEN2(dev)) 4922 if (!IS_GEN2(dev))
4918 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4923 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4919 4924
4920 for_each_encoder_on_crtc(dev, crtc, encoder) 4925 for_each_encoder_on_crtc(dev, crtc, encoder)
4921 if (encoder->pre_enable) 4926 if (encoder->pre_enable)
@@ -4946,10 +4951,10 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
4946 * but leave the pipe running. 4951 * but leave the pipe running.
4947 */ 4952 */
4948 if (IS_GEN2(dev)) 4953 if (IS_GEN2(dev))
4949 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4954 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4950 4955
4951 /* Underruns don't raise interrupts, so check manually. */ 4956 /* Underruns don't raise interrupts, so check manually. */
4952 i9xx_check_fifo_underruns(dev); 4957 i9xx_check_fifo_underruns(dev_priv);
4953} 4958}
4954 4959
4955static void i9xx_pfit_disable(struct intel_crtc *crtc) 4960static void i9xx_pfit_disable(struct intel_crtc *crtc)
@@ -4985,7 +4990,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
4985 * but leave the pipe running. 4990 * but leave the pipe running.
4986 */ 4991 */
4987 if (IS_GEN2(dev)) 4992 if (IS_GEN2(dev))
4988 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); 4993 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4989 4994
4990 /* 4995 /*
4991 * Vblank time updates from the shadow to live plane control register 4996 * Vblank time updates from the shadow to live plane control register
@@ -5031,7 +5036,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
5031 } 5036 }
5032 5037
5033 if (!IS_GEN2(dev)) 5038 if (!IS_GEN2(dev))
5034 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); 5039 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5035 5040
5036 intel_crtc->active = false; 5041 intel_crtc->active = false;
5037 intel_update_watermarks(crtc); 5042 intel_update_watermarks(crtc);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 321701da12ec..ede96065235d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -756,13 +756,13 @@ static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
756} 756}
757 757
758/* intel_fifo_underrun.c */ 758/* intel_fifo_underrun.c */
759bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 759bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
760 enum pipe pipe, bool enable); 760 enum pipe pipe, bool enable);
761bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, 761bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
762 enum transcoder pch_transcoder, 762 enum transcoder pch_transcoder,
763 bool enable); 763 bool enable);
764void i9xx_check_fifo_underruns(struct drm_device *dev); 764void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
765bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, 765bool __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private *dev_priv,
766 enum pipe pipe); 766 enum pipe pipe);
767 767
768/* i915_irq.c */ 768/* i915_irq.c */
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 8e79d2ba787d..0604a112a4ad 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -64,14 +64,13 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
64 return true; 64 return true;
65} 65}
66 66
67void i9xx_check_fifo_underruns(struct drm_device *dev) 67void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv)
68{ 68{
69 struct drm_i915_private *dev_priv = dev->dev_private;
70 struct intel_crtc *crtc; 69 struct intel_crtc *crtc;
71 70
72 spin_lock_irq(&dev_priv->irq_lock); 71 spin_lock_irq(&dev_priv->irq_lock);
73 72
74 for_each_intel_crtc(dev, crtc) { 73 for_each_intel_crtc(dev_priv->dev, crtc) {
75 u32 reg = PIPESTAT(crtc->pipe); 74 u32 reg = PIPESTAT(crtc->pipe);
76 u32 pipestat; 75 u32 pipestat;
77 76
@@ -239,24 +238,23 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
239 return old; 238 return old;
240} 239}
241 240
242bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 241bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
243 enum pipe pipe, bool enable) 242 enum pipe pipe, bool enable)
244{ 243{
245 struct drm_i915_private *dev_priv = dev->dev_private;
246 unsigned long flags; 244 unsigned long flags;
247 bool ret; 245 bool ret;
248 246
249 spin_lock_irqsave(&dev_priv->irq_lock, flags); 247 spin_lock_irqsave(&dev_priv->irq_lock, flags);
250 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable); 248 ret = __intel_set_cpu_fifo_underrun_reporting(dev_priv->dev, pipe,
249 enable);
251 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 250 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
252 251
253 return ret; 252 return ret;
254} 253}
255 254
256bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev, 255bool __cpu_fifo_underrun_reporting_enabled(struct drm_i915_private *dev_priv,
257 enum pipe pipe) 256 enum pipe pipe)
258{ 257{
259 struct drm_i915_private *dev_priv = dev->dev_private;
260 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 258 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
262 260
@@ -277,11 +275,10 @@ bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
277 * 275 *
278 * Returns the previous state of underrun reporting. 276 * Returns the previous state of underrun reporting.
279 */ 277 */
280bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, 278bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
281 enum transcoder pch_transcoder, 279 enum transcoder pch_transcoder,
282 bool enable) 280 bool enable)
283{ 281{
284 struct drm_i915_private *dev_priv = dev->dev_private;
285 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; 282 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
287 unsigned long flags; 284 unsigned long flags;
@@ -301,10 +298,12 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
301 old = !intel_crtc->pch_fifo_underrun_disabled; 298 old = !intel_crtc->pch_fifo_underrun_disabled;
302 intel_crtc->pch_fifo_underrun_disabled = !enable; 299 intel_crtc->pch_fifo_underrun_disabled = !enable;
303 300
304 if (HAS_PCH_IBX(dev)) 301 if (HAS_PCH_IBX(dev_priv->dev))
305 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 302 ibx_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,
303 enable);
306 else 304 else
307 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old); 305 cpt_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,
306 enable, old);
308 307
309 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 308 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
310 return old; 309 return old;