drm/i915/chv: Implement WaDisableShadowRegForCpd

This WA is avoid problem between shadow vs wake FIFO unload
problem during CPD/RC6 transactions on CHV.

v2: Define individual bits GTFIFOCTL (Ville)

v3: move WA to uncore_early_sanitize (ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[Jani: fixed some whitespace issues while applying]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

2 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3da1af46625c..773d1d24e604 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6074,6 +6074,8 @@ enum skl_disp_power_wells {
 #define  GTFIFOCTL                              0x120008
 #define    GT_FIFO_FREE_ENTRIES_MASK            0x7f
 #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
+#define    GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL   (1 << 12)
+#define    GT_FIFO_CTL_RC6_POLICY_STALL         (1 << 11)
 
 #define  HSW_IDICR                              0x9008
 #define    IDIHASHMSK(x)                        (((x) & 0x3f) << 16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ab5cc94588e1..ff2a74651dd4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -360,6 +360,14 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
                 __raw_i915_write32(dev_priv, GTFIFODBG,
                                    __raw_i915_read32(dev_priv, GTFIFODBG));
 
+        /* WaDisableShadowRegForCpd:chv */
+        if (IS_CHERRYVIEW(dev)) {
+                __raw_i915_write32(dev_priv, GTFIFOCTL,
+                                   __raw_i915_read32(dev_priv, GTFIFOCTL) |
+                                   GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
+                                   GT_FIFO_CTL_RC6_POLICY_STALL);
+        }
+
         intel_uncore_forcewake_reset(dev, restore_forcewake);
 }