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authorLennert Buytenhek <buytenh@wantstofly.org>2007-10-18 22:10:28 -0400
committerDale Farnsworth <dale@farnsworth.org>2007-10-23 11:23:02 -0400
commit9f316841440c4c7e59227d0a3fe00a31ead1c436 (patch)
tree02be7ef1601c7863d6b9085363408832dfa514dc /drivers
parente2734d6c61e0fd2b0f3aeac01e8dcd36c99b1a13 (diff)
mv643xx_eth: Disable RX/TX byte swapping on little-endian systems
On little-endian systems, configure the SDMA unit with MV643XX_ETH_BLM_RX_NO_SWAP and MV643XX_ETH_BLM_TX_NO_SWAP. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Tzachi Perelstein <tzachi@marvell.com> Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/mv643xx_eth.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h
index 20acd2e52456..d82b48d685c2 100644
--- a/drivers/net/mv643xx_eth.h
+++ b/drivers/net/mv643xx_eth.h
@@ -266,10 +266,21 @@
266 266
267#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8) 267#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
268 268
269#if defined(__BIG_ENDIAN)
269#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \ 270#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
270 MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \ 271 MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
271 MV643XX_ETH_IPG_INT_RX(0) | \ 272 MV643XX_ETH_IPG_INT_RX(0) | \
272 MV643XX_ETH_TX_BURST_SIZE_4_64BIT 273 MV643XX_ETH_TX_BURST_SIZE_4_64BIT
274#elif defined(__LITTLE_ENDIAN)
275#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
276 MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
277 MV643XX_ETH_BLM_RX_NO_SWAP | \
278 MV643XX_ETH_BLM_TX_NO_SWAP | \
279 MV643XX_ETH_IPG_INT_RX(0) | \
280 MV643XX_ETH_TX_BURST_SIZE_4_64BIT
281#else
282#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
283#endif
273 284
274/* These macros describe Ethernet Port serial control reg (PSCR) bits */ 285/* These macros describe Ethernet Port serial control reg (PSCR) bits */
275#define MV643XX_ETH_SERIAL_PORT_DISABLE 0 286#define MV643XX_ETH_SERIAL_PORT_DISABLE 0