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authorHauke Mehrtens <hauke@hauke-m.de>2012-04-28 20:50:36 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-05-16 12:45:25 -0400
commit9a1fcffa6661b90236373ae808953f7ebc17f987 (patch)
tree421d98e63cda120c59ed52d82b889d422fa8ed16 /drivers
parent712e3c1f33f807db5bdf40e7d01e075e9b995a7c (diff)
brcmsmac: remove pcicore_attach()
This is already done by bcma in bcma_pcicore_serdes_workaround(). Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/aiutils.c3
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/nicpci.c151
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/nicpci.h1
3 files changed, 0 insertions, 155 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
index b64fbc0b37df..cafacb171f27 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
@@ -534,9 +534,6 @@ static struct si_info *ai_doattach(struct si_info *sii,
534 ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval), 534 ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
535 ~0, w); 535 ~0, w);
536 536
537 if (PCIE(sih))
538 pcicore_attach(sii->pch, SI_DOATTACH);
539
540 if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) { 537 if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
541 /* 538 /*
542 * enable 12 mA drive strenth for 43224 and 539 * enable 12 mA drive strenth for 43224 and
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c b/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
index c217f8d3a32b..5de506d4ac71 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
@@ -211,18 +211,11 @@ struct pcicore_info {
211 struct bcma_device *core; 211 struct bcma_device *core;
212 struct si_pub *sih; /* System interconnect handle */ 212 struct si_pub *sih; /* System interconnect handle */
213 struct pci_dev *dev; 213 struct pci_dev *dev;
214 u8 pcie_polarity;
215 214
216 u8 pmecap_offset; /* PM Capability offset in the config space */ 215 u8 pmecap_offset; /* PM Capability offset in the config space */
217 bool pmecap; /* Capable of generating PME */ 216 bool pmecap; /* Capable of generating PME */
218}; 217};
219 218
220/* delay needed between the mdio control/ mdiodata register data access */
221static void pr28829_delay(void)
222{
223 udelay(10);
224}
225
226/* Initialize the PCI core. 219/* Initialize the PCI core.
227 * It's caller's responsibility to make sure that this is done only once 220 * It's caller's responsibility to make sure that this is done only once
228 */ 221 */
@@ -351,103 +344,6 @@ static uint pcie_writereg(struct bcma_device *core, uint addrtype,
351 return 0; 344 return 0;
352} 345}
353 346
354static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
355{
356 uint mdiodata, i = 0;
357 uint pcie_serdes_spinwait = 200;
358
359 mdiodata = (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
360 (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
361 (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) |
362 (blk << 4));
363 bcma_write32(pi->core, PCIEREGOFFS(mdiodata), mdiodata);
364
365 pr28829_delay();
366 /* retry till the transaction is complete */
367 while (i < pcie_serdes_spinwait) {
368 if (bcma_read32(pi->core, PCIEREGOFFS(mdiocontrol)) &
369 MDIOCTL_ACCESS_DONE)
370 break;
371
372 udelay(1000);
373 i++;
374 }
375
376 if (i >= pcie_serdes_spinwait)
377 return false;
378
379 return true;
380}
381
382static int
383pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
384 uint *val)
385{
386 uint mdiodata;
387 uint i = 0;
388 uint pcie_serdes_spinwait = 10;
389
390 /* enable mdio access to SERDES */
391 bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol),
392 MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
393
394 /* new serdes is slower in rw,
395 * using two layers of reg address mapping
396 */
397 if (!pcie_mdiosetblock(pi, physmedia))
398 return 1;
399 mdiodata = ((MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
400 (regaddr << MDIODATA_REGADDR_SHF));
401 pcie_serdes_spinwait *= 20;
402
403 if (!write)
404 mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
405 else
406 mdiodata |= (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
407 *val);
408
409 bcma_write32(pi->core, PCIEREGOFFS(mdiodata), mdiodata);
410
411 pr28829_delay();
412
413 /* retry till the transaction is complete */
414 while (i < pcie_serdes_spinwait) {
415 if (bcma_read32(pi->core, PCIEREGOFFS(mdiocontrol)) &
416 MDIOCTL_ACCESS_DONE) {
417 if (!write) {
418 pr28829_delay();
419 *val = (bcma_read32(pi->core,
420 PCIEREGOFFS(mdiodata)) &
421 MDIODATA_MASK);
422 }
423 /* Disable mdio access to SERDES */
424 bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol), 0);
425 return 0;
426 }
427 udelay(1000);
428 i++;
429 }
430
431 /* Timed out. Disable mdio access to SERDES. */
432 bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol), 0);
433 return 1;
434}
435
436/* use the mdio interface to read from mdio slaves */
437static int
438pcie_mdioread(struct pcicore_info *pi, uint physmedia, uint regaddr,
439 uint *regval)
440{
441 return pcie_mdioop(pi, physmedia, regaddr, false, regval);
442}
443
444/* use the mdio interface to write to mdio slaves */
445static int
446pcie_mdiowrite(struct pcicore_info *pi, uint physmedia, uint regaddr, uint val)
447{
448 return pcie_mdioop(pi, physmedia, regaddr, true, &val);
449}
450
451/* ***** Support functions ***** */ 347/* ***** Support functions ***** */
452static void pcie_extendL1timer(struct pcicore_info *pi, bool extend) 348static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
453{ 349{
@@ -462,53 +358,6 @@ static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
462 w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG); 358 w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
463} 359}
464 360
465/* ***** PCI core WARs ***** */
466/* Done only once at attach time */
467static void pcie_war_polarity(struct pcicore_info *pi)
468{
469 u32 w;
470
471 if (pi->pcie_polarity != 0)
472 return;
473
474 w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_PLP_STATUSREG);
475
476 /* Detect the current polarity at attach and force that polarity and
477 * disable changing the polarity
478 */
479 if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
480 pi->pcie_polarity = SERDES_RX_CTRL_FORCE;
481 else
482 pi->pcie_polarity = (SERDES_RX_CTRL_FORCE |
483 SERDES_RX_CTRL_POLARITY);
484}
485
486/* Apply the polarity determined at the start */
487/* Needs to happen when coming out of 'standby'/'hibernate' */
488static void pcie_war_serdes(struct pcicore_info *pi)
489{
490 u32 w = 0;
491
492 if (pi->pcie_polarity != 0)
493 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
494 pi->pcie_polarity);
495
496 pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
497 if (w & PLL_CTRL_FREQDET_EN) {
498 w &= ~PLL_CTRL_FREQDET_EN;
499 pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
500 }
501}
502
503/* ***** Functions called during driver state changes ***** */
504void pcicore_attach(struct pcicore_info *pi, int state)
505{
506 /* These need to happen in this order only */
507 pcie_war_polarity(pi);
508
509 pcie_war_serdes(pi);
510}
511
512void pcicore_up(struct pcicore_info *pi, int state) 361void pcicore_up(struct pcicore_info *pi, int state)
513{ 362{
514 if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID) 363 if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h b/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h
index 7d7e5e5b4080..460a33e4893d 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h
@@ -64,7 +64,6 @@ struct sbpcieregs;
64extern struct pcicore_info *pcicore_init(struct si_pub *sih, 64extern struct pcicore_info *pcicore_init(struct si_pub *sih,
65 struct bcma_device *core); 65 struct bcma_device *core);
66extern void pcicore_deinit(struct pcicore_info *pch); 66extern void pcicore_deinit(struct pcicore_info *pch);
67extern void pcicore_attach(struct pcicore_info *pch, int state);
68extern void pcicore_up(struct pcicore_info *pch, int state); 67extern void pcicore_up(struct pcicore_info *pch, int state);
69extern void pcicore_down(struct pcicore_info *pch, int state); 68extern void pcicore_down(struct pcicore_info *pch, int state);
70extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id, 69extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,