Merge tag 'v3.19-rockhip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

- two currently unused clocks that need to stay enabled
- fix the lock bit locations of the rk3066 plls
- fix rk3288 core divider values to the ones actually
  specified by the soc vendor

2 files changed, 34 insertions, 21 deletions

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index c54078960847..7eb684c50d42 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -210,6 +210,17 @@ PNAME(mux_sclk_hsadc_p)		= { "hsadc_src", "hsadc_frac", "ext_hsadc" };
 PNAME(mux_mac_p)                = { "gpll", "dpll" };
 PNAME(mux_sclk_macref_p)        = { "mac_src", "ext_rmii" };
 
+static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
+        [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
+                     RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
+        [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
+                     RK2928_MODE_CON, 4, 4, 0, NULL),
+        [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
+                     RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
+        [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
+                     RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
+};
+
 static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
                      RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
@@ -427,11 +438,11 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
         /* hclk_peri gates */
         GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
         GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
-        GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
+        GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
         GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
-        GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS),
-        GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
+        GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
+        GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
         GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
         GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
@@ -592,7 +603,8 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
         GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
         GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
 
-        GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
+        GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
+                        RK2928_CLKGATE_CON(5), 14, GFLAGS),
 
         GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
 
@@ -680,7 +692,8 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
         GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
         GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
 
-        GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
+        GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
+                        RK2928_CLKGATE_CON(7), 3, GFLAGS),
         GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
 
         GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
@@ -735,8 +748,8 @@ static void __init rk3188_common_clk_init(struct device_node *np)
 static void __init rk3066a_clk_init(struct device_node *np)
 {
         rk3188_common_clk_init(np);
-        rockchip_clk_register_plls(rk3188_pll_clks,
-                                   ARRAY_SIZE(rk3188_pll_clks),
+        rockchip_clk_register_plls(rk3066_pll_clks,
+                                   ARRAY_SIZE(rk3066_pll_clks),
                                    RK3066_GRF_SOC_STATUS);
         rockchip_clk_register_branches(rk3066a_clk_branches,
                                   ARRAY_SIZE(rk3066a_clk_branches));
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index ac6be7c0132d..11194b8329fe 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -145,20 +145,20 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = {
         }
 
 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
-        RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4),
-        RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4),
+        RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
+        RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
 };
 
 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {