aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorMitch Williams <mitch.a.williams@intel.com>2007-03-30 14:54:08 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2007-05-02 22:02:34 -0400
commit988cbb15e00e6f924d052874b40c6a5447f9fdd7 (patch)
treea4bea1a5cdbfd8321463cc50b5539bebd4b01155 /drivers
parentdc87c3985e9b442c60994308a96f887579addc39 (diff)
PCI: Flush MSI-X table writes
This patch fixes a kernel bug which is triggered when using the irqbalance daemon with MSI-X hardware. Because both MSI-X interrupt messages and MSI-X table writes are posted, it's possible for them to cross while in-flight. This results in interrupts being received long after the kernel thinks they're disabled, and in interrupts being sent to stale vectors after rebalancing. This patch performs a read flush after writes to the MSI-X table for mask and unmask operations. Since the SMP affinity is set while the interrupt is masked, and since it's unmasked immediately after, no additional flushes are required in the various affinity setting routines. This patch has been validated with (unreleased) network hardware which uses MSI-X. Revised with input from Eric Biederman. Signed-off-by: Mitch Williams <mitch.a.williams@intel.com> Acked-by: "Eric W. Biederman" <ebiederm@xmission.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/msi.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 435c1958a7b7..a4ef93ea4c54 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -68,6 +68,29 @@ static void msix_set_enable(struct pci_dev *dev, int enable)
68 } 68 }
69} 69}
70 70
71static void msix_flush_writes(unsigned int irq)
72{
73 struct msi_desc *entry;
74
75 entry = get_irq_msi(irq);
76 BUG_ON(!entry || !entry->dev);
77 switch (entry->msi_attrib.type) {
78 case PCI_CAP_ID_MSI:
79 /* nothing to do */
80 break;
81 case PCI_CAP_ID_MSIX:
82 {
83 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
84 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
85 readl(entry->mask_base + offset);
86 break;
87 }
88 default:
89 BUG();
90 break;
91 }
92}
93
71static void msi_set_mask_bit(unsigned int irq, int flag) 94static void msi_set_mask_bit(unsigned int irq, int flag)
72{ 95{
73 struct msi_desc *entry; 96 struct msi_desc *entry;
@@ -187,11 +210,13 @@ void write_msi_msg(unsigned int irq, struct msi_msg *msg)
187void mask_msi_irq(unsigned int irq) 210void mask_msi_irq(unsigned int irq)
188{ 211{
189 msi_set_mask_bit(irq, 1); 212 msi_set_mask_bit(irq, 1);
213 msix_flush_writes(irq);
190} 214}
191 215
192void unmask_msi_irq(unsigned int irq) 216void unmask_msi_irq(unsigned int irq)
193{ 217{
194 msi_set_mask_bit(irq, 0); 218 msi_set_mask_bit(irq, 0);
219 msix_flush_writes(irq);
195} 220}
196 221
197static int msi_free_irq(struct pci_dev* dev, int irq); 222static int msi_free_irq(struct pci_dev* dev, int irq);