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authorAlex Deucher <alexander.deucher@amd.com>2012-12-03 19:32:54 -0500
committerAlex Deucher <alexander.deucher@amd.com>2012-12-12 17:16:50 -0500
commit94e014ee98e98dedb080ed1cdf510a583ed0514b (patch)
tree24125645604c9a800874a75465e6b1e3a6ac28fb /drivers
parent8770b86b3e02c3e30f2ffc42753ff9d62bc428bf (diff)
drm/radeon/cayman: add VM CS checker support for CP DMA
Need to verify for copies involving registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c47
1 files changed, 47 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 5435879ad535..62c227104781 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -2932,6 +2932,7 @@ static int evergreen_vm_packet3_check(struct radeon_device *rdev,
2932 u32 idx = pkt->idx + 1; 2932 u32 idx = pkt->idx + 1;
2933 u32 idx_value = ib[idx]; 2933 u32 idx_value = ib[idx];
2934 u32 start_reg, end_reg, reg, i; 2934 u32 start_reg, end_reg, reg, i;
2935 u32 command, info;
2935 2936
2936 switch (pkt->opcode) { 2937 switch (pkt->opcode) {
2937 case PACKET3_NOP: 2938 case PACKET3_NOP:
@@ -3006,6 +3007,52 @@ static int evergreen_vm_packet3_check(struct radeon_device *rdev,
3006 return -EINVAL; 3007 return -EINVAL;
3007 } 3008 }
3008 break; 3009 break;
3010 case PACKET3_CP_DMA:
3011 command = ib[idx + 4];
3012 info = ib[idx + 1];
3013 if (command & PACKET3_CP_DMA_CMD_SAS) {
3014 /* src address space is register */
3015 if (((info & 0x60000000) >> 29) == 0) {
3016 start_reg = idx_value << 2;
3017 if (command & PACKET3_CP_DMA_CMD_SAIC) {
3018 reg = start_reg;
3019 if (!evergreen_vm_reg_valid(reg)) {
3020 DRM_ERROR("CP DMA Bad SRC register\n");
3021 return -EINVAL;
3022 }
3023 } else {
3024 for (i = 0; i < (command & 0x1fffff); i++) {
3025 reg = start_reg + (4 * i);
3026 if (!evergreen_vm_reg_valid(reg)) {
3027 DRM_ERROR("CP DMA Bad SRC register\n");
3028 return -EINVAL;
3029 }
3030 }
3031 }
3032 }
3033 }
3034 if (command & PACKET3_CP_DMA_CMD_DAS) {
3035 /* dst address space is register */
3036 if (((info & 0x00300000) >> 20) == 0) {
3037 start_reg = ib[idx + 2];
3038 if (command & PACKET3_CP_DMA_CMD_DAIC) {
3039 reg = start_reg;
3040 if (!evergreen_vm_reg_valid(reg)) {
3041 DRM_ERROR("CP DMA Bad DST register\n");
3042 return -EINVAL;
3043 }
3044 } else {
3045 for (i = 0; i < (command & 0x1fffff); i++) {
3046 reg = start_reg + (4 * i);
3047 if (!evergreen_vm_reg_valid(reg)) {
3048 DRM_ERROR("CP DMA Bad DST register\n");
3049 return -EINVAL;
3050 }
3051 }
3052 }
3053 }
3054 }
3055 break;
3009 default: 3056 default:
3010 return -EINVAL; 3057 return -EINVAL;
3011 } 3058 }