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authorMatt Carlson <mcarlson@broadcom.com>2009-08-28 10:02:40 -0400
committerDavid S. Miller <davem@davemloft.net>2009-08-29 18:43:01 -0400
commit898a56f8d8170c188e47ae3acb90d2ea9a585ebe (patch)
tree6880f6bec0090eac6cd56458fc23e383b3f7d078 /drivers
parent17375d25d3dcd3d4caf9456fa94f60e29d6b1146 (diff)
tg3: Move general int members to a per-int struct
This patch moves the last_tag, last_tag_irq, and hw_status device members to a per-interrupt structure. It also adds a new interrupt mailbox member (int_mbox) and converts the code to use it rather than a direct preprocessor constant. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c134
-rw-r--r--drivers/net/tg3.h12
2 files changed, 80 insertions, 66 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 27ebe3b363cc..5b8d6e033183 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -615,13 +615,13 @@ static void tg3_disable_ints(struct tg3 *tp)
615{ 615{
616 tw32(TG3PCI_MISC_HOST_CTRL, 616 tw32(TG3PCI_MISC_HOST_CTRL,
617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); 617 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
618 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); 618 tw32_mailbox_f(tp->napi[0].int_mbox, 0x00000001);
619} 619}
620 620
621static inline void tg3_cond_int(struct tg3 *tp) 621static inline void tg3_cond_int(struct tg3 *tp)
622{ 622{
623 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && 623 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
624 (tp->hw_status->status & SD_STATUS_UPDATED)) 624 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
625 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); 625 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
626 else 626 else
627 tw32(HOSTCC_MODE, tp->coalesce_mode | 627 tw32(HOSTCC_MODE, tp->coalesce_mode |
@@ -630,23 +630,22 @@ static inline void tg3_cond_int(struct tg3 *tp)
630 630
631static void tg3_enable_ints(struct tg3 *tp) 631static void tg3_enable_ints(struct tg3 *tp)
632{ 632{
633 struct tg3_napi *tnapi = &tp->napi[0];
633 tp->irq_sync = 0; 634 tp->irq_sync = 0;
634 wmb(); 635 wmb();
635 636
636 tw32(TG3PCI_MISC_HOST_CTRL, 637 tw32(TG3PCI_MISC_HOST_CTRL,
637 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); 638 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
638 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 639 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
639 (tp->last_tag << 24));
640 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) 640 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
641 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 641 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
642 (tp->last_tag << 24));
643 tg3_cond_int(tp); 642 tg3_cond_int(tp);
644} 643}
645 644
646static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) 645static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
647{ 646{
648 struct tg3 *tp = tnapi->tp; 647 struct tg3 *tp = tnapi->tp;
649 struct tg3_hw_status *sblk = tp->hw_status; 648 struct tg3_hw_status *sblk = tnapi->hw_status;
650 unsigned int work_exists = 0; 649 unsigned int work_exists = 0;
651 650
652 /* check for phy events */ 651 /* check for phy events */
@@ -673,8 +672,7 @@ static void tg3_int_reenable(struct tg3_napi *tnapi)
673{ 672{
674 struct tg3 *tp = tnapi->tp; 673 struct tg3 *tp = tnapi->tp;
675 674
676 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 675 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
677 tp->last_tag << 24);
678 mmiowb(); 676 mmiowb();
679 677
680 /* When doing tagged status, this work check is unnecessary. 678 /* When doing tagged status, this work check is unnecessary.
@@ -696,13 +694,14 @@ static inline void tg3_netif_stop(struct tg3 *tp)
696 694
697static inline void tg3_netif_start(struct tg3 *tp) 695static inline void tg3_netif_start(struct tg3 *tp)
698{ 696{
697 struct tg3_napi *tnapi = &tp->napi[0];
699 netif_wake_queue(tp->dev); 698 netif_wake_queue(tp->dev);
700 /* NOTE: unconditional netif_wake_queue is only appropriate 699 /* NOTE: unconditional netif_wake_queue is only appropriate
701 * so long as all callers are assured to have free tx slots 700 * so long as all callers are assured to have free tx slots
702 * (such as after tg3_init_hw) 701 * (such as after tg3_init_hw)
703 */ 702 */
704 napi_enable(&tp->napi[0].napi); 703 napi_enable(&tnapi->napi);
705 tp->hw_status->status |= SD_STATUS_UPDATED; 704 tnapi->hw_status->status |= SD_STATUS_UPDATED;
706 tg3_enable_ints(tp); 705 tg3_enable_ints(tp);
707} 706}
708 707
@@ -3902,9 +3901,9 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3902 else 3901 else
3903 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); 3902 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3904 3903
3905 tp->hw_status->status = 3904 tp->napi[0].hw_status->status =
3906 (SD_STATUS_UPDATED | 3905 (SD_STATUS_UPDATED |
3907 (tp->hw_status->status & ~SD_STATUS_LINK_CHG)); 3906 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3908 3907
3909 for (i = 0; i < 100; i++) { 3908 for (i = 0; i < 100; i++) {
3910 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | 3909 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
@@ -4284,7 +4283,7 @@ static inline u32 tg3_tx_avail(struct tg3 *tp)
4284static void tg3_tx(struct tg3_napi *tnapi) 4283static void tg3_tx(struct tg3_napi *tnapi)
4285{ 4284{
4286 struct tg3 *tp = tnapi->tp; 4285 struct tg3 *tp = tnapi->tp;
4287 u32 hw_idx = tp->hw_status->idx[0].tx_consumer; 4286 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4288 u32 sw_idx = tp->tx_cons; 4287 u32 sw_idx = tp->tx_cons;
4289 4288
4290 while (sw_idx != hw_idx) { 4289 while (sw_idx != hw_idx) {
@@ -4486,7 +4485,7 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
4486 int received; 4485 int received;
4487 struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; 4486 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
4488 4487
4489 hw_idx = tp->hw_status->idx[0].rx_producer; 4488 hw_idx = tnapi->hw_status->idx[0].rx_producer;
4490 /* 4489 /*
4491 * We need to order the read of hw_idx and the read of 4490 * We need to order the read of hw_idx and the read of
4492 * the opaque cookie. 4491 * the opaque cookie.
@@ -4617,7 +4616,7 @@ next_pkt_nopost:
4617 4616
4618 /* Refresh hw_idx to see if there is new work */ 4617 /* Refresh hw_idx to see if there is new work */
4619 if (sw_idx == hw_idx) { 4618 if (sw_idx == hw_idx) {
4620 hw_idx = tp->hw_status->idx[0].rx_producer; 4619 hw_idx = tnapi->hw_status->idx[0].rx_producer;
4621 rmb(); 4620 rmb();
4622 } 4621 }
4623 } 4622 }
@@ -4645,7 +4644,7 @@ next_pkt_nopost:
4645static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) 4644static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4646{ 4645{
4647 struct tg3 *tp = tnapi->tp; 4646 struct tg3 *tp = tnapi->tp;
4648 struct tg3_hw_status *sblk = tp->hw_status; 4647 struct tg3_hw_status *sblk = tnapi->hw_status;
4649 4648
4650 /* handle link change and other phy events */ 4649 /* handle link change and other phy events */
4651 if (!(tp->tg3_flags & 4650 if (!(tp->tg3_flags &
@@ -4690,7 +4689,7 @@ static int tg3_poll(struct napi_struct *napi, int budget)
4690 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); 4689 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4691 struct tg3 *tp = tnapi->tp; 4690 struct tg3 *tp = tnapi->tp;
4692 int work_done = 0; 4691 int work_done = 0;
4693 struct tg3_hw_status *sblk = tp->hw_status; 4692 struct tg3_hw_status *sblk = tnapi->hw_status;
4694 4693
4695 while (1) { 4694 while (1) {
4696 work_done = tg3_poll_work(tnapi, work_done, budget); 4695 work_done = tg3_poll_work(tnapi, work_done, budget);
@@ -4706,8 +4705,8 @@ static int tg3_poll(struct napi_struct *napi, int budget)
4706 * to tell the hw how much work has been processed, 4705 * to tell the hw how much work has been processed,
4707 * so we must read it before checking for more work. 4706 * so we must read it before checking for more work.
4708 */ 4707 */
4709 tp->last_tag = sblk->status_tag; 4708 tnapi->last_tag = sblk->status_tag;
4710 tp->last_irq_tag = tp->last_tag; 4709 tnapi->last_irq_tag = tnapi->last_tag;
4711 rmb(); 4710 rmb();
4712 } else 4711 } else
4713 sblk->status &= ~SD_STATUS_UPDATED; 4712 sblk->status &= ~SD_STATUS_UPDATED;
@@ -4768,7 +4767,7 @@ static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4768 struct tg3_napi *tnapi = dev_id; 4767 struct tg3_napi *tnapi = dev_id;
4769 struct tg3 *tp = tnapi->tp; 4768 struct tg3 *tp = tnapi->tp;
4770 4769
4771 prefetch(tp->hw_status); 4770 prefetch(tnapi->hw_status);
4772 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); 4771 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4773 4772
4774 if (likely(!tg3_irq_sync(tp))) 4773 if (likely(!tg3_irq_sync(tp)))
@@ -4786,7 +4785,7 @@ static irqreturn_t tg3_msi(int irq, void *dev_id)
4786 struct tg3_napi *tnapi = dev_id; 4785 struct tg3_napi *tnapi = dev_id;
4787 struct tg3 *tp = tnapi->tp; 4786 struct tg3 *tp = tnapi->tp;
4788 4787
4789 prefetch(tp->hw_status); 4788 prefetch(tnapi->hw_status);
4790 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); 4789 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4791 /* 4790 /*
4792 * Writing any value to intr-mbox-0 clears PCI INTA# and 4791 * Writing any value to intr-mbox-0 clears PCI INTA# and
@@ -4806,7 +4805,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4806{ 4805{
4807 struct tg3_napi *tnapi = dev_id; 4806 struct tg3_napi *tnapi = dev_id;
4808 struct tg3 *tp = tnapi->tp; 4807 struct tg3 *tp = tnapi->tp;
4809 struct tg3_hw_status *sblk = tp->hw_status; 4808 struct tg3_hw_status *sblk = tnapi->hw_status;
4810 unsigned int handled = 1; 4809 unsigned int handled = 1;
4811 4810
4812 /* In INTx mode, it is possible for the interrupt to arrive at 4811 /* In INTx mode, it is possible for the interrupt to arrive at
@@ -4855,7 +4854,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4855{ 4854{
4856 struct tg3_napi *tnapi = dev_id; 4855 struct tg3_napi *tnapi = dev_id;
4857 struct tg3 *tp = tnapi->tp; 4856 struct tg3 *tp = tnapi->tp;
4858 struct tg3_hw_status *sblk = tp->hw_status; 4857 struct tg3_hw_status *sblk = tnapi->hw_status;
4859 unsigned int handled = 1; 4858 unsigned int handled = 1;
4860 4859
4861 /* In INTx mode, it is possible for the interrupt to arrive at 4860 /* In INTx mode, it is possible for the interrupt to arrive at
@@ -4863,7 +4862,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4863 * Reading the PCI State register will confirm whether the 4862 * Reading the PCI State register will confirm whether the
4864 * interrupt is ours and will flush the status block. 4863 * interrupt is ours and will flush the status block.
4865 */ 4864 */
4866 if (unlikely(sblk->status_tag == tp->last_irq_tag)) { 4865 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
4867 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || 4866 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4868 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { 4867 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4869 handled = 0; 4868 handled = 0;
@@ -4890,7 +4889,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4890 * so that the above check can report that the screaming interrupts 4889 * so that the above check can report that the screaming interrupts
4891 * are unhandled. Eventually they will be silenced. 4890 * are unhandled. Eventually they will be silenced.
4892 */ 4891 */
4893 tp->last_irq_tag = sblk->status_tag; 4892 tnapi->last_irq_tag = sblk->status_tag;
4894 4893
4895 if (tg3_irq_sync(tp)) 4894 if (tg3_irq_sync(tp))
4896 goto out; 4895 goto out;
@@ -4908,7 +4907,7 @@ static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4908{ 4907{
4909 struct tg3_napi *tnapi = dev_id; 4908 struct tg3_napi *tnapi = dev_id;
4910 struct tg3 *tp = tnapi->tp; 4909 struct tg3 *tp = tnapi->tp;
4911 struct tg3_hw_status *sblk = tp->hw_status; 4910 struct tg3_hw_status *sblk = tnapi->hw_status;
4912 4911
4913 if ((sblk->status & SD_STATUS_UPDATED) || 4912 if ((sblk->status & SD_STATUS_UPDATED) ||
4914 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { 4913 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
@@ -5762,6 +5761,8 @@ static int tg3_init_rings(struct tg3 *tp)
5762 */ 5761 */
5763static void tg3_free_consistent(struct tg3 *tp) 5762static void tg3_free_consistent(struct tg3 *tp)
5764{ 5763{
5764 struct tg3_napi *tnapi = &tp->napi[0];
5765
5765 kfree(tp->tx_buffers); 5766 kfree(tp->tx_buffers);
5766 tp->tx_buffers = NULL; 5767 tp->tx_buffers = NULL;
5767 if (tp->rx_rcb) { 5768 if (tp->rx_rcb) {
@@ -5774,10 +5775,11 @@ static void tg3_free_consistent(struct tg3 *tp)
5774 tp->tx_ring, tp->tx_desc_mapping); 5775 tp->tx_ring, tp->tx_desc_mapping);
5775 tp->tx_ring = NULL; 5776 tp->tx_ring = NULL;
5776 } 5777 }
5777 if (tp->hw_status) { 5778 if (tnapi->hw_status) {
5778 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE, 5779 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5779 tp->hw_status, tp->status_mapping); 5780 tnapi->hw_status,
5780 tp->hw_status = NULL; 5781 tnapi->status_mapping);
5782 tnapi->hw_status = NULL;
5781 } 5783 }
5782 if (tp->hw_stats) { 5784 if (tp->hw_stats) {
5783 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats), 5785 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
@@ -5793,6 +5795,8 @@ static void tg3_free_consistent(struct tg3 *tp)
5793 */ 5795 */
5794static int tg3_alloc_consistent(struct tg3 *tp) 5796static int tg3_alloc_consistent(struct tg3 *tp)
5795{ 5797{
5798 struct tg3_napi *tnapi = &tp->napi[0];
5799
5796 if (tg3_rx_prodring_init(tp, &tp->prodring[0])) 5800 if (tg3_rx_prodring_init(tp, &tp->prodring[0]))
5797 return -ENOMEM; 5801 return -ENOMEM;
5798 5802
@@ -5811,19 +5815,20 @@ static int tg3_alloc_consistent(struct tg3 *tp)
5811 if (!tp->tx_ring) 5815 if (!tp->tx_ring)
5812 goto err_out; 5816 goto err_out;
5813 5817
5814 tp->hw_status = pci_alloc_consistent(tp->pdev, 5818 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
5815 TG3_HW_STATUS_SIZE, 5819 TG3_HW_STATUS_SIZE,
5816 &tp->status_mapping); 5820 &tnapi->status_mapping);
5817 if (!tp->hw_status) 5821 if (!tnapi->hw_status)
5818 goto err_out; 5822 goto err_out;
5819 5823
5824 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5825
5820 tp->hw_stats = pci_alloc_consistent(tp->pdev, 5826 tp->hw_stats = pci_alloc_consistent(tp->pdev,
5821 sizeof(struct tg3_hw_stats), 5827 sizeof(struct tg3_hw_stats),
5822 &tp->stats_mapping); 5828 &tp->stats_mapping);
5823 if (!tp->hw_stats) 5829 if (!tp->hw_stats)
5824 goto err_out; 5830 goto err_out;
5825 5831
5826 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5827 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); 5832 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5828 5833
5829 return 0; 5834 return 0;
@@ -5885,6 +5890,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int
5885static int tg3_abort_hw(struct tg3 *tp, int silent) 5890static int tg3_abort_hw(struct tg3 *tp, int silent)
5886{ 5891{
5887 int i, err; 5892 int i, err;
5893 struct tg3_napi *tnapi = &tp->napi[0];
5888 5894
5889 tg3_disable_ints(tp); 5895 tg3_disable_ints(tp);
5890 5896
@@ -5936,8 +5942,8 @@ static int tg3_abort_hw(struct tg3 *tp, int silent)
5936 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); 5942 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5937 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); 5943 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5938 5944
5939 if (tp->hw_status) 5945 if (tnapi->hw_status)
5940 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); 5946 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
5941 if (tp->hw_stats) 5947 if (tp->hw_stats)
5942 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); 5948 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5943 5949
@@ -6264,12 +6270,12 @@ static int tg3_chip_reset(struct tg3 *tp)
6264 * sharing or irqpoll. 6270 * sharing or irqpoll.
6265 */ 6271 */
6266 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; 6272 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6267 if (tp->hw_status) { 6273 if (tp->napi[0].hw_status) {
6268 tp->hw_status->status = 0; 6274 tp->napi[0].hw_status->status = 0;
6269 tp->hw_status->status_tag = 0; 6275 tp->napi[0].hw_status->status_tag = 0;
6270 } 6276 }
6271 tp->last_tag = 0; 6277 tp->napi[0].last_tag = 0;
6272 tp->last_irq_tag = 0; 6278 tp->napi[0].last_irq_tag = 0;
6273 smp_mb(); 6279 smp_mb();
6274 synchronize_irq(tp->pdev->irq); 6280 synchronize_irq(tp->pdev->irq);
6275 6281
@@ -7210,9 +7216,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7210 7216
7211 /* set status block DMA address */ 7217 /* set status block DMA address */
7212 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 7218 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7213 ((u64) tp->status_mapping >> 32)); 7219 ((u64) tp->napi[0].status_mapping >> 32));
7214 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, 7220 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7215 ((u64) tp->status_mapping & 0xffffffff)); 7221 ((u64) tp->napi[0].status_mapping & 0xffffffff));
7216 7222
7217 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 7223 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7218 /* Status/statistics block address. See tg3_timer, 7224 /* Status/statistics block address. See tg3_timer,
@@ -7241,7 +7247,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7241 tg3_write_mem(tp, i, 0); 7247 tg3_write_mem(tp, i, 0);
7242 udelay(40); 7248 udelay(40);
7243 } 7249 }
7244 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); 7250 memset(tp->napi[0].hw_status, 0, TG3_HW_STATUS_SIZE);
7245 7251
7246 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { 7252 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7247 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; 7253 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
@@ -7294,7 +7300,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7294 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 7300 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7295 udelay(100); 7301 udelay(100);
7296 7302
7297 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); 7303 tw32_mailbox_f(tp->napi[0].int_mbox, 0);
7298 7304
7299 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 7305 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7300 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); 7306 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
@@ -7596,7 +7602,7 @@ static void tg3_timer(unsigned long __opaque)
7596 * IRQ status the mailbox/status_block protocol the chip 7602 * IRQ status the mailbox/status_block protocol the chip
7597 * uses with the cpu is race prone. 7603 * uses with the cpu is race prone.
7598 */ 7604 */
7599 if (tp->hw_status->status & SD_STATUS_UPDATED) { 7605 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
7600 tw32(GRC_LOCAL_CTRL, 7606 tw32(GRC_LOCAL_CTRL,
7601 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); 7607 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7602 } else { 7608 } else {
@@ -7740,7 +7746,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
7740 if (err) 7746 if (err)
7741 return err; 7747 return err;
7742 7748
7743 tp->hw_status->status &= ~SD_STATUS_UPDATED; 7749 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
7744 tg3_enable_ints(tp); 7750 tg3_enable_ints(tp);
7745 7751
7746 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | 7752 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
@@ -7749,8 +7755,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
7749 for (i = 0; i < 5; i++) { 7755 for (i = 0; i < 5; i++) {
7750 u32 int_mbox, misc_host_ctrl; 7756 u32 int_mbox, misc_host_ctrl;
7751 7757
7752 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 + 7758 int_mbox = tr32_mailbox(tnapi->int_mbox);
7753 TG3_64BIT_REG_LOW);
7754 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); 7759 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7755 7760
7756 if ((int_mbox != 0) || 7761 if ((int_mbox != 0) ||
@@ -8027,6 +8032,7 @@ err_out1:
8027 u32 val32, val32_2, val32_3, val32_4, val32_5; 8032 u32 val32, val32_2, val32_3, val32_4, val32_5;
8028 u16 val16; 8033 u16 val16;
8029 int i; 8034 int i;
8035 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8030 8036
8031 pci_read_config_word(tp->pdev, PCI_STATUS, &val16); 8037 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8032 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32); 8038 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
@@ -8179,14 +8185,15 @@ err_out1:
8179 val32, val32_2, val32_3, val32_4, val32_5); 8185 val32, val32_2, val32_3, val32_4, val32_5);
8180 8186
8181 /* SW status block */ 8187 /* SW status block */
8182 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n", 8188 printk(KERN_DEBUG
8183 tp->hw_status->status, 8189 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8184 tp->hw_status->status_tag, 8190 sblk->status,
8185 tp->hw_status->rx_jumbo_consumer, 8191 sblk->status_tag,
8186 tp->hw_status->rx_consumer, 8192 sblk->rx_jumbo_consumer,
8187 tp->hw_status->rx_mini_consumer, 8193 sblk->rx_consumer,
8188 tp->hw_status->idx[0].rx_producer, 8194 sblk->rx_mini_consumer,
8189 tp->hw_status->idx[0].tx_consumer); 8195 sblk->idx[0].rx_producer,
8196 sblk->idx[0].tx_consumer);
8190 8197
8191 /* SW statistics block */ 8198 /* SW statistics block */
8192 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n", 8199 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
@@ -9824,8 +9831,12 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9824 dma_addr_t map; 9831 dma_addr_t map;
9825 int num_pkts, tx_len, rx_len, i, err; 9832 int num_pkts, tx_len, rx_len, i, err;
9826 struct tg3_rx_buffer_desc *desc; 9833 struct tg3_rx_buffer_desc *desc;
9834 struct tg3_napi *tnapi, *rnapi;
9827 struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; 9835 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
9828 9836
9837 tnapi = &tp->napi[0];
9838 rnapi = &tp->napi[0];
9839
9829 if (loopback_mode == TG3_MAC_LOOPBACK) { 9840 if (loopback_mode == TG3_MAC_LOOPBACK) {
9830 /* HW errata - mac loopback fails in some cases on 5780. 9841 /* HW errata - mac loopback fails in some cases on 5780.
9831 * Normal traffic and PHY loopback are not affected by 9842 * Normal traffic and PHY loopback are not affected by
@@ -9907,7 +9918,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9907 9918
9908 udelay(10); 9919 udelay(10);
9909 9920
9910 rx_start_idx = tp->hw_status->idx[0].rx_producer; 9921 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
9911 9922
9912 num_pkts = 0; 9923 num_pkts = 0;
9913 9924
@@ -9929,8 +9940,8 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9929 9940
9930 udelay(10); 9941 udelay(10);
9931 9942
9932 tx_idx = tp->hw_status->idx[0].tx_consumer; 9943 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
9933 rx_idx = tp->hw_status->idx[0].rx_producer; 9944 rx_idx = rnapi->hw_status->idx[0].rx_producer;
9934 if ((tx_idx == tp->tx_prod) && 9945 if ((tx_idx == tp->tx_prod) &&
9935 (rx_idx == (rx_start_idx + num_pkts))) 9946 (rx_idx == (rx_start_idx + num_pkts)))
9936 break; 9947 break;
@@ -13401,6 +13412,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
13401 tp->tx_pending = TG3_DEF_TX_RING_PENDING; 13412 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13402 13413
13403 tp->napi[0].tp = tp; 13414 tp->napi[0].tp = tp;
13415 tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
13404 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64); 13416 netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64);
13405 dev->ethtool_ops = &tg3_ethtool_ops; 13417 dev->ethtool_ops = &tg3_ethtool_ops;
13406 dev->watchdog_timeo = TG3_TX_TIMEOUT; 13418 dev->watchdog_timeo = TG3_TX_TIMEOUT;
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index aff3f046c907..f46e6198a82b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2492,6 +2492,13 @@ struct tg3_rx_prodring_set {
2492struct tg3_napi { 2492struct tg3_napi {
2493 struct napi_struct napi ____cacheline_aligned; 2493 struct napi_struct napi ____cacheline_aligned;
2494 struct tg3 *tp; 2494 struct tg3 *tp;
2495 struct tg3_hw_status *hw_status;
2496
2497 u32 last_tag;
2498 u32 last_irq_tag;
2499 u32 int_mbox;
2500
2501 dma_addr_t status_mapping;
2495}; 2502};
2496 2503
2497struct tg3 { 2504struct tg3 {
@@ -2546,11 +2553,6 @@ struct tg3 {
2546 struct net_device *dev; 2553 struct net_device *dev;
2547 struct pci_dev *pdev; 2554 struct pci_dev *pdev;
2548 2555
2549 struct tg3_hw_status *hw_status;
2550 dma_addr_t status_mapping;
2551 u32 last_tag;
2552 u32 last_irq_tag;
2553
2554 u32 msg_enable; 2556 u32 msg_enable;
2555 2557
2556 /* begin "tx thread" cacheline section */ 2558 /* begin "tx thread" cacheline section */