diff options
| author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2012-11-19 04:39:53 -0500 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2012-11-23 21:57:14 -0500 |
| commit | 78f9f3b12c6a25a668c43f026f42596c88d6d0bd (patch) | |
| tree | e8b40a7ae3b3fcc99e955407fb0da0ff8ca3672d /drivers | |
| parent | 423b89595de34f81061d106c34cfca58cde497da (diff) | |
pinctrl: mvebu: fix iomem pointer for dove pinctrl
There has been a change in readl/writel to require registers
addresses marked as IOMEM(). This patch takes care of this and
also replaces ORing address offsets with adding them.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pinctrl/mvebu/pinctrl-dove.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c index ffe74b27d66d..34693f60d39c 100644 --- a/drivers/pinctrl/mvebu/pinctrl-dove.c +++ b/drivers/pinctrl/mvebu/pinctrl-dove.c | |||
| @@ -22,22 +22,22 @@ | |||
| 22 | 22 | ||
| 23 | #include "pinctrl-mvebu.h" | 23 | #include "pinctrl-mvebu.h" |
| 24 | 24 | ||
| 25 | #define DOVE_SB_REGS_VIRT_BASE 0xfde00000 | 25 | #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) |
| 26 | #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) | 26 | #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) |
| 27 | #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) | 27 | #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) |
| 28 | #define DOVE_AU0_AC97_SEL BIT(16) | 28 | #define DOVE_AU0_AC97_SEL BIT(16) |
| 29 | #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) | 29 | #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) |
| 30 | #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) | 30 | #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) |
| 31 | #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) | 31 | #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) |
| 32 | #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) | 32 | #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) |
| 33 | #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) | 33 | #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) |
| 34 | #define DOVE_TWSI_OPTION3_GPIO BIT(22) | 34 | #define DOVE_TWSI_OPTION3_GPIO BIT(22) |
| 35 | #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) | 35 | #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) |
| 36 | #define DOVE_SSP_ON_AU1 BIT(0) | 36 | #define DOVE_SSP_ON_AU1 BIT(0) |
| 37 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) | 37 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) |
| 38 | #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) | 38 | #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) |
| 39 | #define DOVE_NAND_GPIO_EN BIT(0) | 39 | #define DOVE_NAND_GPIO_EN BIT(0) |
| 40 | #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) | 40 | #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) |
| 41 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) | 41 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) |
| 42 | #define DOVE_SPI_GPIO_SEL BIT(5) | 42 | #define DOVE_SPI_GPIO_SEL BIT(5) |
| 43 | #define DOVE_UART1_GPIO_SEL BIT(4) | 43 | #define DOVE_UART1_GPIO_SEL BIT(4) |