diff options
| author | Dave Airlie <airlied@redhat.com> | 2014-01-22 22:50:54 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2014-01-22 22:50:54 -0500 |
| commit | 76f4f415e502e4dfaf409edd0d4ed0dd3a0a0419 (patch) | |
| tree | 7ee5b899a72c2ded6b00a77ba4a3de365a320daf /drivers | |
| parent | 2510538fa000dd13a3e57b79bf073ffb1748976c (diff) | |
| parent | 1139ffb96b3f4e8be9006552d2dd4d302d62c2ee (diff) | |
Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
Summary:
- GK110/GK208 acceleration
- loads more work towards pm, though, still behind a disable wall for now
- error reporting improvements from both Ilia and myself
- more old-school overlay improvements from Ilia
- misc other bits and pieces
* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (68 commits)
drm/nouveau: call drm_vblank_cleanup() earlier
drm/nouveau: create base display from common code
drm/nv50/gr: print mpc trap name when it's not an mp trap
drm/nv50/gr: update list of mp errors, make it a bitfield
drm/nv50/gr: add more trap names to print on error
drm/nouveau/devinit: lock/unlock crtc regs for all devices, not just pre-nv50
drm/nouveau: hold mutex while syncing to kernel channel
drm/nv50-/devinit: prevent use of engines marked as disabled by hw/vbios
drm/nouveau/device: provide a way for devinit to mark engines as disabled
drm/nouveau/devinit: tidy up the subdev class definition
drm/nouveau/bar: tidy up the subdev and object class definitions
drm/nouveau/instmem: tidy up the object class definition
drm/nouveau/instmem: tidy up the subdev class definition
drm/nouveau/pwr: implement a simple i2c stack
drm/nouveau/pwr: have rd/wr32 routines clobber data instead of addr
drm/nve0/fb: turn off some bits in 10f584 at init
drm/nve0/fb/gddr5: merge a fix from ddr3 for one of the timing settings
drm/nve0/fb/gddr5: yet another random 10f200 bit
drm/nvc0-/fb: hook up skeleton interrupt handler
drm/nve0/fb/gddr5: more 10f200 stuff
...
Diffstat (limited to 'drivers')
119 files changed, 12385 insertions, 5854 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index b3fa1ba191b7..e88145ba1bf5 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
| @@ -41,6 +41,7 @@ nouveau-y += core/subdev/bios/init.o | |||
| 41 | nouveau-y += core/subdev/bios/mxm.o | 41 | nouveau-y += core/subdev/bios/mxm.o |
| 42 | nouveau-y += core/subdev/bios/perf.o | 42 | nouveau-y += core/subdev/bios/perf.o |
| 43 | nouveau-y += core/subdev/bios/pll.o | 43 | nouveau-y += core/subdev/bios/pll.o |
| 44 | nouveau-y += core/subdev/bios/ramcfg.o | ||
| 44 | nouveau-y += core/subdev/bios/rammap.o | 45 | nouveau-y += core/subdev/bios/rammap.o |
| 45 | nouveau-y += core/subdev/bios/timing.o | 46 | nouveau-y += core/subdev/bios/timing.o |
| 46 | nouveau-y += core/subdev/bios/therm.o | 47 | nouveau-y += core/subdev/bios/therm.o |
| @@ -71,7 +72,10 @@ nouveau-y += core/subdev/devinit/nv10.o | |||
| 71 | nouveau-y += core/subdev/devinit/nv1a.o | 72 | nouveau-y += core/subdev/devinit/nv1a.o |
| 72 | nouveau-y += core/subdev/devinit/nv20.o | 73 | nouveau-y += core/subdev/devinit/nv20.o |
| 73 | nouveau-y += core/subdev/devinit/nv50.o | 74 | nouveau-y += core/subdev/devinit/nv50.o |
| 75 | nouveau-y += core/subdev/devinit/nv84.o | ||
| 76 | nouveau-y += core/subdev/devinit/nv98.o | ||
| 74 | nouveau-y += core/subdev/devinit/nva3.o | 77 | nouveau-y += core/subdev/devinit/nva3.o |
| 78 | nouveau-y += core/subdev/devinit/nvaf.o | ||
| 75 | nouveau-y += core/subdev/devinit/nvc0.o | 79 | nouveau-y += core/subdev/devinit/nvc0.o |
| 76 | nouveau-y += core/subdev/fb/base.o | 80 | nouveau-y += core/subdev/fb/base.o |
| 77 | nouveau-y += core/subdev/fb/nv04.o | 81 | nouveau-y += core/subdev/fb/nv04.o |
| @@ -232,6 +236,7 @@ nouveau-y += core/engine/fifo/nv50.o | |||
| 232 | nouveau-y += core/engine/fifo/nv84.o | 236 | nouveau-y += core/engine/fifo/nv84.o |
| 233 | nouveau-y += core/engine/fifo/nvc0.o | 237 | nouveau-y += core/engine/fifo/nvc0.o |
| 234 | nouveau-y += core/engine/fifo/nve0.o | 238 | nouveau-y += core/engine/fifo/nve0.o |
| 239 | nouveau-y += core/engine/fifo/nv108.o | ||
| 235 | nouveau-y += core/engine/graph/ctxnv40.o | 240 | nouveau-y += core/engine/graph/ctxnv40.o |
| 236 | nouveau-y += core/engine/graph/ctxnv50.o | 241 | nouveau-y += core/engine/graph/ctxnv50.o |
| 237 | nouveau-y += core/engine/graph/ctxnvc0.o | 242 | nouveau-y += core/engine/graph/ctxnvc0.o |
| @@ -242,6 +247,7 @@ nouveau-y += core/engine/graph/ctxnvd7.o | |||
| 242 | nouveau-y += core/engine/graph/ctxnvd9.o | 247 | nouveau-y += core/engine/graph/ctxnvd9.o |
| 243 | nouveau-y += core/engine/graph/ctxnve4.o | 248 | nouveau-y += core/engine/graph/ctxnve4.o |
| 244 | nouveau-y += core/engine/graph/ctxnvf0.o | 249 | nouveau-y += core/engine/graph/ctxnvf0.o |
| 250 | nouveau-y += core/engine/graph/ctxnv108.o | ||
| 245 | nouveau-y += core/engine/graph/nv04.o | 251 | nouveau-y += core/engine/graph/nv04.o |
| 246 | nouveau-y += core/engine/graph/nv10.o | 252 | nouveau-y += core/engine/graph/nv10.o |
| 247 | nouveau-y += core/engine/graph/nv20.o | 253 | nouveau-y += core/engine/graph/nv20.o |
| @@ -260,6 +266,7 @@ nouveau-y += core/engine/graph/nvd7.o | |||
| 260 | nouveau-y += core/engine/graph/nvd9.o | 266 | nouveau-y += core/engine/graph/nvd9.o |
| 261 | nouveau-y += core/engine/graph/nve4.o | 267 | nouveau-y += core/engine/graph/nve4.o |
| 262 | nouveau-y += core/engine/graph/nvf0.o | 268 | nouveau-y += core/engine/graph/nvf0.o |
| 269 | nouveau-y += core/engine/graph/nv108.o | ||
| 263 | nouveau-y += core/engine/mpeg/nv31.o | 270 | nouveau-y += core/engine/mpeg/nv31.o |
| 264 | nouveau-y += core/engine/mpeg/nv40.o | 271 | nouveau-y += core/engine/mpeg/nv40.o |
| 265 | nouveau-y += core/engine/mpeg/nv44.o | 272 | nouveau-y += core/engine/mpeg/nv44.o |
diff --git a/drivers/gpu/drm/nouveau/core/core/engine.c b/drivers/gpu/drm/nouveau/core/core/engine.c index c8bed4a26833..1f6954ae9dd3 100644 --- a/drivers/gpu/drm/nouveau/core/core/engine.c +++ b/drivers/gpu/drm/nouveau/core/core/engine.c | |||
| @@ -42,11 +42,24 @@ nouveau_engine_create_(struct nouveau_object *parent, | |||
| 42 | if (ret) | 42 | if (ret) |
| 43 | return ret; | 43 | return ret; |
| 44 | 44 | ||
| 45 | if ( parent && | 45 | if (parent) { |
| 46 | !nouveau_boolopt(nv_device(parent)->cfgopt, iname, enable)) { | 46 | struct nouveau_device *device = nv_device(parent); |
| 47 | if (!enable) | 47 | int engidx = nv_engidx(nv_object(engine)); |
| 48 | nv_warn(engine, "disabled, %s=1 to enable\n", iname); | 48 | |
| 49 | return -ENODEV; | 49 | if (device->disable_mask & (1ULL << engidx)) { |
| 50 | if (!nouveau_boolopt(device->cfgopt, iname, false)) { | ||
| 51 | nv_debug(engine, "engine disabled by hw/fw\n"); | ||
| 52 | return -ENODEV; | ||
| 53 | } | ||
| 54 | |||
| 55 | nv_warn(engine, "ignoring hw/fw engine disable\n"); | ||
| 56 | } | ||
| 57 | |||
| 58 | if (!nouveau_boolopt(device->cfgopt, iname, enable)) { | ||
| 59 | if (!enable) | ||
| 60 | nv_warn(engine, "disabled, %s=1 to enable\n", iname); | ||
| 61 | return -ENODEV; | ||
| 62 | } | ||
| 50 | } | 63 | } |
| 51 | 64 | ||
| 52 | INIT_LIST_HEAD(&engine->contexts); | 65 | INIT_LIST_HEAD(&engine->contexts); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c index 993df09ad643..ac3291f781f6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c | |||
| @@ -105,9 +105,6 @@ nvc0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 105 | struct nvc0_copy_priv *priv; | 105 | struct nvc0_copy_priv *priv; |
| 106 | int ret; | 106 | int ret; |
| 107 | 107 | ||
| 108 | if (nv_rd32(parent, 0x022500) & 0x00000100) | ||
| 109 | return -ENODEV; | ||
| 110 | |||
| 111 | ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true, | 108 | ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true, |
| 112 | "PCE0", "copy0", &priv); | 109 | "PCE0", "copy0", &priv); |
| 113 | *pobject = nv_object(priv); | 110 | *pobject = nv_object(priv); |
| @@ -133,9 +130,6 @@ nvc0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 133 | struct nvc0_copy_priv *priv; | 130 | struct nvc0_copy_priv *priv; |
| 134 | int ret; | 131 | int ret; |
| 135 | 132 | ||
| 136 | if (nv_rd32(parent, 0x022500) & 0x00000200) | ||
| 137 | return -ENODEV; | ||
| 138 | |||
| 139 | ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true, | 133 | ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true, |
| 140 | "PCE1", "copy1", &priv); | 134 | "PCE1", "copy1", &priv); |
| 141 | *pobject = nv_object(priv); | 135 | *pobject = nv_object(priv); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c index 30f1ef1edcc5..748a61eb3c6f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c | |||
| @@ -88,9 +88,6 @@ nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 88 | struct nve0_copy_priv *priv; | 88 | struct nve0_copy_priv *priv; |
| 89 | int ret; | 89 | int ret; |
| 90 | 90 | ||
| 91 | if (nv_rd32(parent, 0x022500) & 0x00000100) | ||
| 92 | return -ENODEV; | ||
| 93 | |||
| 94 | ret = nouveau_engine_create(parent, engine, oclass, true, | 91 | ret = nouveau_engine_create(parent, engine, oclass, true, |
| 95 | "PCE0", "copy0", &priv); | 92 | "PCE0", "copy0", &priv); |
| 96 | *pobject = nv_object(priv); | 93 | *pobject = nv_object(priv); |
| @@ -112,9 +109,6 @@ nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 112 | struct nve0_copy_priv *priv; | 109 | struct nve0_copy_priv *priv; |
| 113 | int ret; | 110 | int ret; |
| 114 | 111 | ||
| 115 | if (nv_rd32(parent, 0x022500) & 0x00000200) | ||
| 116 | return -ENODEV; | ||
| 117 | |||
| 118 | ret = nouveau_engine_create(parent, engine, oclass, true, | 112 | ret = nouveau_engine_create(parent, engine, oclass, true, |
| 119 | "PCE1", "copy1", &priv); | 113 | "PCE1", "copy1", &priv); |
| 120 | *pobject = nv_object(priv); | 114 | *pobject = nv_object(priv); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c index dbd2dde7b7e7..32113b08c4d5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c | |||
| @@ -49,12 +49,12 @@ nv04_identify(struct nouveau_device *device) | |||
| 49 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 49 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 50 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 51 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 52 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass; | 52 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; |
| 53 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 53 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 54 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 54 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 55 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 55 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 56 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; | 56 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; |
| 57 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 57 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 58 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 59 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 59 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 60 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; | 60 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; |
| @@ -67,12 +67,12 @@ nv04_identify(struct nouveau_device *device) | |||
| 67 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; | 67 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
| 68 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 68 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 69 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 69 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 70 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass; | 70 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; |
| 71 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 71 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 72 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 73 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; | 74 | device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 77 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 77 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 78 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; | 78 | device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c index 6e03dd6abeea..744f15d7e131 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c | |||
| @@ -51,12 +51,12 @@ nv10_identify(struct nouveau_device *device) | |||
| 51 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 51 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 52 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 52 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 53 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 53 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 54 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; | 54 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
| 55 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 55 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 56 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 56 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 57 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 57 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 58 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 59 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 59 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 60 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 60 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 61 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 61 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 62 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; | 62 | device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; |
| @@ -68,12 +68,12 @@ nv10_identify(struct nouveau_device *device) | |||
| 68 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 68 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 69 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 69 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 70 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 70 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 71 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; | 71 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 72 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 73 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 75 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 76 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 77 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 78 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 78 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 79 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; | 79 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
| @@ -87,12 +87,12 @@ nv10_identify(struct nouveau_device *device) | |||
| 87 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 87 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 88 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 88 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 89 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 89 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 90 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; | 90 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
| 91 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 91 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 92 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 92 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 93 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 93 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 94 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 94 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 95 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 95 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 96 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 97 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 97 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 98 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; | 98 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
| @@ -106,12 +106,12 @@ nv10_identify(struct nouveau_device *device) | |||
| 106 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 106 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 107 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 107 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 108 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 108 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 109 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 109 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 110 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 111 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 112 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 112 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 113 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; | 113 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; |
| 114 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 114 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 115 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 115 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 116 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 116 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 117 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; | 117 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
| @@ -125,12 +125,12 @@ nv10_identify(struct nouveau_device *device) | |||
| 125 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 125 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 126 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 126 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 127 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 127 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 128 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; | 128 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
| 129 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 129 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 130 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 130 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 131 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 131 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 132 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 132 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 133 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 133 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 134 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 134 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 135 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 135 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 136 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; | 136 | device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; |
| @@ -144,12 +144,12 @@ nv10_identify(struct nouveau_device *device) | |||
| 144 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 144 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 145 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 145 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 146 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 146 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 147 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; | 147 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
| 148 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 148 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 149 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 149 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 150 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 150 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 151 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 151 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 152 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 152 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 153 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 153 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 154 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 154 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 155 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 155 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -163,12 +163,12 @@ nv10_identify(struct nouveau_device *device) | |||
| 163 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 163 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 164 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 164 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 165 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 165 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 166 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 166 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 167 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 167 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 168 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 168 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 169 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 169 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 170 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; | 170 | device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; |
| 171 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 171 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 172 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 172 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 173 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 173 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 174 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 174 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -182,12 +182,12 @@ nv10_identify(struct nouveau_device *device) | |||
| 182 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 182 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 183 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 183 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 184 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 184 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 185 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; | 185 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
| 186 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 186 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 187 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 187 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 188 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 188 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 189 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 189 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 190 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 190 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 191 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 191 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 192 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 192 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 193 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 193 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c index dcde53b9f07f..27ba61fb2710 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c | |||
| @@ -52,12 +52,12 @@ nv20_identify(struct nouveau_device *device) | |||
| 52 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 52 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 53 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 53 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 54 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 54 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 55 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; | 55 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
| 56 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 56 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; | 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; |
| 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -71,12 +71,12 @@ nv20_identify(struct nouveau_device *device) | |||
| 71 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 71 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 72 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 73 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; | 74 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 75 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; | 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; |
| 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -90,12 +90,12 @@ nv20_identify(struct nouveau_device *device) | |||
| 90 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 90 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 91 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 91 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 92 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 92 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; | 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
| 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; | 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; |
| 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -109,12 +109,12 @@ nv20_identify(struct nouveau_device *device) | |||
| 109 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 109 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 110 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 111 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 112 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; | 112 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
| 113 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 113 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 114 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 114 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 115 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 115 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 116 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; | 116 | device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; |
| 117 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 117 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 118 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 118 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 119 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 119 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 120 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 120 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c index 7b8662ef4f59..fd47ace67543 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c | |||
| @@ -52,12 +52,12 @@ nv30_identify(struct nouveau_device *device) | |||
| 52 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 52 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 53 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 53 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 54 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 54 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 55 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; | 55 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
| 56 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 56 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 57 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 58 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; | 59 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
| 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 60 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 61 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 62 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 63 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -71,12 +71,12 @@ nv30_identify(struct nouveau_device *device) | |||
| 71 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 71 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 72 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 73 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; | 74 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 75 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; | 76 | device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 77 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; | 78 | device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; |
| 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 79 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 80 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 81 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 82 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -90,12 +90,12 @@ nv30_identify(struct nouveau_device *device) | |||
| 90 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 90 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 91 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 91 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 92 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 92 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; | 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
| 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; | 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; |
| 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 100 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 101 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -110,12 +110,12 @@ nv30_identify(struct nouveau_device *device) | |||
| 110 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 110 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 111 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 112 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 112 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 113 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass; | 113 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; |
| 114 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 114 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 115 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 115 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 116 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 116 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 117 | device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; | 117 | device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; |
| 118 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 118 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 119 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 119 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 120 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 120 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 121 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 121 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
| @@ -130,12 +130,12 @@ nv30_identify(struct nouveau_device *device) | |||
| 130 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; | 130 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass; |
| 131 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 131 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 132 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; | 132 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; |
| 133 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass; | 133 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; |
| 134 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; | 134 | device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; |
| 135 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 135 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 136 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 136 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 137 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; | 137 | device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; |
| 138 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass; | 138 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; |
| 139 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 139 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 140 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 140 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| 141 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; | 141 | device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c index c8c41e93695e..1b653dd74a70 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c | |||
| @@ -57,12 +57,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 57 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 57 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 58 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 58 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 59 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 59 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 60 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 60 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 61 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; | 61 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 62 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 62 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 63 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 63 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 64 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; | 64 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; |
| 65 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 65 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 66 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 66 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 67 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 67 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 68 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 68 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -80,12 +80,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 80 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 80 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 81 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 81 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 82 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 82 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 83 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 83 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 84 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; | 84 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 85 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 85 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 86 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 86 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 87 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; | 87 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 88 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 88 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 89 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 89 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 90 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 90 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 91 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 91 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -103,12 +103,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 103 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 103 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 104 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 104 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 105 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 105 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 106 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 106 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 107 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; | 107 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 108 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 108 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 109 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 109 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; | 110 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 111 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 112 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 112 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 113 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 113 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 114 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 114 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -126,12 +126,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 126 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 126 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 127 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 127 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 128 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 128 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 129 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 129 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 130 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; | 130 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 131 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 131 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 132 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 132 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 133 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; | 133 | device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; |
| 134 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 134 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 135 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 135 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 136 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 136 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 137 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 137 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -149,12 +149,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 149 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 149 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 150 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 150 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 151 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 151 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 152 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 152 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 153 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; | 153 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 154 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 154 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 155 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 155 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 156 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; | 156 | device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; |
| 157 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 157 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 158 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; | 158 | device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; |
| 159 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 159 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 160 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 160 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -172,12 +172,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 172 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 172 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 173 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 173 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 174 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 174 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 175 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 175 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 176 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; | 176 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 177 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 177 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 178 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 178 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 179 | device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; | 179 | device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; |
| 180 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 180 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 181 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 181 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 182 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 182 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 183 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 183 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -195,12 +195,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 195 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 195 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 196 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 196 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 197 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 197 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 198 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 198 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 199 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; | 199 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 200 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 200 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 201 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 201 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 202 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; | 202 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; |
| 203 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 203 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 204 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 204 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 205 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 205 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 206 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 206 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -218,12 +218,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 218 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 218 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 219 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 219 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 220 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 220 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 221 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 221 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 222 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; | 222 | device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; |
| 223 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 223 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 224 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 224 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 225 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; | 225 | device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; |
| 226 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 226 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 227 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; | 227 | device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; |
| 228 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 228 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 229 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 229 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -241,12 +241,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 241 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 241 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 242 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 242 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 243 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 243 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 244 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 244 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 245 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; | 245 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 246 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 246 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 247 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 247 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 248 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; | 248 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; |
| 249 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 249 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 250 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 250 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 251 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 251 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 252 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 252 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -264,12 +264,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 264 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 264 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 265 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 265 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 266 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 266 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 267 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 267 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 268 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; | 268 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 269 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 269 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 270 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 270 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 271 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 271 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 272 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 272 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 273 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 273 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 274 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 274 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 275 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 275 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -287,12 +287,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 287 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 287 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 288 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 288 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 289 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 289 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 290 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 290 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 291 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; | 291 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 292 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 292 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 293 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 293 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 294 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; | 294 | device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; |
| 295 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 295 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 296 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 296 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 298 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 298 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -310,12 +310,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 310 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 310 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 311 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 311 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 312 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 312 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 313 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 313 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 314 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; | 314 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 315 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 315 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 316 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 316 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 317 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 317 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 318 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 318 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 319 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 319 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 320 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 320 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 321 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 321 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -333,12 +333,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 333 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass; | 333 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv4e_i2c_oclass; |
| 334 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 334 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 335 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 335 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 336 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 336 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 337 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; | 337 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 338 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 338 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 339 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 339 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 340 | device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; | 340 | device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; |
| 341 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 341 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 342 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 342 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 343 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 343 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 344 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 344 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -356,12 +356,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 356 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 356 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 357 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 357 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 358 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 358 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 359 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 359 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 360 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; | 360 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 361 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 361 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 362 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 362 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 363 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 363 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 364 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 364 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 365 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 365 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 366 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 366 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 367 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 367 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -379,12 +379,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 379 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 379 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 380 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 380 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 381 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 381 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 382 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 382 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 383 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; | 383 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 384 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 384 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 385 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 385 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 386 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 386 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 387 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 387 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 388 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 388 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 389 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 389 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 390 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 390 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
| @@ -402,12 +402,12 @@ nv40_identify(struct nouveau_device *device) | |||
| 402 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; | 402 | device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass; |
| 403 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; | 403 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; |
| 404 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; | 404 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; |
| 405 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass; | 405 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; |
| 406 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; | 406 | device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; |
| 407 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; | 407 | device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; |
| 408 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 408 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 409 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; | 409 | device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; |
| 410 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass; | 410 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; |
| 411 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; | 411 | device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; |
| 412 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 412 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 413 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; | 413 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c index db3fc7be856a..81d5c26643d5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c | |||
| @@ -65,12 +65,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; | 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; |
| 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; | 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; |
| 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; |
| 69 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; | 69 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
| 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; | 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; | 72 | device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 73 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 74 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 75 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 76 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -90,12 +90,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 90 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; | 90 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 91 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 91 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 92 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 92 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 93 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; | 94 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
| 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; | 95 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 96 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 97 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 98 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 99 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 100 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 100 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 101 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 101 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -118,12 +118,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 118 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; | 118 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 119 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 119 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 120 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 120 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 121 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 121 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 122 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; | 122 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
| 123 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; | 123 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 124 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 124 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 125 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 125 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 126 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 126 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 127 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 127 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 128 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 128 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 129 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 129 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -146,12 +146,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 146 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; | 146 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 147 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 147 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 148 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 148 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 149 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 149 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 150 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; | 150 | device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; |
| 151 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; | 151 | device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; |
| 152 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 152 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 153 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 153 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 154 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 154 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 155 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 155 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 156 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 156 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 157 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 157 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -174,12 +174,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 174 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; | 174 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 175 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 175 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 176 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 176 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 177 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 177 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 178 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; | 178 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; |
| 179 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 179 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 180 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 180 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 181 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 181 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 182 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 182 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 183 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 183 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 184 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 184 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 185 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 185 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -202,12 +202,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 202 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; | 202 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 203 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 203 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 204 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 204 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 205 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 205 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 206 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; | 206 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; |
| 207 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 207 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 208 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 208 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 209 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 209 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 210 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 210 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 211 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 211 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 212 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 212 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 213 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 213 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -230,12 +230,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 230 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; | 230 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 231 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 231 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 232 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 232 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 233 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 233 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
| 234 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 234 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 235 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 235 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 236 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 236 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 237 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 237 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 238 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 238 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 239 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 239 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 240 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 240 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 241 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 241 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -258,12 +258,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 258 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; | 258 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; |
| 259 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 259 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 260 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 260 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 261 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 261 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; |
| 262 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 262 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 263 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 263 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 264 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 264 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 265 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; | 265 | device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; |
| 266 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 266 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 267 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 267 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 268 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 268 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 269 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 269 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -286,12 +286,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 286 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; | 286 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; |
| 287 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 287 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 288 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 288 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 289 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 289 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
| 290 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 290 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 291 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 291 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 292 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 292 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 293 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; | 293 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; |
| 294 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 294 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 295 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 295 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 296 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 296 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 297 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -314,12 +314,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 314 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; | 314 | device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; |
| 315 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 315 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
| 316 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 316 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 317 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; | 317 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; |
| 318 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 318 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 319 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 319 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 320 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 320 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 321 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; | 321 | device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; |
| 322 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 322 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 323 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 323 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 324 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 324 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 325 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 325 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| @@ -342,12 +342,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 342 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; | 342 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
| 343 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 343 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 344 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 344 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 345 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; | 345 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
| 346 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 346 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 347 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 347 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 348 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 348 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 349 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; | 349 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 350 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 350 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 351 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 351 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 352 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 352 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 353 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; | 353 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
| @@ -372,12 +372,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 372 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; | 372 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
| 373 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 373 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 374 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 374 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 375 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; | 375 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
| 376 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 376 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 377 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 377 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 378 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 378 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 379 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; | 379 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 380 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 380 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 381 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 381 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 382 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 382 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 383 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; | 383 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
| @@ -401,12 +401,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 401 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; | 401 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
| 402 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 402 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 403 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 403 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 404 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; | 404 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; |
| 405 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 405 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 406 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 406 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 407 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 407 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 408 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; | 408 | device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; |
| 409 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 409 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 410 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 410 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 411 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 411 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 412 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; | 412 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
| @@ -430,12 +430,12 @@ nv50_identify(struct nouveau_device *device) | |||
| 430 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; | 430 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; |
| 431 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 431 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 432 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 432 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 433 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass; | 433 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass; |
| 434 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 434 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; |
| 435 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; | 435 | device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; |
| 436 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 436 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 437 | device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; | 437 | device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; |
| 438 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 438 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 439 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; | 439 | device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; |
| 440 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; | 440 | device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; |
| 441 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; | 441 | device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c index dbc5e33de94f..b7d66b59f43d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c | |||
| @@ -65,14 +65,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 69 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; | 69 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; |
| 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 72 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -97,14 +97,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 97 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 97 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 98 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 98 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 99 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 100 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 100 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 101 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; | 101 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; |
| 102 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 102 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 103 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 103 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 104 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 104 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 105 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 105 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 106 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 106 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 107 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 107 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 108 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 108 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 109 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 109 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 110 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -129,14 +129,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 129 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 129 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 130 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 130 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 131 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 131 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 132 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 132 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 133 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 133 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 134 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 134 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 135 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 135 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 136 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 136 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 137 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 137 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 138 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 138 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 139 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 139 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 140 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 140 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 141 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 141 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 142 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 142 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -160,14 +160,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 160 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 160 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 161 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 161 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 162 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 162 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 163 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 163 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 164 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; | 164 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; |
| 165 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 165 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 166 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 166 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 167 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 167 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 168 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 168 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 169 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 169 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 170 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 170 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 171 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 171 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 172 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 172 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 173 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 173 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -192,14 +192,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 192 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 192 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 193 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 193 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 194 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 194 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 195 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 195 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 196 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 196 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 197 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 197 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 198 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 198 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 199 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 199 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 200 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 200 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 201 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 201 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 202 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 202 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 203 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 203 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 204 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 204 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 205 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 205 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -224,14 +224,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 224 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 224 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 225 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 225 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 226 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 226 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 227 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 227 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 228 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 228 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 229 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 229 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 230 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 230 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 231 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 231 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 232 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 232 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 233 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 233 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 234 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 234 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 235 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 235 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 236 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 236 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 237 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 237 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -255,14 +255,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 255 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 255 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 256 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 256 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
| 257 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 257 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 258 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 258 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 259 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; | 259 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; |
| 260 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 260 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 261 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 261 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 262 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 262 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 263 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 263 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 264 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 264 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 265 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 265 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 266 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 266 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 267 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 267 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 268 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; | 268 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass; |
| @@ -287,14 +287,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 287 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 287 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 288 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 288 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 289 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 289 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 290 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 290 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 291 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 291 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 292 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 292 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 293 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 293 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 294 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 294 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 295 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 295 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 296 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 296 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 297 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 297 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 298 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 298 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 299 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 299 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 300 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 300 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -318,14 +318,14 @@ nvc0_identify(struct nouveau_device *device) | |||
| 318 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; | 318 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
| 319 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 319 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 320 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 320 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 321 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 321 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 322 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 322 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 323 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 323 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 324 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 324 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 325 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; | 325 | device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; |
| 326 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 326 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 327 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; | 327 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; |
| 328 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 328 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 329 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 329 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 330 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 330 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 331 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; | 331 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c index 3900104976fc..987edbc30a09 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c | |||
| @@ -65,14 +65,14 @@ nve0_identify(struct nouveau_device *device) | |||
| 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; | 65 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
| 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 66 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 67 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 68 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 69 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 69 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 70 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 71 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 72 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 72 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 73 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 74 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 75 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 76 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 77 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 78 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -98,14 +98,14 @@ nve0_identify(struct nouveau_device *device) | |||
| 98 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; | 98 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
| 99 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 99 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 100 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 100 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 101 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 101 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 102 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 102 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 103 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 103 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 104 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 104 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 105 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 105 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 106 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 106 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 107 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 107 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 108 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 108 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 109 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 109 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 110 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 111 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -131,14 +131,14 @@ nve0_identify(struct nouveau_device *device) | |||
| 131 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; | 131 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
| 132 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 132 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 133 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 133 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 134 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 134 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 135 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 135 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 136 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 136 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 137 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 137 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 138 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 138 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 139 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 139 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 140 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 140 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 141 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 141 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 142 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 142 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 143 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 143 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 144 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 144 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -164,14 +164,14 @@ nve0_identify(struct nouveau_device *device) | |||
| 164 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; | 164 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
| 165 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 165 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 166 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 166 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 167 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 167 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 168 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 168 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 169 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 169 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 170 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 170 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 171 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 171 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 172 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 172 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 173 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 173 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 174 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 174 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 175 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 175 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 176 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 176 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 177 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; | 177 | device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass; |
| @@ -199,29 +199,27 @@ nve0_identify(struct nouveau_device *device) | |||
| 199 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; | 199 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; |
| 200 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 200 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
| 201 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 201 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
| 202 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass; | 202 | device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; |
| 203 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 203 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; |
| 204 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; | 204 | device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; |
| 205 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 205 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
| 206 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; | 206 | device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; |
| 207 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; | 207 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
| 208 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; | 208 | device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; |
| 209 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; | 209 | device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; |
| 210 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; | 210 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 211 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; | 211 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
| 212 | device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass; | 212 | device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass; |
| 213 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; | 213 | device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; |
| 214 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; | 214 | device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass; |
| 215 | #if 0 | 215 | device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; |
| 216 | device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; | ||
| 217 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; | 216 | device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; |
| 218 | device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; | 217 | device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; |
| 219 | #endif | ||
| 220 | device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; | 218 | device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass; |
| 221 | #if 0 | ||
| 222 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; | 219 | device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; |
| 223 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; | 220 | device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; |
| 224 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; | 221 | device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; |
| 222 | #if 0 | ||
| 225 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; | 223 | device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; |
| 226 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; | 224 | device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; |
| 227 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; | 225 | device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c index 378a015091d2..d52c0f50a1a9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c | |||
| @@ -967,9 +967,6 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 967 | int heads = nv_rd32(parent, 0x022448); | 967 | int heads = nv_rd32(parent, 0x022448); |
| 968 | int ret; | 968 | int ret; |
| 969 | 969 | ||
| 970 | if (nv_rd32(parent, 0x022500) & 0x00000001) | ||
| 971 | return -ENODEV; | ||
| 972 | |||
| 973 | ret = nouveau_disp_create(parent, engine, oclass, heads, | 970 | ret = nouveau_disp_create(parent, engine, oclass, heads, |
| 974 | "PDISP", "display", &priv); | 971 | "PDISP", "display", &priv); |
| 975 | *pobject = nv_object(priv); | 972 | *pobject = nv_object(priv); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c index fb1fe6ae5e74..20725b363d58 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c | |||
| @@ -54,9 +54,6 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 54 | int heads = nv_rd32(parent, 0x022448); | 54 | int heads = nv_rd32(parent, 0x022448); |
| 55 | int ret; | 55 | int ret; |
| 56 | 56 | ||
| 57 | if (nv_rd32(parent, 0x022500) & 0x00000001) | ||
| 58 | return -ENODEV; | ||
| 59 | |||
| 60 | ret = nouveau_disp_create(parent, engine, oclass, heads, | 57 | ret = nouveau_disp_create(parent, engine, oclass, heads, |
| 61 | "PDISP", "display", &priv); | 58 | "PDISP", "display", &priv); |
| 62 | *pobject = nv_object(priv); | 59 | *pobject = nv_object(priv); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c index 42aa6b97dbea..a488c36e40f9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c | |||
| @@ -54,9 +54,6 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 54 | int heads = nv_rd32(parent, 0x022448); | 54 | int heads = nv_rd32(parent, 0x022448); |
| 55 | int ret; | 55 | int ret; |
| 56 | 56 | ||
| 57 | if (nv_rd32(parent, 0x022500) & 0x00000001) | ||
| 58 | return -ENODEV; | ||
| 59 | |||
| 60 | ret = nouveau_disp_create(parent, engine, oclass, heads, | 57 | ret = nouveau_disp_create(parent, engine, oclass, heads, |
| 61 | "PDISP", "display", &priv); | 58 | "PDISP", "display", &priv); |
| 62 | *pobject = nv_object(priv); | 59 | *pobject = nv_object(priv); |
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c b/drivers/gpu/drm/nouveau/core/engine/disp/vga.c index 5a1c68474597..8836c3cb99c3 100644 --- a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c +++ b/drivers/gpu/drm/nouveau/core/engine/disp/vga.c | |||
| @@ -138,10 +138,15 @@ nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value) | |||
| 138 | bool | 138 | bool |
| 139 | nv_lockvgac(void *obj, bool lock) | 139 | nv_lockvgac(void *obj, bool lock) |
| 140 | { | 140 | { |
| 141 | struct nouveau_device *dev = nv_device(obj); | ||
| 142 | |||
| 141 | bool locked = !nv_rdvgac(obj, 0, 0x1f); | 143 | bool locked = !nv_rdvgac(obj, 0, 0x1f); |
| 142 | u8 data = lock ? 0x99 : 0x57; | 144 | u8 data = lock ? 0x99 : 0x57; |
| 143 | nv_wrvgac(obj, 0, 0x1f, data); | 145 | if (dev->card_type < NV_50) |
| 144 | if (nv_device(obj)->chipset == 0x11) { | 146 | nv_wrvgac(obj, 0, 0x1f, data); |
| 147 | else | ||
| 148 | nv_wrvgac(obj, 0, 0x3f, data); | ||
| 149 | if (dev->chipset == 0x11) { | ||
| 145 | if (!(nv_rd32(obj, 0x001084) & 0x10000000)) | 150 | if (!(nv_rd32(obj, 0x001084) & 0x10000000)) |
| 146 | nv_wrvgac(obj, 1, 0x1f, data); | 151 | nv_wrvgac(obj, 1, 0x1f, data); |
| 147 | } | 152 | } |
diff --git a/drivers/gpu/drm/nouveau/core/engine/falcon.c b/drivers/gpu/drm/nouveau/core/engine/falcon.c index e03fc8e4dc1d..5e077e4ed7f6 100644 --- a/drivers/gpu/drm/nouveau/core/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/core/engine/falcon.c | |||
| @@ -56,6 +56,16 @@ _nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data) | |||
| 56 | nv_wr32(falcon, falcon->addr + addr, data); | 56 | nv_wr32(falcon, falcon->addr + addr, data); |
| 57 | } | 57 | } |
| 58 | 58 | ||
| 59 | static void * | ||
| 60 | vmemdup(const void *src, size_t len) | ||
| 61 | { | ||
| 62 | void *p = vmalloc(len); | ||
| 63 | |||
| 64 | if (p) | ||
| 65 | memcpy(p, src, len); | ||
| 66 | return p; | ||
| 67 | } | ||
| 68 | |||
| 59 | int | 69 | int |
| 60 | _nouveau_falcon_init(struct nouveau_object *object) | 70 | _nouveau_falcon_init(struct nouveau_object *object) |
| 61 | { | 71 | { |
| @@ -111,7 +121,7 @@ _nouveau_falcon_init(struct nouveau_object *object) | |||
| 111 | 121 | ||
| 112 | ret = request_firmware(&fw, name, &device->pdev->dev); | 122 | ret = request_firmware(&fw, name, &device->pdev->dev); |
| 113 | if (ret == 0) { | 123 | if (ret == 0) { |
| 114 | falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL); | 124 | falcon->code.data = vmemdup(fw->data, fw->size); |
| 115 | falcon->code.size = fw->size; | 125 | falcon->code.size = fw->size; |
| 116 | falcon->data.data = NULL; | 126 | falcon->data.data = NULL; |
| 117 | falcon->data.size = 0; | 127 | falcon->data.size = 0; |
| @@ -134,7 +144,7 @@ _nouveau_falcon_init(struct nouveau_object *object) | |||
| 134 | return ret; | 144 | return ret; |
| 135 | } | 145 | } |
| 136 | 146 | ||
| 137 | falcon->data.data = kmemdup(fw->data, fw->size, GFP_KERNEL); | 147 | falcon->data.data = vmemdup(fw->data, fw->size); |
| 138 | falcon->data.size = fw->size; | 148 | falcon->data.size = fw->size; |
| 139 | release_firmware(fw); | 149 | release_firmware(fw); |
| 140 | if (!falcon->data.data) | 150 | if (!falcon->data.data) |
| @@ -149,7 +159,7 @@ _nouveau_falcon_init(struct nouveau_object *object) | |||
| 149 | return ret; | 159 | return ret; |
| 150 | } | 160 | } |
| 151 | 161 | ||
| 152 | falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL); | 162 | falcon->code.data = vmemdup(fw->data, fw->size); |
| 153 | falcon->code.size = fw->size; | 163 | falcon->code.size = fw->size; |
| 154 | release_firmware(fw); | 164 | release_firmware(fw); |
| 155 | if (!falcon->code.data) | 165 | if (!falcon->code.data) |
| @@ -235,8 +245,8 @@ _nouveau_falcon_fini(struct nouveau_object *object, bool suspend) | |||
| 235 | if (!suspend) { | 245 | if (!suspend) { |
| 236 | nouveau_gpuobj_ref(NULL, &falcon->core); | 246 | nouveau_gpuobj_ref(NULL, &falcon->core); |
| 237 | if (falcon->external) { | 247 | if (falcon->external) { |
| 238 | kfree(falcon->data.data); | 248 | vfree(falcon->data.data); |
| 239 | kfree(falcon->code.data); | 249 | vfree(falcon->code.data); |
| 240 | falcon->code.data = NULL; | 250 | falcon->code.data = NULL; |
| 241 | } | 251 | } |
| 242 | } | 252 | } |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c new file mode 100644 index 000000000000..09362a51ba57 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include "nve0.h" | ||
| 26 | |||
| 27 | struct nouveau_oclass * | ||
| 28 | nv108_fifo_oclass = &(struct nve0_fifo_impl) { | ||
| 29 | .base.handle = NV_ENGINE(FIFO, 0x08), | ||
| 30 | .base.ofuncs = &(struct nouveau_ofuncs) { | ||
| 31 | .ctor = nve0_fifo_ctor, | ||
| 32 | .dtor = nve0_fifo_dtor, | ||
| 33 | .init = nve0_fifo_init, | ||
| 34 | .fini = _nouveau_fifo_fini, | ||
| 35 | }, | ||
| 36 | .channels = 1024, | ||
| 37 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c index 9ac94d4e5646..b22a33f0702d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | 33 | ||
| 34 | #include <subdev/timer.h> | 34 | #include <subdev/timer.h> |
| 35 | #include <subdev/bar.h> | 35 | #include <subdev/bar.h> |
| 36 | #include <subdev/fb.h> | ||
| 36 | #include <subdev/vm.h> | 37 | #include <subdev/vm.h> |
| 37 | 38 | ||
| 38 | #include <engine/dmaobj.h> | 39 | #include <engine/dmaobj.h> |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c index 04f412922d2d..9a850fe19515 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c | |||
| @@ -33,10 +33,12 @@ | |||
| 33 | 33 | ||
| 34 | #include <subdev/timer.h> | 34 | #include <subdev/timer.h> |
| 35 | #include <subdev/bar.h> | 35 | #include <subdev/bar.h> |
| 36 | #include <subdev/fb.h> | ||
| 36 | #include <subdev/vm.h> | 37 | #include <subdev/vm.h> |
| 37 | 38 | ||
| 38 | #include <engine/dmaobj.h> | 39 | #include <engine/dmaobj.h> |
| 39 | #include <engine/fifo.h> | 40 | |
| 41 | #include "nve0.h" | ||
| 40 | 42 | ||
| 41 | #define _(a,b) { (a), ((1ULL << (a)) | (b)) } | 43 | #define _(a,b) { (a), ((1ULL << (a)) | (b)) } |
| 42 | static const struct { | 44 | static const struct { |
| @@ -56,8 +58,8 @@ static const struct { | |||
| 56 | #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) | 58 | #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) |
| 57 | 59 | ||
| 58 | struct nve0_fifo_engn { | 60 | struct nve0_fifo_engn { |
| 59 | struct nouveau_gpuobj *playlist[2]; | 61 | struct nouveau_gpuobj *runlist[2]; |
| 60 | int cur_playlist; | 62 | int cur_runlist; |
| 61 | }; | 63 | }; |
| 62 | 64 | ||
| 63 | struct nve0_fifo_priv { | 65 | struct nve0_fifo_priv { |
| @@ -86,7 +88,7 @@ struct nve0_fifo_chan { | |||
| 86 | ******************************************************************************/ | 88 | ******************************************************************************/ |
| 87 | 89 | ||
| 88 | static void | 90 | static void |
| 89 | nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine) | 91 | nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine) |
| 90 | { | 92 | { |
| 91 | struct nouveau_bar *bar = nouveau_bar(priv); | 93 | struct nouveau_bar *bar = nouveau_bar(priv); |
| 92 | struct nve0_fifo_engn *engn = &priv->engine[engine]; | 94 | struct nve0_fifo_engn *engn = &priv->engine[engine]; |
| @@ -95,8 +97,8 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine) | |||
| 95 | int i, p; | 97 | int i, p; |
| 96 | 98 | ||
| 97 | mutex_lock(&nv_subdev(priv)->mutex); | 99 | mutex_lock(&nv_subdev(priv)->mutex); |
| 98 | cur = engn->playlist[engn->cur_playlist]; | 100 | cur = engn->runlist[engn->cur_runlist]; |
| 99 | engn->cur_playlist = !engn->cur_playlist; | 101 | engn->cur_runlist = !engn->cur_runlist; |
| 100 | 102 | ||
| 101 | for (i = 0, p = 0; i < priv->base.max; i++) { | 103 | for (i = 0, p = 0; i < priv->base.max; i++) { |
| 102 | u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001; | 104 | u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001; |
| @@ -111,7 +113,7 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine) | |||
| 111 | nv_wr32(priv, 0x002270, cur->addr >> 12); | 113 | nv_wr32(priv, 0x002270, cur->addr >> 12); |
| 112 | nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); | 114 | nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); |
| 113 | if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000)) | 115 | if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000)) |
| 114 | nv_error(priv, "playlist %d update timeout\n", engine); | 116 | nv_error(priv, "runlist %d update timeout\n", engine); |
| 115 | mutex_unlock(&nv_subdev(priv)->mutex); | 117 | mutex_unlock(&nv_subdev(priv)->mutex); |
| 116 | } | 118 | } |
| 117 | 119 | ||
| @@ -278,7 +280,7 @@ nve0_fifo_chan_init(struct nouveau_object *object) | |||
| 278 | nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); | 280 | nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); |
| 279 | nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); | 281 | nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); |
| 280 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); | 282 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); |
| 281 | nve0_fifo_playlist_update(priv, chan->engine); | 283 | nve0_fifo_runlist_update(priv, chan->engine); |
| 282 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); | 284 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); |
| 283 | return 0; | 285 | return 0; |
| 284 | } | 286 | } |
| @@ -291,7 +293,7 @@ nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend) | |||
| 291 | u32 chid = chan->base.chid; | 293 | u32 chid = chan->base.chid; |
| 292 | 294 | ||
| 293 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); | 295 | nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); |
| 294 | nve0_fifo_playlist_update(priv, chan->engine); | 296 | nve0_fifo_runlist_update(priv, chan->engine); |
| 295 | nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); | 297 | nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); |
| 296 | 298 | ||
| 297 | return nouveau_fifo_channel_fini(&chan->base, suspend); | 299 | return nouveau_fifo_channel_fini(&chan->base, suspend); |
| @@ -375,54 +377,189 @@ nve0_fifo_cclass = { | |||
| 375 | * PFIFO engine | 377 | * PFIFO engine |
| 376 | ******************************************************************************/ | 378 | ******************************************************************************/ |
| 377 | 379 | ||
| 378 | static const struct nouveau_enum nve0_fifo_fault_unit[] = { | 380 | static const struct nouveau_enum nve0_fifo_sched_reason[] = { |
| 381 | { 0x0a, "CTXSW_TIMEOUT" }, | ||
| 382 | {} | ||
| 383 | }; | ||
| 384 | |||
| 385 | static const struct nouveau_enum nve0_fifo_fault_engine[] = { | ||
| 386 | { 0x00, "GR", NULL, NVDEV_ENGINE_GR }, | ||
| 387 | { 0x03, "IFB" }, | ||
| 388 | { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, | ||
| 389 | { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, | ||
| 390 | { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO }, | ||
| 391 | { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, | ||
| 392 | { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, | ||
| 393 | { 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP }, | ||
| 394 | { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP }, | ||
| 395 | { 0x13, "PERF" }, | ||
| 396 | { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP }, | ||
| 397 | { 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 }, | ||
| 398 | { 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 }, | ||
| 399 | { 0x17, "PMU" }, | ||
| 400 | { 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC }, | ||
| 401 | { 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 }, | ||
| 379 | {} | 402 | {} |
| 380 | }; | 403 | }; |
| 381 | 404 | ||
| 382 | static const struct nouveau_enum nve0_fifo_fault_reason[] = { | 405 | static const struct nouveau_enum nve0_fifo_fault_reason[] = { |
| 383 | { 0x00, "PT_NOT_PRESENT" }, | 406 | { 0x00, "PDE" }, |
| 384 | { 0x01, "PT_TOO_SHORT" }, | 407 | { 0x01, "PDE_SIZE" }, |
| 385 | { 0x02, "PAGE_NOT_PRESENT" }, | 408 | { 0x02, "PTE" }, |
| 386 | { 0x03, "VM_LIMIT_EXCEEDED" }, | 409 | { 0x03, "VA_LIMIT_VIOLATION" }, |
| 387 | { 0x04, "NO_CHANNEL" }, | 410 | { 0x04, "UNBOUND_INST_BLOCK" }, |
| 388 | { 0x05, "PAGE_SYSTEM_ONLY" }, | 411 | { 0x05, "PRIV_VIOLATION" }, |
| 389 | { 0x06, "PAGE_READ_ONLY" }, | 412 | { 0x06, "RO_VIOLATION" }, |
| 390 | { 0x0a, "COMPRESSED_SYSRAM" }, | 413 | { 0x07, "WO_VIOLATION" }, |
| 391 | { 0x0c, "INVALID_STORAGE_TYPE" }, | 414 | { 0x08, "PITCH_MASK_VIOLATION" }, |
| 415 | { 0x09, "WORK_CREATION" }, | ||
| 416 | { 0x0a, "UNSUPPORTED_APERTURE" }, | ||
| 417 | { 0x0b, "COMPRESSION_FAILURE" }, | ||
| 418 | { 0x0c, "UNSUPPORTED_KIND" }, | ||
| 419 | { 0x0d, "REGION_VIOLATION" }, | ||
| 420 | { 0x0e, "BOTH_PTES_VALID" }, | ||
| 421 | { 0x0f, "INFO_TYPE_POISONED" }, | ||
| 392 | {} | 422 | {} |
| 393 | }; | 423 | }; |
| 394 | 424 | ||
| 395 | static const struct nouveau_enum nve0_fifo_fault_hubclient[] = { | 425 | static const struct nouveau_enum nve0_fifo_fault_hubclient[] = { |
| 426 | { 0x00, "VIP" }, | ||
| 427 | { 0x01, "CE0" }, | ||
| 428 | { 0x02, "CE1" }, | ||
| 429 | { 0x03, "DNISO" }, | ||
| 430 | { 0x04, "FE" }, | ||
| 431 | { 0x05, "FECS" }, | ||
| 432 | { 0x06, "HOST" }, | ||
| 433 | { 0x07, "HOST_CPU" }, | ||
| 434 | { 0x08, "HOST_CPU_NB" }, | ||
| 435 | { 0x09, "ISO" }, | ||
| 436 | { 0x0a, "MMU" }, | ||
| 437 | { 0x0b, "MSPDEC" }, | ||
| 438 | { 0x0c, "MSPPP" }, | ||
| 439 | { 0x0d, "MSVLD" }, | ||
| 440 | { 0x0e, "NISO" }, | ||
| 441 | { 0x0f, "P2P" }, | ||
| 442 | { 0x10, "PD" }, | ||
| 443 | { 0x11, "PERF" }, | ||
| 444 | { 0x12, "PMU" }, | ||
| 445 | { 0x13, "RASTERTWOD" }, | ||
| 446 | { 0x14, "SCC" }, | ||
| 447 | { 0x15, "SCC_NB" }, | ||
| 448 | { 0x16, "SEC" }, | ||
| 449 | { 0x17, "SSYNC" }, | ||
| 450 | { 0x18, "GR_COPY" }, | ||
| 451 | { 0x19, "CE2" }, | ||
| 452 | { 0x1a, "XV" }, | ||
| 453 | { 0x1b, "MMU_NB" }, | ||
| 454 | { 0x1c, "MSENC" }, | ||
| 455 | { 0x1d, "DFALCON" }, | ||
| 456 | { 0x1e, "SKED" }, | ||
| 457 | { 0x1f, "AFALCON" }, | ||
| 396 | {} | 458 | {} |
| 397 | }; | 459 | }; |
| 398 | 460 | ||
| 399 | static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = { | 461 | static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = { |
| 462 | { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, | ||
| 463 | { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, | ||
| 464 | { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, | ||
| 465 | { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" }, | ||
| 466 | { 0x0c, "RAST" }, | ||
| 467 | { 0x0d, "GCC" }, | ||
| 468 | { 0x0e, "GPCCS" }, | ||
| 469 | { 0x0f, "PROP_0" }, | ||
| 470 | { 0x10, "PROP_1" }, | ||
| 471 | { 0x11, "PROP_2" }, | ||
| 472 | { 0x12, "PROP_3" }, | ||
| 473 | { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" }, | ||
| 474 | { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" }, | ||
| 475 | { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" }, | ||
| 476 | { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" }, | ||
| 477 | { 0x1f, "GPM" }, | ||
| 478 | { 0x20, "LTP_UTLB_0" }, | ||
| 479 | { 0x21, "LTP_UTLB_1" }, | ||
| 480 | { 0x22, "LTP_UTLB_2" }, | ||
| 481 | { 0x23, "LTP_UTLB_3" }, | ||
| 482 | { 0x24, "GPC_RGG_UTLB" }, | ||
| 400 | {} | 483 | {} |
| 401 | }; | 484 | }; |
| 402 | 485 | ||
| 403 | static const struct nouveau_bitfield nve0_fifo_subfifo_intr[] = { | 486 | static const struct nouveau_bitfield nve0_fifo_pbdma_intr[] = { |
| 404 | { 0x00200000, "ILLEGAL_MTHD" }, | 487 | { 0x00000001, "MEMREQ" }, |
| 405 | { 0x00800000, "EMPTY_SUBC" }, | 488 | { 0x00000002, "MEMACK_TIMEOUT" }, |
| 489 | { 0x00000004, "MEMACK_EXTRA" }, | ||
| 490 | { 0x00000008, "MEMDAT_TIMEOUT" }, | ||
| 491 | { 0x00000010, "MEMDAT_EXTRA" }, | ||
| 492 | { 0x00000020, "MEMFLUSH" }, | ||
| 493 | { 0x00000040, "MEMOP" }, | ||
| 494 | { 0x00000080, "LBCONNECT" }, | ||
| 495 | { 0x00000100, "LBREQ" }, | ||
| 496 | { 0x00000200, "LBACK_TIMEOUT" }, | ||
| 497 | { 0x00000400, "LBACK_EXTRA" }, | ||
| 498 | { 0x00000800, "LBDAT_TIMEOUT" }, | ||
| 499 | { 0x00001000, "LBDAT_EXTRA" }, | ||
| 500 | { 0x00002000, "GPFIFO" }, | ||
| 501 | { 0x00004000, "GPPTR" }, | ||
| 502 | { 0x00008000, "GPENTRY" }, | ||
| 503 | { 0x00010000, "GPCRC" }, | ||
| 504 | { 0x00020000, "PBPTR" }, | ||
| 505 | { 0x00040000, "PBENTRY" }, | ||
| 506 | { 0x00080000, "PBCRC" }, | ||
| 507 | { 0x00100000, "XBARCONNECT" }, | ||
| 508 | { 0x00200000, "METHOD" }, | ||
| 509 | { 0x00400000, "METHODCRC" }, | ||
| 510 | { 0x00800000, "DEVICE" }, | ||
| 511 | { 0x02000000, "SEMAPHORE" }, | ||
| 512 | { 0x04000000, "ACQUIRE" }, | ||
| 513 | { 0x08000000, "PRI" }, | ||
| 514 | { 0x20000000, "NO_CTXSW_SEG" }, | ||
| 515 | { 0x40000000, "PBSEG" }, | ||
| 516 | { 0x80000000, "SIGNATURE" }, | ||
| 406 | {} | 517 | {} |
| 407 | }; | 518 | }; |
| 408 | 519 | ||
| 409 | static void | 520 | static void |
| 410 | nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit) | 521 | nve0_fifo_intr_sched(struct nve0_fifo_priv *priv) |
| 522 | { | ||
| 523 | u32 intr = nv_rd32(priv, 0x00254c); | ||
| 524 | u32 code = intr & 0x000000ff; | ||
| 525 | nv_error(priv, "SCHED_ERROR ["); | ||
| 526 | nouveau_enum_print(nve0_fifo_sched_reason, code); | ||
| 527 | pr_cont("]\n"); | ||
| 528 | } | ||
| 529 | |||
| 530 | static void | ||
| 531 | nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv) | ||
| 532 | { | ||
| 533 | u32 stat = nv_rd32(priv, 0x00256c); | ||
| 534 | nv_error(priv, "CHSW_ERROR 0x%08x\n", stat); | ||
| 535 | nv_wr32(priv, 0x00256c, stat); | ||
| 536 | } | ||
| 537 | |||
| 538 | static void | ||
| 539 | nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv) | ||
| 540 | { | ||
| 541 | u32 stat = nv_rd32(priv, 0x00259c); | ||
| 542 | nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat); | ||
| 543 | } | ||
| 544 | |||
| 545 | static void | ||
| 546 | nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) | ||
| 411 | { | 547 | { |
| 412 | u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10)); | 548 | u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10)); |
| 413 | u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10)); | 549 | u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10)); |
| 414 | u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10)); | 550 | u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10)); |
| 415 | u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10)); | 551 | u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10)); |
| 416 | u32 client = (stat & 0x00001f00) >> 8; | 552 | u32 client = (stat & 0x00001f00) >> 8; |
| 417 | const struct nouveau_enum *en; | 553 | struct nouveau_engine *engine = NULL; |
| 418 | struct nouveau_engine *engine; | ||
| 419 | struct nouveau_object *engctx = NULL; | 554 | struct nouveau_object *engctx = NULL; |
| 555 | const struct nouveau_enum *en; | ||
| 556 | const char *name = "unknown"; | ||
| 420 | 557 | ||
| 421 | nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ? | 558 | nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ? |
| 422 | "write" : "read", (u64)vahi << 32 | valo); | 559 | "write" : "read", (u64)vahi << 32 | valo); |
| 423 | nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f); | 560 | nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f); |
| 424 | pr_cont("] from "); | 561 | pr_cont("] from "); |
| 425 | en = nouveau_enum_print(nve0_fifo_fault_unit, unit); | 562 | en = nouveau_enum_print(nve0_fifo_fault_engine, unit); |
| 426 | if (stat & 0x00000040) { | 563 | if (stat & 0x00000040) { |
| 427 | pr_cont("/"); | 564 | pr_cont("/"); |
| 428 | nouveau_enum_print(nve0_fifo_fault_hubclient, client); | 565 | nouveau_enum_print(nve0_fifo_fault_hubclient, client); |
| @@ -432,14 +569,22 @@ nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit) | |||
| 432 | } | 569 | } |
| 433 | 570 | ||
| 434 | if (en && en->data2) { | 571 | if (en && en->data2) { |
| 435 | engine = nouveau_engine(priv, en->data2); | 572 | if (en->data2 == NVDEV_SUBDEV_BAR) { |
| 436 | if (engine) | 573 | nv_mask(priv, 0x001704, 0x00000000, 0x00000000); |
| 437 | engctx = nouveau_engctx_get(engine, inst); | 574 | name = "BAR1"; |
| 438 | 575 | } else | |
| 576 | if (en->data2 == NVDEV_SUBDEV_INSTMEM) { | ||
| 577 | nv_mask(priv, 0x001714, 0x00000000, 0x00000000); | ||
| 578 | name = "BAR3"; | ||
| 579 | } else { | ||
| 580 | engine = nouveau_engine(priv, en->data2); | ||
| 581 | if (engine) { | ||
| 582 | engctx = nouveau_engctx_get(engine, inst); | ||
| 583 | name = nouveau_client_name(engctx); | ||
| 584 | } | ||
| 585 | } | ||
| 439 | } | 586 | } |
| 440 | 587 | pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, name); | |
| 441 | pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12, | ||
| 442 | nouveau_client_name(engctx)); | ||
| 443 | 588 | ||
| 444 | nouveau_engctx_put(engctx); | 589 | nouveau_engctx_put(engctx); |
| 445 | } | 590 | } |
| @@ -471,7 +616,7 @@ out: | |||
| 471 | } | 616 | } |
| 472 | 617 | ||
| 473 | static void | 618 | static void |
| 474 | nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit) | 619 | nve0_fifo_intr_pbdma(struct nve0_fifo_priv *priv, int unit) |
| 475 | { | 620 | { |
| 476 | u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); | 621 | u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); |
| 477 | u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); | 622 | u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); |
| @@ -487,11 +632,11 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit) | |||
| 487 | } | 632 | } |
| 488 | 633 | ||
| 489 | if (show) { | 634 | if (show) { |
| 490 | nv_error(priv, "SUBFIFO%d:", unit); | 635 | nv_error(priv, "PBDMA%d:", unit); |
| 491 | nouveau_bitfield_print(nve0_fifo_subfifo_intr, show); | 636 | nouveau_bitfield_print(nve0_fifo_pbdma_intr, show); |
| 492 | pr_cont("\n"); | 637 | pr_cont("\n"); |
| 493 | nv_error(priv, | 638 | nv_error(priv, |
| 494 | "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", | 639 | "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", |
| 495 | unit, chid, | 640 | unit, chid, |
| 496 | nouveau_client_name_for_fifo_chid(&priv->base, chid), | 641 | nouveau_client_name_for_fifo_chid(&priv->base, chid), |
| 497 | subc, mthd, data); | 642 | subc, mthd, data); |
| @@ -508,19 +653,56 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) | |||
| 508 | u32 mask = nv_rd32(priv, 0x002140); | 653 | u32 mask = nv_rd32(priv, 0x002140); |
| 509 | u32 stat = nv_rd32(priv, 0x002100) & mask; | 654 | u32 stat = nv_rd32(priv, 0x002100) & mask; |
| 510 | 655 | ||
| 656 | if (stat & 0x00000001) { | ||
| 657 | u32 stat = nv_rd32(priv, 0x00252c); | ||
| 658 | nv_error(priv, "BIND_ERROR 0x%08x\n", stat); | ||
| 659 | nv_wr32(priv, 0x002100, 0x00000001); | ||
| 660 | stat &= ~0x00000001; | ||
| 661 | } | ||
| 662 | |||
| 663 | if (stat & 0x00000010) { | ||
| 664 | nv_error(priv, "PIO_ERROR\n"); | ||
| 665 | nv_wr32(priv, 0x002100, 0x00000010); | ||
| 666 | stat &= ~0x00000010; | ||
| 667 | } | ||
| 668 | |||
| 511 | if (stat & 0x00000100) { | 669 | if (stat & 0x00000100) { |
| 512 | nv_warn(priv, "unknown status 0x00000100\n"); | 670 | nve0_fifo_intr_sched(priv); |
| 513 | nv_wr32(priv, 0x002100, 0x00000100); | 671 | nv_wr32(priv, 0x002100, 0x00000100); |
| 514 | stat &= ~0x00000100; | 672 | stat &= ~0x00000100; |
| 515 | } | 673 | } |
| 516 | 674 | ||
| 675 | if (stat & 0x00010000) { | ||
| 676 | nve0_fifo_intr_chsw(priv); | ||
| 677 | nv_wr32(priv, 0x002100, 0x00010000); | ||
| 678 | stat &= ~0x00010000; | ||
| 679 | } | ||
| 680 | |||
| 681 | if (stat & 0x00800000) { | ||
| 682 | nv_error(priv, "FB_FLUSH_TIMEOUT\n"); | ||
| 683 | nv_wr32(priv, 0x002100, 0x00800000); | ||
| 684 | stat &= ~0x00800000; | ||
| 685 | } | ||
| 686 | |||
| 687 | if (stat & 0x01000000) { | ||
| 688 | nv_error(priv, "LB_ERROR\n"); | ||
| 689 | nv_wr32(priv, 0x002100, 0x01000000); | ||
| 690 | stat &= ~0x01000000; | ||
| 691 | } | ||
| 692 | |||
| 693 | if (stat & 0x08000000) { | ||
| 694 | nve0_fifo_intr_dropped_fault(priv); | ||
| 695 | nv_wr32(priv, 0x002100, 0x08000000); | ||
| 696 | stat &= ~0x08000000; | ||
| 697 | } | ||
| 698 | |||
| 517 | if (stat & 0x10000000) { | 699 | if (stat & 0x10000000) { |
| 518 | u32 units = nv_rd32(priv, 0x00259c); | 700 | u32 units = nv_rd32(priv, 0x00259c); |
| 519 | u32 u = units; | 701 | u32 u = units; |
| 520 | 702 | ||
| 521 | while (u) { | 703 | while (u) { |
| 522 | int i = ffs(u) - 1; | 704 | int i = ffs(u) - 1; |
| 523 | nve0_fifo_isr_vm_fault(priv, i); | 705 | nve0_fifo_intr_fault(priv, i); |
| 524 | u &= ~(1 << i); | 706 | u &= ~(1 << i); |
| 525 | } | 707 | } |
| 526 | 708 | ||
| @@ -529,22 +711,28 @@ nve0_fifo_intr(struct nouveau_subdev *subdev) | |||
| 529 | } | 711 | } |
| 530 | 712 | ||
| 531 | if (stat & 0x20000000) { | 713 | if (stat & 0x20000000) { |
| 532 | u32 units = nv_rd32(priv, 0x0025a0); | 714 | u32 mask = nv_rd32(priv, 0x0025a0); |
| 533 | u32 u = units; | 715 | u32 temp = mask; |
| 534 | 716 | ||
| 535 | while (u) { | 717 | while (temp) { |
| 536 | int i = ffs(u) - 1; | 718 | u32 unit = ffs(temp) - 1; |
| 537 | nve0_fifo_isr_subfifo_intr(priv, i); | 719 | nve0_fifo_intr_pbdma(priv, unit); |
| 538 | u &= ~(1 << i); | 720 | temp &= ~(1 << unit); |
| 539 | } | 721 | } |
| 540 | 722 | ||
| 541 | nv_wr32(priv, 0x0025a0, units); | 723 | nv_wr32(priv, 0x0025a0, mask); |
| 542 | stat &= ~0x20000000; | 724 | stat &= ~0x20000000; |
| 543 | } | 725 | } |
| 544 | 726 | ||
| 545 | if (stat & 0x40000000) { | 727 | if (stat & 0x40000000) { |
| 546 | nv_warn(priv, "unknown status 0x40000000\n"); | 728 | u32 mask = nv_mask(priv, 0x002a00, 0x00000000, 0x00000000); |
| 547 | nv_mask(priv, 0x002a00, 0x00000000, 0x00000000); | 729 | |
| 730 | while (mask) { | ||
| 731 | u32 engn = ffs(mask) - 1; | ||
| 732 | /* runlist event, not currently used */ | ||
| 733 | mask &= ~(1 << engn); | ||
| 734 | } | ||
| 735 | |||
| 548 | stat &= ~0x40000000; | 736 | stat &= ~0x40000000; |
| 549 | } | 737 | } |
| 550 | 738 | ||
| @@ -575,53 +763,52 @@ nve0_fifo_uevent_disable(struct nouveau_event *event, int index) | |||
| 575 | nv_mask(priv, 0x002140, 0x80000000, 0x00000000); | 763 | nv_mask(priv, 0x002140, 0x80000000, 0x00000000); |
| 576 | } | 764 | } |
| 577 | 765 | ||
| 578 | static int | 766 | int |
| 579 | nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 767 | nve0_fifo_fini(struct nouveau_object *object, bool suspend) |
| 580 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
| 581 | struct nouveau_object **pobject) | ||
| 582 | { | 768 | { |
| 583 | struct nve0_fifo_priv *priv; | 769 | struct nve0_fifo_priv *priv = (void *)object; |
| 584 | int ret, i; | 770 | int ret; |
| 585 | 771 | ||
| 586 | ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv); | 772 | ret = nouveau_fifo_fini(&priv->base, suspend); |
| 587 | *pobject = nv_object(priv); | ||
| 588 | if (ret) | 773 | if (ret) |
| 589 | return ret; | 774 | return ret; |
| 590 | 775 | ||
| 591 | for (i = 0; i < FIFO_ENGINE_NR; i++) { | 776 | /* allow mmu fault interrupts, even when we're not using fifo */ |
| 592 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, | 777 | nv_mask(priv, 0x002140, 0x10000000, 0x10000000); |
| 593 | 0, &priv->engine[i].playlist[0]); | 778 | return 0; |
| 594 | if (ret) | 779 | } |
| 595 | return ret; | ||
| 596 | 780 | ||
| 597 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, | 781 | int |
| 598 | 0, &priv->engine[i].playlist[1]); | 782 | nve0_fifo_init(struct nouveau_object *object) |
| 599 | if (ret) | 783 | { |
| 600 | return ret; | 784 | struct nve0_fifo_priv *priv = (void *)object; |
| 601 | } | 785 | int ret, i; |
| 602 | 786 | ||
| 603 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 4096 * 0x200, 0x1000, | 787 | ret = nouveau_fifo_init(&priv->base); |
| 604 | NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); | ||
| 605 | if (ret) | 788 | if (ret) |
| 606 | return ret; | 789 | return ret; |
| 607 | 790 | ||
| 608 | ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, | 791 | /* enable all available PBDMA units */ |
| 609 | &priv->user.bar); | 792 | nv_wr32(priv, 0x000204, 0xffffffff); |
| 610 | if (ret) | 793 | priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204)); |
| 611 | return ret; | 794 | nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr); |
| 612 | 795 | ||
| 613 | priv->base.uevent->enable = nve0_fifo_uevent_enable; | 796 | /* PBDMA[n] */ |
| 614 | priv->base.uevent->disable = nve0_fifo_uevent_disable; | 797 | for (i = 0; i < priv->spoon_nr; i++) { |
| 615 | priv->base.uevent->priv = priv; | 798 | nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 799 | nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ | ||
| 800 | nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ | ||
| 801 | } | ||
| 616 | 802 | ||
| 617 | nv_subdev(priv)->unit = 0x00000100; | 803 | nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); |
| 618 | nv_subdev(priv)->intr = nve0_fifo_intr; | 804 | |
| 619 | nv_engine(priv)->cclass = &nve0_fifo_cclass; | 805 | nv_wr32(priv, 0x002a00, 0xffffffff); |
| 620 | nv_engine(priv)->sclass = nve0_fifo_sclass; | 806 | nv_wr32(priv, 0x002100, 0xffffffff); |
| 807 | nv_wr32(priv, 0x002140, 0x3fffffff); | ||
| 621 | return 0; | 808 | return 0; |
| 622 | } | 809 | } |
| 623 | 810 | ||
| 624 | static void | 811 | void |
| 625 | nve0_fifo_dtor(struct nouveau_object *object) | 812 | nve0_fifo_dtor(struct nouveau_object *object) |
| 626 | { | 813 | { |
| 627 | struct nve0_fifo_priv *priv = (void *)object; | 814 | struct nve0_fifo_priv *priv = (void *)object; |
| @@ -631,50 +818,69 @@ nve0_fifo_dtor(struct nouveau_object *object) | |||
| 631 | nouveau_gpuobj_ref(NULL, &priv->user.mem); | 818 | nouveau_gpuobj_ref(NULL, &priv->user.mem); |
| 632 | 819 | ||
| 633 | for (i = 0; i < FIFO_ENGINE_NR; i++) { | 820 | for (i = 0; i < FIFO_ENGINE_NR; i++) { |
| 634 | nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]); | 821 | nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[1]); |
| 635 | nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]); | 822 | nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[0]); |
| 636 | } | 823 | } |
| 637 | 824 | ||
| 638 | nouveau_fifo_destroy(&priv->base); | 825 | nouveau_fifo_destroy(&priv->base); |
| 639 | } | 826 | } |
| 640 | 827 | ||
| 641 | static int | 828 | int |
| 642 | nve0_fifo_init(struct nouveau_object *object) | 829 | nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 830 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
| 831 | struct nouveau_object **pobject) | ||
| 643 | { | 832 | { |
| 644 | struct nve0_fifo_priv *priv = (void *)object; | 833 | struct nve0_fifo_impl *impl = (void *)oclass; |
| 834 | struct nve0_fifo_priv *priv; | ||
| 645 | int ret, i; | 835 | int ret, i; |
| 646 | 836 | ||
| 647 | ret = nouveau_fifo_init(&priv->base); | 837 | ret = nouveau_fifo_create(parent, engine, oclass, 0, |
| 838 | impl->channels - 1, &priv); | ||
| 839 | *pobject = nv_object(priv); | ||
| 648 | if (ret) | 840 | if (ret) |
| 649 | return ret; | 841 | return ret; |
| 650 | 842 | ||
| 651 | /* enable all available PSUBFIFOs */ | 843 | for (i = 0; i < FIFO_ENGINE_NR; i++) { |
| 652 | nv_wr32(priv, 0x000204, 0xffffffff); | 844 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, |
| 653 | priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204)); | 845 | 0, &priv->engine[i].runlist[0]); |
| 654 | nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr); | 846 | if (ret) |
| 847 | return ret; | ||
| 655 | 848 | ||
| 656 | /* PSUBFIFO[n] */ | 849 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, |
| 657 | for (i = 0; i < priv->spoon_nr; i++) { | 850 | 0, &priv->engine[i].runlist[1]); |
| 658 | nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); | 851 | if (ret) |
| 659 | nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ | 852 | return ret; |
| 660 | nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ | ||
| 661 | } | 853 | } |
| 662 | 854 | ||
| 663 | nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); | 855 | ret = nouveau_gpuobj_new(nv_object(priv), NULL, 4096 * 0x200, 0x1000, |
| 856 | NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); | ||
| 857 | if (ret) | ||
| 858 | return ret; | ||
| 664 | 859 | ||
| 665 | nv_wr32(priv, 0x002a00, 0xffffffff); | 860 | ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, |
| 666 | nv_wr32(priv, 0x002100, 0xffffffff); | 861 | &priv->user.bar); |
| 667 | nv_wr32(priv, 0x002140, 0x3fffffff); | 862 | if (ret) |
| 863 | return ret; | ||
| 864 | |||
| 865 | priv->base.uevent->enable = nve0_fifo_uevent_enable; | ||
| 866 | priv->base.uevent->disable = nve0_fifo_uevent_disable; | ||
| 867 | priv->base.uevent->priv = priv; | ||
| 868 | |||
| 869 | nv_subdev(priv)->unit = 0x00000100; | ||
| 870 | nv_subdev(priv)->intr = nve0_fifo_intr; | ||
| 871 | nv_engine(priv)->cclass = &nve0_fifo_cclass; | ||
| 872 | nv_engine(priv)->sclass = nve0_fifo_sclass; | ||
| 668 | return 0; | 873 | return 0; |
| 669 | } | 874 | } |
| 670 | 875 | ||
| 671 | struct nouveau_oclass * | 876 | struct nouveau_oclass * |
| 672 | nve0_fifo_oclass = &(struct nouveau_oclass) { | 877 | nve0_fifo_oclass = &(struct nve0_fifo_impl) { |
| 673 | .handle = NV_ENGINE(FIFO, 0xe0), | 878 | .base.handle = NV_ENGINE(FIFO, 0xe0), |
| 674 | .ofuncs = &(struct nouveau_ofuncs) { | 879 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 675 | .ctor = nve0_fifo_ctor, | 880 | .ctor = nve0_fifo_ctor, |
| 676 | .dtor = nve0_fifo_dtor, | 881 | .dtor = nve0_fifo_dtor, |
| 677 | .init = nve0_fifo_init, | 882 | .init = nve0_fifo_init, |
| 678 | .fini = _nouveau_fifo_fini, | 883 | .fini = nve0_fifo_fini, |
| 679 | }, | 884 | }, |
| 680 | }; | 885 | .channels = 4096, |
| 886 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h new file mode 100644 index 000000000000..014344ebee66 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | #ifndef __NVKM_FIFO_NVE0_H__ | ||
| 2 | #define __NVKM_FIFO_NVE0_H__ | ||
| 3 | |||
| 4 | #include <engine/fifo.h> | ||
| 5 | |||
| 6 | int nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *, | ||
| 7 | struct nouveau_oclass *, void *, u32, | ||
| 8 | struct nouveau_object **); | ||
| 9 | void nve0_fifo_dtor(struct nouveau_object *); | ||
| 10 | int nve0_fifo_init(struct nouveau_object *); | ||
| 11 | |||
| 12 | struct nve0_fifo_impl { | ||
| 13 | struct nouveau_oclass base; | ||
| 14 | u32 channels; | ||
| 15 | }; | ||
| 16 | |||
| 17 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c new file mode 100644 index 000000000000..a86bd3352bf8 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c | |||
| @@ -0,0 +1,1408 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include "nvc0.h" | ||
| 26 | |||
| 27 | static struct nvc0_graph_init | ||
| 28 | nv108_grctx_init_icmd[] = { | ||
| 29 | { 0x001000, 1, 0x01, 0x00000004 }, | ||
| 30 | { 0x000039, 3, 0x01, 0x00000000 }, | ||
| 31 | { 0x0000a9, 1, 0x01, 0x0000ffff }, | ||
| 32 | { 0x000038, 1, 0x01, 0x0fac6881 }, | ||
| 33 | { 0x00003d, 1, 0x01, 0x00000001 }, | ||
| 34 | { 0x0000e8, 8, 0x01, 0x00000400 }, | ||
| 35 | { 0x000078, 8, 0x01, 0x00000300 }, | ||
| 36 | { 0x000050, 1, 0x01, 0x00000011 }, | ||
| 37 | { 0x000058, 8, 0x01, 0x00000008 }, | ||
| 38 | { 0x000208, 8, 0x01, 0x00000001 }, | ||
| 39 | { 0x000081, 1, 0x01, 0x00000001 }, | ||
| 40 | { 0x000085, 1, 0x01, 0x00000004 }, | ||
| 41 | { 0x000088, 1, 0x01, 0x00000400 }, | ||
| 42 | { 0x000090, 1, 0x01, 0x00000300 }, | ||
| 43 | { 0x000098, 1, 0x01, 0x00001001 }, | ||
| 44 | { 0x0000e3, 1, 0x01, 0x00000001 }, | ||
| 45 | { 0x0000da, 1, 0x01, 0x00000001 }, | ||
| 46 | { 0x0000f8, 1, 0x01, 0x00000003 }, | ||
| 47 | { 0x0000fa, 1, 0x01, 0x00000001 }, | ||
| 48 | { 0x00009f, 4, 0x01, 0x0000ffff }, | ||
| 49 | { 0x0000b1, 1, 0x01, 0x00000001 }, | ||
| 50 | { 0x0000ad, 1, 0x01, 0x0000013e }, | ||
| 51 | { 0x0000e1, 1, 0x01, 0x00000010 }, | ||
| 52 | { 0x000290, 16, 0x01, 0x00000000 }, | ||
| 53 | { 0x0003b0, 16, 0x01, 0x00000000 }, | ||
| 54 | { 0x0002a0, 16, 0x01, 0x00000000 }, | ||
| 55 | { 0x000420, 16, 0x01, 0x00000000 }, | ||
| 56 | { 0x0002b0, 16, 0x01, 0x00000000 }, | ||
| 57 | { 0x000430, 16, 0x01, 0x00000000 }, | ||
| 58 | { 0x0002c0, 16, 0x01, 0x00000000 }, | ||
| 59 | { 0x0004d0, 16, 0x01, 0x00000000 }, | ||
| 60 | { 0x000720, 16, 0x01, 0x00000000 }, | ||
| 61 | { 0x0008c0, 16, 0x01, 0x00000000 }, | ||
| 62 | { 0x000890, 16, 0x01, 0x00000000 }, | ||
| 63 | { 0x0008e0, 16, 0x01, 0x00000000 }, | ||
| 64 | { 0x0008a0, 16, 0x01, 0x00000000 }, | ||
| 65 | { 0x0008f0, 16, 0x01, 0x00000000 }, | ||
| 66 | { 0x00094c, 1, 0x01, 0x000000ff }, | ||
| 67 | { 0x00094d, 1, 0x01, 0xffffffff }, | ||
| 68 | { 0x00094e, 1, 0x01, 0x00000002 }, | ||
| 69 | { 0x0002ec, 1, 0x01, 0x00000001 }, | ||
| 70 | { 0x0002f2, 2, 0x01, 0x00000001 }, | ||
| 71 | { 0x0002f5, 1, 0x01, 0x00000001 }, | ||
| 72 | { 0x0002f7, 1, 0x01, 0x00000001 }, | ||
| 73 | { 0x000303, 1, 0x01, 0x00000001 }, | ||
| 74 | { 0x0002e6, 1, 0x01, 0x00000001 }, | ||
| 75 | { 0x000466, 1, 0x01, 0x00000052 }, | ||
| 76 | { 0x000301, 1, 0x01, 0x3f800000 }, | ||
| 77 | { 0x000304, 1, 0x01, 0x30201000 }, | ||
| 78 | { 0x000305, 1, 0x01, 0x70605040 }, | ||
| 79 | { 0x000306, 1, 0x01, 0xb8a89888 }, | ||
| 80 | { 0x000307, 1, 0x01, 0xf8e8d8c8 }, | ||
| 81 | { 0x00030a, 1, 0x01, 0x00ffff00 }, | ||
| 82 | { 0x00030b, 1, 0x01, 0x0000001a }, | ||
| 83 | { 0x00030c, 1, 0x01, 0x00000001 }, | ||
| 84 | { 0x000318, 1, 0x01, 0x00000001 }, | ||
| 85 | { 0x000340, 1, 0x01, 0x00000000 }, | ||
| 86 | { 0x000375, 1, 0x01, 0x00000001 }, | ||
| 87 | { 0x00037d, 1, 0x01, 0x00000006 }, | ||
| 88 | { 0x0003a0, 1, 0x01, 0x00000002 }, | ||
| 89 | { 0x0003aa, 1, 0x01, 0x00000001 }, | ||
| 90 | { 0x0003a9, 1, 0x01, 0x00000001 }, | ||
| 91 | { 0x000380, 1, 0x01, 0x00000001 }, | ||
| 92 | { 0x000383, 1, 0x01, 0x00000011 }, | ||
| 93 | { 0x000360, 1, 0x01, 0x00000040 }, | ||
| 94 | { 0x000366, 2, 0x01, 0x00000000 }, | ||
| 95 | { 0x000368, 1, 0x01, 0x00000fff }, | ||
| 96 | { 0x000370, 2, 0x01, 0x00000000 }, | ||
| 97 | { 0x000372, 1, 0x01, 0x000fffff }, | ||
| 98 | { 0x00037a, 1, 0x01, 0x00000012 }, | ||
| 99 | { 0x000619, 1, 0x01, 0x00000003 }, | ||
| 100 | { 0x000811, 1, 0x01, 0x00000003 }, | ||
| 101 | { 0x000812, 1, 0x01, 0x00000004 }, | ||
| 102 | { 0x000813, 1, 0x01, 0x00000006 }, | ||
| 103 | { 0x000814, 1, 0x01, 0x00000008 }, | ||
| 104 | { 0x000815, 1, 0x01, 0x0000000b }, | ||
| 105 | { 0x000800, 6, 0x01, 0x00000001 }, | ||
| 106 | { 0x000632, 1, 0x01, 0x00000001 }, | ||
| 107 | { 0x000633, 1, 0x01, 0x00000002 }, | ||
| 108 | { 0x000634, 1, 0x01, 0x00000003 }, | ||
| 109 | { 0x000635, 1, 0x01, 0x00000004 }, | ||
| 110 | { 0x000654, 1, 0x01, 0x3f800000 }, | ||
| 111 | { 0x000657, 1, 0x01, 0x3f800000 }, | ||
| 112 | { 0x000655, 2, 0x01, 0x3f800000 }, | ||
| 113 | { 0x0006cd, 1, 0x01, 0x3f800000 }, | ||
| 114 | { 0x0007f5, 1, 0x01, 0x3f800000 }, | ||
| 115 | { 0x0007dc, 1, 0x01, 0x39291909 }, | ||
| 116 | { 0x0007dd, 1, 0x01, 0x79695949 }, | ||
| 117 | { 0x0007de, 1, 0x01, 0xb9a99989 }, | ||
| 118 | { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, | ||
| 119 | { 0x0007e8, 1, 0x01, 0x00003210 }, | ||
| 120 | { 0x0007e9, 1, 0x01, 0x00007654 }, | ||
| 121 | { 0x0007ea, 1, 0x01, 0x00000098 }, | ||
| 122 | { 0x0007ec, 1, 0x01, 0x39291909 }, | ||
| 123 | { 0x0007ed, 1, 0x01, 0x79695949 }, | ||
| 124 | { 0x0007ee, 1, 0x01, 0xb9a99989 }, | ||
| 125 | { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, | ||
| 126 | { 0x0007f0, 1, 0x01, 0x00003210 }, | ||
| 127 | { 0x0007f1, 1, 0x01, 0x00007654 }, | ||
| 128 | { 0x0007f2, 1, 0x01, 0x00000098 }, | ||
| 129 | { 0x0005a5, 1, 0x01, 0x00000001 }, | ||
| 130 | { 0x000980, 128, 0x01, 0x00000000 }, | ||
| 131 | { 0x000468, 1, 0x01, 0x00000004 }, | ||
| 132 | { 0x00046c, 1, 0x01, 0x00000001 }, | ||
| 133 | { 0x000470, 96, 0x01, 0x00000000 }, | ||
| 134 | { 0x000510, 16, 0x01, 0x3f800000 }, | ||
| 135 | { 0x000520, 1, 0x01, 0x000002b6 }, | ||
| 136 | { 0x000529, 1, 0x01, 0x00000001 }, | ||
| 137 | { 0x000530, 16, 0x01, 0xffff0000 }, | ||
| 138 | { 0x000585, 1, 0x01, 0x0000003f }, | ||
| 139 | { 0x000576, 1, 0x01, 0x00000003 }, | ||
| 140 | { 0x00057b, 1, 0x01, 0x00000059 }, | ||
| 141 | { 0x000586, 1, 0x01, 0x00000040 }, | ||
| 142 | { 0x000582, 2, 0x01, 0x00000080 }, | ||
| 143 | { 0x0005c2, 1, 0x01, 0x00000001 }, | ||
| 144 | { 0x000638, 2, 0x01, 0x00000001 }, | ||
| 145 | { 0x00063a, 1, 0x01, 0x00000002 }, | ||
| 146 | { 0x00063b, 2, 0x01, 0x00000001 }, | ||
| 147 | { 0x00063d, 1, 0x01, 0x00000002 }, | ||
| 148 | { 0x00063e, 1, 0x01, 0x00000001 }, | ||
| 149 | { 0x0008b8, 8, 0x01, 0x00000001 }, | ||
| 150 | { 0x000900, 8, 0x01, 0x00000001 }, | ||
| 151 | { 0x000908, 8, 0x01, 0x00000002 }, | ||
| 152 | { 0x000910, 16, 0x01, 0x00000001 }, | ||
| 153 | { 0x000920, 8, 0x01, 0x00000002 }, | ||
| 154 | { 0x000928, 8, 0x01, 0x00000001 }, | ||
| 155 | { 0x000662, 1, 0x01, 0x00000001 }, | ||
| 156 | { 0x000648, 9, 0x01, 0x00000001 }, | ||
| 157 | { 0x000658, 1, 0x01, 0x0000000f }, | ||
| 158 | { 0x0007ff, 1, 0x01, 0x0000000a }, | ||
| 159 | { 0x00066a, 1, 0x01, 0x40000000 }, | ||
| 160 | { 0x00066b, 1, 0x01, 0x10000000 }, | ||
| 161 | { 0x00066c, 2, 0x01, 0xffff0000 }, | ||
| 162 | { 0x0007af, 2, 0x01, 0x00000008 }, | ||
| 163 | { 0x0007f6, 1, 0x01, 0x00000001 }, | ||
| 164 | { 0x00080b, 1, 0x01, 0x00000002 }, | ||
| 165 | { 0x0006b2, 1, 0x01, 0x00000055 }, | ||
| 166 | { 0x0007ad, 1, 0x01, 0x00000003 }, | ||
| 167 | { 0x000937, 1, 0x01, 0x00000001 }, | ||
| 168 | { 0x000971, 1, 0x01, 0x00000008 }, | ||
| 169 | { 0x000972, 1, 0x01, 0x00000040 }, | ||
| 170 | { 0x000973, 1, 0x01, 0x0000012c }, | ||
| 171 | { 0x00097c, 1, 0x01, 0x00000040 }, | ||
| 172 | { 0x000979, 1, 0x01, 0x00000003 }, | ||
| 173 | { 0x000975, 1, 0x01, 0x00000020 }, | ||
| 174 | { 0x000976, 1, 0x01, 0x00000001 }, | ||
| 175 | { 0x000977, 1, 0x01, 0x00000020 }, | ||
| 176 | { 0x000978, 1, 0x01, 0x00000001 }, | ||
| 177 | { 0x000957, 1, 0x01, 0x00000003 }, | ||
| 178 | { 0x00095e, 1, 0x01, 0x20164010 }, | ||
| 179 | { 0x00095f, 1, 0x01, 0x00000020 }, | ||
| 180 | { 0x000a0d, 1, 0x01, 0x00000006 }, | ||
| 181 | { 0x00097d, 1, 0x01, 0x00000020 }, | ||
| 182 | { 0x000683, 1, 0x01, 0x00000006 }, | ||
| 183 | { 0x000685, 1, 0x01, 0x003fffff }, | ||
| 184 | { 0x000687, 1, 0x01, 0x003fffff }, | ||
| 185 | { 0x0006a0, 1, 0x01, 0x00000005 }, | ||
| 186 | { 0x000840, 1, 0x01, 0x00400008 }, | ||
| 187 | { 0x000841, 1, 0x01, 0x08000080 }, | ||
| 188 | { 0x000842, 1, 0x01, 0x00400008 }, | ||
| 189 | { 0x000843, 1, 0x01, 0x08000080 }, | ||
| 190 | { 0x0006aa, 1, 0x01, 0x00000001 }, | ||
| 191 | { 0x0006ab, 1, 0x01, 0x00000002 }, | ||
| 192 | { 0x0006ac, 1, 0x01, 0x00000080 }, | ||
| 193 | { 0x0006ad, 2, 0x01, 0x00000100 }, | ||
| 194 | { 0x0006b1, 1, 0x01, 0x00000011 }, | ||
| 195 | { 0x0006bb, 1, 0x01, 0x000000cf }, | ||
| 196 | { 0x0006ce, 1, 0x01, 0x2a712488 }, | ||
| 197 | { 0x000739, 1, 0x01, 0x4085c000 }, | ||
| 198 | { 0x00073a, 1, 0x01, 0x00000080 }, | ||
| 199 | { 0x000786, 1, 0x01, 0x80000100 }, | ||
| 200 | { 0x00073c, 1, 0x01, 0x00010100 }, | ||
| 201 | { 0x00073d, 1, 0x01, 0x02800000 }, | ||
| 202 | { 0x000787, 1, 0x01, 0x000000cf }, | ||
| 203 | { 0x00078c, 1, 0x01, 0x00000008 }, | ||
| 204 | { 0x000792, 1, 0x01, 0x00000001 }, | ||
| 205 | { 0x000794, 3, 0x01, 0x00000001 }, | ||
| 206 | { 0x000797, 1, 0x01, 0x000000cf }, | ||
| 207 | { 0x000836, 1, 0x01, 0x00000001 }, | ||
| 208 | { 0x00079a, 1, 0x01, 0x00000002 }, | ||
| 209 | { 0x000833, 1, 0x01, 0x04444480 }, | ||
| 210 | { 0x0007a1, 1, 0x01, 0x00000001 }, | ||
| 211 | { 0x0007a3, 3, 0x01, 0x00000001 }, | ||
| 212 | { 0x000831, 1, 0x01, 0x00000004 }, | ||
| 213 | { 0x000b07, 1, 0x01, 0x00000002 }, | ||
| 214 | { 0x000b08, 2, 0x01, 0x00000100 }, | ||
| 215 | { 0x000b0a, 1, 0x01, 0x00000001 }, | ||
| 216 | { 0x000a04, 1, 0x01, 0x000000ff }, | ||
| 217 | { 0x000a0b, 1, 0x01, 0x00000040 }, | ||
| 218 | { 0x00097f, 1, 0x01, 0x00000100 }, | ||
| 219 | { 0x000a02, 1, 0x01, 0x00000001 }, | ||
| 220 | { 0x000809, 1, 0x01, 0x00000007 }, | ||
| 221 | { 0x00c221, 1, 0x01, 0x00000040 }, | ||
| 222 | { 0x00c1b0, 8, 0x01, 0x0000000f }, | ||
| 223 | { 0x00c1b8, 1, 0x01, 0x0fac6881 }, | ||
| 224 | { 0x00c1b9, 1, 0x01, 0x00fac688 }, | ||
| 225 | { 0x00c401, 1, 0x01, 0x00000001 }, | ||
| 226 | { 0x00c402, 1, 0x01, 0x00010001 }, | ||
| 227 | { 0x00c403, 2, 0x01, 0x00000001 }, | ||
| 228 | { 0x00c40e, 1, 0x01, 0x00000020 }, | ||
| 229 | { 0x00c500, 1, 0x01, 0x00000003 }, | ||
| 230 | { 0x01e100, 1, 0x01, 0x00000001 }, | ||
| 231 | { 0x001000, 1, 0x01, 0x00000002 }, | ||
| 232 | { 0x0006aa, 1, 0x01, 0x00000001 }, | ||
| 233 | { 0x0006ad, 2, 0x01, 0x00000100 }, | ||
| 234 | { 0x0006b1, 1, 0x01, 0x00000011 }, | ||
| 235 | { 0x00078c, 1, 0x01, 0x00000008 }, | ||
| 236 | { 0x000792, 1, 0x01, 0x00000001 }, | ||
| 237 | { 0x000794, 3, 0x01, 0x00000001 }, | ||
| 238 | { 0x000797, 1, 0x01, 0x000000cf }, | ||
| 239 | { 0x00079a, 1, 0x01, 0x00000002 }, | ||
| 240 | { 0x0007a1, 1, 0x01, 0x00000001 }, | ||
| 241 | { 0x0007a3, 3, 0x01, 0x00000001 }, | ||
| 242 | { 0x000831, 1, 0x01, 0x00000004 }, | ||
| 243 | { 0x01e100, 1, 0x01, 0x00000001 }, | ||
| 244 | { 0x001000, 1, 0x01, 0x00000008 }, | ||
| 245 | { 0x000039, 3, 0x01, 0x00000000 }, | ||
| 246 | { 0x000380, 1, 0x01, 0x00000001 }, | ||
| 247 | { 0x000366, 2, 0x01, 0x00000000 }, | ||
| 248 | { 0x000368, 1, 0x01, 0x00000fff }, | ||
| 249 | { 0x000370, 2, 0x01, 0x00000000 }, | ||
| 250 | { 0x000372, 1, 0x01, 0x000fffff }, | ||
| 251 | { 0x000813, 1, 0x01, 0x00000006 }, | ||
| 252 | { 0x000814, 1, 0x01, 0x00000008 }, | ||
| 253 | { 0x000957, 1, 0x01, 0x00000003 }, | ||
| 254 | { 0x000b07, 1, 0x01, 0x00000002 }, | ||
| 255 | { 0x000b08, 2, 0x01, 0x00000100 }, | ||
| 256 | { 0x000b0a, 1, 0x01, 0x00000001 }, | ||
| 257 | { 0x000a04, 1, 0x01, 0x000000ff }, | ||
| 258 | { 0x000a0b, 1, 0x01, 0x00000040 }, | ||
| 259 | { 0x00097f, 1, 0x01, 0x00000100 }, | ||
| 260 | { 0x000a02, 1, 0x01, 0x00000001 }, | ||
| 261 | { 0x000809, 1, 0x01, 0x00000007 }, | ||
| 262 | { 0x00c221, 1, 0x01, 0x00000040 }, | ||
| 263 | { 0x00c401, 1, 0x01, 0x00000001 }, | ||
| 264 | { 0x00c402, 1, 0x01, 0x00010001 }, | ||
| 265 | { 0x00c403, 2, 0x01, 0x00000001 }, | ||
| 266 | { 0x00c40e, 1, 0x01, 0x00000020 }, | ||
| 267 | { 0x00c500, 1, 0x01, 0x00000003 }, | ||
| 268 | { 0x01e100, 1, 0x01, 0x00000001 }, | ||
| 269 | { 0x001000, 1, 0x01, 0x00000001 }, | ||
| 270 | { 0x000b07, 1, 0x01, 0x00000002 }, | ||
| 271 | { 0x000b08, 2, 0x01, 0x00000100 }, | ||
| 272 | { 0x000b0a, 1, 0x01, 0x00000001 }, | ||
| 273 | { 0x01e100, 1, 0x01, 0x00000001 }, | ||
| 274 | {} | ||
| 275 | }; | ||
| 276 | |||
| 277 | static struct nvc0_graph_init | ||
| 278 | nv108_grctx_init_a197[] = { | ||
| 279 | { 0x000800, 1, 0x04, 0x00000000 }, | ||
| 280 | { 0x000840, 1, 0x04, 0x00000000 }, | ||
| 281 | { 0x000880, 1, 0x04, 0x00000000 }, | ||
| 282 | { 0x0008c0, 1, 0x04, 0x00000000 }, | ||
| 283 | { 0x000900, 1, 0x04, 0x00000000 }, | ||
| 284 | { 0x000940, 1, 0x04, 0x00000000 }, | ||
| 285 | { 0x000980, 1, 0x04, 0x00000000 }, | ||
| 286 | { 0x0009c0, 1, 0x04, 0x00000000 }, | ||
| 287 | { 0x000804, 1, 0x04, 0x00000000 }, | ||
| 288 | { 0x000844, 1, 0x04, 0x00000000 }, | ||
| 289 | { 0x000884, 1, 0x04, 0x00000000 }, | ||
| 290 | { 0x0008c4, 1, 0x04, 0x00000000 }, | ||
| 291 | { 0x000904, 1, 0x04, 0x00000000 }, | ||
| 292 | { 0x000944, 1, 0x04, 0x00000000 }, | ||
| 293 | { 0x000984, 1, 0x04, 0x00000000 }, | ||
| 294 | { 0x0009c4, 1, 0x04, 0x00000000 }, | ||
| 295 | { 0x000808, 1, 0x04, 0x00000400 }, | ||
| 296 | { 0x000848, 1, 0x04, 0x00000400 }, | ||
| 297 | { 0x000888, 1, 0x04, 0x00000400 }, | ||
| 298 | { 0x0008c8, 1, 0x04, 0x00000400 }, | ||
| 299 | { 0x000908, 1, 0x04, 0x00000400 }, | ||
| 300 | { 0x000948, 1, 0x04, 0x00000400 }, | ||
| 301 | { 0x000988, 1, 0x04, 0x00000400 }, | ||
| 302 | { 0x0009c8, 1, 0x04, 0x00000400 }, | ||
| 303 | { 0x00080c, 1, 0x04, 0x00000300 }, | ||
| 304 | { 0x00084c, 1, 0x04, 0x00000300 }, | ||
| 305 | { 0x00088c, 1, 0x04, 0x00000300 }, | ||
| 306 | { 0x0008cc, 1, 0x04, 0x00000300 }, | ||
| 307 | { 0x00090c, 1, 0x04, 0x00000300 }, | ||
| 308 | { 0x00094c, 1, 0x04, 0x00000300 }, | ||
| 309 | { 0x00098c, 1, 0x04, 0x00000300 }, | ||
| 310 | { 0x0009cc, 1, 0x04, 0x00000300 }, | ||
| 311 | { 0x000810, 1, 0x04, 0x000000cf }, | ||
| 312 | { 0x000850, 1, 0x04, 0x00000000 }, | ||
| 313 | { 0x000890, 1, 0x04, 0x00000000 }, | ||
| 314 | { 0x0008d0, 1, 0x04, 0x00000000 }, | ||
| 315 | { 0x000910, 1, 0x04, 0x00000000 }, | ||
| 316 | { 0x000950, 1, 0x04, 0x00000000 }, | ||
| 317 | { 0x000990, 1, 0x04, 0x00000000 }, | ||
| 318 | { 0x0009d0, 1, 0x04, 0x00000000 }, | ||
| 319 | { 0x000814, 1, 0x04, 0x00000040 }, | ||
| 320 | { 0x000854, 1, 0x04, 0x00000040 }, | ||
| 321 | { 0x000894, 1, 0x04, 0x00000040 }, | ||
| 322 | { 0x0008d4, 1, 0x04, 0x00000040 }, | ||
| 323 | { 0x000914, 1, 0x04, 0x00000040 }, | ||
| 324 | { 0x000954, 1, 0x04, 0x00000040 }, | ||
| 325 | { 0x000994, 1, 0x04, 0x00000040 }, | ||
| 326 | { 0x0009d4, 1, 0x04, 0x00000040 }, | ||
| 327 | { 0x000818, 1, 0x04, 0x00000001 }, | ||
| 328 | { 0x000858, 1, 0x04, 0x00000001 }, | ||
| 329 | { 0x000898, 1, 0x04, 0x00000001 }, | ||
| 330 | { 0x0008d8, 1, 0x04, 0x00000001 }, | ||
| 331 | { 0x000918, 1, 0x04, 0x00000001 }, | ||
| 332 | { 0x000958, 1, 0x04, 0x00000001 }, | ||
| 333 | { 0x000998, 1, 0x04, 0x00000001 }, | ||
| 334 | { 0x0009d8, 1, 0x04, 0x00000001 }, | ||
| 335 | { 0x00081c, 1, 0x04, 0x00000000 }, | ||
| 336 | { 0x00085c, 1, 0x04, 0x00000000 }, | ||
| 337 | { 0x00089c, 1, 0x04, 0x00000000 }, | ||
| 338 | { 0x0008dc, 1, 0x04, 0x00000000 }, | ||
| 339 | { 0x00091c, 1, 0x04, 0x00000000 }, | ||
| 340 | { 0x00095c, 1, 0x04, 0x00000000 }, | ||
| 341 | { 0x00099c, 1, 0x04, 0x00000000 }, | ||
| 342 | { 0x0009dc, 1, 0x04, 0x00000000 }, | ||
| 343 | { 0x000820, 1, 0x04, 0x00000000 }, | ||
| 344 | { 0x000860, 1, 0x04, 0x00000000 }, | ||
| 345 | { 0x0008a0, 1, 0x04, 0x00000000 }, | ||
| 346 | { 0x0008e0, 1, 0x04, 0x00000000 }, | ||
| 347 | { 0x000920, 1, 0x04, 0x00000000 }, | ||
| 348 | { 0x000960, 1, 0x04, 0x00000000 }, | ||
| 349 | { 0x0009a0, 1, 0x04, 0x00000000 }, | ||
| 350 | { 0x0009e0, 1, 0x04, 0x00000000 }, | ||
| 351 | { 0x001c00, 1, 0x04, 0x00000000 }, | ||
| 352 | { 0x001c10, 1, 0x04, 0x00000000 }, | ||
| 353 | { 0x001c20, 1, 0x04, 0x00000000 }, | ||
| 354 | { 0x001c30, 1, 0x04, 0x00000000 }, | ||
| 355 | { 0x001c40, 1, 0x04, 0x00000000 }, | ||
| 356 | { 0x001c50, 1, 0x04, 0x00000000 }, | ||
| 357 | { 0x001c60, 1, 0x04, 0x00000000 }, | ||
| 358 | { 0x001c70, 1, 0x04, 0x00000000 }, | ||
| 359 | { 0x001c80, 1, 0x04, 0x00000000 }, | ||
| 360 | { 0x001c90, 1, 0x04, 0x00000000 }, | ||
| 361 | { 0x001ca0, 1, 0x04, 0x00000000 }, | ||
| 362 | { 0x001cb0, 1, 0x04, 0x00000000 }, | ||
| 363 | { 0x001cc0, 1, 0x04, 0x00000000 }, | ||
| 364 | { 0x001cd0, 1, 0x04, 0x00000000 }, | ||
| 365 | { 0x001ce0, 1, 0x04, 0x00000000 }, | ||
| 366 | { 0x001cf0, 1, 0x04, 0x00000000 }, | ||
| 367 | { 0x001c04, 1, 0x04, 0x00000000 }, | ||
| 368 | { 0x001c14, 1, 0x04, 0x00000000 }, | ||
| 369 | { 0x001c24, 1, 0x04, 0x00000000 }, | ||
| 370 | { 0x001c34, 1, 0x04, 0x00000000 }, | ||
| 371 | { 0x001c44, 1, 0x04, 0x00000000 }, | ||
| 372 | { 0x001c54, 1, 0x04, 0x00000000 }, | ||
| 373 | { 0x001c64, 1, 0x04, 0x00000000 }, | ||
| 374 | { 0x001c74, 1, 0x04, 0x00000000 }, | ||
| 375 | { 0x001c84, 1, 0x04, 0x00000000 }, | ||
| 376 | { 0x001c94, 1, 0x04, 0x00000000 }, | ||
| 377 | { 0x001ca4, 1, 0x04, 0x00000000 }, | ||
| 378 | { 0x001cb4, 1, 0x04, 0x00000000 }, | ||
| 379 | { 0x001cc4, 1, 0x04, 0x00000000 }, | ||
| 380 | { 0x001cd4, 1, 0x04, 0x00000000 }, | ||
| 381 | { 0x001ce4, 1, 0x04, 0x00000000 }, | ||
| 382 | { 0x001cf4, 1, 0x04, 0x00000000 }, | ||
| 383 | { 0x001c08, 1, 0x04, 0x00000000 }, | ||
| 384 | { 0x001c18, 1, 0x04, 0x00000000 }, | ||
| 385 | { 0x001c28, 1, 0x04, 0x00000000 }, | ||
| 386 | { 0x001c38, 1, 0x04, 0x00000000 }, | ||
| 387 | { 0x001c48, 1, 0x04, 0x00000000 }, | ||
| 388 | { 0x001c58, 1, 0x04, 0x00000000 }, | ||
| 389 | { 0x001c68, 1, 0x04, 0x00000000 }, | ||
| 390 | { 0x001c78, 1, 0x04, 0x00000000 }, | ||
| 391 | { 0x001c88, 1, 0x04, 0x00000000 }, | ||
| 392 | { 0x001c98, 1, 0x04, 0x00000000 }, | ||
| 393 | { 0x001ca8, 1, 0x04, 0x00000000 }, | ||
| 394 | { 0x001cb8, 1, 0x04, 0x00000000 }, | ||
| 395 | { 0x001cc8, 1, 0x04, 0x00000000 }, | ||
| 396 | { 0x001cd8, 1, 0x04, 0x00000000 }, | ||
| 397 | { 0x001ce8, 1, 0x04, 0x00000000 }, | ||
| 398 | { 0x001cf8, 1, 0x04, 0x00000000 }, | ||
| 399 | { 0x001c0c, 1, 0x04, 0x00000000 }, | ||
| 400 | { 0x001c1c, 1, 0x04, 0x00000000 }, | ||
| 401 | { 0x001c2c, 1, 0x04, 0x00000000 }, | ||
| 402 | { 0x001c3c, 1, 0x04, 0x00000000 }, | ||
| 403 | { 0x001c4c, 1, 0x04, 0x00000000 }, | ||
| 404 | { 0x001c5c, 1, 0x04, 0x00000000 }, | ||
| 405 | { 0x001c6c, 1, 0x04, 0x00000000 }, | ||
| 406 | { 0x001c7c, 1, 0x04, 0x00000000 }, | ||
| 407 | { 0x001c8c, 1, 0x04, 0x00000000 }, | ||
| 408 | { 0x001c9c, 1, 0x04, 0x00000000 }, | ||
| 409 | { 0x001cac, 1, 0x04, 0x00000000 }, | ||
| 410 | { 0x001cbc, 1, 0x04, 0x00000000 }, | ||
| 411 | { 0x001ccc, 1, 0x04, 0x00000000 }, | ||
| 412 | { 0x001cdc, 1, 0x04, 0x00000000 }, | ||
| 413 | { 0x001cec, 1, 0x04, 0x00000000 }, | ||
| 414 | { 0x001cfc, 2, 0x04, 0x00000000 }, | ||
| 415 | { 0x001d10, 1, 0x04, 0x00000000 }, | ||
| 416 | { 0x001d20, 1, 0x04, 0x00000000 }, | ||
| 417 | { 0x001d30, 1, 0x04, 0x00000000 }, | ||
| 418 | { 0x001d40, 1, 0x04, 0x00000000 }, | ||
| 419 | { 0x001d50, 1, 0x04, 0x00000000 }, | ||
| 420 | { 0x001d60, 1, 0x04, 0x00000000 }, | ||
| 421 | { 0x001d70, 1, 0x04, 0x00000000 }, | ||
| 422 | { 0x001d80, 1, 0x04, 0x00000000 }, | ||
| 423 | { 0x001d90, 1, 0x04, 0x00000000 }, | ||
| 424 | { 0x001da0, 1, 0x04, 0x00000000 }, | ||
| 425 | { 0x001db0, 1, 0x04, 0x00000000 }, | ||
| 426 | { 0x001dc0, 1, 0x04, 0x00000000 }, | ||
| 427 | { 0x001dd0, 1, 0x04, 0x00000000 }, | ||
| 428 | { 0x001de0, 1, 0x04, 0x00000000 }, | ||
| 429 | { 0x001df0, 1, 0x04, 0x00000000 }, | ||
| 430 | { 0x001d04, 1, 0x04, 0x00000000 }, | ||
| 431 | { 0x001d14, 1, 0x04, 0x00000000 }, | ||
| 432 | { 0x001d24, 1, 0x04, 0x00000000 }, | ||
| 433 | { 0x001d34, 1, 0x04, 0x00000000 }, | ||
| 434 | { 0x001d44, 1, 0x04, 0x00000000 }, | ||
| 435 | { 0x001d54, 1, 0x04, 0x00000000 }, | ||
| 436 | { 0x001d64, 1, 0x04, 0x00000000 }, | ||
| 437 | { 0x001d74, 1, 0x04, 0x00000000 }, | ||
| 438 | { 0x001d84, 1, 0x04, 0x00000000 }, | ||
| 439 | { 0x001d94, 1, 0x04, 0x00000000 }, | ||
| 440 | { 0x001da4, 1, 0x04, 0x00000000 }, | ||
| 441 | { 0x001db4, 1, 0x04, 0x00000000 }, | ||
| 442 | { 0x001dc4, 1, 0x04, 0x00000000 }, | ||
| 443 | { 0x001dd4, 1, 0x04, 0x00000000 }, | ||
| 444 | { 0x001de4, 1, 0x04, 0x00000000 }, | ||
| 445 | { 0x001df4, 1, 0x04, 0x00000000 }, | ||
| 446 | { 0x001d08, 1, 0x04, 0x00000000 }, | ||
| 447 | { 0x001d18, 1, 0x04, 0x00000000 }, | ||
| 448 | { 0x001d28, 1, 0x04, 0x00000000 }, | ||
| 449 | { 0x001d38, 1, 0x04, 0x00000000 }, | ||
| 450 | { 0x001d48, 1, 0x04, 0x00000000 }, | ||
| 451 | { 0x001d58, 1, 0x04, 0x00000000 }, | ||
| 452 | { 0x001d68, 1, 0x04, 0x00000000 }, | ||
| 453 | { 0x001d78, 1, 0x04, 0x00000000 }, | ||
| 454 | { 0x001d88, 1, 0x04, 0x00000000 }, | ||
| 455 | { 0x001d98, 1, 0x04, 0x00000000 }, | ||
| 456 | { 0x001da8, 1, 0x04, 0x00000000 }, | ||
| 457 | { 0x001db8, 1, 0x04, 0x00000000 }, | ||
| 458 | { 0x001dc8, 1, 0x04, 0x00000000 }, | ||
| 459 | { 0x001dd8, 1, 0x04, 0x00000000 }, | ||
| 460 | { 0x001de8, 1, 0x04, 0x00000000 }, | ||
| 461 | { 0x001df8, 1, 0x04, 0x00000000 }, | ||
| 462 | { 0x001d0c, 1, 0x04, 0x00000000 }, | ||
| 463 | { 0x001d1c, 1, 0x04, 0x00000000 }, | ||
| 464 | { 0x001d2c, 1, 0x04, 0x00000000 }, | ||
| 465 | { 0x001d3c, 1, 0x04, 0x00000000 }, | ||
| 466 | { 0x001d4c, 1, 0x04, 0x00000000 }, | ||
| 467 | { 0x001d5c, 1, 0x04, 0x00000000 }, | ||
| 468 | { 0x001d6c, 1, 0x04, 0x00000000 }, | ||
| 469 | { 0x001d7c, 1, 0x04, 0x00000000 }, | ||
| 470 | { 0x001d8c, 1, 0x04, 0x00000000 }, | ||
| 471 | { 0x001d9c, 1, 0x04, 0x00000000 }, | ||
| 472 | { 0x001dac, 1, 0x04, 0x00000000 }, | ||
| 473 | { 0x001dbc, 1, 0x04, 0x00000000 }, | ||
| 474 | { 0x001dcc, 1, 0x04, 0x00000000 }, | ||
| 475 | { 0x001ddc, 1, 0x04, 0x00000000 }, | ||
| 476 | { 0x001dec, 1, 0x04, 0x00000000 }, | ||
| 477 | { 0x001dfc, 1, 0x04, 0x00000000 }, | ||
| 478 | { 0x001f00, 1, 0x04, 0x00000000 }, | ||
| 479 | { 0x001f08, 1, 0x04, 0x00000000 }, | ||
| 480 | { 0x001f10, 1, 0x04, 0x00000000 }, | ||
| 481 | { 0x001f18, 1, 0x04, 0x00000000 }, | ||
| 482 | { 0x001f20, 1, 0x04, 0x00000000 }, | ||
| 483 | { 0x001f28, 1, 0x04, 0x00000000 }, | ||
| 484 | { 0x001f30, 1, 0x04, 0x00000000 }, | ||
| 485 | { 0x001f38, 1, 0x04, 0x00000000 }, | ||
| 486 | { 0x001f40, 1, 0x04, 0x00000000 }, | ||
| 487 | { 0x001f48, 1, 0x04, 0x00000000 }, | ||
| 488 | { 0x001f50, 1, 0x04, 0x00000000 }, | ||
| 489 | { 0x001f58, 1, 0x04, 0x00000000 }, | ||
| 490 | { 0x001f60, 1, 0x04, 0x00000000 }, | ||
| 491 | { 0x001f68, 1, 0x04, 0x00000000 }, | ||
| 492 | { 0x001f70, 1, 0x04, 0x00000000 }, | ||
| 493 | { 0x001f78, 1, 0x04, 0x00000000 }, | ||
| 494 | { 0x001f04, 1, 0x04, 0x00000000 }, | ||
| 495 | { 0x001f0c, 1, 0x04, 0x00000000 }, | ||
| 496 | { 0x001f14, 1, 0x04, 0x00000000 }, | ||
| 497 | { 0x001f1c, 1, 0x04, 0x00000000 }, | ||
| 498 | { 0x001f24, 1, 0x04, 0x00000000 }, | ||
| 499 | { 0x001f2c, 1, 0x04, 0x00000000 }, | ||
| 500 | { 0x001f34, 1, 0x04, 0x00000000 }, | ||
| 501 | { 0x001f3c, 1, 0x04, 0x00000000 }, | ||
| 502 | { 0x001f44, 1, 0x04, 0x00000000 }, | ||
| 503 | { 0x001f4c, 1, 0x04, 0x00000000 }, | ||
| 504 | { 0x001f54, 1, 0x04, 0x00000000 }, | ||
| 505 | { 0x001f5c, 1, 0x04, 0x00000000 }, | ||
| 506 | { 0x001f64, 1, 0x04, 0x00000000 }, | ||
| 507 | { 0x001f6c, 1, 0x04, 0x00000000 }, | ||
| 508 | { 0x001f74, 1, 0x04, 0x00000000 }, | ||
| 509 | { 0x001f7c, 2, 0x04, 0x00000000 }, | ||
| 510 | { 0x001f88, 1, 0x04, 0x00000000 }, | ||
| 511 | { 0x001f90, 1, 0x04, 0x00000000 }, | ||
| 512 | { 0x001f98, 1, 0x04, 0x00000000 }, | ||
| 513 | { 0x001fa0, 1, 0x04, 0x00000000 }, | ||
| 514 | { 0x001fa8, 1, 0x04, 0x00000000 }, | ||
| 515 | { 0x001fb0, 1, 0x04, 0x00000000 }, | ||
| 516 | { 0x001fb8, 1, 0x04, 0x00000000 }, | ||
| 517 | { 0x001fc0, 1, 0x04, 0x00000000 }, | ||
| 518 | { 0x001fc8, 1, 0x04, 0x00000000 }, | ||
| 519 | { 0x001fd0, 1, 0x04, 0x00000000 }, | ||
| 520 | { 0x001fd8, 1, 0x04, 0x00000000 }, | ||
| 521 | { 0x001fe0, 1, 0x04, 0x00000000 }, | ||
| 522 | { 0x001fe8, 1, 0x04, 0x00000000 }, | ||
| 523 | { 0x001ff0, 1, 0x04, 0x00000000 }, | ||
| 524 | { 0x001ff8, 1, 0x04, 0x00000000 }, | ||
| 525 | { 0x001f84, 1, 0x04, 0x00000000 }, | ||
| 526 | { 0x001f8c, 1, 0x04, 0x00000000 }, | ||
| 527 | { 0x001f94, 1, 0x04, 0x00000000 }, | ||
| 528 | { 0x001f9c, 1, 0x04, 0x00000000 }, | ||
| 529 | { 0x001fa4, 1, 0x04, 0x00000000 }, | ||
| 530 | { 0x001fac, 1, 0x04, 0x00000000 }, | ||
| 531 | { 0x001fb4, 1, 0x04, 0x00000000 }, | ||
| 532 | { 0x001fbc, 1, 0x04, 0x00000000 }, | ||
| 533 | { 0x001fc4, 1, 0x04, 0x00000000 }, | ||
| 534 | { 0x001fcc, 1, 0x04, 0x00000000 }, | ||
| 535 | { 0x001fd4, 1, 0x04, 0x00000000 }, | ||
| 536 | { 0x001fdc, 1, 0x04, 0x00000000 }, | ||
| 537 | { 0x001fe4, 1, 0x04, 0x00000000 }, | ||
| 538 | { 0x001fec, 1, 0x04, 0x00000000 }, | ||
| 539 | { 0x001ff4, 1, 0x04, 0x00000000 }, | ||
| 540 | { 0x001ffc, 2, 0x04, 0x00000000 }, | ||
| 541 | { 0x002040, 1, 0x04, 0x00000011 }, | ||
| 542 | { 0x002080, 1, 0x04, 0x00000020 }, | ||
| 543 | { 0x0020c0, 1, 0x04, 0x00000030 }, | ||
| 544 | { 0x002100, 1, 0x04, 0x00000040 }, | ||
| 545 | { 0x002140, 1, 0x04, 0x00000051 }, | ||
| 546 | { 0x00200c, 1, 0x04, 0x00000001 }, | ||
| 547 | { 0x00204c, 1, 0x04, 0x00000001 }, | ||
| 548 | { 0x00208c, 1, 0x04, 0x00000001 }, | ||
| 549 | { 0x0020cc, 1, 0x04, 0x00000001 }, | ||
| 550 | { 0x00210c, 1, 0x04, 0x00000001 }, | ||
| 551 | { 0x00214c, 1, 0x04, 0x00000001 }, | ||
| 552 | { 0x002010, 1, 0x04, 0x00000000 }, | ||
| 553 | { 0x002050, 1, 0x04, 0x00000000 }, | ||
| 554 | { 0x002090, 1, 0x04, 0x00000001 }, | ||
| 555 | { 0x0020d0, 1, 0x04, 0x00000002 }, | ||
| 556 | { 0x002110, 1, 0x04, 0x00000003 }, | ||
| 557 | { 0x002150, 1, 0x04, 0x00000004 }, | ||
| 558 | { 0x000380, 1, 0x04, 0x00000000 }, | ||
| 559 | { 0x0003a0, 1, 0x04, 0x00000000 }, | ||
| 560 | { 0x0003c0, 1, 0x04, 0x00000000 }, | ||
| 561 | { 0x0003e0, 1, 0x04, 0x00000000 }, | ||
| 562 | { 0x000384, 1, 0x04, 0x00000000 }, | ||
| 563 | { 0x0003a4, 1, 0x04, 0x00000000 }, | ||
| 564 | { 0x0003c4, 1, 0x04, 0x00000000 }, | ||
| 565 | { 0x0003e4, 1, 0x04, 0x00000000 }, | ||
| 566 | { 0x000388, 1, 0x04, 0x00000000 }, | ||
| 567 | { 0x0003a8, 1, 0x04, 0x00000000 }, | ||
| 568 | { 0x0003c8, 1, 0x04, 0x00000000 }, | ||
| 569 | { 0x0003e8, 1, 0x04, 0x00000000 }, | ||
| 570 | { 0x00038c, 1, 0x04, 0x00000000 }, | ||
| 571 | { 0x0003ac, 1, 0x04, 0x00000000 }, | ||
| 572 | { 0x0003cc, 1, 0x04, 0x00000000 }, | ||
| 573 | { 0x0003ec, 1, 0x04, 0x00000000 }, | ||
| 574 | { 0x000700, 1, 0x04, 0x00000000 }, | ||
| 575 | { 0x000710, 1, 0x04, 0x00000000 }, | ||
| 576 | { 0x000720, 1, 0x04, 0x00000000 }, | ||
| 577 | { 0x000730, 1, 0x04, 0x00000000 }, | ||
| 578 | { 0x000704, 1, 0x04, 0x00000000 }, | ||
| 579 | { 0x000714, 1, 0x04, 0x00000000 }, | ||
| 580 | { 0x000724, 1, 0x04, 0x00000000 }, | ||
| 581 | { 0x000734, 1, 0x04, 0x00000000 }, | ||
| 582 | { 0x000708, 1, 0x04, 0x00000000 }, | ||
| 583 | { 0x000718, 1, 0x04, 0x00000000 }, | ||
| 584 | { 0x000728, 1, 0x04, 0x00000000 }, | ||
| 585 | { 0x000738, 1, 0x04, 0x00000000 }, | ||
| 586 | { 0x002800, 128, 0x04, 0x00000000 }, | ||
| 587 | { 0x000a00, 1, 0x04, 0x00000000 }, | ||
| 588 | { 0x000a20, 1, 0x04, 0x00000000 }, | ||
| 589 | { 0x000a40, 1, 0x04, 0x00000000 }, | ||
| 590 | { 0x000a60, 1, 0x04, 0x00000000 }, | ||
| 591 | { 0x000a80, 1, 0x04, 0x00000000 }, | ||
| 592 | { 0x000aa0, 1, 0x04, 0x00000000 }, | ||
| 593 | { 0x000ac0, 1, 0x04, 0x00000000 }, | ||
| 594 | { 0x000ae0, 1, 0x04, 0x00000000 }, | ||
| 595 | { 0x000b00, 1, 0x04, 0x00000000 }, | ||
| 596 | { 0x000b20, 1, 0x04, 0x00000000 }, | ||
| 597 | { 0x000b40, 1, 0x04, 0x00000000 }, | ||
| 598 | { 0x000b60, 1, 0x04, 0x00000000 }, | ||
| 599 | { 0x000b80, 1, 0x04, 0x00000000 }, | ||
| 600 | { 0x000ba0, 1, 0x04, 0x00000000 }, | ||
| 601 | { 0x000bc0, 1, 0x04, 0x00000000 }, | ||
| 602 | { 0x000be0, 1, 0x04, 0x00000000 }, | ||
| 603 | { 0x000a04, 1, 0x04, 0x00000000 }, | ||
| 604 | { 0x000a24, 1, 0x04, 0x00000000 }, | ||
| 605 | { 0x000a44, 1, 0x04, 0x00000000 }, | ||
| 606 | { 0x000a64, 1, 0x04, 0x00000000 }, | ||
| 607 | { 0x000a84, 1, 0x04, 0x00000000 }, | ||
| 608 | { 0x000aa4, 1, 0x04, 0x00000000 }, | ||
| 609 | { 0x000ac4, 1, 0x04, 0x00000000 }, | ||
| 610 | { 0x000ae4, 1, 0x04, 0x00000000 }, | ||
| 611 | { 0x000b04, 1, 0x04, 0x00000000 }, | ||
| 612 | { 0x000b24, 1, 0x04, 0x00000000 }, | ||
| 613 | { 0x000b44, 1, 0x04, 0x00000000 }, | ||
| 614 | { 0x000b64, 1, 0x04, 0x00000000 }, | ||
| 615 | { 0x000b84, 1, 0x04, 0x00000000 }, | ||
| 616 | { 0x000ba4, 1, 0x04, 0x00000000 }, | ||
| 617 | { 0x000bc4, 1, 0x04, 0x00000000 }, | ||
| 618 | { 0x000be4, 1, 0x04, 0x00000000 }, | ||
| 619 | { 0x000a08, 1, 0x04, 0x00000000 }, | ||
| 620 | { 0x000a28, 1, 0x04, 0x00000000 }, | ||
| 621 | { 0x000a48, 1, 0x04, 0x00000000 }, | ||
| 622 | { 0x000a68, 1, 0x04, 0x00000000 }, | ||
| 623 | { 0x000a88, 1, 0x04, 0x00000000 }, | ||
| 624 | { 0x000aa8, 1, 0x04, 0x00000000 }, | ||
| 625 | { 0x000ac8, 1, 0x04, 0x00000000 }, | ||
| 626 | { 0x000ae8, 1, 0x04, 0x00000000 }, | ||
| 627 | { 0x000b08, 1, 0x04, 0x00000000 }, | ||
| 628 | { 0x000b28, 1, 0x04, 0x00000000 }, | ||
| 629 | { 0x000b48, 1, 0x04, 0x00000000 }, | ||
| 630 | { 0x000b68, 1, 0x04, 0x00000000 }, | ||
| 631 | { 0x000b88, 1, 0x04, 0x00000000 }, | ||
| 632 | { 0x000ba8, 1, 0x04, 0x00000000 }, | ||
| 633 | { 0x000bc8, 1, 0x04, 0x00000000 }, | ||
| 634 | { 0x000be8, 1, 0x04, 0x00000000 }, | ||
| 635 | { 0x000a0c, 1, 0x04, 0x00000000 }, | ||
| 636 | { 0x000a2c, 1, 0x04, 0x00000000 }, | ||
| 637 | { 0x000a4c, 1, 0x04, 0x00000000 }, | ||
| 638 | { 0x000a6c, 1, 0x04, 0x00000000 }, | ||
| 639 | { 0x000a8c, 1, 0x04, 0x00000000 }, | ||
| 640 | { 0x000aac, 1, 0x04, 0x00000000 }, | ||
| 641 | { 0x000acc, 1, 0x04, 0x00000000 }, | ||
| 642 | { 0x000aec, 1, 0x04, 0x00000000 }, | ||
| 643 | { 0x000b0c, 1, 0x04, 0x00000000 }, | ||
| 644 | { 0x000b2c, 1, 0x04, 0x00000000 }, | ||
| 645 | { 0x000b4c, 1, 0x04, 0x00000000 }, | ||
| 646 | { 0x000b6c, 1, 0x04, 0x00000000 }, | ||
| 647 | { 0x000b8c, 1, 0x04, 0x00000000 }, | ||
| 648 | { 0x000bac, 1, 0x04, 0x00000000 }, | ||
| 649 | { 0x000bcc, 1, 0x04, 0x00000000 }, | ||
| 650 | { 0x000bec, 1, 0x04, 0x00000000 }, | ||
| 651 | { 0x000a10, 1, 0x04, 0x00000000 }, | ||
| 652 | { 0x000a30, 1, 0x04, 0x00000000 }, | ||
| 653 | { 0x000a50, 1, 0x04, 0x00000000 }, | ||
| 654 | { 0x000a70, 1, 0x04, 0x00000000 }, | ||
| 655 | { 0x000a90, 1, 0x04, 0x00000000 }, | ||
| 656 | { 0x000ab0, 1, 0x04, 0x00000000 }, | ||
| 657 | { 0x000ad0, 1, 0x04, 0x00000000 }, | ||
| 658 | { 0x000af0, 1, 0x04, 0x00000000 }, | ||
| 659 | { 0x000b10, 1, 0x04, 0x00000000 }, | ||
| 660 | { 0x000b30, 1, 0x04, 0x00000000 }, | ||
| 661 | { 0x000b50, 1, 0x04, 0x00000000 }, | ||
| 662 | { 0x000b70, 1, 0x04, 0x00000000 }, | ||
| 663 | { 0x000b90, 1, 0x04, 0x00000000 }, | ||
| 664 | { 0x000bb0, 1, 0x04, 0x00000000 }, | ||
| 665 | { 0x000bd0, 1, 0x04, 0x00000000 }, | ||
| 666 | { 0x000bf0, 1, 0x04, 0x00000000 }, | ||
| 667 | { 0x000a14, 1, 0x04, 0x00000000 }, | ||
| 668 | { 0x000a34, 1, 0x04, 0x00000000 }, | ||
| 669 | { 0x000a54, 1, 0x04, 0x00000000 }, | ||
| 670 | { 0x000a74, 1, 0x04, 0x00000000 }, | ||
| 671 | { 0x000a94, 1, 0x04, 0x00000000 }, | ||
| 672 | { 0x000ab4, 1, 0x04, 0x00000000 }, | ||
| 673 | { 0x000ad4, 1, 0x04, 0x00000000 }, | ||
| 674 | { 0x000af4, 1, 0x04, 0x00000000 }, | ||
| 675 | { 0x000b14, 1, 0x04, 0x00000000 }, | ||
| 676 | { 0x000b34, 1, 0x04, 0x00000000 }, | ||
| 677 | { 0x000b54, 1, 0x04, 0x00000000 }, | ||
| 678 | { 0x000b74, 1, 0x04, 0x00000000 }, | ||
| 679 | { 0x000b94, 1, 0x04, 0x00000000 }, | ||
| 680 | { 0x000bb4, 1, 0x04, 0x00000000 }, | ||
| 681 | { 0x000bd4, 1, 0x04, 0x00000000 }, | ||
| 682 | { 0x000bf4, 1, 0x04, 0x00000000 }, | ||
| 683 | { 0x000c00, 1, 0x04, 0x00000000 }, | ||
| 684 | { 0x000c10, 1, 0x04, 0x00000000 }, | ||
| 685 | { 0x000c20, 1, 0x04, 0x00000000 }, | ||
| 686 | { 0x000c30, 1, 0x04, 0x00000000 }, | ||
| 687 | { 0x000c40, 1, 0x04, 0x00000000 }, | ||
| 688 | { 0x000c50, 1, 0x04, 0x00000000 }, | ||
| 689 | { 0x000c60, 1, 0x04, 0x00000000 }, | ||
| 690 | { 0x000c70, 1, 0x04, 0x00000000 }, | ||
| 691 | { 0x000c80, 1, 0x04, 0x00000000 }, | ||
| 692 | { 0x000c90, 1, 0x04, 0x00000000 }, | ||
| 693 | { 0x000ca0, 1, 0x04, 0x00000000 }, | ||
| 694 | { 0x000cb0, 1, 0x04, 0x00000000 }, | ||
| 695 | { 0x000cc0, 1, 0x04, 0x00000000 }, | ||
| 696 | { 0x000cd0, 1, 0x04, 0x00000000 }, | ||
| 697 | { 0x000ce0, 1, 0x04, 0x00000000 }, | ||
| 698 | { 0x000cf0, 1, 0x04, 0x00000000 }, | ||
| 699 | { 0x000c04, 1, 0x04, 0x00000000 }, | ||
| 700 | { 0x000c14, 1, 0x04, 0x00000000 }, | ||
| 701 | { 0x000c24, 1, 0x04, 0x00000000 }, | ||
| 702 | { 0x000c34, 1, 0x04, 0x00000000 }, | ||
| 703 | { 0x000c44, 1, 0x04, 0x00000000 }, | ||
| 704 | { 0x000c54, 1, 0x04, 0x00000000 }, | ||
| 705 | { 0x000c64, 1, 0x04, 0x00000000 }, | ||
| 706 | { 0x000c74, 1, 0x04, 0x00000000 }, | ||
| 707 | { 0x000c84, 1, 0x04, 0x00000000 }, | ||
| 708 | { 0x000c94, 1, 0x04, 0x00000000 }, | ||
| 709 | { 0x000ca4, 1, 0x04, 0x00000000 }, | ||
| 710 | { 0x000cb4, 1, 0x04, 0x00000000 }, | ||
| 711 | { 0x000cc4, 1, 0x04, 0x00000000 }, | ||
| 712 | { 0x000cd4, 1, 0x04, 0x00000000 }, | ||
| 713 | { 0x000ce4, 1, 0x04, 0x00000000 }, | ||
| 714 | { 0x000cf4, 1, 0x04, 0x00000000 }, | ||
| 715 | { 0x000c08, 1, 0x04, 0x00000000 }, | ||
| 716 | { 0x000c18, 1, 0x04, 0x00000000 }, | ||
| 717 | { 0x000c28, 1, 0x04, 0x00000000 }, | ||
| 718 | { 0x000c38, 1, 0x04, 0x00000000 }, | ||
| 719 | { 0x000c48, 1, 0x04, 0x00000000 }, | ||
| 720 | { 0x000c58, 1, 0x04, 0x00000000 }, | ||
| 721 | { 0x000c68, 1, 0x04, 0x00000000 }, | ||
| 722 | { 0x000c78, 1, 0x04, 0x00000000 }, | ||
| 723 | { 0x000c88, 1, 0x04, 0x00000000 }, | ||
| 724 | { 0x000c98, 1, 0x04, 0x00000000 }, | ||
| 725 | { 0x000ca8, 1, 0x04, 0x00000000 }, | ||
| 726 | { 0x000cb8, 1, 0x04, 0x00000000 }, | ||
| 727 | { 0x000cc8, 1, 0x04, 0x00000000 }, | ||
| 728 | { 0x000cd8, 1, 0x04, 0x00000000 }, | ||
| 729 | { 0x000ce8, 1, 0x04, 0x00000000 }, | ||
| 730 | { 0x000cf8, 1, 0x04, 0x00000000 }, | ||
| 731 | { 0x000c0c, 1, 0x04, 0x3f800000 }, | ||
| 732 | { 0x000c1c, 1, 0x04, 0x3f800000 }, | ||
| 733 | { 0x000c2c, 1, 0x04, 0x3f800000 }, | ||
| 734 | { 0x000c3c, 1, 0x04, 0x3f800000 }, | ||
| 735 | { 0x000c4c, 1, 0x04, 0x3f800000 }, | ||
| 736 | { 0x000c5c, 1, 0x04, 0x3f800000 }, | ||
| 737 | { 0x000c6c, 1, 0x04, 0x3f800000 }, | ||
| 738 | { 0x000c7c, 1, 0x04, 0x3f800000 }, | ||
| 739 | { 0x000c8c, 1, 0x04, 0x3f800000 }, | ||
| 740 | { 0x000c9c, 1, 0x04, 0x3f800000 }, | ||
| 741 | { 0x000cac, 1, 0x04, 0x3f800000 }, | ||
| 742 | { 0x000cbc, 1, 0x04, 0x3f800000 }, | ||
| 743 | { 0x000ccc, 1, 0x04, 0x3f800000 }, | ||
| 744 | { 0x000cdc, 1, 0x04, 0x3f800000 }, | ||
| 745 | { 0x000cec, 1, 0x04, 0x3f800000 }, | ||
| 746 | { 0x000cfc, 1, 0x04, 0x3f800000 }, | ||
| 747 | { 0x000d00, 1, 0x04, 0xffff0000 }, | ||
| 748 | { 0x000d08, 1, 0x04, 0xffff0000 }, | ||
| 749 | { 0x000d10, 1, 0x04, 0xffff0000 }, | ||
| 750 | { 0x000d18, 1, 0x04, 0xffff0000 }, | ||
| 751 | { 0x000d20, 1, 0x04, 0xffff0000 }, | ||
| 752 | { 0x000d28, 1, 0x04, 0xffff0000 }, | ||
| 753 | { 0x000d30, 1, 0x04, 0xffff0000 }, | ||
| 754 | { 0x000d38, 1, 0x04, 0xffff0000 }, | ||
| 755 | { 0x000d04, 1, 0x04, 0xffff0000 }, | ||
| 756 | { 0x000d0c, 1, 0x04, 0xffff0000 }, | ||
| 757 | { 0x000d14, 1, 0x04, 0xffff0000 }, | ||
| 758 | { 0x000d1c, 1, 0x04, 0xffff0000 }, | ||
| 759 | { 0x000d24, 1, 0x04, 0xffff0000 }, | ||
| 760 | { 0x000d2c, 1, 0x04, 0xffff0000 }, | ||
| 761 | { 0x000d34, 1, 0x04, 0xffff0000 }, | ||
| 762 | { 0x000d3c, 1, 0x04, 0xffff0000 }, | ||
| 763 | { 0x000e00, 1, 0x04, 0x00000000 }, | ||
| 764 | { 0x000e10, 1, 0x04, 0x00000000 }, | ||
| 765 | { 0x000e20, 1, 0x04, 0x00000000 }, | ||
| 766 | { 0x000e30, 1, 0x04, 0x00000000 }, | ||
| 767 | { 0x000e40, 1, 0x04, 0x00000000 }, | ||
| 768 | { 0x000e50, 1, 0x04, 0x00000000 }, | ||
| 769 | { 0x000e60, 1, 0x04, 0x00000000 }, | ||
| 770 | { 0x000e70, 1, 0x04, 0x00000000 }, | ||
| 771 | { 0x000e80, 1, 0x04, 0x00000000 }, | ||
| 772 | { 0x000e90, 1, 0x04, 0x00000000 }, | ||
| 773 | { 0x000ea0, 1, 0x04, 0x00000000 }, | ||
| 774 | { 0x000eb0, 1, 0x04, 0x00000000 }, | ||
| 775 | { 0x000ec0, 1, 0x04, 0x00000000 }, | ||
| 776 | { 0x000ed0, 1, 0x04, 0x00000000 }, | ||
| 777 | { 0x000ee0, 1, 0x04, 0x00000000 }, | ||
| 778 | { 0x000ef0, 1, 0x04, 0x00000000 }, | ||
| 779 | { 0x000e04, 1, 0x04, 0xffff0000 }, | ||
| 780 | { 0x000e14, 1, 0x04, 0xffff0000 }, | ||
| 781 | { 0x000e24, 1, 0x04, 0xffff0000 }, | ||
| 782 | { 0x000e34, 1, 0x04, 0xffff0000 }, | ||
| 783 | { 0x000e44, 1, 0x04, 0xffff0000 }, | ||
| 784 | { 0x000e54, 1, 0x04, 0xffff0000 }, | ||
| 785 | { 0x000e64, 1, 0x04, 0xffff0000 }, | ||
| 786 | { 0x000e74, 1, 0x04, 0xffff0000 }, | ||
| 787 | { 0x000e84, 1, 0x04, 0xffff0000 }, | ||
| 788 | { 0x000e94, 1, 0x04, 0xffff0000 }, | ||
| 789 | { 0x000ea4, 1, 0x04, 0xffff0000 }, | ||
| 790 | { 0x000eb4, 1, 0x04, 0xffff0000 }, | ||
| 791 | { 0x000ec4, 1, 0x04, 0xffff0000 }, | ||
| 792 | { 0x000ed4, 1, 0x04, 0xffff0000 }, | ||
| 793 | { 0x000ee4, 1, 0x04, 0xffff0000 }, | ||
| 794 | { 0x000ef4, 1, 0x04, 0xffff0000 }, | ||
| 795 | { 0x000e08, 1, 0x04, 0xffff0000 }, | ||
| 796 | { 0x000e18, 1, 0x04, 0xffff0000 }, | ||
| 797 | { 0x000e28, 1, 0x04, 0xffff0000 }, | ||
| 798 | { 0x000e38, 1, 0x04, 0xffff0000 }, | ||
| 799 | { 0x000e48, 1, 0x04, 0xffff0000 }, | ||
| 800 | { 0x000e58, 1, 0x04, 0xffff0000 }, | ||
| 801 | { 0x000e68, 1, 0x04, 0xffff0000 }, | ||
| 802 | { 0x000e78, 1, 0x04, 0xffff0000 }, | ||
| 803 | { 0x000e88, 1, 0x04, 0xffff0000 }, | ||
| 804 | { 0x000e98, 1, 0x04, 0xffff0000 }, | ||
| 805 | { 0x000ea8, 1, 0x04, 0xffff0000 }, | ||
| 806 | { 0x000eb8, 1, 0x04, 0xffff0000 }, | ||
| 807 | { 0x000ec8, 1, 0x04, 0xffff0000 }, | ||
| 808 | { 0x000ed8, 1, 0x04, 0xffff0000 }, | ||
| 809 | { 0x000ee8, 1, 0x04, 0xffff0000 }, | ||
| 810 | { 0x000ef8, 1, 0x04, 0xffff0000 }, | ||
| 811 | { 0x000d40, 1, 0x04, 0x00000000 }, | ||
| 812 | { 0x000d48, 1, 0x04, 0x00000000 }, | ||
| 813 | { 0x000d50, 1, 0x04, 0x00000000 }, | ||
| 814 | { 0x000d58, 1, 0x04, 0x00000000 }, | ||
| 815 | { 0x000d44, 1, 0x04, 0x00000000 }, | ||
| 816 | { 0x000d4c, 1, 0x04, 0x00000000 }, | ||
| 817 | { 0x000d54, 1, 0x04, 0x00000000 }, | ||
| 818 | { 0x000d5c, 1, 0x04, 0x00000000 }, | ||
| 819 | { 0x001e00, 1, 0x04, 0x00000001 }, | ||
| 820 | { 0x001e20, 1, 0x04, 0x00000001 }, | ||
| 821 | { 0x001e40, 1, 0x04, 0x00000001 }, | ||
| 822 | { 0x001e60, 1, 0x04, 0x00000001 }, | ||
| 823 | { 0x001e80, 1, 0x04, 0x00000001 }, | ||
| 824 | { 0x001ea0, 1, 0x04, 0x00000001 }, | ||
| 825 | { 0x001ec0, 1, 0x04, 0x00000001 }, | ||
| 826 | { 0x001ee0, 1, 0x04, 0x00000001 }, | ||
| 827 | { 0x001e04, 1, 0x04, 0x00000001 }, | ||
| 828 | { 0x001e24, 1, 0x04, 0x00000001 }, | ||
| 829 | { 0x001e44, 1, 0x04, 0x00000001 }, | ||
| 830 | { 0x001e64, 1, 0x04, 0x00000001 }, | ||
| 831 | { 0x001e84, 1, 0x04, 0x00000001 }, | ||
| 832 | { 0x001ea4, 1, 0x04, 0x00000001 }, | ||
| 833 | { 0x001ec4, 1, 0x04, 0x00000001 }, | ||
| 834 | { 0x001ee4, 1, 0x04, 0x00000001 }, | ||
| 835 | { 0x001e08, 1, 0x04, 0x00000002 }, | ||
| 836 | { 0x001e28, 1, 0x04, 0x00000002 }, | ||
| 837 | { 0x001e48, 1, 0x04, 0x00000002 }, | ||
| 838 | { 0x001e68, 1, 0x04, 0x00000002 }, | ||
| 839 | { 0x001e88, 1, 0x04, 0x00000002 }, | ||
| 840 | { 0x001ea8, 1, 0x04, 0x00000002 }, | ||
| 841 | { 0x001ec8, 1, 0x04, 0x00000002 }, | ||
| 842 | { 0x001ee8, 1, 0x04, 0x00000002 }, | ||
| 843 | { 0x001e0c, 1, 0x04, 0x00000001 }, | ||
| 844 | { 0x001e2c, 1, 0x04, 0x00000001 }, | ||
| 845 | { 0x001e4c, 1, 0x04, 0x00000001 }, | ||
| 846 | { 0x001e6c, 1, 0x04, 0x00000001 }, | ||
| 847 | { 0x001e8c, 1, 0x04, 0x00000001 }, | ||
| 848 | { 0x001eac, 1, 0x04, 0x00000001 }, | ||
| 849 | { 0x001ecc, 1, 0x04, 0x00000001 }, | ||
| 850 | { 0x001eec, 1, 0x04, 0x00000001 }, | ||
| 851 | { 0x001e10, 1, 0x04, 0x00000001 }, | ||
| 852 | { 0x001e30, 1, 0x04, 0x00000001 }, | ||
| 853 | { 0x001e50, 1, 0x04, 0x00000001 }, | ||
| 854 | { 0x001e70, 1, 0x04, 0x00000001 }, | ||
| 855 | { 0x001e90, 1, 0x04, 0x00000001 }, | ||
| 856 | { 0x001eb0, 1, 0x04, 0x00000001 }, | ||
| 857 | { 0x001ed0, 1, 0x04, 0x00000001 }, | ||
| 858 | { 0x001ef0, 1, 0x04, 0x00000001 }, | ||
| 859 | { 0x001e14, 1, 0x04, 0x00000002 }, | ||
| 860 | { 0x001e34, 1, 0x04, 0x00000002 }, | ||
| 861 | { 0x001e54, 1, 0x04, 0x00000002 }, | ||
| 862 | { 0x001e74, 1, 0x04, 0x00000002 }, | ||
| 863 | { 0x001e94, 1, 0x04, 0x00000002 }, | ||
| 864 | { 0x001eb4, 1, 0x04, 0x00000002 }, | ||
| 865 | { 0x001ed4, 1, 0x04, 0x00000002 }, | ||
| 866 | { 0x001ef4, 1, 0x04, 0x00000002 }, | ||
| 867 | { 0x001e18, 1, 0x04, 0x00000001 }, | ||
| 868 | { 0x001e38, 1, 0x04, 0x00000001 }, | ||
| 869 | { 0x001e58, 1, 0x04, 0x00000001 }, | ||
| 870 | { 0x001e78, 1, 0x04, 0x00000001 }, | ||
| 871 | { 0x001e98, 1, 0x04, 0x00000001 }, | ||
| 872 | { 0x001eb8, 1, 0x04, 0x00000001 }, | ||
| 873 | { 0x001ed8, 1, 0x04, 0x00000001 }, | ||
| 874 | { 0x001ef8, 1, 0x04, 0x00000001 }, | ||
| 875 | { 0x003400, 128, 0x04, 0x00000000 }, | ||
| 876 | { 0x00030c, 1, 0x04, 0x00000001 }, | ||
| 877 | { 0x001944, 1, 0x04, 0x00000000 }, | ||
| 878 | { 0x001514, 1, 0x04, 0x00000000 }, | ||
| 879 | { 0x000d68, 1, 0x04, 0x0000ffff }, | ||
| 880 | { 0x00121c, 1, 0x04, 0x0fac6881 }, | ||
| 881 | { 0x000fac, 1, 0x04, 0x00000001 }, | ||
| 882 | { 0x001538, 1, 0x04, 0x00000001 }, | ||
| 883 | { 0x000fe0, 2, 0x04, 0x00000000 }, | ||
| 884 | { 0x000fe8, 1, 0x04, 0x00000014 }, | ||
| 885 | { 0x000fec, 1, 0x04, 0x00000040 }, | ||
| 886 | { 0x000ff0, 1, 0x04, 0x00000000 }, | ||
| 887 | { 0x00179c, 1, 0x04, 0x00000000 }, | ||
| 888 | { 0x001228, 1, 0x04, 0x00000400 }, | ||
| 889 | { 0x00122c, 1, 0x04, 0x00000300 }, | ||
| 890 | { 0x001230, 1, 0x04, 0x00010001 }, | ||
| 891 | { 0x0007f8, 1, 0x04, 0x00000000 }, | ||
| 892 | { 0x0015b4, 1, 0x04, 0x00000001 }, | ||
| 893 | { 0x0015cc, 1, 0x04, 0x00000000 }, | ||
| 894 | { 0x001534, 1, 0x04, 0x00000000 }, | ||
| 895 | { 0x000fb0, 1, 0x04, 0x00000000 }, | ||
| 896 | { 0x0015d0, 1, 0x04, 0x00000000 }, | ||
| 897 | { 0x00153c, 1, 0x04, 0x00000000 }, | ||
| 898 | { 0x0016b4, 1, 0x04, 0x00000003 }, | ||
| 899 | { 0x000fbc, 4, 0x04, 0x0000ffff }, | ||
| 900 | { 0x000df8, 2, 0x04, 0x00000000 }, | ||
| 901 | { 0x001948, 1, 0x04, 0x00000000 }, | ||
| 902 | { 0x001970, 1, 0x04, 0x00000001 }, | ||
| 903 | { 0x00161c, 1, 0x04, 0x000009f0 }, | ||
| 904 | { 0x000dcc, 1, 0x04, 0x00000010 }, | ||
| 905 | { 0x00163c, 1, 0x04, 0x00000000 }, | ||
| 906 | { 0x0015e4, 1, 0x04, 0x00000000 }, | ||
| 907 | { 0x001160, 32, 0x04, 0x25e00040 }, | ||
| 908 | { 0x001880, 32, 0x04, 0x00000000 }, | ||
| 909 | { 0x000f84, 2, 0x04, 0x00000000 }, | ||
| 910 | { 0x0017c8, 2, 0x04, 0x00000000 }, | ||
| 911 | { 0x0017d0, 1, 0x04, 0x000000ff }, | ||
| 912 | { 0x0017d4, 1, 0x04, 0xffffffff }, | ||
| 913 | { 0x0017d8, 1, 0x04, 0x00000002 }, | ||
| 914 | { 0x0017dc, 1, 0x04, 0x00000000 }, | ||
| 915 | { 0x0015f4, 2, 0x04, 0x00000000 }, | ||
| 916 | { 0x001434, 2, 0x04, 0x00000000 }, | ||
| 917 | { 0x000d74, 1, 0x04, 0x00000000 }, | ||
| 918 | { 0x000dec, 1, 0x04, 0x00000001 }, | ||
| 919 | { 0x0013a4, 1, 0x04, 0x00000000 }, | ||
| 920 | { 0x001318, 1, 0x04, 0x00000001 }, | ||
| 921 | { 0x001644, 1, 0x04, 0x00000000 }, | ||
| 922 | { 0x000748, 1, 0x04, 0x00000000 }, | ||
| 923 | { 0x000de8, 1, 0x04, 0x00000000 }, | ||
| 924 | { 0x001648, 1, 0x04, 0x00000000 }, | ||
| 925 | { 0x0012a4, 1, 0x04, 0x00000000 }, | ||
| 926 | { 0x001120, 4, 0x04, 0x00000000 }, | ||
| 927 | { 0x001118, 1, 0x04, 0x00000000 }, | ||
| 928 | { 0x00164c, 1, 0x04, 0x00000000 }, | ||
| 929 | { 0x001658, 1, 0x04, 0x00000000 }, | ||
| 930 | { 0x001910, 1, 0x04, 0x00000290 }, | ||
| 931 | { 0x001518, 1, 0x04, 0x00000000 }, | ||
| 932 | { 0x00165c, 1, 0x04, 0x00000001 }, | ||
| 933 | { 0x001520, 1, 0x04, 0x00000000 }, | ||
| 934 | { 0x001604, 1, 0x04, 0x00000000 }, | ||
| 935 | { 0x001570, 1, 0x04, 0x00000000 }, | ||
| 936 | { 0x0013b0, 2, 0x04, 0x3f800000 }, | ||
| 937 | { 0x00020c, 1, 0x04, 0x00000000 }, | ||
| 938 | { 0x001670, 1, 0x04, 0x30201000 }, | ||
| 939 | { 0x001674, 1, 0x04, 0x70605040 }, | ||
| 940 | { 0x001678, 1, 0x04, 0xb8a89888 }, | ||
| 941 | { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, | ||
| 942 | { 0x00166c, 1, 0x04, 0x00000000 }, | ||
| 943 | { 0x001680, 1, 0x04, 0x00ffff00 }, | ||
| 944 | { 0x0012d0, 1, 0x04, 0x00000003 }, | ||
| 945 | { 0x0012d4, 1, 0x04, 0x00000002 }, | ||
| 946 | { 0x001684, 2, 0x04, 0x00000000 }, | ||
| 947 | { 0x000dac, 2, 0x04, 0x00001b02 }, | ||
| 948 | { 0x000db4, 1, 0x04, 0x00000000 }, | ||
| 949 | { 0x00168c, 1, 0x04, 0x00000000 }, | ||
| 950 | { 0x0015bc, 1, 0x04, 0x00000000 }, | ||
| 951 | { 0x00156c, 1, 0x04, 0x00000000 }, | ||
| 952 | { 0x00187c, 1, 0x04, 0x00000000 }, | ||
| 953 | { 0x001110, 1, 0x04, 0x00000001 }, | ||
| 954 | { 0x000dc0, 3, 0x04, 0x00000000 }, | ||
| 955 | { 0x001234, 1, 0x04, 0x00000000 }, | ||
| 956 | { 0x001690, 1, 0x04, 0x00000000 }, | ||
| 957 | { 0x0012ac, 1, 0x04, 0x00000001 }, | ||
| 958 | { 0x0002c4, 1, 0x04, 0x00000000 }, | ||
| 959 | { 0x000790, 5, 0x04, 0x00000000 }, | ||
| 960 | { 0x00077c, 1, 0x04, 0x00000000 }, | ||
| 961 | { 0x001000, 1, 0x04, 0x00000010 }, | ||
| 962 | { 0x0010fc, 1, 0x04, 0x00000000 }, | ||
| 963 | { 0x001290, 1, 0x04, 0x00000000 }, | ||
| 964 | { 0x000218, 1, 0x04, 0x00000010 }, | ||
| 965 | { 0x0012d8, 1, 0x04, 0x00000000 }, | ||
| 966 | { 0x0012dc, 1, 0x04, 0x00000010 }, | ||
| 967 | { 0x000d94, 1, 0x04, 0x00000001 }, | ||
| 968 | { 0x00155c, 2, 0x04, 0x00000000 }, | ||
| 969 | { 0x001564, 1, 0x04, 0x00000fff }, | ||
| 970 | { 0x001574, 2, 0x04, 0x00000000 }, | ||
| 971 | { 0x00157c, 1, 0x04, 0x000fffff }, | ||
| 972 | { 0x001354, 1, 0x04, 0x00000000 }, | ||
| 973 | { 0x001610, 1, 0x04, 0x00000012 }, | ||
| 974 | { 0x001608, 2, 0x04, 0x00000000 }, | ||
| 975 | { 0x00260c, 1, 0x04, 0x00000000 }, | ||
| 976 | { 0x0007ac, 1, 0x04, 0x00000000 }, | ||
| 977 | { 0x00162c, 1, 0x04, 0x00000003 }, | ||
| 978 | { 0x000210, 1, 0x04, 0x00000000 }, | ||
| 979 | { 0x000320, 1, 0x04, 0x00000000 }, | ||
| 980 | { 0x000324, 6, 0x04, 0x3f800000 }, | ||
| 981 | { 0x000750, 1, 0x04, 0x00000000 }, | ||
| 982 | { 0x000760, 1, 0x04, 0x39291909 }, | ||
| 983 | { 0x000764, 1, 0x04, 0x79695949 }, | ||
| 984 | { 0x000768, 1, 0x04, 0xb9a99989 }, | ||
| 985 | { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, | ||
| 986 | { 0x000770, 1, 0x04, 0x30201000 }, | ||
| 987 | { 0x000774, 1, 0x04, 0x70605040 }, | ||
| 988 | { 0x000778, 1, 0x04, 0x00009080 }, | ||
| 989 | { 0x000780, 1, 0x04, 0x39291909 }, | ||
| 990 | { 0x000784, 1, 0x04, 0x79695949 }, | ||
| 991 | { 0x000788, 1, 0x04, 0xb9a99989 }, | ||
| 992 | { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, | ||
| 993 | { 0x0007d0, 1, 0x04, 0x30201000 }, | ||
| 994 | { 0x0007d4, 1, 0x04, 0x70605040 }, | ||
| 995 | { 0x0007d8, 1, 0x04, 0x00009080 }, | ||
| 996 | { 0x00037c, 1, 0x04, 0x00000001 }, | ||
| 997 | { 0x000740, 2, 0x04, 0x00000000 }, | ||
| 998 | { 0x002600, 1, 0x04, 0x00000000 }, | ||
| 999 | { 0x001918, 1, 0x04, 0x00000000 }, | ||
| 1000 | { 0x00191c, 1, 0x04, 0x00000900 }, | ||
| 1001 | { 0x001920, 1, 0x04, 0x00000405 }, | ||
| 1002 | { 0x001308, 1, 0x04, 0x00000001 }, | ||
| 1003 | { 0x001924, 1, 0x04, 0x00000000 }, | ||
| 1004 | { 0x0013ac, 1, 0x04, 0x00000000 }, | ||
| 1005 | { 0x00192c, 1, 0x04, 0x00000001 }, | ||
| 1006 | { 0x00193c, 1, 0x04, 0x00002c1c }, | ||
| 1007 | { 0x000d7c, 1, 0x04, 0x00000000 }, | ||
| 1008 | { 0x000f8c, 1, 0x04, 0x00000000 }, | ||
| 1009 | { 0x0002c0, 1, 0x04, 0x00000001 }, | ||
| 1010 | { 0x001510, 1, 0x04, 0x00000000 }, | ||
| 1011 | { 0x001940, 1, 0x04, 0x00000000 }, | ||
| 1012 | { 0x000ff4, 2, 0x04, 0x00000000 }, | ||
| 1013 | { 0x00194c, 2, 0x04, 0x00000000 }, | ||
| 1014 | { 0x001968, 1, 0x04, 0x00000000 }, | ||
| 1015 | { 0x001590, 1, 0x04, 0x0000003f }, | ||
| 1016 | { 0x0007e8, 4, 0x04, 0x00000000 }, | ||
| 1017 | { 0x00196c, 1, 0x04, 0x00000011 }, | ||
| 1018 | { 0x0002e4, 1, 0x04, 0x0000b001 }, | ||
| 1019 | { 0x00036c, 2, 0x04, 0x00000000 }, | ||
| 1020 | { 0x00197c, 1, 0x04, 0x00000000 }, | ||
| 1021 | { 0x000fcc, 2, 0x04, 0x00000000 }, | ||
| 1022 | { 0x0002d8, 1, 0x04, 0x00000040 }, | ||
| 1023 | { 0x001980, 1, 0x04, 0x00000080 }, | ||
| 1024 | { 0x001504, 1, 0x04, 0x00000080 }, | ||
| 1025 | { 0x001984, 1, 0x04, 0x00000000 }, | ||
| 1026 | { 0x000300, 1, 0x04, 0x00000001 }, | ||
| 1027 | { 0x0013a8, 1, 0x04, 0x00000000 }, | ||
| 1028 | { 0x0012ec, 1, 0x04, 0x00000000 }, | ||
| 1029 | { 0x001310, 1, 0x04, 0x00000000 }, | ||
| 1030 | { 0x001314, 1, 0x04, 0x00000001 }, | ||
| 1031 | { 0x001380, 1, 0x04, 0x00000000 }, | ||
| 1032 | { 0x001384, 4, 0x04, 0x00000001 }, | ||
| 1033 | { 0x001394, 1, 0x04, 0x00000000 }, | ||
| 1034 | { 0x00139c, 1, 0x04, 0x00000000 }, | ||
| 1035 | { 0x001398, 1, 0x04, 0x00000000 }, | ||
| 1036 | { 0x001594, 1, 0x04, 0x00000000 }, | ||
| 1037 | { 0x001598, 4, 0x04, 0x00000001 }, | ||
| 1038 | { 0x000f54, 3, 0x04, 0x00000000 }, | ||
| 1039 | { 0x0019bc, 1, 0x04, 0x00000000 }, | ||
| 1040 | { 0x000f9c, 2, 0x04, 0x00000000 }, | ||
| 1041 | { 0x0012cc, 1, 0x04, 0x00000000 }, | ||
| 1042 | { 0x0012e8, 1, 0x04, 0x00000000 }, | ||
| 1043 | { 0x00130c, 1, 0x04, 0x00000001 }, | ||
| 1044 | { 0x001360, 8, 0x04, 0x00000000 }, | ||
| 1045 | { 0x00133c, 2, 0x04, 0x00000001 }, | ||
| 1046 | { 0x001344, 1, 0x04, 0x00000002 }, | ||
| 1047 | { 0x001348, 2, 0x04, 0x00000001 }, | ||
| 1048 | { 0x001350, 1, 0x04, 0x00000002 }, | ||
| 1049 | { 0x001358, 1, 0x04, 0x00000001 }, | ||
| 1050 | { 0x0012e4, 1, 0x04, 0x00000000 }, | ||
| 1051 | { 0x00131c, 4, 0x04, 0x00000000 }, | ||
| 1052 | { 0x0019c0, 1, 0x04, 0x00000000 }, | ||
| 1053 | { 0x001140, 1, 0x04, 0x00000000 }, | ||
| 1054 | { 0x0019c4, 1, 0x04, 0x00000000 }, | ||
| 1055 | { 0x0019c8, 1, 0x04, 0x00001500 }, | ||
| 1056 | { 0x00135c, 1, 0x04, 0x00000000 }, | ||
| 1057 | { 0x000f90, 1, 0x04, 0x00000000 }, | ||
| 1058 | { 0x0019e0, 8, 0x04, 0x00000001 }, | ||
| 1059 | { 0x0019cc, 1, 0x04, 0x00000001 }, | ||
| 1060 | { 0x0015b8, 1, 0x04, 0x00000000 }, | ||
| 1061 | { 0x001a00, 1, 0x04, 0x00001111 }, | ||
| 1062 | { 0x001a04, 7, 0x04, 0x00000000 }, | ||
| 1063 | { 0x000d6c, 2, 0x04, 0xffff0000 }, | ||
| 1064 | { 0x0010f8, 1, 0x04, 0x00001010 }, | ||
| 1065 | { 0x000d80, 5, 0x04, 0x00000000 }, | ||
| 1066 | { 0x000da0, 1, 0x04, 0x00000000 }, | ||
| 1067 | { 0x0007a4, 2, 0x04, 0x00000000 }, | ||
| 1068 | { 0x001508, 1, 0x04, 0x80000000 }, | ||
| 1069 | { 0x00150c, 1, 0x04, 0x40000000 }, | ||
| 1070 | { 0x001668, 1, 0x04, 0x00000000 }, | ||
| 1071 | { 0x000318, 2, 0x04, 0x00000008 }, | ||
| 1072 | { 0x000d9c, 1, 0x04, 0x00000001 }, | ||
| 1073 | { 0x000ddc, 1, 0x04, 0x00000002 }, | ||
| 1074 | { 0x000374, 1, 0x04, 0x00000000 }, | ||
| 1075 | { 0x000378, 1, 0x04, 0x00000020 }, | ||
| 1076 | { 0x0007dc, 1, 0x04, 0x00000000 }, | ||
| 1077 | { 0x00074c, 1, 0x04, 0x00000055 }, | ||
| 1078 | { 0x001420, 1, 0x04, 0x00000003 }, | ||
| 1079 | { 0x0017bc, 2, 0x04, 0x00000000 }, | ||
| 1080 | { 0x0017c4, 1, 0x04, 0x00000001 }, | ||
| 1081 | { 0x001008, 1, 0x04, 0x00000008 }, | ||
| 1082 | { 0x00100c, 1, 0x04, 0x00000040 }, | ||
| 1083 | { 0x001010, 1, 0x04, 0x0000012c }, | ||
| 1084 | { 0x000d60, 1, 0x04, 0x00000040 }, | ||
| 1085 | { 0x00075c, 1, 0x04, 0x00000003 }, | ||
| 1086 | { 0x001018, 1, 0x04, 0x00000020 }, | ||
| 1087 | { 0x00101c, 1, 0x04, 0x00000001 }, | ||
| 1088 | { 0x001020, 1, 0x04, 0x00000020 }, | ||
| 1089 | { 0x001024, 1, 0x04, 0x00000001 }, | ||
| 1090 | { 0x001444, 3, 0x04, 0x00000000 }, | ||
| 1091 | { 0x000360, 1, 0x04, 0x20164010 }, | ||
| 1092 | { 0x000364, 1, 0x04, 0x00000020 }, | ||
| 1093 | { 0x000368, 1, 0x04, 0x00000000 }, | ||
| 1094 | { 0x000de4, 1, 0x04, 0x00000000 }, | ||
| 1095 | { 0x000204, 1, 0x04, 0x00000006 }, | ||
| 1096 | { 0x000208, 1, 0x04, 0x00000000 }, | ||
| 1097 | { 0x0002cc, 2, 0x04, 0x003fffff }, | ||
| 1098 | { 0x001220, 1, 0x04, 0x00000005 }, | ||
| 1099 | { 0x000fdc, 1, 0x04, 0x00000000 }, | ||
| 1100 | { 0x000f98, 1, 0x04, 0x00400008 }, | ||
| 1101 | { 0x001284, 1, 0x04, 0x08000080 }, | ||
| 1102 | { 0x001450, 1, 0x04, 0x00400008 }, | ||
| 1103 | { 0x001454, 1, 0x04, 0x08000080 }, | ||
| 1104 | { 0x000214, 1, 0x04, 0x00000000 }, | ||
| 1105 | {} | ||
| 1106 | }; | ||
| 1107 | |||
| 1108 | static struct nvc0_graph_init | ||
| 1109 | nv108_grctx_init_unk40xx[] = { | ||
| 1110 | { 0x404004, 8, 0x04, 0x00000000 }, | ||
| 1111 | { 0x404024, 1, 0x04, 0x0000e000 }, | ||
| 1112 | { 0x404028, 8, 0x04, 0x00000000 }, | ||
| 1113 | { 0x4040a8, 8, 0x04, 0x00000000 }, | ||
| 1114 | { 0x4040c8, 1, 0x04, 0xf800008f }, | ||
| 1115 | { 0x4040d0, 6, 0x04, 0x00000000 }, | ||
| 1116 | { 0x4040e8, 1, 0x04, 0x00001000 }, | ||
| 1117 | { 0x4040f8, 1, 0x04, 0x00000000 }, | ||
| 1118 | { 0x404100, 10, 0x04, 0x00000000 }, | ||
| 1119 | { 0x404130, 2, 0x04, 0x00000000 }, | ||
| 1120 | { 0x404138, 1, 0x04, 0x20000040 }, | ||
| 1121 | { 0x404150, 1, 0x04, 0x0000002e }, | ||
| 1122 | { 0x404154, 1, 0x04, 0x00000400 }, | ||
| 1123 | { 0x404158, 1, 0x04, 0x00000200 }, | ||
| 1124 | { 0x404164, 1, 0x04, 0x00000055 }, | ||
| 1125 | { 0x40417c, 2, 0x04, 0x00000000 }, | ||
| 1126 | { 0x404194, 1, 0x04, 0x01000700 }, | ||
| 1127 | { 0x4041a0, 4, 0x04, 0x00000000 }, | ||
| 1128 | { 0x404200, 1, 0x04, 0x0000a197 }, | ||
| 1129 | { 0x404204, 1, 0x04, 0x0000a1c0 }, | ||
| 1130 | { 0x404208, 1, 0x04, 0x0000a140 }, | ||
| 1131 | { 0x40420c, 1, 0x04, 0x0000902d }, | ||
| 1132 | {} | ||
| 1133 | }; | ||
| 1134 | |||
| 1135 | static struct nvc0_graph_init | ||
| 1136 | nv108_grctx_init_unk58xx[] = { | ||
| 1137 | { 0x405800, 1, 0x04, 0x0f8000bf }, | ||
| 1138 | { 0x405830, 1, 0x04, 0x02180648 }, | ||
| 1139 | { 0x405834, 1, 0x04, 0x08000000 }, | ||
| 1140 | { 0x405838, 1, 0x04, 0x00000000 }, | ||
| 1141 | { 0x405854, 1, 0x04, 0x00000000 }, | ||
| 1142 | { 0x405870, 4, 0x04, 0x00000001 }, | ||
| 1143 | { 0x405a00, 2, 0x04, 0x00000000 }, | ||
| 1144 | { 0x405a18, 1, 0x04, 0x00000000 }, | ||
| 1145 | { 0x405a1c, 1, 0x04, 0x000000ff }, | ||
| 1146 | {} | ||
| 1147 | }; | ||
| 1148 | |||
| 1149 | static struct nvc0_graph_init | ||
| 1150 | nv108_grctx_init_unk64xx[] = { | ||
| 1151 | { 0x4064a8, 1, 0x04, 0x00000000 }, | ||
| 1152 | { 0x4064ac, 1, 0x04, 0x00003fff }, | ||
| 1153 | { 0x4064b0, 3, 0x04, 0x00000000 }, | ||
| 1154 | { 0x4064c0, 1, 0x04, 0x802000f0 }, | ||
| 1155 | { 0x4064c4, 1, 0x04, 0x0192ffff }, | ||
| 1156 | { 0x4064c8, 1, 0x04, 0x00c20200 }, | ||
| 1157 | { 0x4064cc, 9, 0x04, 0x00000000 }, | ||
| 1158 | { 0x4064fc, 1, 0x04, 0x0000022a }, | ||
| 1159 | {} | ||
| 1160 | }; | ||
| 1161 | |||
| 1162 | static struct nvc0_graph_init | ||
| 1163 | nv108_grctx_init_unk78xx[] = { | ||
| 1164 | { 0x407804, 1, 0x04, 0x00000063 }, | ||
| 1165 | { 0x40780c, 1, 0x04, 0x0a418820 }, | ||
| 1166 | { 0x407810, 1, 0x04, 0x062080e6 }, | ||
| 1167 | { 0x407814, 1, 0x04, 0x020398a4 }, | ||
| 1168 | { 0x407818, 1, 0x04, 0x0e629062 }, | ||
| 1169 | { 0x40781c, 1, 0x04, 0x0a418820 }, | ||
| 1170 | { 0x407820, 1, 0x04, 0x000000e6 }, | ||
| 1171 | { 0x4078bc, 1, 0x04, 0x00000103 }, | ||
| 1172 | {} | ||
| 1173 | }; | ||
| 1174 | |||
| 1175 | static struct nvc0_graph_init | ||
| 1176 | nv108_grctx_init_unk88xx[] = { | ||
| 1177 | { 0x408800, 1, 0x04, 0x32802a3c }, | ||
| 1178 | { 0x408804, 1, 0x04, 0x00000040 }, | ||
| 1179 | { 0x408808, 1, 0x04, 0x1003e005 }, | ||
| 1180 | { 0x408840, 1, 0x04, 0x0000000b }, | ||
| 1181 | { 0x408900, 1, 0x04, 0xb080b801 }, | ||
| 1182 | { 0x408904, 1, 0x04, 0x62000001 }, | ||
| 1183 | { 0x408908, 1, 0x04, 0x02c8102f }, | ||
| 1184 | { 0x408980, 1, 0x04, 0x0000011d }, | ||
| 1185 | {} | ||
| 1186 | }; | ||
| 1187 | |||
| 1188 | static struct nvc0_graph_init | ||
| 1189 | nv108_grctx_init_gpc_0[] = { | ||
| 1190 | { 0x418380, 1, 0x04, 0x00000016 }, | ||
| 1191 | { 0x418400, 1, 0x04, 0x38005e00 }, | ||
| 1192 | { 0x418404, 1, 0x04, 0x71e0ffff }, | ||
| 1193 | { 0x41840c, 1, 0x04, 0x00001008 }, | ||
| 1194 | { 0x418410, 1, 0x04, 0x0fff0fff }, | ||
| 1195 | { 0x418414, 1, 0x04, 0x02200fff }, | ||
| 1196 | { 0x418450, 6, 0x04, 0x00000000 }, | ||
| 1197 | { 0x418468, 1, 0x04, 0x00000001 }, | ||
| 1198 | { 0x41846c, 2, 0x04, 0x00000000 }, | ||
| 1199 | { 0x418600, 1, 0x04, 0x0000007f }, | ||
| 1200 | { 0x418684, 1, 0x04, 0x0000001f }, | ||
| 1201 | { 0x418700, 1, 0x04, 0x00000002 }, | ||
| 1202 | { 0x418704, 2, 0x04, 0x00000080 }, | ||
| 1203 | { 0x41870c, 2, 0x04, 0x00000000 }, | ||
| 1204 | { 0x418800, 1, 0x04, 0x7006863a }, | ||
| 1205 | { 0x418808, 1, 0x04, 0x00000000 }, | ||
| 1206 | { 0x41880c, 1, 0x04, 0x00000030 }, | ||
| 1207 | { 0x418810, 1, 0x04, 0x00000000 }, | ||
| 1208 | { 0x418828, 1, 0x04, 0x00000044 }, | ||
| 1209 | { 0x418830, 1, 0x04, 0x10000001 }, | ||
| 1210 | { 0x4188d8, 1, 0x04, 0x00000008 }, | ||
| 1211 | { 0x4188e0, 1, 0x04, 0x01000000 }, | ||
| 1212 | { 0x4188e8, 5, 0x04, 0x00000000 }, | ||
| 1213 | { 0x4188fc, 1, 0x04, 0x20100058 }, | ||
| 1214 | { 0x41891c, 1, 0x04, 0x00ff00ff }, | ||
| 1215 | { 0x418924, 1, 0x04, 0x00000000 }, | ||
| 1216 | { 0x418928, 1, 0x04, 0x00ffff00 }, | ||
| 1217 | { 0x41892c, 1, 0x04, 0x0000ff00 }, | ||
| 1218 | { 0x418b00, 1, 0x04, 0x0000001e }, | ||
| 1219 | { 0x418b08, 1, 0x04, 0x0a418820 }, | ||
| 1220 | { 0x418b0c, 1, 0x04, 0x062080e6 }, | ||
| 1221 | { 0x418b10, 1, 0x04, 0x020398a4 }, | ||
| 1222 | { 0x418b14, 1, 0x04, 0x0e629062 }, | ||
| 1223 | { 0x418b18, 1, 0x04, 0x0a418820 }, | ||
| 1224 | { 0x418b1c, 1, 0x04, 0x000000e6 }, | ||
| 1225 | { 0x418bb8, 1, 0x04, 0x00000103 }, | ||
| 1226 | { 0x418c08, 1, 0x04, 0x00000001 }, | ||
| 1227 | { 0x418c10, 8, 0x04, 0x00000000 }, | ||
| 1228 | { 0x418c40, 1, 0x04, 0xffffffff }, | ||
| 1229 | { 0x418c6c, 1, 0x04, 0x00000001 }, | ||
| 1230 | { 0x418c80, 1, 0x04, 0x2020000c }, | ||
| 1231 | { 0x418c8c, 1, 0x04, 0x00000001 }, | ||
| 1232 | { 0x418d24, 1, 0x04, 0x00000000 }, | ||
| 1233 | { 0x419000, 1, 0x04, 0x00000780 }, | ||
| 1234 | { 0x419004, 2, 0x04, 0x00000000 }, | ||
| 1235 | { 0x419014, 1, 0x04, 0x00000004 }, | ||
| 1236 | {} | ||
| 1237 | }; | ||
| 1238 | |||
| 1239 | static struct nvc0_graph_init | ||
| 1240 | nv108_grctx_init_tpc[] = { | ||
| 1241 | { 0x419848, 1, 0x04, 0x00000000 }, | ||
| 1242 | { 0x419864, 1, 0x04, 0x00000129 }, | ||
| 1243 | { 0x419888, 1, 0x04, 0x00000000 }, | ||
| 1244 | { 0x419a00, 1, 0x04, 0x000100f0 }, | ||
| 1245 | { 0x419a04, 1, 0x04, 0x00000001 }, | ||
| 1246 | { 0x419a08, 1, 0x04, 0x00000421 }, | ||
| 1247 | { 0x419a0c, 1, 0x04, 0x00120000 }, | ||
| 1248 | { 0x419a10, 1, 0x04, 0x00000000 }, | ||
| 1249 | { 0x419a14, 1, 0x04, 0x00000200 }, | ||
| 1250 | { 0x419a1c, 1, 0x04, 0x0000c000 }, | ||
| 1251 | { 0x419a20, 1, 0x04, 0x00000800 }, | ||
| 1252 | { 0x419a30, 1, 0x04, 0x00000001 }, | ||
| 1253 | { 0x419ac4, 1, 0x04, 0x0037f440 }, | ||
| 1254 | { 0x419c00, 1, 0x04, 0x0000001a }, | ||
| 1255 | { 0x419c04, 1, 0x04, 0x80000006 }, | ||
| 1256 | { 0x419c08, 1, 0x04, 0x00000002 }, | ||
| 1257 | { 0x419c20, 1, 0x04, 0x00000000 }, | ||
| 1258 | { 0x419c24, 1, 0x04, 0x00084210 }, | ||
| 1259 | { 0x419c28, 1, 0x04, 0x3efbefbe }, | ||
| 1260 | { 0x419ce8, 1, 0x04, 0x00000000 }, | ||
| 1261 | { 0x419cf4, 1, 0x04, 0x00000203 }, | ||
| 1262 | { 0x419e04, 1, 0x04, 0x00000000 }, | ||
| 1263 | { 0x419e08, 1, 0x04, 0x0000001d }, | ||
| 1264 | { 0x419e0c, 1, 0x04, 0x00000000 }, | ||
| 1265 | { 0x419e10, 1, 0x04, 0x00001c02 }, | ||
| 1266 | { 0x419e44, 1, 0x04, 0x0013eff2 }, | ||
| 1267 | { 0x419e48, 1, 0x04, 0x00000000 }, | ||
| 1268 | { 0x419e4c, 1, 0x04, 0x0000007f }, | ||
| 1269 | { 0x419e50, 2, 0x04, 0x00000000 }, | ||
| 1270 | { 0x419e58, 1, 0x04, 0x00000001 }, | ||
| 1271 | { 0x419e5c, 3, 0x04, 0x00000000 }, | ||
| 1272 | { 0x419e68, 1, 0x04, 0x00000002 }, | ||
| 1273 | { 0x419e6c, 12, 0x04, 0x00000000 }, | ||
| 1274 | { 0x419eac, 1, 0x04, 0x00001f8f }, | ||
| 1275 | { 0x419eb0, 1, 0x04, 0x0db00da0 }, | ||
| 1276 | { 0x419eb8, 1, 0x04, 0x00000000 }, | ||
| 1277 | { 0x419ec8, 1, 0x04, 0x0001304f }, | ||
| 1278 | { 0x419f30, 4, 0x04, 0x00000000 }, | ||
| 1279 | { 0x419f40, 1, 0x04, 0x00000018 }, | ||
| 1280 | { 0x419f44, 3, 0x04, 0x00000000 }, | ||
| 1281 | { 0x419f58, 1, 0x04, 0x00000020 }, | ||
| 1282 | { 0x419f70, 1, 0x04, 0x00000000 }, | ||
| 1283 | { 0x419f78, 1, 0x04, 0x000001eb }, | ||
| 1284 | { 0x419f7c, 1, 0x04, 0x00000404 }, | ||
| 1285 | {} | ||
| 1286 | }; | ||
| 1287 | |||
| 1288 | static struct nvc0_graph_init | ||
| 1289 | nv108_grctx_init_unk[] = { | ||
| 1290 | { 0x41be24, 1, 0x04, 0x00000006 }, | ||
| 1291 | { 0x41bec0, 1, 0x04, 0x10000000 }, | ||
| 1292 | { 0x41bec4, 1, 0x04, 0x00037f7f }, | ||
| 1293 | { 0x41bee4, 1, 0x04, 0x00000000 }, | ||
| 1294 | { 0x41bef0, 1, 0x04, 0x000003ff }, | ||
| 1295 | { 0x41bf00, 1, 0x04, 0x0a418820 }, | ||
| 1296 | { 0x41bf04, 1, 0x04, 0x062080e6 }, | ||
| 1297 | { 0x41bf08, 1, 0x04, 0x020398a4 }, | ||
| 1298 | { 0x41bf0c, 1, 0x04, 0x0e629062 }, | ||
| 1299 | { 0x41bf10, 1, 0x04, 0x0a418820 }, | ||
| 1300 | { 0x41bf14, 1, 0x04, 0x000000e6 }, | ||
| 1301 | { 0x41bfd0, 1, 0x04, 0x00900103 }, | ||
| 1302 | { 0x41bfe0, 1, 0x04, 0x00400001 }, | ||
| 1303 | { 0x41bfe4, 1, 0x04, 0x00000000 }, | ||
| 1304 | {} | ||
| 1305 | }; | ||
| 1306 | |||
| 1307 | static void | ||
| 1308 | nv108_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) | ||
| 1309 | { | ||
| 1310 | u32 magic[GPC_MAX][2]; | ||
| 1311 | u32 offset; | ||
| 1312 | int gpc; | ||
| 1313 | |||
| 1314 | mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); | ||
| 1315 | mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS); | ||
| 1316 | mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW); | ||
| 1317 | mmio_list(0x40800c, 0x00000000, 8, 1); | ||
| 1318 | mmio_list(0x408010, 0x80000000, 0, 0); | ||
| 1319 | mmio_list(0x419004, 0x00000000, 8, 1); | ||
| 1320 | mmio_list(0x419008, 0x00000000, 0, 0); | ||
| 1321 | mmio_list(0x408004, 0x00000000, 8, 0); | ||
| 1322 | mmio_list(0x408008, 0x80000030, 0, 0); | ||
| 1323 | mmio_list(0x418808, 0x00000000, 8, 0); | ||
| 1324 | mmio_list(0x41880c, 0x80000030, 0, 0); | ||
| 1325 | mmio_list(0x418810, 0x80000000, 12, 2); | ||
| 1326 | mmio_list(0x419848, 0x10000000, 12, 2); | ||
| 1327 | |||
| 1328 | mmio_list(0x405830, 0x02180648, 0, 0); | ||
| 1329 | mmio_list(0x4064c4, 0x0192ffff, 0, 0); | ||
| 1330 | |||
| 1331 | for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) { | ||
| 1332 | u16 magic0 = 0x0218 * priv->tpc_nr[gpc]; | ||
| 1333 | u16 magic1 = 0x0648 * priv->tpc_nr[gpc]; | ||
| 1334 | magic[gpc][0] = 0x10000000 | (magic0 << 16) | offset; | ||
| 1335 | magic[gpc][1] = 0x00000000 | (magic1 << 16); | ||
| 1336 | offset += 0x0324 * priv->tpc_nr[gpc]; | ||
| 1337 | } | ||
| 1338 | |||
| 1339 | for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | ||
| 1340 | mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0); | ||
| 1341 | mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0); | ||
| 1342 | offset += 0x07ff * priv->tpc_nr[gpc]; | ||
| 1343 | } | ||
| 1344 | |||
| 1345 | mmio_list(0x17e91c, 0x0b040a0b, 0, 0); | ||
| 1346 | mmio_list(0x17e920, 0x00090d08, 0, 0); | ||
| 1347 | } | ||
| 1348 | |||
| 1349 | static struct nvc0_graph_init * | ||
| 1350 | nv108_grctx_init_hub[] = { | ||
| 1351 | nvc0_grctx_init_base, | ||
| 1352 | nv108_grctx_init_unk40xx, | ||
| 1353 | nvf0_grctx_init_unk44xx, | ||
| 1354 | nve4_grctx_init_unk46xx, | ||
| 1355 | nve4_grctx_init_unk47xx, | ||
| 1356 | nv108_grctx_init_unk58xx, | ||
| 1357 | nvf0_grctx_init_unk5bxx, | ||
| 1358 | nvf0_grctx_init_unk60xx, | ||
| 1359 | nv108_grctx_init_unk64xx, | ||
| 1360 | nv108_grctx_init_unk78xx, | ||
| 1361 | nve4_grctx_init_unk80xx, | ||
| 1362 | nv108_grctx_init_unk88xx, | ||
| 1363 | NULL | ||
| 1364 | }; | ||
| 1365 | |||
| 1366 | struct nvc0_graph_init * | ||
| 1367 | nv108_grctx_init_gpc[] = { | ||
| 1368 | nv108_grctx_init_gpc_0, | ||
| 1369 | nvc0_grctx_init_gpc_1, | ||
| 1370 | nv108_grctx_init_tpc, | ||
| 1371 | nv108_grctx_init_unk, | ||
| 1372 | NULL | ||
| 1373 | }; | ||
| 1374 | |||
| 1375 | struct nvc0_graph_init | ||
| 1376 | nv108_grctx_init_mthd_magic[] = { | ||
| 1377 | { 0x3410, 1, 0x04, 0x8e0e2006 }, | ||
| 1378 | { 0x3414, 1, 0x04, 0x00000038 }, | ||
| 1379 | {} | ||
| 1380 | }; | ||
| 1381 | |||
| 1382 | static struct nvc0_graph_mthd | ||
| 1383 | nv108_grctx_init_mthd[] = { | ||
| 1384 | { 0xa197, nv108_grctx_init_a197, }, | ||
| 1385 | { 0x902d, nvc0_grctx_init_902d, }, | ||
| 1386 | { 0x902d, nv108_grctx_init_mthd_magic, }, | ||
| 1387 | {} | ||
| 1388 | }; | ||
| 1389 | |||
| 1390 | struct nouveau_oclass * | ||
| 1391 | nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { | ||
| 1392 | .base.handle = NV_ENGCTX(GR, 0x08), | ||
| 1393 | .base.ofuncs = &(struct nouveau_ofuncs) { | ||
| 1394 | .ctor = nvc0_graph_context_ctor, | ||
| 1395 | .dtor = nvc0_graph_context_dtor, | ||
| 1396 | .init = _nouveau_graph_context_init, | ||
| 1397 | .fini = _nouveau_graph_context_fini, | ||
| 1398 | .rd32 = _nouveau_graph_context_rd32, | ||
| 1399 | .wr32 = _nouveau_graph_context_wr32, | ||
| 1400 | }, | ||
| 1401 | .main = nve4_grctx_generate_main, | ||
| 1402 | .mods = nv108_grctx_generate_mods, | ||
| 1403 | .unkn = nve4_grctx_generate_unkn, | ||
| 1404 | .hub = nv108_grctx_init_hub, | ||
| 1405 | .gpc = nv108_grctx_init_gpc, | ||
| 1406 | .icmd = nv108_grctx_init_icmd, | ||
| 1407 | .mthd = nv108_grctx_init_mthd, | ||
| 1408 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c index dcb2ebb8c29d..44012c3da538 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c | |||
| @@ -50,7 +50,7 @@ nvf0_grctx_init_unk40xx[] = { | |||
| 50 | {} | 50 | {} |
| 51 | }; | 51 | }; |
| 52 | 52 | ||
| 53 | static struct nvc0_graph_init | 53 | struct nvc0_graph_init |
| 54 | nvf0_grctx_init_unk44xx[] = { | 54 | nvf0_grctx_init_unk44xx[] = { |
| 55 | { 0x404404, 12, 0x04, 0x00000000 }, | 55 | { 0x404404, 12, 0x04, 0x00000000 }, |
| 56 | { 0x404438, 1, 0x04, 0x00000000 }, | 56 | { 0x404438, 1, 0x04, 0x00000000 }, |
| @@ -62,7 +62,7 @@ nvf0_grctx_init_unk44xx[] = { | |||
| 62 | {} | 62 | {} |
| 63 | }; | 63 | }; |
| 64 | 64 | ||
| 65 | static struct nvc0_graph_init | 65 | struct nvc0_graph_init |
| 66 | nvf0_grctx_init_unk5bxx[] = { | 66 | nvf0_grctx_init_unk5bxx[] = { |
| 67 | { 0x405b00, 1, 0x04, 0x00000000 }, | 67 | { 0x405b00, 1, 0x04, 0x00000000 }, |
| 68 | { 0x405b10, 1, 0x04, 0x00001000 }, | 68 | { 0x405b10, 1, 0x04, 0x00001000 }, |
| @@ -70,7 +70,7 @@ nvf0_grctx_init_unk5bxx[] = { | |||
| 70 | {} | 70 | {} |
| 71 | }; | 71 | }; |
| 72 | 72 | ||
| 73 | static struct nvc0_graph_init | 73 | struct nvc0_graph_init |
| 74 | nvf0_grctx_init_unk60xx[] = { | 74 | nvf0_grctx_init_unk60xx[] = { |
| 75 | { 0x406020, 1, 0x04, 0x034103c1 }, | 75 | { 0x406020, 1, 0x04, 0x034103c1 }, |
| 76 | { 0x406028, 4, 0x04, 0x00000001 }, | 76 | { 0x406028, 4, 0x04, 0x00000001 }, |
| @@ -286,7 +286,6 @@ nvf0_grctx_init_hub[] = { | |||
| 286 | nvf0_grctx_init_unk64xx, | 286 | nvf0_grctx_init_unk64xx, |
| 287 | nve4_grctx_init_unk80xx, | 287 | nve4_grctx_init_unk80xx, |
| 288 | nvf0_grctx_init_unk88xx, | 288 | nvf0_grctx_init_unk88xx, |
| 289 | nvd9_grctx_init_rop, | ||
| 290 | NULL | 289 | NULL |
| 291 | }; | 290 | }; |
| 292 | 291 | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc index 5d24b6de16cc..e148961b8075 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc | |||
| @@ -38,7 +38,7 @@ queue_put: | |||
| 38 | cmpu b32 $r8 $r9 | 38 | cmpu b32 $r8 $r9 |
| 39 | bra ne #queue_put_next | 39 | bra ne #queue_put_next |
| 40 | mov $r15 E_CMD_OVERFLOW | 40 | mov $r15 E_CMD_OVERFLOW |
| 41 | call #error | 41 | call(error) |
| 42 | ret | 42 | ret |
| 43 | 43 | ||
| 44 | // store cmd/data on queue | 44 | // store cmd/data on queue |
| @@ -92,18 +92,16 @@ queue_get_done: | |||
| 92 | // Out: $r15 value | 92 | // Out: $r15 value |
| 93 | // | 93 | // |
| 94 | nv_rd32: | 94 | nv_rd32: |
| 95 | mov $r11 0x728 | ||
| 96 | shl b32 $r11 6 | ||
| 97 | mov b32 $r12 $r14 | 95 | mov b32 $r12 $r14 |
| 98 | bset $r12 31 // MMIO_CTRL_PENDING | 96 | bset $r12 31 // MMIO_CTRL_PENDING |
| 99 | iowr I[$r11 + 0x000] $r12 // MMIO_CTRL | 97 | nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12) |
| 100 | nv_rd32_wait: | 98 | nv_rd32_wait: |
| 101 | iord $r12 I[$r11 + 0x000] | 99 | nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0) |
| 102 | xbit $r12 $r12 31 | 100 | xbit $r12 $r12 31 |
| 103 | bra ne #nv_rd32_wait | 101 | bra ne #nv_rd32_wait |
| 104 | mov $r10 6 // DONE_MMIO_RD | 102 | mov $r10 6 // DONE_MMIO_RD |
| 105 | call #wait_doneo | 103 | call(wait_doneo) |
| 106 | iord $r15 I[$r11 + 0x100] // MMIO_RDVAL | 104 | nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0) |
| 107 | ret | 105 | ret |
| 108 | 106 | ||
| 109 | // nv_wr32 - write 32-bit value to nv register | 107 | // nv_wr32 - write 32-bit value to nv register |
| @@ -112,37 +110,17 @@ nv_rd32: | |||
| 112 | // $r15 value | 110 | // $r15 value |
| 113 | // | 111 | // |
| 114 | nv_wr32: | 112 | nv_wr32: |
| 115 | mov $r11 0x728 | 113 | nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15) |
| 116 | shl b32 $r11 6 | ||
| 117 | iowr I[$r11 + 0x200] $r15 // MMIO_WRVAL | ||
| 118 | mov b32 $r12 $r14 | 114 | mov b32 $r12 $r14 |
| 119 | bset $r12 31 // MMIO_CTRL_PENDING | 115 | bset $r12 31 // MMIO_CTRL_PENDING |
| 120 | bset $r12 30 // MMIO_CTRL_WRITE | 116 | bset $r12 30 // MMIO_CTRL_WRITE |
| 121 | iowr I[$r11 + 0x000] $r12 // MMIO_CTRL | 117 | nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12) |
| 122 | nv_wr32_wait: | 118 | nv_wr32_wait: |
| 123 | iord $r12 I[$r11 + 0x000] | 119 | nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0) |
| 124 | xbit $r12 $r12 31 | 120 | xbit $r12 $r12 31 |
| 125 | bra ne #nv_wr32_wait | 121 | bra ne #nv_wr32_wait |
| 126 | ret | 122 | ret |
| 127 | 123 | ||
| 128 | // (re)set watchdog timer | ||
| 129 | // | ||
| 130 | // In : $r15 timeout | ||
| 131 | // | ||
| 132 | watchdog_reset: | ||
| 133 | mov $r8 0x430 | ||
| 134 | shl b32 $r8 6 | ||
| 135 | bset $r15 31 | ||
| 136 | iowr I[$r8 + 0x000] $r15 | ||
| 137 | ret | ||
| 138 | |||
| 139 | // clear watchdog timer | ||
| 140 | watchdog_clear: | ||
| 141 | mov $r8 0x430 | ||
| 142 | shl b32 $r8 6 | ||
| 143 | iowr I[$r8 + 0x000] $r0 | ||
| 144 | ret | ||
| 145 | |||
| 146 | // wait_donez - wait on FUC_DONE bit to become clear | 124 | // wait_donez - wait on FUC_DONE bit to become clear |
| 147 | // | 125 | // |
| 148 | // In : $r10 bit to wait on | 126 | // In : $r10 bit to wait on |
| @@ -163,13 +141,9 @@ wait_donez: | |||
| 163 | // | 141 | // |
| 164 | wait_doneo: | 142 | wait_doneo: |
| 165 | trace_set(T_WAIT); | 143 | trace_set(T_WAIT); |
| 166 | mov $r8 0x818 | 144 | nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10) |
| 167 | shl b32 $r8 6 | ||
| 168 | iowr I[$r8 + 0x000] $r10 | ||
| 169 | wait_doneo_e: | 145 | wait_doneo_e: |
| 170 | mov $r8 0x400 | 146 | nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0) |
| 171 | shl b32 $r8 6 | ||
| 172 | iord $r8 I[$r8 + 0x000] | ||
| 173 | xbit $r8 $r8 $r10 | 147 | xbit $r8 $r8 $r10 |
| 174 | bra e #wait_doneo_e | 148 | bra e #wait_doneo_e |
| 175 | trace_clr(T_WAIT) | 149 | trace_clr(T_WAIT) |
| @@ -209,21 +183,18 @@ mmctx_size: | |||
| 209 | // | 183 | // |
| 210 | mmctx_xfer: | 184 | mmctx_xfer: |
| 211 | trace_set(T_MMCTX) | 185 | trace_set(T_MMCTX) |
| 212 | mov $r8 0x710 | ||
| 213 | shl b32 $r8 6 | ||
| 214 | clear b32 $r9 | 186 | clear b32 $r9 |
| 215 | or $r11 $r11 | 187 | or $r11 $r11 |
| 216 | bra e #mmctx_base_disabled | 188 | bra e #mmctx_base_disabled |
| 217 | iowr I[$r8 + 0x000] $r11 // MMCTX_BASE | 189 | nv_iowr(NV_PGRAPH_FECS_MMCTX_BASE, 0, $r11) |
| 218 | bset $r9 0 // BASE_EN | 190 | bset $r9 0 // BASE_EN |
| 219 | mmctx_base_disabled: | 191 | mmctx_base_disabled: |
| 220 | or $r14 $r14 | 192 | or $r14 $r14 |
| 221 | bra e #mmctx_multi_disabled | 193 | bra e #mmctx_multi_disabled |
| 222 | iowr I[$r8 + 0x200] $r14 // MMCTX_MULTI_STRIDE | 194 | nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE, 0, $r14) |
| 223 | iowr I[$r8 + 0x300] $r15 // MMCTX_MULTI_MASK | 195 | nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_MASK, 0, $r15) |
| 224 | bset $r9 1 // MULTI_EN | 196 | bset $r9 1 // MULTI_EN |
| 225 | mmctx_multi_disabled: | 197 | mmctx_multi_disabled: |
| 226 | add b32 $r8 0x100 | ||
| 227 | 198 | ||
| 228 | xbit $r11 $r10 0 | 199 | xbit $r11 $r10 0 |
| 229 | shl b32 $r11 16 // DIR | 200 | shl b32 $r11 16 // DIR |
| @@ -231,20 +202,20 @@ mmctx_xfer: | |||
| 231 | xbit $r14 $r10 1 | 202 | xbit $r14 $r10 1 |
| 232 | shl b32 $r14 17 | 203 | shl b32 $r14 17 |
| 233 | or $r11 $r14 // START_TRIGGER | 204 | or $r11 $r14 // START_TRIGGER |
| 234 | iowr I[$r8 + 0x000] $r11 // MMCTX_CTRL | 205 | nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11) |
| 235 | 206 | ||
| 236 | // loop over the mmio list, and send requests to the hw | 207 | // loop over the mmio list, and send requests to the hw |
| 237 | mmctx_exec_loop: | 208 | mmctx_exec_loop: |
| 238 | // wait for space in mmctx queue | 209 | // wait for space in mmctx queue |
| 239 | mmctx_wait_free: | 210 | mmctx_wait_free: |
| 240 | iord $r14 I[$r8 + 0x000] // MMCTX_CTRL | 211 | nv_iord($r14, NV_PGRAPH_FECS_MMCTX_CTRL, 0) |
| 241 | and $r14 0x1f | 212 | and $r14 0x1f |
| 242 | bra e #mmctx_wait_free | 213 | bra e #mmctx_wait_free |
| 243 | 214 | ||
| 244 | // queue up an entry | 215 | // queue up an entry |
| 245 | ld b32 $r14 D[$r12] | 216 | ld b32 $r14 D[$r12] |
| 246 | or $r14 $r9 | 217 | or $r14 $r9 |
| 247 | iowr I[$r8 + 0x300] $r14 | 218 | nv_iowr(NV_PGRAPH_FECS_MMCTX_QUEUE, 0, $r14) |
| 248 | add b32 $r12 4 | 219 | add b32 $r12 4 |
| 249 | cmpu b32 $r12 $r13 | 220 | cmpu b32 $r12 $r13 |
| 250 | bra ne #mmctx_exec_loop | 221 | bra ne #mmctx_exec_loop |
| @@ -253,22 +224,22 @@ mmctx_xfer: | |||
| 253 | bra ne #mmctx_stop | 224 | bra ne #mmctx_stop |
| 254 | // wait for queue to empty | 225 | // wait for queue to empty |
| 255 | mmctx_fini_wait: | 226 | mmctx_fini_wait: |
| 256 | iord $r11 I[$r8 + 0x000] // MMCTX_CTRL | 227 | nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0) |
| 257 | and $r11 0x1f | 228 | and $r11 0x1f |
| 258 | cmpu b32 $r11 0x10 | 229 | cmpu b32 $r11 0x10 |
| 259 | bra ne #mmctx_fini_wait | 230 | bra ne #mmctx_fini_wait |
| 260 | mov $r10 2 // DONE_MMCTX | 231 | mov $r10 2 // DONE_MMCTX |
| 261 | call #wait_donez | 232 | call(wait_donez) |
| 262 | bra #mmctx_done | 233 | bra #mmctx_done |
| 263 | mmctx_stop: | 234 | mmctx_stop: |
| 264 | xbit $r11 $r10 0 | 235 | xbit $r11 $r10 0 |
| 265 | shl b32 $r11 16 // DIR | 236 | shl b32 $r11 16 // DIR |
| 266 | bset $r11 12 // QLIMIT = 0x10 | 237 | bset $r11 12 // QLIMIT = 0x10 |
| 267 | bset $r11 18 // STOP_TRIGGER | 238 | bset $r11 18 // STOP_TRIGGER |
| 268 | iowr I[$r8 + 0x000] $r11 // MMCTX_CTRL | 239 | nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11) |
| 269 | mmctx_stop_wait: | 240 | mmctx_stop_wait: |
| 270 | // wait for STOP_TRIGGER to clear | 241 | // wait for STOP_TRIGGER to clear |
| 271 | iord $r11 I[$r8 + 0x000] // MMCTX_CTRL | 242 | nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0) |
| 272 | xbit $r11 $r11 18 | 243 | xbit $r11 $r11 18 |
| 273 | bra ne #mmctx_stop_wait | 244 | bra ne #mmctx_stop_wait |
| 274 | mmctx_done: | 245 | mmctx_done: |
| @@ -280,28 +251,24 @@ mmctx_xfer: | |||
| 280 | strand_wait: | 251 | strand_wait: |
| 281 | push $r10 | 252 | push $r10 |
| 282 | mov $r10 2 | 253 | mov $r10 2 |
| 283 | call #wait_donez | 254 | call(wait_donez) |
| 284 | pop $r10 | 255 | pop $r10 |
| 285 | ret | 256 | ret |
| 286 | 257 | ||
| 287 | // unknown - call before issuing strand commands | 258 | // unknown - call before issuing strand commands |
| 288 | // | 259 | // |
| 289 | strand_pre: | 260 | strand_pre: |
| 290 | mov $r8 0x4afc | 261 | mov $r9 NV_PGRAPH_FECS_STRAND_CMD_ENABLE |
| 291 | sethi $r8 0x20000 | 262 | nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9) |
| 292 | mov $r9 0xc | 263 | call(strand_wait) |
| 293 | iowr I[$r8] $r9 | ||
| 294 | call #strand_wait | ||
| 295 | ret | 264 | ret |
| 296 | 265 | ||
| 297 | // unknown - call after issuing strand commands | 266 | // unknown - call after issuing strand commands |
| 298 | // | 267 | // |
| 299 | strand_post: | 268 | strand_post: |
| 300 | mov $r8 0x4afc | 269 | mov $r9 NV_PGRAPH_FECS_STRAND_CMD_DISABLE |
| 301 | sethi $r8 0x20000 | 270 | nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9) |
| 302 | mov $r9 0xd | 271 | call(strand_wait) |
| 303 | iowr I[$r8] $r9 | ||
| 304 | call #strand_wait | ||
| 305 | ret | 272 | ret |
| 306 | 273 | ||
| 307 | // Selects strand set?! | 274 | // Selects strand set?! |
| @@ -309,18 +276,14 @@ strand_post: | |||
| 309 | // In: $r14 id | 276 | // In: $r14 id |
| 310 | // | 277 | // |
| 311 | strand_set: | 278 | strand_set: |
| 312 | mov $r10 0x4ffc | ||
| 313 | sethi $r10 0x20000 | ||
| 314 | sub b32 $r11 $r10 0x500 | ||
| 315 | mov $r12 0xf | 279 | mov $r12 0xf |
| 316 | iowr I[$r10 + 0x000] $r12 // 0x93c = 0xf | 280 | nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r12) |
| 317 | mov $r12 0xb | 281 | mov $r12 NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER |
| 318 | iowr I[$r11 + 0x000] $r12 // 0x928 = 0xb | 282 | nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) |
| 319 | call #strand_wait | 283 | nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r14) |
| 320 | iowr I[$r10 + 0x000] $r14 // 0x93c = <id> | 284 | mov $r12 NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER |
| 321 | mov $r12 0xa | 285 | nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) |
| 322 | iowr I[$r11 + 0x000] $r12 // 0x928 = 0xa | 286 | call(strand_wait) |
| 323 | call #strand_wait | ||
| 324 | ret | 287 | ret |
| 325 | 288 | ||
| 326 | // Initialise strand context data | 289 | // Initialise strand context data |
| @@ -332,30 +295,27 @@ strand_set: | |||
| 332 | // | 295 | // |
| 333 | strand_ctx_init: | 296 | strand_ctx_init: |
| 334 | trace_set(T_STRINIT) | 297 | trace_set(T_STRINIT) |
| 335 | call #strand_pre | 298 | call(strand_pre) |
| 336 | mov $r14 3 | 299 | mov $r14 3 |
| 337 | call #strand_set | 300 | call(strand_set) |
| 338 | mov $r10 0x46fc | 301 | |
| 339 | sethi $r10 0x20000 | 302 | clear b32 $r12 |
| 340 | add b32 $r11 $r10 0x400 | 303 | nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r12) |
| 341 | iowr I[$r10 + 0x100] $r0 // STRAND_FIRST_GENE = 0 | 304 | mov $r12 NV_PGRAPH_FECS_STRAND_CMD_SEEK |
| 342 | mov $r12 1 | 305 | nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) |
| 343 | iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_FIRST_GENE | 306 | call(strand_wait) |
| 344 | call #strand_wait | ||
| 345 | sub b32 $r12 $r0 1 | 307 | sub b32 $r12 $r0 1 |
| 346 | iowr I[$r10 + 0x000] $r12 // STRAND_GENE_CNT = 0xffffffff | 308 | nv_iowr(NV_PGRAPH_FECS_STRAND_DATA, 0x3f, $r12) |
| 347 | mov $r12 2 | 309 | mov $r12 NV_PGRAPH_FECS_STRAND_CMD_GET_INFO |
| 348 | iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_GENE_CNT | 310 | nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) |
| 349 | call #strand_wait | 311 | call(strand_wait) |
| 350 | call #strand_post | 312 | call(strand_post) |
| 351 | 313 | ||
| 352 | // read the size of each strand, poke the context offset of | 314 | // read the size of each strand, poke the context offset of |
| 353 | // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry | 315 | // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry |
| 354 | // about it later then. | 316 | // about it later then. |
| 355 | mov $r8 0x880 | 317 | nv_mkio($r8, NV_PGRAPH_FECS_STRAND_SAVE_SWBASE, 0x00) |
| 356 | shl b32 $r8 6 | 318 | nv_iord($r9, NV_PGRAPH_FECS_STRANDS_CNT, 0x00) |
| 357 | iord $r9 I[$r8 + 0x000] // STRANDS | ||
| 358 | add b32 $r8 0x2200 | ||
| 359 | shr b32 $r14 $r15 8 | 319 | shr b32 $r14 $r15 8 |
| 360 | ctx_init_strand_loop: | 320 | ctx_init_strand_loop: |
| 361 | iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE | 321 | iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc index 5547c1b3f4f2..96cbcea3b2c9 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc | |||
| @@ -58,12 +58,9 @@ mmio_list_base: | |||
| 58 | // | 58 | // |
| 59 | error: | 59 | error: |
| 60 | push $r14 | 60 | push $r14 |
| 61 | mov $r14 -0x67ec // 0x9814 | 61 | nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15) |
| 62 | sethi $r14 0x400000 | ||
| 63 | call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code | ||
| 64 | add b32 $r14 0x41c | ||
| 65 | mov $r15 1 | 62 | mov $r15 1 |
| 66 | call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET | 63 | nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15) |
| 67 | pop $r14 | 64 | pop $r14 |
| 68 | ret | 65 | ret |
| 69 | 66 | ||
| @@ -84,46 +81,40 @@ init: | |||
| 84 | mov $sp $r0 | 81 | mov $sp $r0 |
| 85 | 82 | ||
| 86 | // enable fifo access | 83 | // enable fifo access |
| 87 | mov $r1 0x1200 | 84 | mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO |
| 88 | mov $r2 2 | 85 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2) |
| 89 | iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE | ||
| 90 | 86 | ||
| 91 | // setup i0 handler, and route all interrupts to it | 87 | // setup i0 handler, and route all interrupts to it |
| 92 | mov $r1 #ih | 88 | mov $r1 #ih |
| 93 | mov $iv0 $r1 | 89 | mov $iv0 $r1 |
| 94 | mov $r1 0x400 | 90 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0) |
| 95 | iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH | ||
| 96 | 91 | ||
| 97 | // enable fifo interrupt | 92 | // enable fifo interrupt |
| 98 | mov $r2 4 | 93 | mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO |
| 99 | iowr I[$r1 + 0x000] $r2 // INTR_EN_SET | 94 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2) |
| 100 | 95 | ||
| 101 | // enable interrupts | 96 | // enable interrupts |
| 102 | bset $flags ie0 | 97 | bset $flags ie0 |
| 103 | 98 | ||
| 104 | // figure out which GPC we are, and how many TPCs we have | 99 | // figure out which GPC we are, and how many TPCs we have |
| 105 | mov $r1 0x608 | 100 | nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0) |
| 106 | shl b32 $r1 6 | ||
| 107 | iord $r2 I[$r1 + 0x000] // UNITS | ||
| 108 | mov $r3 1 | 101 | mov $r3 1 |
| 109 | and $r2 0x1f | 102 | and $r2 0x1f |
| 110 | shl b32 $r3 $r2 | 103 | shl b32 $r3 $r2 |
| 111 | sub b32 $r3 1 | 104 | sub b32 $r3 1 |
| 112 | st b32 D[$r0 + #tpc_count] $r2 | 105 | st b32 D[$r0 + #tpc_count] $r2 |
| 113 | st b32 D[$r0 + #tpc_mask] $r3 | 106 | st b32 D[$r0 + #tpc_mask] $r3 |
| 114 | add b32 $r1 0x400 | 107 | nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0) |
| 115 | iord $r2 I[$r1 + 0x000] // MYINDEX | ||
| 116 | st b32 D[$r0 + #gpc_id] $r2 | 108 | st b32 D[$r0 + #gpc_id] $r2 |
| 117 | 109 | ||
| 118 | #if NV_PGRAPH_GPCX_UNK__SIZE > 0 | 110 | #if NV_PGRAPH_GPCX_UNK__SIZE > 0 |
| 119 | // figure out which, and how many, UNKs are actually present | 111 | // figure out which, and how many, UNKs are actually present |
| 120 | mov $r14 0x0c30 | 112 | imm32($r14, 0x500c30) |
| 121 | sethi $r14 0x500000 | ||
| 122 | clear b32 $r2 | 113 | clear b32 $r2 |
| 123 | clear b32 $r3 | 114 | clear b32 $r3 |
| 124 | clear b32 $r4 | 115 | clear b32 $r4 |
| 125 | init_unk_loop: | 116 | init_unk_loop: |
| 126 | call #nv_rd32 | 117 | call(nv_rd32) |
| 127 | cmp b32 $r15 0 | 118 | cmp b32 $r15 0 |
| 128 | bra z #init_unk_next | 119 | bra z #init_unk_next |
| 129 | mov $r15 1 | 120 | mov $r15 1 |
| @@ -146,23 +137,21 @@ init: | |||
| 146 | 137 | ||
| 147 | // set mmctx base addresses now so we don't have to do it later, | 138 | // set mmctx base addresses now so we don't have to do it later, |
| 148 | // they don't currently ever change | 139 | // they don't currently ever change |
| 149 | mov $r4 0x700 | ||
| 150 | shl b32 $r4 6 | ||
| 151 | shr b32 $r5 $r2 8 | 140 | shr b32 $r5 $r2 8 |
| 152 | iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE | 141 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5) |
| 153 | iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE | 142 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5) |
| 154 | 143 | ||
| 155 | // calculate GPC mmio context size | 144 | // calculate GPC mmio context size |
| 156 | ld b32 $r14 D[$r0 + #gpc_mmio_list_head] | 145 | ld b32 $r14 D[$r0 + #gpc_mmio_list_head] |
| 157 | ld b32 $r15 D[$r0 + #gpc_mmio_list_tail] | 146 | ld b32 $r15 D[$r0 + #gpc_mmio_list_tail] |
| 158 | call #mmctx_size | 147 | call(mmctx_size) |
| 159 | add b32 $r2 $r15 | 148 | add b32 $r2 $r15 |
| 160 | add b32 $r3 $r15 | 149 | add b32 $r3 $r15 |
| 161 | 150 | ||
| 162 | // calculate per-TPC mmio context size | 151 | // calculate per-TPC mmio context size |
| 163 | ld b32 $r14 D[$r0 + #tpc_mmio_list_head] | 152 | ld b32 $r14 D[$r0 + #tpc_mmio_list_head] |
| 164 | ld b32 $r15 D[$r0 + #tpc_mmio_list_tail] | 153 | ld b32 $r15 D[$r0 + #tpc_mmio_list_tail] |
| 165 | call #mmctx_size | 154 | call(mmctx_size) |
| 166 | ld b32 $r14 D[$r0 + #tpc_count] | 155 | ld b32 $r14 D[$r0 + #tpc_count] |
| 167 | mulu $r14 $r15 | 156 | mulu $r14 $r15 |
| 168 | add b32 $r2 $r14 | 157 | add b32 $r2 $r14 |
| @@ -172,7 +161,7 @@ init: | |||
| 172 | // calculate per-UNK mmio context size | 161 | // calculate per-UNK mmio context size |
| 173 | ld b32 $r14 D[$r0 + #unk_mmio_list_head] | 162 | ld b32 $r14 D[$r0 + #unk_mmio_list_head] |
| 174 | ld b32 $r15 D[$r0 + #unk_mmio_list_tail] | 163 | ld b32 $r15 D[$r0 + #unk_mmio_list_tail] |
| 175 | call #mmctx_size | 164 | call(mmctx_size) |
| 176 | ld b32 $r14 D[$r0 + #unk_count] | 165 | ld b32 $r14 D[$r0 + #unk_count] |
| 177 | mulu $r14 $r15 | 166 | mulu $r14 $r15 |
| 178 | add b32 $r2 $r14 | 167 | add b32 $r2 $r14 |
| @@ -180,9 +169,8 @@ init: | |||
| 180 | #endif | 169 | #endif |
| 181 | 170 | ||
| 182 | // round up base/size to 256 byte boundary (for strand SWBASE) | 171 | // round up base/size to 256 byte boundary (for strand SWBASE) |
| 183 | add b32 $r4 0x1300 | ||
| 184 | shr b32 $r3 2 | 172 | shr b32 $r3 2 |
| 185 | iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!? | 173 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?! |
| 186 | shr b32 $r2 8 | 174 | shr b32 $r2 8 |
| 187 | shr b32 $r3 6 | 175 | shr b32 $r3 6 |
| 188 | add b32 $r2 1 | 176 | add b32 $r2 1 |
| @@ -192,7 +180,7 @@ init: | |||
| 192 | 180 | ||
| 193 | // calculate size of strand context data | 181 | // calculate size of strand context data |
| 194 | mov b32 $r15 $r2 | 182 | mov b32 $r15 $r2 |
| 195 | call #strand_ctx_init | 183 | call(strand_ctx_init) |
| 196 | add b32 $r3 $r15 | 184 | add b32 $r3 $r15 |
| 197 | 185 | ||
| 198 | // save context size, and tell HUB we're done | 186 | // save context size, and tell HUB we're done |
| @@ -208,7 +196,7 @@ main: | |||
| 208 | bset $flags $p0 | 196 | bset $flags $p0 |
| 209 | sleep $p0 | 197 | sleep $p0 |
| 210 | mov $r13 #cmd_queue | 198 | mov $r13 #cmd_queue |
| 211 | call #queue_get | 199 | call(queue_get) |
| 212 | bra $p1 #main | 200 | bra $p1 #main |
| 213 | 201 | ||
| 214 | // 0x0000-0x0003 are all context transfers | 202 | // 0x0000-0x0003 are all context transfers |
| @@ -224,13 +212,13 @@ main: | |||
| 224 | or $r1 $r14 | 212 | or $r1 $r14 |
| 225 | mov $flags $r1 | 213 | mov $flags $r1 |
| 226 | // transfer context data | 214 | // transfer context data |
| 227 | call #ctx_xfer | 215 | call(ctx_xfer) |
| 228 | bra #main | 216 | bra #main |
| 229 | 217 | ||
| 230 | main_not_ctx_xfer: | 218 | main_not_ctx_xfer: |
| 231 | shl b32 $r15 $r14 16 | 219 | shl b32 $r15 $r14 16 |
| 232 | or $r15 E_BAD_COMMAND | 220 | or $r15 E_BAD_COMMAND |
| 233 | call #error | 221 | call(error) |
| 234 | bra #main | 222 | bra #main |
| 235 | 223 | ||
| 236 | // interrupt handler | 224 | // interrupt handler |
| @@ -247,22 +235,20 @@ ih: | |||
| 247 | clear b32 $r0 | 235 | clear b32 $r0 |
| 248 | 236 | ||
| 249 | // incoming fifo command? | 237 | // incoming fifo command? |
| 250 | iord $r10 I[$r0 + 0x200] // INTR | 238 | nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0) |
| 251 | and $r11 $r10 0x00000004 | 239 | and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO |
| 252 | bra e #ih_no_fifo | 240 | bra e #ih_no_fifo |
| 253 | // queue incoming fifo command for later processing | 241 | // queue incoming fifo command for later processing |
| 254 | mov $r11 0x1900 | ||
| 255 | mov $r13 #cmd_queue | 242 | mov $r13 #cmd_queue |
| 256 | iord $r14 I[$r11 + 0x100] // FIFO_CMD | 243 | nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0) |
| 257 | iord $r15 I[$r11 + 0x000] // FIFO_DATA | 244 | nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0) |
| 258 | call #queue_put | 245 | call(queue_put) |
| 259 | add b32 $r11 0x400 | ||
| 260 | mov $r14 1 | 246 | mov $r14 1 |
| 261 | iowr I[$r11 + 0x000] $r14 // FIFO_ACK | 247 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14) |
| 262 | 248 | ||
| 263 | // ack, and wake up main() | 249 | // ack, and wake up main() |
| 264 | ih_no_fifo: | 250 | ih_no_fifo: |
| 265 | iowr I[$r0 + 0x100] $r10 // INTR_ACK | 251 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10) |
| 266 | 252 | ||
| 267 | pop $r15 | 253 | pop $r15 |
| 268 | pop $r14 | 254 | pop $r14 |
| @@ -283,9 +269,7 @@ hub_barrier_done: | |||
| 283 | mov $r15 1 | 269 | mov $r15 1 |
| 284 | ld b32 $r14 D[$r0 + #gpc_id] | 270 | ld b32 $r14 D[$r0 + #gpc_id] |
| 285 | shl b32 $r15 $r14 | 271 | shl b32 $r15 $r14 |
| 286 | mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET | 272 | nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET |
| 287 | sethi $r14 0x400000 | ||
| 288 | call #nv_wr32 | ||
| 289 | ret | 273 | ret |
| 290 | 274 | ||
| 291 | // Disables various things, waits a bit, and re-enables them.. | 275 | // Disables various things, waits a bit, and re-enables them.. |
| @@ -295,16 +279,15 @@ hub_barrier_done: | |||
| 295 | // funny things happen. | 279 | // funny things happen. |
| 296 | // | 280 | // |
| 297 | ctx_redswitch: | 281 | ctx_redswitch: |
| 298 | mov $r14 0x614 | 282 | mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER |
| 299 | shl b32 $r14 6 | 283 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15) |
| 300 | mov $r15 0x020 | 284 | mov $r14 8 |
| 301 | iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER | ||
| 302 | mov $r15 8 | ||
| 303 | ctx_redswitch_delay: | 285 | ctx_redswitch_delay: |
| 304 | sub b32 $r15 1 | 286 | sub b32 $r14 1 |
| 305 | bra ne #ctx_redswitch_delay | 287 | bra ne #ctx_redswitch_delay |
| 306 | mov $r15 0xa20 | 288 | or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 |
| 307 | iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER | 289 | or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE |
| 290 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15) | ||
| 308 | ret | 291 | ret |
| 309 | 292 | ||
| 310 | // Transfer GPC context data between GPU and storage area | 293 | // Transfer GPC context data between GPU and storage area |
| @@ -317,46 +300,37 @@ ctx_redswitch: | |||
| 317 | // | 300 | // |
| 318 | ctx_xfer: | 301 | ctx_xfer: |
| 319 | // set context base address | 302 | // set context base address |
| 320 | mov $r1 0xa04 | 303 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15) |
| 321 | shl b32 $r1 6 | ||
| 322 | iowr I[$r1 + 0x000] $r15// MEM_BASE | ||
| 323 | bra not $p1 #ctx_xfer_not_load | 304 | bra not $p1 #ctx_xfer_not_load |
| 324 | call #ctx_redswitch | 305 | call(ctx_redswitch) |
| 325 | ctx_xfer_not_load: | 306 | ctx_xfer_not_load: |
| 326 | 307 | ||
| 327 | // strands | 308 | // strands |
| 328 | mov $r1 0x4afc | 309 | call(strand_pre) |
| 329 | sethi $r1 0x20000 | 310 | clear b32 $r2 |
| 330 | mov $r2 0xc | 311 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2) |
| 331 | iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c | 312 | xbit $r2 $flags $p1 // SAVE/LOAD |
| 332 | call #strand_wait | 313 | add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE |
| 333 | mov $r2 0x47fc | 314 | nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2) |
| 334 | sethi $r2 0x20000 | ||
| 335 | iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00 | ||
| 336 | xbit $r2 $flags $p1 | ||
| 337 | add b32 $r2 3 | ||
| 338 | iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD) | ||
| 339 | 315 | ||
| 340 | // mmio context | 316 | // mmio context |
| 341 | xbit $r10 $flags $p1 // direction | 317 | xbit $r10 $flags $p1 // direction |
| 342 | or $r10 2 // first | 318 | or $r10 2 // first |
| 343 | mov $r11 0x0000 | 319 | imm32($r11,0x500000) |
| 344 | sethi $r11 0x500000 | ||
| 345 | ld b32 $r12 D[$r0 + #gpc_id] | 320 | ld b32 $r12 D[$r0 + #gpc_id] |
| 346 | shl b32 $r12 15 | 321 | shl b32 $r12 15 |
| 347 | add b32 $r11 $r12 // base = NV_PGRAPH_GPCn | 322 | add b32 $r11 $r12 // base = NV_PGRAPH_GPCn |
| 348 | ld b32 $r12 D[$r0 + #gpc_mmio_list_head] | 323 | ld b32 $r12 D[$r0 + #gpc_mmio_list_head] |
| 349 | ld b32 $r13 D[$r0 + #gpc_mmio_list_tail] | 324 | ld b32 $r13 D[$r0 + #gpc_mmio_list_tail] |
| 350 | mov $r14 0 // not multi | 325 | mov $r14 0 // not multi |
| 351 | call #mmctx_xfer | 326 | call(mmctx_xfer) |
| 352 | 327 | ||
| 353 | // per-TPC mmio context | 328 | // per-TPC mmio context |
| 354 | xbit $r10 $flags $p1 // direction | 329 | xbit $r10 $flags $p1 // direction |
| 355 | #if !NV_PGRAPH_GPCX_UNK__SIZE | 330 | #if !NV_PGRAPH_GPCX_UNK__SIZE |
| 356 | or $r10 4 // last | 331 | or $r10 4 // last |
| 357 | #endif | 332 | #endif |
| 358 | mov $r11 0x4000 | 333 | imm32($r11, 0x504000) |
| 359 | sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0 | ||
| 360 | ld b32 $r12 D[$r0 + #gpc_id] | 334 | ld b32 $r12 D[$r0 + #gpc_id] |
| 361 | shl b32 $r12 15 | 335 | shl b32 $r12 15 |
| 362 | add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0 | 336 | add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0 |
| @@ -364,14 +338,13 @@ ctx_xfer: | |||
| 364 | ld b32 $r13 D[$r0 + #tpc_mmio_list_tail] | 338 | ld b32 $r13 D[$r0 + #tpc_mmio_list_tail] |
| 365 | ld b32 $r15 D[$r0 + #tpc_mask] | 339 | ld b32 $r15 D[$r0 + #tpc_mask] |
| 366 | mov $r14 0x800 // stride = 0x800 | 340 | mov $r14 0x800 // stride = 0x800 |
| 367 | call #mmctx_xfer | 341 | call(mmctx_xfer) |
| 368 | 342 | ||
| 369 | #if NV_PGRAPH_GPCX_UNK__SIZE > 0 | 343 | #if NV_PGRAPH_GPCX_UNK__SIZE > 0 |
| 370 | // per-UNK mmio context | 344 | // per-UNK mmio context |
| 371 | xbit $r10 $flags $p1 // direction | 345 | xbit $r10 $flags $p1 // direction |
| 372 | or $r10 4 // last | 346 | or $r10 4 // last |
| 373 | mov $r11 0x3000 | 347 | imm32($r11, 0x503000) |
| 374 | sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_UNK0 | ||
| 375 | ld b32 $r12 D[$r0 + #gpc_id] | 348 | ld b32 $r12 D[$r0 + #gpc_id] |
| 376 | shl b32 $r12 15 | 349 | shl b32 $r12 15 |
| 377 | add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0 | 350 | add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0 |
| @@ -379,11 +352,11 @@ ctx_xfer: | |||
| 379 | ld b32 $r13 D[$r0 + #unk_mmio_list_tail] | 352 | ld b32 $r13 D[$r0 + #unk_mmio_list_tail] |
| 380 | ld b32 $r15 D[$r0 + #unk_mask] | 353 | ld b32 $r15 D[$r0 + #unk_mask] |
| 381 | mov $r14 0x200 // stride = 0x200 | 354 | mov $r14 0x200 // stride = 0x200 |
| 382 | call #mmctx_xfer | 355 | call(mmctx_xfer) |
| 383 | #endif | 356 | #endif |
| 384 | 357 | ||
| 385 | // wait for strands to finish | 358 | // wait for strands to finish |
| 386 | call #strand_wait | 359 | call(strand_wait) |
| 387 | 360 | ||
| 388 | // if load, or a save without a load following, do some | 361 | // if load, or a save without a load following, do some |
| 389 | // unknown stuff that's done after finishing a block of | 362 | // unknown stuff that's done after finishing a block of |
| @@ -391,14 +364,10 @@ ctx_xfer: | |||
| 391 | bra $p1 #ctx_xfer_post | 364 | bra $p1 #ctx_xfer_post |
| 392 | bra not $p2 #ctx_xfer_done | 365 | bra not $p2 #ctx_xfer_done |
| 393 | ctx_xfer_post: | 366 | ctx_xfer_post: |
| 394 | mov $r1 0x4afc | 367 | call(strand_post) |
| 395 | sethi $r1 0x20000 | ||
| 396 | mov $r2 0xd | ||
| 397 | iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d | ||
| 398 | call #strand_wait | ||
| 399 | 368 | ||
| 400 | // mark completion in HUB's barrier | 369 | // mark completion in HUB's barrier |
| 401 | ctx_xfer_done: | 370 | ctx_xfer_done: |
| 402 | call #hub_barrier_done | 371 | call(hub_barrier_done) |
| 403 | ret | 372 | ret |
| 404 | #endif | 373 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 new file mode 100644 index 000000000000..bd30262d635b --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 | ||
| 26 | |||
| 27 | #define CHIPSET GK208 | ||
| 28 | #include "macros.fuc" | ||
| 29 | |||
| 30 | .section #nv108_grgpc_data | ||
| 31 | #define INCLUDE_DATA | ||
| 32 | #include "com.fuc" | ||
| 33 | #include "gpc.fuc" | ||
| 34 | #undef INCLUDE_DATA | ||
| 35 | |||
| 36 | .section #nv108_grgpc_code | ||
| 37 | #define INCLUDE_CODE | ||
| 38 | bra #init | ||
| 39 | #include "com.fuc" | ||
| 40 | #include "gpc.fuc" | ||
| 41 | .align 256 | ||
| 42 | #undef INCLUDE_CODE | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h new file mode 100644 index 000000000000..27dc1280dc10 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h | |||
| @@ -0,0 +1,473 @@ | |||
| 1 | uint32_t nv108_grgpc_data[] = { | ||
| 2 | /* 0x0000: gpc_mmio_list_head */ | ||
| 3 | 0x0000006c, | ||
| 4 | /* 0x0004: gpc_mmio_list_tail */ | ||
| 5 | /* 0x0004: tpc_mmio_list_head */ | ||
| 6 | 0x0000006c, | ||
| 7 | /* 0x0008: tpc_mmio_list_tail */ | ||
| 8 | /* 0x0008: unk_mmio_list_head */ | ||
| 9 | 0x0000006c, | ||
| 10 | /* 0x000c: unk_mmio_list_tail */ | ||
| 11 | 0x0000006c, | ||
| 12 | /* 0x0010: gpc_id */ | ||
| 13 | 0x00000000, | ||
| 14 | /* 0x0014: tpc_count */ | ||
| 15 | 0x00000000, | ||
| 16 | /* 0x0018: tpc_mask */ | ||
| 17 | 0x00000000, | ||
| 18 | /* 0x001c: unk_count */ | ||
| 19 | 0x00000000, | ||
| 20 | /* 0x0020: unk_mask */ | ||
| 21 | 0x00000000, | ||
| 22 | /* 0x0024: cmd_queue */ | ||
| 23 | 0x00000000, | ||
| 24 | 0x00000000, | ||
| 25 | 0x00000000, | ||
| 26 | 0x00000000, | ||
| 27 | 0x00000000, | ||
| 28 | 0x00000000, | ||
| 29 | 0x00000000, | ||
| 30 | 0x00000000, | ||
| 31 | 0x00000000, | ||
| 32 | 0x00000000, | ||
| 33 | 0x00000000, | ||
| 34 | 0x00000000, | ||
| 35 | 0x00000000, | ||
| 36 | 0x00000000, | ||
| 37 | 0x00000000, | ||
| 38 | 0x00000000, | ||
| 39 | 0x00000000, | ||
| 40 | 0x00000000, | ||
| 41 | }; | ||
| 42 | |||
| 43 | uint32_t nv108_grgpc_code[] = { | ||
| 44 | 0x03140ef5, | ||
| 45 | /* 0x0004: queue_put */ | ||
| 46 | 0x9800d898, | ||
| 47 | 0x86f001d9, | ||
| 48 | 0xf489a408, | ||
| 49 | 0x020f0b1b, | ||
| 50 | 0x0002f87e, | ||
| 51 | /* 0x001a: queue_put_next */ | ||
| 52 | 0x98c400f8, | ||
| 53 | 0x0384b607, | ||
| 54 | 0xb6008dbb, | ||
| 55 | 0x8eb50880, | ||
| 56 | 0x018fb500, | ||
| 57 | 0xf00190b6, | ||
| 58 | 0xd9b50f94, | ||
| 59 | /* 0x0037: queue_get */ | ||
| 60 | 0xf400f801, | ||
| 61 | 0xd8980131, | ||
| 62 | 0x01d99800, | ||
| 63 | 0x0bf489a4, | ||
| 64 | 0x0789c421, | ||
| 65 | 0xbb0394b6, | ||
| 66 | 0x90b6009d, | ||
| 67 | 0x009e9808, | ||
| 68 | 0xb6019f98, | ||
| 69 | 0x84f00180, | ||
| 70 | 0x00d8b50f, | ||
| 71 | /* 0x0063: queue_get_done */ | ||
| 72 | 0xf80132f4, | ||
| 73 | /* 0x0065: nv_rd32 */ | ||
| 74 | 0xf0ecb200, | ||
| 75 | 0x00801fc9, | ||
| 76 | 0x0cf601ca, | ||
| 77 | /* 0x0073: nv_rd32_wait */ | ||
| 78 | 0x8c04bd00, | ||
| 79 | 0xcf01ca00, | ||
| 80 | 0xccc800cc, | ||
| 81 | 0xf61bf41f, | ||
| 82 | 0xec7e060a, | ||
| 83 | 0x008f0000, | ||
| 84 | 0xffcf01cb, | ||
| 85 | /* 0x008f: nv_wr32 */ | ||
| 86 | 0x8000f800, | ||
| 87 | 0xf601cc00, | ||
| 88 | 0x04bd000f, | ||
| 89 | 0xc9f0ecb2, | ||
| 90 | 0x1ec9f01f, | ||
| 91 | 0x01ca0080, | ||
| 92 | 0xbd000cf6, | ||
| 93 | /* 0x00a9: nv_wr32_wait */ | ||
| 94 | 0xca008c04, | ||
| 95 | 0x00cccf01, | ||
| 96 | 0xf41fccc8, | ||
| 97 | 0x00f8f61b, | ||
| 98 | /* 0x00b8: wait_donez */ | ||
| 99 | 0x99f094bd, | ||
| 100 | 0x37008000, | ||
| 101 | 0x0009f602, | ||
| 102 | 0x008004bd, | ||
| 103 | 0x0af60206, | ||
| 104 | /* 0x00cf: wait_donez_ne */ | ||
| 105 | 0x8804bd00, | ||
| 106 | 0xcf010000, | ||
| 107 | 0x8aff0088, | ||
| 108 | 0xf61bf488, | ||
| 109 | 0x99f094bd, | ||
| 110 | 0x17008000, | ||
| 111 | 0x0009f602, | ||
| 112 | 0x00f804bd, | ||
| 113 | /* 0x00ec: wait_doneo */ | ||
| 114 | 0x99f094bd, | ||
| 115 | 0x37008000, | ||
| 116 | 0x0009f602, | ||
| 117 | 0x008004bd, | ||
| 118 | 0x0af60206, | ||
| 119 | /* 0x0103: wait_doneo_e */ | ||
| 120 | 0x8804bd00, | ||
| 121 | 0xcf010000, | ||
| 122 | 0x8aff0088, | ||
| 123 | 0xf60bf488, | ||
| 124 | 0x99f094bd, | ||
| 125 | 0x17008000, | ||
| 126 | 0x0009f602, | ||
| 127 | 0x00f804bd, | ||
| 128 | /* 0x0120: mmctx_size */ | ||
| 129 | /* 0x0122: nv_mmctx_size_loop */ | ||
| 130 | 0xe89894bd, | ||
| 131 | 0x1a85b600, | ||
| 132 | 0xb60180b6, | ||
| 133 | 0x98bb0284, | ||
| 134 | 0x04e0b600, | ||
| 135 | 0x1bf4efa4, | ||
| 136 | 0xf89fb2ec, | ||
| 137 | /* 0x013d: mmctx_xfer */ | ||
| 138 | 0xf094bd00, | ||
| 139 | 0x00800199, | ||
| 140 | 0x09f60237, | ||
| 141 | 0xbd04bd00, | ||
| 142 | 0x05bbfd94, | ||
| 143 | 0x800f0bf4, | ||
| 144 | 0xf601c400, | ||
| 145 | 0x04bd000b, | ||
| 146 | /* 0x015f: mmctx_base_disabled */ | ||
| 147 | 0xfd0099f0, | ||
| 148 | 0x0bf405ee, | ||
| 149 | 0xc6008018, | ||
| 150 | 0x000ef601, | ||
| 151 | 0x008004bd, | ||
| 152 | 0x0ff601c7, | ||
| 153 | 0xf004bd00, | ||
| 154 | /* 0x017a: mmctx_multi_disabled */ | ||
| 155 | 0xabc80199, | ||
| 156 | 0x10b4b600, | ||
| 157 | 0xc80cb9f0, | ||
| 158 | 0xe4b601ae, | ||
| 159 | 0x05befd11, | ||
| 160 | 0x01c50080, | ||
| 161 | 0xbd000bf6, | ||
| 162 | /* 0x0195: mmctx_exec_loop */ | ||
| 163 | /* 0x0195: mmctx_wait_free */ | ||
| 164 | 0xc5008e04, | ||
| 165 | 0x00eecf01, | ||
| 166 | 0xf41fe4f0, | ||
| 167 | 0xce98f60b, | ||
| 168 | 0x05e9fd00, | ||
| 169 | 0x01c80080, | ||
| 170 | 0xbd000ef6, | ||
| 171 | 0x04c0b604, | ||
| 172 | 0x1bf4cda4, | ||
| 173 | 0x02abc8df, | ||
| 174 | /* 0x01bf: mmctx_fini_wait */ | ||
| 175 | 0x8b1c1bf4, | ||
| 176 | 0xcf01c500, | ||
| 177 | 0xb4f000bb, | ||
| 178 | 0x10b4b01f, | ||
| 179 | 0x0af31bf4, | ||
| 180 | 0x00b87e02, | ||
| 181 | 0x250ef400, | ||
| 182 | /* 0x01d8: mmctx_stop */ | ||
| 183 | 0xb600abc8, | ||
| 184 | 0xb9f010b4, | ||
| 185 | 0x12b9f00c, | ||
| 186 | 0x01c50080, | ||
| 187 | 0xbd000bf6, | ||
| 188 | /* 0x01ed: mmctx_stop_wait */ | ||
| 189 | 0xc5008b04, | ||
| 190 | 0x00bbcf01, | ||
| 191 | 0xf412bbc8, | ||
| 192 | /* 0x01fa: mmctx_done */ | ||
| 193 | 0x94bdf61b, | ||
| 194 | 0x800199f0, | ||
| 195 | 0xf6021700, | ||
| 196 | 0x04bd0009, | ||
| 197 | /* 0x020a: strand_wait */ | ||
| 198 | 0xa0f900f8, | ||
| 199 | 0xb87e020a, | ||
| 200 | 0xa0fc0000, | ||
| 201 | /* 0x0216: strand_pre */ | ||
| 202 | 0x0c0900f8, | ||
| 203 | 0x024afc80, | ||
| 204 | 0xbd0009f6, | ||
| 205 | 0x020a7e04, | ||
| 206 | /* 0x0227: strand_post */ | ||
| 207 | 0x0900f800, | ||
| 208 | 0x4afc800d, | ||
| 209 | 0x0009f602, | ||
| 210 | 0x0a7e04bd, | ||
| 211 | 0x00f80002, | ||
| 212 | /* 0x0238: strand_set */ | ||
| 213 | 0xfc800f0c, | ||
| 214 | 0x0cf6024f, | ||
| 215 | 0x0c04bd00, | ||
| 216 | 0x4afc800b, | ||
| 217 | 0x000cf602, | ||
| 218 | 0xfc8004bd, | ||
| 219 | 0x0ef6024f, | ||
| 220 | 0x0c04bd00, | ||
| 221 | 0x4afc800a, | ||
| 222 | 0x000cf602, | ||
| 223 | 0x0a7e04bd, | ||
| 224 | 0x00f80002, | ||
| 225 | /* 0x0268: strand_ctx_init */ | ||
| 226 | 0x99f094bd, | ||
| 227 | 0x37008003, | ||
| 228 | 0x0009f602, | ||
| 229 | 0x167e04bd, | ||
| 230 | 0x030e0002, | ||
| 231 | 0x0002387e, | ||
| 232 | 0xfc80c4bd, | ||
| 233 | 0x0cf60247, | ||
| 234 | 0x0c04bd00, | ||
| 235 | 0x4afc8001, | ||
| 236 | 0x000cf602, | ||
| 237 | 0x0a7e04bd, | ||
| 238 | 0x0c920002, | ||
| 239 | 0x46fc8001, | ||
| 240 | 0x000cf602, | ||
| 241 | 0x020c04bd, | ||
| 242 | 0x024afc80, | ||
| 243 | 0xbd000cf6, | ||
| 244 | 0x020a7e04, | ||
| 245 | 0x02277e00, | ||
| 246 | 0x42008800, | ||
| 247 | 0x20008902, | ||
| 248 | 0x0099cf02, | ||
| 249 | /* 0x02c7: ctx_init_strand_loop */ | ||
| 250 | 0xf608fe95, | ||
| 251 | 0x8ef6008e, | ||
| 252 | 0x808acf40, | ||
| 253 | 0xb606a5b6, | ||
| 254 | 0xeabb01a0, | ||
| 255 | 0x0480b600, | ||
| 256 | 0xf40192b6, | ||
| 257 | 0xe4b6e81b, | ||
| 258 | 0xf2efbc08, | ||
| 259 | 0x99f094bd, | ||
| 260 | 0x17008003, | ||
| 261 | 0x0009f602, | ||
| 262 | 0x00f804bd, | ||
| 263 | /* 0x02f8: error */ | ||
| 264 | 0xffb2e0f9, | ||
| 265 | 0x4098148e, | ||
| 266 | 0x00008f7e, | ||
| 267 | 0xffb2010f, | ||
| 268 | 0x409c1c8e, | ||
| 269 | 0x00008f7e, | ||
| 270 | 0x00f8e0fc, | ||
| 271 | /* 0x0314: init */ | ||
| 272 | 0x04fe04bd, | ||
| 273 | 0x40020200, | ||
| 274 | 0x02f61200, | ||
| 275 | 0x4104bd00, | ||
| 276 | 0x10fe0465, | ||
| 277 | 0x07004000, | ||
| 278 | 0xbd0000f6, | ||
| 279 | 0x40040204, | ||
| 280 | 0x02f60400, | ||
| 281 | 0xf404bd00, | ||
| 282 | 0x00821031, | ||
| 283 | 0x22cf0182, | ||
| 284 | 0xf0010300, | ||
| 285 | 0x32bb1f24, | ||
| 286 | 0x0132b604, | ||
| 287 | 0xb50502b5, | ||
| 288 | 0x00820603, | ||
| 289 | 0x22cf0186, | ||
| 290 | 0x0402b500, | ||
| 291 | 0x500c308e, | ||
| 292 | 0x34bd24bd, | ||
| 293 | /* 0x036a: init_unk_loop */ | ||
| 294 | 0x657e44bd, | ||
| 295 | 0xf6b00000, | ||
| 296 | 0x0e0bf400, | ||
| 297 | 0xf2bb010f, | ||
| 298 | 0x054ffd04, | ||
| 299 | /* 0x037f: init_unk_next */ | ||
| 300 | 0xb60130b6, | ||
| 301 | 0xe0b60120, | ||
| 302 | 0x0126b004, | ||
| 303 | /* 0x038b: init_unk_done */ | ||
| 304 | 0xb5e21bf4, | ||
| 305 | 0x04b50703, | ||
| 306 | 0x01008208, | ||
| 307 | 0x0022cf02, | ||
| 308 | 0x259534bd, | ||
| 309 | 0xc0008008, | ||
| 310 | 0x0005f601, | ||
| 311 | 0x008004bd, | ||
| 312 | 0x05f601c1, | ||
| 313 | 0x9804bd00, | ||
| 314 | 0x0f98000e, | ||
| 315 | 0x01207e01, | ||
| 316 | 0x002fbb00, | ||
| 317 | 0x98003fbb, | ||
| 318 | 0x0f98010e, | ||
| 319 | 0x01207e02, | ||
| 320 | 0x050e9800, | ||
| 321 | 0xbb00effd, | ||
| 322 | 0x3ebb002e, | ||
| 323 | 0x020e9800, | ||
| 324 | 0x7e030f98, | ||
| 325 | 0x98000120, | ||
| 326 | 0xeffd070e, | ||
| 327 | 0x002ebb00, | ||
| 328 | 0xb6003ebb, | ||
| 329 | 0x00800235, | ||
| 330 | 0x03f601d3, | ||
| 331 | 0xb604bd00, | ||
| 332 | 0x35b60825, | ||
| 333 | 0x0120b606, | ||
| 334 | 0xb60130b6, | ||
| 335 | 0x34b60824, | ||
| 336 | 0x7e2fb208, | ||
| 337 | 0xbb000268, | ||
| 338 | 0x0080003f, | ||
| 339 | 0x03f60201, | ||
| 340 | 0xbd04bd00, | ||
| 341 | 0x1f29f024, | ||
| 342 | 0x02300080, | ||
| 343 | 0xbd0002f6, | ||
| 344 | /* 0x0429: main */ | ||
| 345 | 0x0031f404, | ||
| 346 | 0x0d0028f4, | ||
| 347 | 0x00377e24, | ||
| 348 | 0xf401f400, | ||
| 349 | 0xf404e4b0, | ||
| 350 | 0x81fe1d18, | ||
| 351 | 0xbd060201, | ||
| 352 | 0x0412fd20, | ||
| 353 | 0xfd01e4b6, | ||
| 354 | 0x18fe051e, | ||
| 355 | 0x04fc7e00, | ||
| 356 | 0xd40ef400, | ||
| 357 | /* 0x0458: main_not_ctx_xfer */ | ||
| 358 | 0xf010ef94, | ||
| 359 | 0xf87e01f5, | ||
| 360 | 0x0ef40002, | ||
| 361 | /* 0x0465: ih */ | ||
| 362 | 0xfe80f9c7, | ||
| 363 | 0x80f90188, | ||
| 364 | 0xa0f990f9, | ||
| 365 | 0xd0f9b0f9, | ||
| 366 | 0xf0f9e0f9, | ||
| 367 | 0x004a04bd, | ||
| 368 | 0x00aacf02, | ||
| 369 | 0xf404abc4, | ||
| 370 | 0x240d1f0b, | ||
| 371 | 0xcf1a004e, | ||
| 372 | 0x004f00ee, | ||
| 373 | 0x00ffcf19, | ||
| 374 | 0x0000047e, | ||
| 375 | 0x0040010e, | ||
| 376 | 0x000ef61d, | ||
| 377 | /* 0x04a2: ih_no_fifo */ | ||
| 378 | 0x004004bd, | ||
| 379 | 0x000af601, | ||
| 380 | 0xf0fc04bd, | ||
| 381 | 0xd0fce0fc, | ||
| 382 | 0xa0fcb0fc, | ||
| 383 | 0x80fc90fc, | ||
| 384 | 0xfc0088fe, | ||
| 385 | 0x0032f480, | ||
| 386 | /* 0x04c2: hub_barrier_done */ | ||
| 387 | 0x010f01f8, | ||
| 388 | 0xbb040e98, | ||
| 389 | 0xffb204fe, | ||
| 390 | 0x4094188e, | ||
| 391 | 0x00008f7e, | ||
| 392 | /* 0x04d6: ctx_redswitch */ | ||
| 393 | 0x200f00f8, | ||
| 394 | 0x01850080, | ||
| 395 | 0xbd000ff6, | ||
| 396 | /* 0x04e3: ctx_redswitch_delay */ | ||
| 397 | 0xb6080e04, | ||
| 398 | 0x1bf401e2, | ||
| 399 | 0x00f5f1fd, | ||
| 400 | 0x00f5f108, | ||
| 401 | 0x85008002, | ||
| 402 | 0x000ff601, | ||
| 403 | 0x00f804bd, | ||
| 404 | /* 0x04fc: ctx_xfer */ | ||
| 405 | 0x02810080, | ||
| 406 | 0xbd000ff6, | ||
| 407 | 0x0711f404, | ||
| 408 | 0x0004d67e, | ||
| 409 | /* 0x050c: ctx_xfer_not_load */ | ||
| 410 | 0x0002167e, | ||
| 411 | 0xfc8024bd, | ||
| 412 | 0x02f60247, | ||
| 413 | 0xf004bd00, | ||
| 414 | 0x20b6012c, | ||
| 415 | 0x4afc8003, | ||
| 416 | 0x0002f602, | ||
| 417 | 0xacf004bd, | ||
| 418 | 0x02a5f001, | ||
| 419 | 0x5000008b, | ||
| 420 | 0xb6040c98, | ||
| 421 | 0xbcbb0fc4, | ||
| 422 | 0x000c9800, | ||
| 423 | 0x0e010d98, | ||
| 424 | 0x013d7e00, | ||
| 425 | 0x01acf000, | ||
| 426 | 0x5040008b, | ||
| 427 | 0xb6040c98, | ||
| 428 | 0xbcbb0fc4, | ||
| 429 | 0x010c9800, | ||
| 430 | 0x98020d98, | ||
| 431 | 0x004e060f, | ||
| 432 | 0x013d7e08, | ||
| 433 | 0x01acf000, | ||
| 434 | 0x8b04a5f0, | ||
| 435 | 0x98503000, | ||
| 436 | 0xc4b6040c, | ||
| 437 | 0x00bcbb0f, | ||
| 438 | 0x98020c98, | ||
| 439 | 0x0f98030d, | ||
| 440 | 0x02004e08, | ||
| 441 | 0x00013d7e, | ||
| 442 | 0x00020a7e, | ||
| 443 | 0xf40601f4, | ||
| 444 | /* 0x0596: ctx_xfer_post */ | ||
| 445 | 0x277e0712, | ||
| 446 | /* 0x059a: ctx_xfer_done */ | ||
| 447 | 0xc27e0002, | ||
| 448 | 0x00f80004, | ||
| 449 | 0x00000000, | ||
| 450 | 0x00000000, | ||
| 451 | 0x00000000, | ||
| 452 | 0x00000000, | ||
| 453 | 0x00000000, | ||
| 454 | 0x00000000, | ||
| 455 | 0x00000000, | ||
| 456 | 0x00000000, | ||
| 457 | 0x00000000, | ||
| 458 | 0x00000000, | ||
| 459 | 0x00000000, | ||
| 460 | 0x00000000, | ||
| 461 | 0x00000000, | ||
| 462 | 0x00000000, | ||
| 463 | 0x00000000, | ||
| 464 | 0x00000000, | ||
| 465 | 0x00000000, | ||
| 466 | 0x00000000, | ||
| 467 | 0x00000000, | ||
| 468 | 0x00000000, | ||
| 469 | 0x00000000, | ||
| 470 | 0x00000000, | ||
| 471 | 0x00000000, | ||
| 472 | 0x00000000, | ||
| 473 | }; | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h index f2b0dea80116..0e7b01efae8d 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h | |||
| @@ -37,14 +37,14 @@ uint32_t nvc0_grgpc_data[] = { | |||
| 37 | }; | 37 | }; |
| 38 | 38 | ||
| 39 | uint32_t nvc0_grgpc_code[] = { | 39 | uint32_t nvc0_grgpc_code[] = { |
| 40 | 0x03180ef5, | 40 | 0x03a10ef5, |
| 41 | /* 0x0004: queue_put */ | 41 | /* 0x0004: queue_put */ |
| 42 | 0x9800d898, | 42 | 0x9800d898, |
| 43 | 0x86f001d9, | 43 | 0x86f001d9, |
| 44 | 0x0489b808, | 44 | 0x0489b808, |
| 45 | 0xf00c1bf4, | 45 | 0xf00c1bf4, |
| 46 | 0x21f502f7, | 46 | 0x21f502f7, |
| 47 | 0x00f802fe, | 47 | 0x00f8037e, |
| 48 | /* 0x001c: queue_put_next */ | 48 | /* 0x001c: queue_put_next */ |
| 49 | 0xb60798c4, | 49 | 0xb60798c4, |
| 50 | 0x8dbb0384, | 50 | 0x8dbb0384, |
| @@ -68,184 +68,214 @@ uint32_t nvc0_grgpc_code[] = { | |||
| 68 | /* 0x0066: queue_get_done */ | 68 | /* 0x0066: queue_get_done */ |
| 69 | 0x00f80132, | 69 | 0x00f80132, |
| 70 | /* 0x0068: nv_rd32 */ | 70 | /* 0x0068: nv_rd32 */ |
| 71 | 0x0728b7f1, | 71 | 0xf002ecb9, |
| 72 | 0xb906b4b6, | 72 | 0x07f11fc9, |
| 73 | 0xc9f002ec, | 73 | 0x03f0ca00, |
| 74 | 0x00bcd01f, | 74 | 0x000cd001, |
| 75 | /* 0x0078: nv_rd32_wait */ | 75 | /* 0x007a: nv_rd32_wait */ |
| 76 | 0xc800bccf, | 76 | 0xc7f104bd, |
| 77 | 0x1bf41fcc, | 77 | 0xc3f0ca00, |
| 78 | 0x06a7f0fa, | 78 | 0x00cccf01, |
| 79 | 0x010921f5, | 79 | 0xf41fccc8, |
| 80 | 0xf840bfcf, | 80 | 0xa7f0f31b, |
| 81 | /* 0x008d: nv_wr32 */ | 81 | 0x1021f506, |
| 82 | 0x28b7f100, | 82 | 0x00f7f101, |
| 83 | 0x06b4b607, | 83 | 0x01f3f0cb, |
| 84 | 0xb980bfd0, | 84 | 0xf800ffcf, |
| 85 | 0xc9f002ec, | 85 | /* 0x009d: nv_wr32 */ |
| 86 | 0x1ec9f01f, | 86 | 0x0007f100, |
| 87 | /* 0x00a3: nv_wr32_wait */ | 87 | 0x0103f0cc, |
| 88 | 0xcf00bcd0, | 88 | 0xbd000fd0, |
| 89 | 0xccc800bc, | 89 | 0x02ecb904, |
| 90 | 0xfa1bf41f, | 90 | 0xf01fc9f0, |
| 91 | /* 0x00ae: watchdog_reset */ | 91 | 0x07f11ec9, |
| 92 | 0x87f100f8, | 92 | 0x03f0ca00, |
| 93 | 0x84b60430, | 93 | 0x000cd001, |
| 94 | 0x1ff9f006, | 94 | /* 0x00be: nv_wr32_wait */ |
| 95 | 0xf8008fd0, | 95 | 0xc7f104bd, |
| 96 | /* 0x00bd: watchdog_clear */ | 96 | 0xc3f0ca00, |
| 97 | 0x3087f100, | 97 | 0x00cccf01, |
| 98 | 0x0684b604, | 98 | 0xf41fccc8, |
| 99 | 0xf80080d0, | 99 | 0x00f8f31b, |
| 100 | /* 0x00c9: wait_donez */ | 100 | /* 0x00d0: wait_donez */ |
| 101 | 0xf094bd00, | 101 | 0x99f094bd, |
| 102 | 0x07f10099, | 102 | 0x0007f100, |
| 103 | 0x03f00f00, | 103 | 0x0203f00f, |
| 104 | 0x0009d002, | 104 | 0xbd0009d0, |
| 105 | 0x07f104bd, | 105 | 0x0007f104, |
| 106 | 0x03f00600, | 106 | 0x0203f006, |
| 107 | 0x000ad002, | 107 | 0xbd000ad0, |
| 108 | /* 0x00e6: wait_donez_ne */ | 108 | /* 0x00ed: wait_donez_ne */ |
| 109 | 0x87f104bd, | 109 | 0x0087f104, |
| 110 | 0x83f00000, | 110 | 0x0183f000, |
| 111 | 0x0088cf01, | 111 | 0xff0088cf, |
| 112 | 0xf4888aff, | 112 | 0x1bf4888a, |
| 113 | 0x94bdf31b, | 113 | 0xf094bdf3, |
| 114 | 0xf10099f0, | ||
| 115 | 0xf0170007, | ||
| 116 | 0x09d00203, | ||
| 117 | 0xf804bd00, | ||
| 118 | /* 0x0109: wait_doneo */ | ||
| 119 | 0xf094bd00, | ||
| 120 | 0x07f10099, | 114 | 0x07f10099, |
| 121 | 0x03f00f00, | 115 | 0x03f01700, |
| 122 | 0x0009d002, | 116 | 0x0009d002, |
| 123 | 0x87f104bd, | 117 | 0x00f804bd, |
| 124 | 0x84b60818, | 118 | /* 0x0110: wait_doneo */ |
| 125 | 0x008ad006, | ||
| 126 | /* 0x0124: wait_doneo_e */ | ||
| 127 | 0x040087f1, | ||
| 128 | 0xcf0684b6, | ||
| 129 | 0x8aff0088, | ||
| 130 | 0xf30bf488, | ||
| 131 | 0x99f094bd, | 119 | 0x99f094bd, |
| 132 | 0x0007f100, | 120 | 0x0007f100, |
| 133 | 0x0203f017, | 121 | 0x0203f00f, |
| 134 | 0xbd0009d0, | 122 | 0xbd0009d0, |
| 135 | /* 0x0147: mmctx_size */ | 123 | 0x0007f104, |
| 136 | 0xbd00f804, | 124 | 0x0203f006, |
| 137 | /* 0x0149: nv_mmctx_size_loop */ | 125 | 0xbd000ad0, |
| 138 | 0x00e89894, | 126 | /* 0x012d: wait_doneo_e */ |
| 139 | 0xb61a85b6, | 127 | 0x0087f104, |
| 140 | 0x84b60180, | 128 | 0x0183f000, |
| 141 | 0x0098bb02, | 129 | 0xff0088cf, |
| 142 | 0xb804e0b6, | 130 | 0x0bf4888a, |
| 143 | 0x1bf404ef, | 131 | 0xf094bdf3, |
| 144 | 0x029fb9eb, | 132 | 0x07f10099, |
| 145 | /* 0x0166: mmctx_xfer */ | 133 | 0x03f01700, |
| 146 | 0x94bd00f8, | 134 | 0x0009d002, |
| 147 | 0xf10199f0, | 135 | 0x00f804bd, |
| 148 | 0xf00f0007, | 136 | /* 0x0150: mmctx_size */ |
| 149 | 0x09d00203, | 137 | /* 0x0152: nv_mmctx_size_loop */ |
| 150 | 0xf104bd00, | 138 | 0xe89894bd, |
| 151 | 0xb6071087, | 139 | 0x1a85b600, |
| 152 | 0x94bd0684, | 140 | 0xb60180b6, |
| 153 | 0xf405bbfd, | 141 | 0x98bb0284, |
| 154 | 0x8bd0090b, | 142 | 0x04e0b600, |
| 155 | 0x0099f000, | 143 | 0xf404efb8, |
| 156 | /* 0x018c: mmctx_base_disabled */ | 144 | 0x9fb9eb1b, |
| 157 | 0xf405eefd, | 145 | /* 0x016f: mmctx_xfer */ |
| 158 | 0x8ed00c0b, | 146 | 0xbd00f802, |
| 159 | 0xc08fd080, | 147 | 0x0199f094, |
| 160 | /* 0x019b: mmctx_multi_disabled */ | 148 | 0x0f0007f1, |
| 161 | 0xb70199f0, | 149 | 0xd00203f0, |
| 162 | 0xc8010080, | 150 | 0x04bd0009, |
| 151 | 0xbbfd94bd, | ||
| 152 | 0x120bf405, | ||
| 153 | 0xc40007f1, | ||
| 154 | 0xd00103f0, | ||
| 155 | 0x04bd000b, | ||
| 156 | /* 0x0197: mmctx_base_disabled */ | ||
| 157 | 0xfd0099f0, | ||
| 158 | 0x0bf405ee, | ||
| 159 | 0x0007f11e, | ||
| 160 | 0x0103f0c6, | ||
| 161 | 0xbd000ed0, | ||
| 162 | 0x0007f104, | ||
| 163 | 0x0103f0c7, | ||
| 164 | 0xbd000fd0, | ||
| 165 | 0x0199f004, | ||
| 166 | /* 0x01b8: mmctx_multi_disabled */ | ||
| 167 | 0xb600abc8, | ||
| 168 | 0xb9f010b4, | ||
| 169 | 0x01aec80c, | ||
| 170 | 0xfd11e4b6, | ||
| 171 | 0x07f105be, | ||
| 172 | 0x03f0c500, | ||
| 173 | 0x000bd001, | ||
| 174 | /* 0x01d6: mmctx_exec_loop */ | ||
| 175 | /* 0x01d6: mmctx_wait_free */ | ||
| 176 | 0xe7f104bd, | ||
| 177 | 0xe3f0c500, | ||
| 178 | 0x00eecf01, | ||
| 179 | 0xf41fe4f0, | ||
| 180 | 0xce98f30b, | ||
| 181 | 0x05e9fd00, | ||
| 182 | 0xc80007f1, | ||
| 183 | 0xd00103f0, | ||
| 184 | 0x04bd000e, | ||
| 185 | 0xb804c0b6, | ||
| 186 | 0x1bf404cd, | ||
| 187 | 0x02abc8d8, | ||
| 188 | /* 0x0207: mmctx_fini_wait */ | ||
| 189 | 0xf11f1bf4, | ||
| 190 | 0xf0c500b7, | ||
| 191 | 0xbbcf01b3, | ||
| 192 | 0x1fb4f000, | ||
| 193 | 0xf410b4b0, | ||
| 194 | 0xa7f0f01b, | ||
| 195 | 0xd021f402, | ||
| 196 | /* 0x0223: mmctx_stop */ | ||
| 197 | 0xc82b0ef4, | ||
| 163 | 0xb4b600ab, | 198 | 0xb4b600ab, |
| 164 | 0x0cb9f010, | 199 | 0x0cb9f010, |
| 165 | 0xb601aec8, | 200 | 0xf112b9f0, |
| 166 | 0xbefd11e4, | 201 | 0xf0c50007, |
| 167 | 0x008bd005, | 202 | 0x0bd00103, |
| 168 | /* 0x01b4: mmctx_exec_loop */ | 203 | /* 0x023b: mmctx_stop_wait */ |
| 169 | /* 0x01b4: mmctx_wait_free */ | 204 | 0xf104bd00, |
| 170 | 0xf0008ecf, | 205 | 0xf0c500b7, |
| 171 | 0x0bf41fe4, | 206 | 0xbbcf01b3, |
| 172 | 0x00ce98fa, | 207 | 0x12bbc800, |
| 173 | 0xd005e9fd, | 208 | /* 0x024b: mmctx_done */ |
| 174 | 0xc0b6c08e, | 209 | 0xbdf31bf4, |
| 175 | 0x04cdb804, | 210 | 0x0199f094, |
| 176 | 0xc8e81bf4, | 211 | 0x170007f1, |
| 177 | 0x1bf402ab, | 212 | 0xd00203f0, |
| 178 | /* 0x01d5: mmctx_fini_wait */ | 213 | 0x04bd0009, |
| 179 | 0x008bcf18, | 214 | /* 0x025e: strand_wait */ |
| 180 | 0xb01fb4f0, | 215 | 0xa0f900f8, |
| 181 | 0x1bf410b4, | 216 | 0xf402a7f0, |
| 182 | 0x02a7f0f7, | 217 | 0xa0fcd021, |
| 183 | 0xf4c921f4, | 218 | /* 0x026a: strand_pre */ |
| 184 | /* 0x01ea: mmctx_stop */ | 219 | 0x97f000f8, |
| 185 | 0xabc81b0e, | 220 | 0xfc07f10c, |
| 186 | 0x10b4b600, | 221 | 0x0203f04a, |
| 187 | 0xf00cb9f0, | 222 | 0xbd0009d0, |
| 188 | 0x8bd012b9, | 223 | 0x5e21f504, |
| 189 | /* 0x01f9: mmctx_stop_wait */ | 224 | /* 0x027f: strand_post */ |
| 190 | 0x008bcf00, | 225 | 0xf000f802, |
| 191 | 0xf412bbc8, | 226 | 0x07f10d97, |
| 192 | /* 0x0202: mmctx_done */ | 227 | 0x03f04afc, |
| 193 | 0x94bdfa1b, | ||
| 194 | 0xf10199f0, | ||
| 195 | 0xf0170007, | ||
| 196 | 0x09d00203, | ||
| 197 | 0xf804bd00, | ||
| 198 | /* 0x0215: strand_wait */ | ||
| 199 | 0xf0a0f900, | ||
| 200 | 0x21f402a7, | ||
| 201 | 0xf8a0fcc9, | ||
| 202 | /* 0x0221: strand_pre */ | ||
| 203 | 0xfc87f100, | ||
| 204 | 0x0283f04a, | ||
| 205 | 0xd00c97f0, | ||
| 206 | 0x21f50089, | ||
| 207 | 0x00f80215, | ||
| 208 | /* 0x0234: strand_post */ | ||
| 209 | 0x4afc87f1, | ||
| 210 | 0xf00283f0, | ||
| 211 | 0x89d00d97, | ||
| 212 | 0x1521f500, | ||
| 213 | /* 0x0247: strand_set */ | ||
| 214 | 0xf100f802, | ||
| 215 | 0xf04ffca7, | ||
| 216 | 0xaba202a3, | ||
| 217 | 0xc7f00500, | ||
| 218 | 0x00acd00f, | ||
| 219 | 0xd00bc7f0, | ||
| 220 | 0x21f500bc, | ||
| 221 | 0xaed00215, | ||
| 222 | 0x0ac7f000, | ||
| 223 | 0xf500bcd0, | ||
| 224 | 0xf8021521, | ||
| 225 | /* 0x0271: strand_ctx_init */ | ||
| 226 | 0xf094bd00, | ||
| 227 | 0x07f10399, | ||
| 228 | 0x03f00f00, | ||
| 229 | 0x0009d002, | 228 | 0x0009d002, |
| 230 | 0x21f504bd, | 229 | 0x21f504bd, |
| 231 | 0xe7f00221, | 230 | 0x00f8025e, |
| 232 | 0x4721f503, | 231 | /* 0x0294: strand_set */ |
| 233 | 0xfca7f102, | 232 | 0xf10fc7f0, |
| 234 | 0x02a3f046, | 233 | 0xf04ffc07, |
| 235 | 0x0400aba0, | 234 | 0x0cd00203, |
| 236 | 0xf040a0d0, | 235 | 0xf004bd00, |
| 237 | 0xbcd001c7, | 236 | 0x07f10bc7, |
| 238 | 0x1521f500, | 237 | 0x03f04afc, |
| 239 | 0x010c9202, | 238 | 0x000cd002, |
| 240 | 0xf000acd0, | 239 | 0x07f104bd, |
| 241 | 0xbcd002c7, | 240 | 0x03f04ffc, |
| 242 | 0x1521f500, | 241 | 0x000ed002, |
| 243 | 0x3421f502, | 242 | 0xc7f004bd, |
| 244 | 0x8087f102, | 243 | 0xfc07f10a, |
| 245 | 0x0684b608, | 244 | 0x0203f04a, |
| 246 | 0xb70089cf, | 245 | 0xbd000cd0, |
| 247 | 0x95220080, | 246 | 0x5e21f504, |
| 248 | /* 0x02ca: ctx_init_strand_loop */ | 247 | /* 0x02d3: strand_ctx_init */ |
| 248 | 0xbd00f802, | ||
| 249 | 0x0399f094, | ||
| 250 | 0x0f0007f1, | ||
| 251 | 0xd00203f0, | ||
| 252 | 0x04bd0009, | ||
| 253 | 0x026a21f5, | ||
| 254 | 0xf503e7f0, | ||
| 255 | 0xbd029421, | ||
| 256 | 0xfc07f1c4, | ||
| 257 | 0x0203f047, | ||
| 258 | 0xbd000cd0, | ||
| 259 | 0x01c7f004, | ||
| 260 | 0x4afc07f1, | ||
| 261 | 0xd00203f0, | ||
| 262 | 0x04bd000c, | ||
| 263 | 0x025e21f5, | ||
| 264 | 0xf1010c92, | ||
| 265 | 0xf046fc07, | ||
| 266 | 0x0cd00203, | ||
| 267 | 0xf004bd00, | ||
| 268 | 0x07f102c7, | ||
| 269 | 0x03f04afc, | ||
| 270 | 0x000cd002, | ||
| 271 | 0x21f504bd, | ||
| 272 | 0x21f5025e, | ||
| 273 | 0x87f1027f, | ||
| 274 | 0x83f04200, | ||
| 275 | 0x0097f102, | ||
| 276 | 0x0293f020, | ||
| 277 | 0x950099cf, | ||
| 278 | /* 0x034a: ctx_init_strand_loop */ | ||
| 249 | 0x8ed008fe, | 279 | 0x8ed008fe, |
| 250 | 0x408ed000, | 280 | 0x408ed000, |
| 251 | 0xb6808acf, | 281 | 0xb6808acf, |
| @@ -259,167 +289,199 @@ uint32_t nvc0_grgpc_code[] = { | |||
| 259 | 0x170007f1, | 289 | 0x170007f1, |
| 260 | 0xd00203f0, | 290 | 0xd00203f0, |
| 261 | 0x04bd0009, | 291 | 0x04bd0009, |
| 262 | /* 0x02fe: error */ | 292 | /* 0x037e: error */ |
| 263 | 0xe0f900f8, | 293 | 0xe0f900f8, |
| 264 | 0x9814e7f1, | 294 | 0xf102ffb9, |
| 265 | 0xf440e3f0, | 295 | 0xf09814e7, |
| 266 | 0xe0b78d21, | 296 | 0x21f440e3, |
| 267 | 0xf7f0041c, | 297 | 0x01f7f09d, |
| 268 | 0x8d21f401, | 298 | 0xf102ffb9, |
| 269 | 0x00f8e0fc, | 299 | 0xf09c1ce7, |
| 270 | /* 0x0318: init */ | 300 | 0x21f440e3, |
| 271 | 0x04fe04bd, | 301 | 0xf8e0fc9d, |
| 272 | 0x0017f100, | 302 | /* 0x03a1: init */ |
| 273 | 0x0227f012, | 303 | 0xfe04bd00, |
| 274 | 0xf10012d0, | 304 | 0x27f00004, |
| 275 | 0xfe042617, | 305 | 0x0007f102, |
| 276 | 0x17f10010, | 306 | 0x0003f012, |
| 277 | 0x10d00400, | 307 | 0xbd0002d0, |
| 278 | 0x0427f0c0, | 308 | 0xd517f104, |
| 279 | 0xf40012d0, | 309 | 0x0010fe04, |
| 280 | 0x17f11031, | 310 | 0x070007f1, |
| 281 | 0x14b60608, | 311 | 0xd00003f0, |
| 282 | 0x0012cf06, | 312 | 0x04bd0000, |
| 313 | 0xf10427f0, | ||
| 314 | 0xf0040007, | ||
| 315 | 0x02d00003, | ||
| 316 | 0xf404bd00, | ||
| 317 | 0x27f11031, | ||
| 318 | 0x23f08200, | ||
| 319 | 0x0022cf01, | ||
| 283 | 0xf00137f0, | 320 | 0xf00137f0, |
| 284 | 0x32bb1f24, | 321 | 0x32bb1f24, |
| 285 | 0x0132b604, | 322 | 0x0132b604, |
| 286 | 0x80050280, | 323 | 0x80050280, |
| 287 | 0x10b70603, | 324 | 0x27f10603, |
| 288 | 0x12cf0400, | 325 | 0x23f08600, |
| 289 | 0x04028000, | 326 | 0x0022cf01, |
| 290 | 0x010027f1, | 327 | 0xf1040280, |
| 291 | 0xcf0223f0, | 328 | 0xf0010027, |
| 292 | 0x34bd0022, | 329 | 0x22cf0223, |
| 293 | 0x070047f1, | 330 | 0x9534bd00, |
| 294 | 0x950644b6, | 331 | 0x07f10825, |
| 295 | 0x45d00825, | 332 | 0x03f0c000, |
| 296 | 0x4045d000, | 333 | 0x0005d001, |
| 297 | 0x98000e98, | 334 | 0x07f104bd, |
| 298 | 0x21f5010f, | 335 | 0x03f0c100, |
| 299 | 0x2fbb0147, | 336 | 0x0005d001, |
| 300 | 0x003fbb00, | 337 | 0x0e9804bd, |
| 301 | 0x98010e98, | 338 | 0x010f9800, |
| 302 | 0x21f5020f, | 339 | 0x015021f5, |
| 303 | 0x0e980147, | 340 | 0xbb002fbb, |
| 304 | 0x00effd05, | 341 | 0x0e98003f, |
| 305 | 0xbb002ebb, | 342 | 0x020f9801, |
| 306 | 0x40b7003e, | 343 | 0x015021f5, |
| 307 | 0x35b61300, | 344 | 0xfd050e98, |
| 308 | 0x0043d002, | 345 | 0x2ebb00ef, |
| 309 | 0xb60825b6, | 346 | 0x003ebb00, |
| 310 | 0x20b60635, | 347 | 0xf10235b6, |
| 311 | 0x0130b601, | 348 | 0xf0d30007, |
| 312 | 0xb60824b6, | 349 | 0x03d00103, |
| 313 | 0x2fb90834, | 350 | 0xb604bd00, |
| 314 | 0x7121f502, | 351 | 0x35b60825, |
| 315 | 0x003fbb02, | 352 | 0x0120b606, |
| 316 | 0x010007f1, | 353 | 0xb60130b6, |
| 354 | 0x34b60824, | ||
| 355 | 0x022fb908, | ||
| 356 | 0x02d321f5, | ||
| 357 | 0xf1003fbb, | ||
| 358 | 0xf0010007, | ||
| 359 | 0x03d00203, | ||
| 360 | 0xbd04bd00, | ||
| 361 | 0x1f29f024, | ||
| 362 | 0x080007f1, | ||
| 317 | 0xd00203f0, | 363 | 0xd00203f0, |
| 318 | 0x04bd0003, | 364 | 0x04bd0002, |
| 319 | 0x29f024bd, | 365 | /* 0x0498: main */ |
| 320 | 0x0007f11f, | 366 | 0xf40031f4, |
| 321 | 0x0203f008, | 367 | 0xd7f00028, |
| 322 | 0xbd0002d0, | 368 | 0x3921f41c, |
| 323 | /* 0x03e9: main */ | 369 | 0xb0f401f4, |
| 324 | 0x0031f404, | 370 | 0x18f404e4, |
| 325 | 0xf00028f4, | 371 | 0x0181fe1e, |
| 326 | 0x21f41cd7, | 372 | 0xbd0627f0, |
| 327 | 0xf401f439, | 373 | 0x0412fd20, |
| 328 | 0xf404e4b0, | 374 | 0xfd01e4b6, |
| 329 | 0x81fe1e18, | 375 | 0x18fe051e, |
| 330 | 0x0627f001, | 376 | 0x8d21f500, |
| 331 | 0x12fd20bd, | 377 | 0xd30ef405, |
| 332 | 0x01e4b604, | 378 | /* 0x04c8: main_not_ctx_xfer */ |
| 333 | 0xfe051efd, | 379 | 0xf010ef94, |
| 334 | 0x21f50018, | 380 | 0x21f501f5, |
| 335 | 0x0ef404ad, | 381 | 0x0ef4037e, |
| 336 | /* 0x0419: main_not_ctx_xfer */ | 382 | /* 0x04d5: ih */ |
| 337 | 0x10ef94d3, | 383 | 0xfe80f9c6, |
| 338 | 0xf501f5f0, | 384 | 0x80f90188, |
| 339 | 0xf402fe21, | 385 | 0xa0f990f9, |
| 340 | /* 0x0426: ih */ | 386 | 0xd0f9b0f9, |
| 341 | 0x80f9c60e, | 387 | 0xf0f9e0f9, |
| 342 | 0xf90188fe, | 388 | 0xa7f104bd, |
| 343 | 0xf990f980, | 389 | 0xa3f00200, |
| 344 | 0xf9b0f9a0, | 390 | 0x00aacf00, |
| 345 | 0xf9e0f9d0, | 391 | 0xf404abc4, |
| 346 | 0xcf04bdf0, | 392 | 0xd7f02c0b, |
| 347 | 0xabc4800a, | 393 | 0x00e7f11c, |
| 348 | 0x1d0bf404, | 394 | 0x00e3f01a, |
| 349 | 0x1900b7f1, | 395 | 0xf100eecf, |
| 350 | 0xcf1cd7f0, | 396 | 0xf01900f7, |
| 351 | 0xbfcf40be, | 397 | 0xffcf00f3, |
| 352 | 0x0421f400, | 398 | 0x0421f400, |
| 353 | 0x0400b0b7, | 399 | 0xf101e7f0, |
| 354 | 0xd001e7f0, | 400 | 0xf01d0007, |
| 355 | /* 0x045e: ih_no_fifo */ | 401 | 0x0ed00003, |
| 356 | 0x0ad000be, | 402 | /* 0x0523: ih_no_fifo */ |
| 357 | 0xfcf0fc40, | 403 | 0xf104bd00, |
| 358 | 0xfcd0fce0, | 404 | 0xf0010007, |
| 359 | 0xfca0fcb0, | 405 | 0x0ad00003, |
| 360 | 0xfe80fc90, | 406 | 0xfc04bd00, |
| 361 | 0x80fc0088, | 407 | 0xfce0fcf0, |
| 362 | 0xf80032f4, | 408 | 0xfcb0fcd0, |
| 363 | /* 0x0479: hub_barrier_done */ | 409 | 0xfc90fca0, |
| 364 | 0x01f7f001, | 410 | 0x0088fe80, |
| 365 | 0xbb040e98, | 411 | 0x32f480fc, |
| 366 | 0xe7f104fe, | 412 | /* 0x0547: hub_barrier_done */ |
| 367 | 0xe3f09418, | 413 | 0xf001f800, |
| 368 | 0x8d21f440, | 414 | 0x0e9801f7, |
| 369 | /* 0x048e: ctx_redswitch */ | 415 | 0x04febb04, |
| 370 | 0xe7f100f8, | 416 | 0xf102ffb9, |
| 371 | 0xe4b60614, | 417 | 0xf09418e7, |
| 372 | 0x20f7f006, | 418 | 0x21f440e3, |
| 373 | 0xf000efd0, | 419 | /* 0x055f: ctx_redswitch */ |
| 374 | /* 0x049e: ctx_redswitch_delay */ | 420 | 0xf000f89d, |
| 375 | 0xf2b608f7, | 421 | 0x07f120f7, |
| 376 | 0xfd1bf401, | 422 | 0x03f08500, |
| 377 | 0x0a20f7f1, | 423 | 0x000fd001, |
| 378 | 0xf800efd0, | 424 | 0xe7f004bd, |
| 379 | /* 0x04ad: ctx_xfer */ | 425 | /* 0x0571: ctx_redswitch_delay */ |
| 380 | 0x0417f100, | 426 | 0x01e2b608, |
| 381 | 0x0614b60a, | 427 | 0xf1fd1bf4, |
| 382 | 0xf4001fd0, | 428 | 0xf10800f5, |
| 383 | 0x21f50711, | 429 | 0xf10200f5, |
| 384 | /* 0x04be: ctx_xfer_not_load */ | 430 | 0xf0850007, |
| 385 | 0x17f1048e, | 431 | 0x0fd00103, |
| 386 | 0x13f04afc, | 432 | 0xf804bd00, |
| 387 | 0x0c27f002, | 433 | /* 0x058d: ctx_xfer */ |
| 388 | 0xf50012d0, | 434 | 0x0007f100, |
| 389 | 0xf1021521, | 435 | 0x0203f081, |
| 390 | 0xf047fc27, | 436 | 0xbd000fd0, |
| 391 | 0x20d00223, | 437 | 0x0711f404, |
| 392 | 0x012cf000, | 438 | 0x055f21f5, |
| 393 | 0xd00320b6, | 439 | /* 0x05a0: ctx_xfer_not_load */ |
| 394 | 0xacf00012, | 440 | 0x026a21f5, |
| 395 | 0x02a5f001, | 441 | 0x07f124bd, |
| 396 | 0xf000b7f0, | 442 | 0x03f047fc, |
| 397 | 0x0c9850b3, | 443 | 0x0002d002, |
| 398 | 0x0fc4b604, | 444 | 0x2cf004bd, |
| 399 | 0x9800bcbb, | 445 | 0x0320b601, |
| 400 | 0x0d98000c, | 446 | 0x4afc07f1, |
| 401 | 0x00e7f001, | 447 | 0xd00203f0, |
| 402 | 0x016621f5, | 448 | 0x04bd0002, |
| 403 | 0xf001acf0, | 449 | 0xf001acf0, |
| 404 | 0xb7f104a5, | 450 | 0xb7f102a5, |
| 405 | 0xb3f04000, | 451 | 0xb3f00000, |
| 406 | 0x040c9850, | 452 | 0x040c9850, |
| 407 | 0xbb0fc4b6, | 453 | 0xbb0fc4b6, |
| 408 | 0x0c9800bc, | 454 | 0x0c9800bc, |
| 409 | 0x020d9801, | 455 | 0x010d9800, |
| 410 | 0xf1060f98, | 456 | 0xf500e7f0, |
| 411 | 0xf50800e7, | 457 | 0xf0016f21, |
| 412 | 0xf5016621, | 458 | 0xa5f001ac, |
| 413 | 0xf4021521, | 459 | 0x00b7f104, |
| 414 | 0x12f40601, | 460 | 0x50b3f040, |
| 415 | /* 0x0535: ctx_xfer_post */ | 461 | 0xb6040c98, |
| 416 | 0xfc17f114, | 462 | 0xbcbb0fc4, |
| 417 | 0x0213f04a, | 463 | 0x010c9800, |
| 418 | 0xd00d27f0, | 464 | 0x98020d98, |
| 419 | 0x21f50012, | 465 | 0xe7f1060f, |
| 420 | /* 0x0546: ctx_xfer_done */ | 466 | 0x21f50800, |
| 421 | 0x21f50215, | 467 | 0x21f5016f, |
| 422 | 0x00f80479, | 468 | 0x01f4025e, |
| 469 | 0x0712f406, | ||
| 470 | /* 0x0618: ctx_xfer_post */ | ||
| 471 | 0x027f21f5, | ||
| 472 | /* 0x061c: ctx_xfer_done */ | ||
| 473 | 0x054721f5, | ||
| 474 | 0x000000f8, | ||
| 475 | 0x00000000, | ||
| 476 | 0x00000000, | ||
| 477 | 0x00000000, | ||
| 478 | 0x00000000, | ||
| 479 | 0x00000000, | ||
| 480 | 0x00000000, | ||
| 481 | 0x00000000, | ||
| 482 | 0x00000000, | ||
| 483 | 0x00000000, | ||
| 484 | 0x00000000, | ||
| 423 | 0x00000000, | 485 | 0x00000000, |
| 424 | 0x00000000, | 486 | 0x00000000, |
| 425 | 0x00000000, | 487 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h index dd346c2a1624..84dd32db28a0 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h | |||
| @@ -41,14 +41,14 @@ uint32_t nvd7_grgpc_data[] = { | |||
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | uint32_t nvd7_grgpc_code[] = { | 43 | uint32_t nvd7_grgpc_code[] = { |
| 44 | 0x03180ef5, | 44 | 0x03a10ef5, |
| 45 | /* 0x0004: queue_put */ | 45 | /* 0x0004: queue_put */ |
| 46 | 0x9800d898, | 46 | 0x9800d898, |
| 47 | 0x86f001d9, | 47 | 0x86f001d9, |
| 48 | 0x0489b808, | 48 | 0x0489b808, |
| 49 | 0xf00c1bf4, | 49 | 0xf00c1bf4, |
| 50 | 0x21f502f7, | 50 | 0x21f502f7, |
| 51 | 0x00f802fe, | 51 | 0x00f8037e, |
| 52 | /* 0x001c: queue_put_next */ | 52 | /* 0x001c: queue_put_next */ |
| 53 | 0xb60798c4, | 53 | 0xb60798c4, |
| 54 | 0x8dbb0384, | 54 | 0x8dbb0384, |
| @@ -72,184 +72,214 @@ uint32_t nvd7_grgpc_code[] = { | |||
| 72 | /* 0x0066: queue_get_done */ | 72 | /* 0x0066: queue_get_done */ |
| 73 | 0x00f80132, | 73 | 0x00f80132, |
| 74 | /* 0x0068: nv_rd32 */ | 74 | /* 0x0068: nv_rd32 */ |
| 75 | 0x0728b7f1, | 75 | 0xf002ecb9, |
| 76 | 0xb906b4b6, | 76 | 0x07f11fc9, |
| 77 | 0xc9f002ec, | 77 | 0x03f0ca00, |
| 78 | 0x00bcd01f, | 78 | 0x000cd001, |
| 79 | /* 0x0078: nv_rd32_wait */ | 79 | /* 0x007a: nv_rd32_wait */ |
| 80 | 0xc800bccf, | 80 | 0xc7f104bd, |
| 81 | 0x1bf41fcc, | 81 | 0xc3f0ca00, |
| 82 | 0x06a7f0fa, | 82 | 0x00cccf01, |
| 83 | 0x010921f5, | 83 | 0xf41fccc8, |
| 84 | 0xf840bfcf, | 84 | 0xa7f0f31b, |
| 85 | /* 0x008d: nv_wr32 */ | 85 | 0x1021f506, |
| 86 | 0x28b7f100, | 86 | 0x00f7f101, |
| 87 | 0x06b4b607, | 87 | 0x01f3f0cb, |
| 88 | 0xb980bfd0, | 88 | 0xf800ffcf, |
| 89 | 0xc9f002ec, | 89 | /* 0x009d: nv_wr32 */ |
| 90 | 0x1ec9f01f, | 90 | 0x0007f100, |
| 91 | /* 0x00a3: nv_wr32_wait */ | 91 | 0x0103f0cc, |
| 92 | 0xcf00bcd0, | 92 | 0xbd000fd0, |
| 93 | 0xccc800bc, | 93 | 0x02ecb904, |
| 94 | 0xfa1bf41f, | 94 | 0xf01fc9f0, |
| 95 | /* 0x00ae: watchdog_reset */ | 95 | 0x07f11ec9, |
| 96 | 0x87f100f8, | 96 | 0x03f0ca00, |
| 97 | 0x84b60430, | 97 | 0x000cd001, |
| 98 | 0x1ff9f006, | 98 | /* 0x00be: nv_wr32_wait */ |
| 99 | 0xf8008fd0, | 99 | 0xc7f104bd, |
| 100 | /* 0x00bd: watchdog_clear */ | 100 | 0xc3f0ca00, |
| 101 | 0x3087f100, | 101 | 0x00cccf01, |
| 102 | 0x0684b604, | 102 | 0xf41fccc8, |
| 103 | 0xf80080d0, | 103 | 0x00f8f31b, |
| 104 | /* 0x00c9: wait_donez */ | 104 | /* 0x00d0: wait_donez */ |
| 105 | 0xf094bd00, | 105 | 0x99f094bd, |
| 106 | 0x07f10099, | 106 | 0x0007f100, |
| 107 | 0x03f00f00, | 107 | 0x0203f00f, |
| 108 | 0x0009d002, | 108 | 0xbd0009d0, |
| 109 | 0x07f104bd, | 109 | 0x0007f104, |
| 110 | 0x03f00600, | 110 | 0x0203f006, |
| 111 | 0x000ad002, | 111 | 0xbd000ad0, |
| 112 | /* 0x00e6: wait_donez_ne */ | 112 | /* 0x00ed: wait_donez_ne */ |
| 113 | 0x87f104bd, | 113 | 0x0087f104, |
| 114 | 0x83f00000, | 114 | 0x0183f000, |
| 115 | 0x0088cf01, | 115 | 0xff0088cf, |
| 116 | 0xf4888aff, | 116 | 0x1bf4888a, |
| 117 | 0x94bdf31b, | 117 | 0xf094bdf3, |
| 118 | 0xf10099f0, | ||
| 119 | 0xf0170007, | ||
| 120 | 0x09d00203, | ||
| 121 | 0xf804bd00, | ||
| 122 | /* 0x0109: wait_doneo */ | ||
| 123 | 0xf094bd00, | ||
| 124 | 0x07f10099, | 118 | 0x07f10099, |
| 125 | 0x03f00f00, | 119 | 0x03f01700, |
| 126 | 0x0009d002, | 120 | 0x0009d002, |
| 127 | 0x87f104bd, | 121 | 0x00f804bd, |
| 128 | 0x84b60818, | 122 | /* 0x0110: wait_doneo */ |
| 129 | 0x008ad006, | ||
| 130 | /* 0x0124: wait_doneo_e */ | ||
| 131 | 0x040087f1, | ||
| 132 | 0xcf0684b6, | ||
| 133 | 0x8aff0088, | ||
| 134 | 0xf30bf488, | ||
| 135 | 0x99f094bd, | 123 | 0x99f094bd, |
| 136 | 0x0007f100, | 124 | 0x0007f100, |
| 137 | 0x0203f017, | 125 | 0x0203f00f, |
| 138 | 0xbd0009d0, | 126 | 0xbd0009d0, |
| 139 | /* 0x0147: mmctx_size */ | 127 | 0x0007f104, |
| 140 | 0xbd00f804, | 128 | 0x0203f006, |
| 141 | /* 0x0149: nv_mmctx_size_loop */ | 129 | 0xbd000ad0, |
| 142 | 0x00e89894, | 130 | /* 0x012d: wait_doneo_e */ |
| 143 | 0xb61a85b6, | 131 | 0x0087f104, |
| 144 | 0x84b60180, | 132 | 0x0183f000, |
| 145 | 0x0098bb02, | 133 | 0xff0088cf, |
| 146 | 0xb804e0b6, | 134 | 0x0bf4888a, |
| 147 | 0x1bf404ef, | 135 | 0xf094bdf3, |
| 148 | 0x029fb9eb, | 136 | 0x07f10099, |
| 149 | /* 0x0166: mmctx_xfer */ | 137 | 0x03f01700, |
| 150 | 0x94bd00f8, | 138 | 0x0009d002, |
| 151 | 0xf10199f0, | 139 | 0x00f804bd, |
| 152 | 0xf00f0007, | 140 | /* 0x0150: mmctx_size */ |
| 153 | 0x09d00203, | 141 | /* 0x0152: nv_mmctx_size_loop */ |
| 154 | 0xf104bd00, | 142 | 0xe89894bd, |
| 155 | 0xb6071087, | 143 | 0x1a85b600, |
| 156 | 0x94bd0684, | 144 | 0xb60180b6, |
| 157 | 0xf405bbfd, | 145 | 0x98bb0284, |
| 158 | 0x8bd0090b, | 146 | 0x04e0b600, |
| 159 | 0x0099f000, | 147 | 0xf404efb8, |
| 160 | /* 0x018c: mmctx_base_disabled */ | 148 | 0x9fb9eb1b, |
| 161 | 0xf405eefd, | 149 | /* 0x016f: mmctx_xfer */ |
| 162 | 0x8ed00c0b, | 150 | 0xbd00f802, |
| 163 | 0xc08fd080, | 151 | 0x0199f094, |
| 164 | /* 0x019b: mmctx_multi_disabled */ | 152 | 0x0f0007f1, |
| 165 | 0xb70199f0, | 153 | 0xd00203f0, |
| 166 | 0xc8010080, | 154 | 0x04bd0009, |
| 155 | 0xbbfd94bd, | ||
| 156 | 0x120bf405, | ||
| 157 | 0xc40007f1, | ||
| 158 | 0xd00103f0, | ||
| 159 | 0x04bd000b, | ||
| 160 | /* 0x0197: mmctx_base_disabled */ | ||
| 161 | 0xfd0099f0, | ||
| 162 | 0x0bf405ee, | ||
| 163 | 0x0007f11e, | ||
| 164 | 0x0103f0c6, | ||
| 165 | 0xbd000ed0, | ||
| 166 | 0x0007f104, | ||
| 167 | 0x0103f0c7, | ||
| 168 | 0xbd000fd0, | ||
| 169 | 0x0199f004, | ||
| 170 | /* 0x01b8: mmctx_multi_disabled */ | ||
| 171 | 0xb600abc8, | ||
| 172 | 0xb9f010b4, | ||
| 173 | 0x01aec80c, | ||
| 174 | 0xfd11e4b6, | ||
| 175 | 0x07f105be, | ||
| 176 | 0x03f0c500, | ||
| 177 | 0x000bd001, | ||
| 178 | /* 0x01d6: mmctx_exec_loop */ | ||
| 179 | /* 0x01d6: mmctx_wait_free */ | ||
| 180 | 0xe7f104bd, | ||
| 181 | 0xe3f0c500, | ||
| 182 | 0x00eecf01, | ||
| 183 | 0xf41fe4f0, | ||
| 184 | 0xce98f30b, | ||
| 185 | 0x05e9fd00, | ||
| 186 | 0xc80007f1, | ||
| 187 | 0xd00103f0, | ||
| 188 | 0x04bd000e, | ||
| 189 | 0xb804c0b6, | ||
| 190 | 0x1bf404cd, | ||
| 191 | 0x02abc8d8, | ||
| 192 | /* 0x0207: mmctx_fini_wait */ | ||
| 193 | 0xf11f1bf4, | ||
| 194 | 0xf0c500b7, | ||
| 195 | 0xbbcf01b3, | ||
| 196 | 0x1fb4f000, | ||
| 197 | 0xf410b4b0, | ||
| 198 | 0xa7f0f01b, | ||
| 199 | 0xd021f402, | ||
| 200 | /* 0x0223: mmctx_stop */ | ||
| 201 | 0xc82b0ef4, | ||
| 167 | 0xb4b600ab, | 202 | 0xb4b600ab, |
| 168 | 0x0cb9f010, | 203 | 0x0cb9f010, |
| 169 | 0xb601aec8, | 204 | 0xf112b9f0, |
| 170 | 0xbefd11e4, | 205 | 0xf0c50007, |
| 171 | 0x008bd005, | 206 | 0x0bd00103, |
| 172 | /* 0x01b4: mmctx_exec_loop */ | 207 | /* 0x023b: mmctx_stop_wait */ |
| 173 | /* 0x01b4: mmctx_wait_free */ | 208 | 0xf104bd00, |
| 174 | 0xf0008ecf, | 209 | 0xf0c500b7, |
| 175 | 0x0bf41fe4, | 210 | 0xbbcf01b3, |
| 176 | 0x00ce98fa, | 211 | 0x12bbc800, |
| 177 | 0xd005e9fd, | 212 | /* 0x024b: mmctx_done */ |
| 178 | 0xc0b6c08e, | 213 | 0xbdf31bf4, |
| 179 | 0x04cdb804, | 214 | 0x0199f094, |
| 180 | 0xc8e81bf4, | 215 | 0x170007f1, |
| 181 | 0x1bf402ab, | 216 | 0xd00203f0, |
| 182 | /* 0x01d5: mmctx_fini_wait */ | 217 | 0x04bd0009, |
| 183 | 0x008bcf18, | 218 | /* 0x025e: strand_wait */ |
| 184 | 0xb01fb4f0, | 219 | 0xa0f900f8, |
| 185 | 0x1bf410b4, | 220 | 0xf402a7f0, |
| 186 | 0x02a7f0f7, | 221 | 0xa0fcd021, |
| 187 | 0xf4c921f4, | 222 | /* 0x026a: strand_pre */ |
| 188 | /* 0x01ea: mmctx_stop */ | 223 | 0x97f000f8, |
| 189 | 0xabc81b0e, | 224 | 0xfc07f10c, |
| 190 | 0x10b4b600, | 225 | 0x0203f04a, |
| 191 | 0xf00cb9f0, | 226 | 0xbd0009d0, |
| 192 | 0x8bd012b9, | 227 | 0x5e21f504, |
| 193 | /* 0x01f9: mmctx_stop_wait */ | 228 | /* 0x027f: strand_post */ |
| 194 | 0x008bcf00, | 229 | 0xf000f802, |
| 195 | 0xf412bbc8, | 230 | 0x07f10d97, |
| 196 | /* 0x0202: mmctx_done */ | 231 | 0x03f04afc, |
| 197 | 0x94bdfa1b, | ||
| 198 | 0xf10199f0, | ||
| 199 | 0xf0170007, | ||
| 200 | 0x09d00203, | ||
| 201 | 0xf804bd00, | ||
| 202 | /* 0x0215: strand_wait */ | ||
| 203 | 0xf0a0f900, | ||
| 204 | 0x21f402a7, | ||
| 205 | 0xf8a0fcc9, | ||
| 206 | /* 0x0221: strand_pre */ | ||
| 207 | 0xfc87f100, | ||
| 208 | 0x0283f04a, | ||
| 209 | 0xd00c97f0, | ||
| 210 | 0x21f50089, | ||
| 211 | 0x00f80215, | ||
| 212 | /* 0x0234: strand_post */ | ||
| 213 | 0x4afc87f1, | ||
| 214 | 0xf00283f0, | ||
| 215 | 0x89d00d97, | ||
| 216 | 0x1521f500, | ||
| 217 | /* 0x0247: strand_set */ | ||
| 218 | 0xf100f802, | ||
| 219 | 0xf04ffca7, | ||
| 220 | 0xaba202a3, | ||
| 221 | 0xc7f00500, | ||
| 222 | 0x00acd00f, | ||
| 223 | 0xd00bc7f0, | ||
| 224 | 0x21f500bc, | ||
| 225 | 0xaed00215, | ||
| 226 | 0x0ac7f000, | ||
| 227 | 0xf500bcd0, | ||
| 228 | 0xf8021521, | ||
| 229 | /* 0x0271: strand_ctx_init */ | ||
| 230 | 0xf094bd00, | ||
| 231 | 0x07f10399, | ||
| 232 | 0x03f00f00, | ||
| 233 | 0x0009d002, | 232 | 0x0009d002, |
| 234 | 0x21f504bd, | 233 | 0x21f504bd, |
| 235 | 0xe7f00221, | 234 | 0x00f8025e, |
| 236 | 0x4721f503, | 235 | /* 0x0294: strand_set */ |
| 237 | 0xfca7f102, | 236 | 0xf10fc7f0, |
| 238 | 0x02a3f046, | 237 | 0xf04ffc07, |
| 239 | 0x0400aba0, | 238 | 0x0cd00203, |
| 240 | 0xf040a0d0, | 239 | 0xf004bd00, |
| 241 | 0xbcd001c7, | 240 | 0x07f10bc7, |
| 242 | 0x1521f500, | 241 | 0x03f04afc, |
| 243 | 0x010c9202, | 242 | 0x000cd002, |
| 244 | 0xf000acd0, | 243 | 0x07f104bd, |
| 245 | 0xbcd002c7, | 244 | 0x03f04ffc, |
| 246 | 0x1521f500, | 245 | 0x000ed002, |
| 247 | 0x3421f502, | 246 | 0xc7f004bd, |
| 248 | 0x8087f102, | 247 | 0xfc07f10a, |
| 249 | 0x0684b608, | 248 | 0x0203f04a, |
| 250 | 0xb70089cf, | 249 | 0xbd000cd0, |
| 251 | 0x95220080, | 250 | 0x5e21f504, |
| 252 | /* 0x02ca: ctx_init_strand_loop */ | 251 | /* 0x02d3: strand_ctx_init */ |
| 252 | 0xbd00f802, | ||
| 253 | 0x0399f094, | ||
| 254 | 0x0f0007f1, | ||
| 255 | 0xd00203f0, | ||
| 256 | 0x04bd0009, | ||
| 257 | 0x026a21f5, | ||
| 258 | 0xf503e7f0, | ||
| 259 | 0xbd029421, | ||
| 260 | 0xfc07f1c4, | ||
| 261 | 0x0203f047, | ||
| 262 | 0xbd000cd0, | ||
| 263 | 0x01c7f004, | ||
| 264 | 0x4afc07f1, | ||
| 265 | 0xd00203f0, | ||
| 266 | 0x04bd000c, | ||
| 267 | 0x025e21f5, | ||
| 268 | 0xf1010c92, | ||
| 269 | 0xf046fc07, | ||
| 270 | 0x0cd00203, | ||
| 271 | 0xf004bd00, | ||
| 272 | 0x07f102c7, | ||
| 273 | 0x03f04afc, | ||
| 274 | 0x000cd002, | ||
| 275 | 0x21f504bd, | ||
| 276 | 0x21f5025e, | ||
| 277 | 0x87f1027f, | ||
| 278 | 0x83f04200, | ||
| 279 | 0x0097f102, | ||
| 280 | 0x0293f020, | ||
| 281 | 0x950099cf, | ||
| 282 | /* 0x034a: ctx_init_strand_loop */ | ||
| 253 | 0x8ed008fe, | 283 | 0x8ed008fe, |
| 254 | 0x408ed000, | 284 | 0x408ed000, |
| 255 | 0xb6808acf, | 285 | 0xb6808acf, |
| @@ -263,198 +293,230 @@ uint32_t nvd7_grgpc_code[] = { | |||
| 263 | 0x170007f1, | 293 | 0x170007f1, |
| 264 | 0xd00203f0, | 294 | 0xd00203f0, |
| 265 | 0x04bd0009, | 295 | 0x04bd0009, |
| 266 | /* 0x02fe: error */ | 296 | /* 0x037e: error */ |
| 267 | 0xe0f900f8, | 297 | 0xe0f900f8, |
| 268 | 0x9814e7f1, | 298 | 0xf102ffb9, |
| 269 | 0xf440e3f0, | 299 | 0xf09814e7, |
| 270 | 0xe0b78d21, | 300 | 0x21f440e3, |
| 271 | 0xf7f0041c, | 301 | 0x01f7f09d, |
| 272 | 0x8d21f401, | 302 | 0xf102ffb9, |
| 273 | 0x00f8e0fc, | 303 | 0xf09c1ce7, |
| 274 | /* 0x0318: init */ | 304 | 0x21f440e3, |
| 275 | 0x04fe04bd, | 305 | 0xf8e0fc9d, |
| 276 | 0x0017f100, | 306 | /* 0x03a1: init */ |
| 277 | 0x0227f012, | 307 | 0xfe04bd00, |
| 278 | 0xf10012d0, | 308 | 0x27f00004, |
| 279 | 0xfe047017, | 309 | 0x0007f102, |
| 280 | 0x17f10010, | 310 | 0x0003f012, |
| 281 | 0x10d00400, | 311 | 0xbd0002d0, |
| 282 | 0x0427f0c0, | 312 | 0x1f17f104, |
| 283 | 0xf40012d0, | 313 | 0x0010fe05, |
| 284 | 0x17f11031, | 314 | 0x070007f1, |
| 285 | 0x14b60608, | 315 | 0xd00003f0, |
| 286 | 0x0012cf06, | 316 | 0x04bd0000, |
| 317 | 0xf10427f0, | ||
| 318 | 0xf0040007, | ||
| 319 | 0x02d00003, | ||
| 320 | 0xf404bd00, | ||
| 321 | 0x27f11031, | ||
| 322 | 0x23f08200, | ||
| 323 | 0x0022cf01, | ||
| 287 | 0xf00137f0, | 324 | 0xf00137f0, |
| 288 | 0x32bb1f24, | 325 | 0x32bb1f24, |
| 289 | 0x0132b604, | 326 | 0x0132b604, |
| 290 | 0x80050280, | 327 | 0x80050280, |
| 291 | 0x10b70603, | 328 | 0x27f10603, |
| 292 | 0x12cf0400, | 329 | 0x23f08600, |
| 293 | 0x04028000, | 330 | 0x0022cf01, |
| 294 | 0x0c30e7f1, | 331 | 0xf1040280, |
| 295 | 0xbd50e3f0, | 332 | 0xf00c30e7, |
| 296 | 0xbd34bd24, | 333 | 0x24bd50e3, |
| 297 | /* 0x0371: init_unk_loop */ | 334 | 0x44bd34bd, |
| 298 | 0x6821f444, | 335 | /* 0x0410: init_unk_loop */ |
| 299 | 0xf400f6b0, | 336 | 0xb06821f4, |
| 300 | 0xf7f00f0b, | 337 | 0x0bf400f6, |
| 301 | 0x04f2bb01, | 338 | 0x01f7f00f, |
| 302 | 0xb6054ffd, | 339 | 0xfd04f2bb, |
| 303 | /* 0x0386: init_unk_next */ | 340 | 0x30b6054f, |
| 304 | 0x20b60130, | 341 | /* 0x0425: init_unk_next */ |
| 305 | 0x04e0b601, | 342 | 0x0120b601, |
| 306 | 0xf40126b0, | 343 | 0xb004e0b6, |
| 307 | /* 0x0392: init_unk_done */ | 344 | 0x1bf40126, |
| 308 | 0x0380e21b, | 345 | /* 0x0431: init_unk_done */ |
| 309 | 0x08048007, | 346 | 0x070380e2, |
| 310 | 0x010027f1, | 347 | 0xf1080480, |
| 311 | 0xcf0223f0, | 348 | 0xf0010027, |
| 312 | 0x34bd0022, | 349 | 0x22cf0223, |
| 313 | 0x070047f1, | 350 | 0x9534bd00, |
| 314 | 0x950644b6, | 351 | 0x07f10825, |
| 315 | 0x45d00825, | 352 | 0x03f0c000, |
| 316 | 0x4045d000, | 353 | 0x0005d001, |
| 317 | 0x98000e98, | 354 | 0x07f104bd, |
| 318 | 0x21f5010f, | 355 | 0x03f0c100, |
| 319 | 0x2fbb0147, | 356 | 0x0005d001, |
| 320 | 0x003fbb00, | 357 | 0x0e9804bd, |
| 321 | 0x98010e98, | 358 | 0x010f9800, |
| 322 | 0x21f5020f, | 359 | 0x015021f5, |
| 323 | 0x0e980147, | 360 | 0xbb002fbb, |
| 324 | 0x00effd05, | 361 | 0x0e98003f, |
| 325 | 0xbb002ebb, | 362 | 0x020f9801, |
| 326 | 0x0e98003e, | 363 | 0x015021f5, |
| 327 | 0x030f9802, | 364 | 0xfd050e98, |
| 328 | 0x014721f5, | ||
| 329 | 0xfd070e98, | ||
| 330 | 0x2ebb00ef, | 365 | 0x2ebb00ef, |
| 331 | 0x003ebb00, | 366 | 0x003ebb00, |
| 332 | 0x130040b7, | 367 | 0x98020e98, |
| 333 | 0xd00235b6, | 368 | 0x21f5030f, |
| 334 | 0x25b60043, | 369 | 0x0e980150, |
| 335 | 0x0635b608, | 370 | 0x00effd07, |
| 336 | 0xb60120b6, | 371 | 0xbb002ebb, |
| 337 | 0x24b60130, | 372 | 0x35b6003e, |
| 338 | 0x0834b608, | 373 | 0x0007f102, |
| 339 | 0xf5022fb9, | 374 | 0x0103f0d3, |
| 340 | 0xbb027121, | 375 | 0xbd0003d0, |
| 341 | 0x07f1003f, | 376 | 0x0825b604, |
| 342 | 0x03f00100, | 377 | 0xb60635b6, |
| 343 | 0x0003d002, | 378 | 0x30b60120, |
| 344 | 0x24bd04bd, | 379 | 0x0824b601, |
| 345 | 0xf11f29f0, | 380 | 0xb90834b6, |
| 346 | 0xf0080007, | 381 | 0x21f5022f, |
| 347 | 0x02d00203, | 382 | 0x3fbb02d3, |
| 348 | /* 0x0433: main */ | 383 | 0x0007f100, |
| 384 | 0x0203f001, | ||
| 385 | 0xbd0003d0, | ||
| 386 | 0xf024bd04, | ||
| 387 | 0x07f11f29, | ||
| 388 | 0x03f00800, | ||
| 389 | 0x0002d002, | ||
| 390 | /* 0x04e2: main */ | ||
| 391 | 0x31f404bd, | ||
| 392 | 0x0028f400, | ||
| 393 | 0xf424d7f0, | ||
| 394 | 0x01f43921, | ||
| 395 | 0x04e4b0f4, | ||
| 396 | 0xfe1e18f4, | ||
| 397 | 0x27f00181, | ||
| 398 | 0xfd20bd06, | ||
| 399 | 0xe4b60412, | ||
| 400 | 0x051efd01, | ||
| 401 | 0xf50018fe, | ||
| 402 | 0xf405d721, | ||
| 403 | /* 0x0512: main_not_ctx_xfer */ | ||
| 404 | 0xef94d30e, | ||
| 405 | 0x01f5f010, | ||
| 406 | 0x037e21f5, | ||
| 407 | /* 0x051f: ih */ | ||
| 408 | 0xf9c60ef4, | ||
| 409 | 0x0188fe80, | ||
| 410 | 0x90f980f9, | ||
| 411 | 0xb0f9a0f9, | ||
| 412 | 0xe0f9d0f9, | ||
| 413 | 0x04bdf0f9, | ||
| 414 | 0x0200a7f1, | ||
| 415 | 0xcf00a3f0, | ||
| 416 | 0xabc400aa, | ||
| 417 | 0x2c0bf404, | ||
| 418 | 0xf124d7f0, | ||
| 419 | 0xf01a00e7, | ||
| 420 | 0xeecf00e3, | ||
| 421 | 0x00f7f100, | ||
| 422 | 0x00f3f019, | ||
| 423 | 0xf400ffcf, | ||
| 424 | 0xe7f00421, | ||
| 425 | 0x0007f101, | ||
| 426 | 0x0003f01d, | ||
| 427 | 0xbd000ed0, | ||
| 428 | /* 0x056d: ih_no_fifo */ | ||
| 429 | 0x0007f104, | ||
| 430 | 0x0003f001, | ||
| 431 | 0xbd000ad0, | ||
| 432 | 0xfcf0fc04, | ||
| 433 | 0xfcd0fce0, | ||
| 434 | 0xfca0fcb0, | ||
| 435 | 0xfe80fc90, | ||
| 436 | 0x80fc0088, | ||
| 437 | 0xf80032f4, | ||
| 438 | /* 0x0591: hub_barrier_done */ | ||
| 439 | 0x01f7f001, | ||
| 440 | 0xbb040e98, | ||
| 441 | 0xffb904fe, | ||
| 442 | 0x18e7f102, | ||
| 443 | 0x40e3f094, | ||
| 444 | 0xf89d21f4, | ||
| 445 | /* 0x05a9: ctx_redswitch */ | ||
| 446 | 0x20f7f000, | ||
| 447 | 0x850007f1, | ||
| 448 | 0xd00103f0, | ||
| 449 | 0x04bd000f, | ||
| 450 | /* 0x05bb: ctx_redswitch_delay */ | ||
| 451 | 0xb608e7f0, | ||
| 452 | 0x1bf401e2, | ||
| 453 | 0x00f5f1fd, | ||
| 454 | 0x00f5f108, | ||
| 455 | 0x0007f102, | ||
| 456 | 0x0103f085, | ||
| 457 | 0xbd000fd0, | ||
| 458 | /* 0x05d7: ctx_xfer */ | ||
| 459 | 0xf100f804, | ||
| 460 | 0xf0810007, | ||
| 461 | 0x0fd00203, | ||
| 349 | 0xf404bd00, | 462 | 0xf404bd00, |
| 350 | 0x28f40031, | 463 | 0x21f50711, |
| 351 | 0x24d7f000, | 464 | /* 0x05ea: ctx_xfer_not_load */ |
| 352 | 0xf43921f4, | 465 | 0x21f505a9, |
| 353 | 0xe4b0f401, | 466 | 0x24bd026a, |
| 354 | 0x1e18f404, | 467 | 0x47fc07f1, |
| 355 | 0xf00181fe, | 468 | 0xd00203f0, |
| 356 | 0x20bd0627, | 469 | 0x04bd0002, |
| 357 | 0xb60412fd, | 470 | 0xb6012cf0, |
| 358 | 0x1efd01e4, | 471 | 0x07f10320, |
| 359 | 0x0018fe05, | 472 | 0x03f04afc, |
| 360 | 0x04f721f5, | 473 | 0x0002d002, |
| 361 | /* 0x0463: main_not_ctx_xfer */ | 474 | 0xacf004bd, |
| 362 | 0x94d30ef4, | 475 | 0x02a5f001, |
| 363 | 0xf5f010ef, | 476 | 0x0000b7f1, |
| 364 | 0xfe21f501, | ||
| 365 | 0xc60ef402, | ||
| 366 | /* 0x0470: ih */ | ||
| 367 | 0x88fe80f9, | ||
| 368 | 0xf980f901, | ||
| 369 | 0xf9a0f990, | ||
| 370 | 0xf9d0f9b0, | ||
| 371 | 0xbdf0f9e0, | ||
| 372 | 0x800acf04, | ||
| 373 | 0xf404abc4, | ||
| 374 | 0xb7f11d0b, | ||
| 375 | 0xd7f01900, | ||
| 376 | 0x40becf24, | ||
| 377 | 0xf400bfcf, | ||
| 378 | 0xb0b70421, | ||
| 379 | 0xe7f00400, | ||
| 380 | 0x00bed001, | ||
| 381 | /* 0x04a8: ih_no_fifo */ | ||
| 382 | 0xfc400ad0, | ||
| 383 | 0xfce0fcf0, | ||
| 384 | 0xfcb0fcd0, | ||
| 385 | 0xfc90fca0, | ||
| 386 | 0x0088fe80, | ||
| 387 | 0x32f480fc, | ||
| 388 | /* 0x04c3: hub_barrier_done */ | ||
| 389 | 0xf001f800, | ||
| 390 | 0x0e9801f7, | ||
| 391 | 0x04febb04, | ||
| 392 | 0x9418e7f1, | ||
| 393 | 0xf440e3f0, | ||
| 394 | 0x00f88d21, | ||
| 395 | /* 0x04d8: ctx_redswitch */ | ||
| 396 | 0x0614e7f1, | ||
| 397 | 0xf006e4b6, | ||
| 398 | 0xefd020f7, | ||
| 399 | 0x08f7f000, | ||
| 400 | /* 0x04e8: ctx_redswitch_delay */ | ||
| 401 | 0xf401f2b6, | ||
| 402 | 0xf7f1fd1b, | ||
| 403 | 0xefd00a20, | ||
| 404 | /* 0x04f7: ctx_xfer */ | ||
| 405 | 0xf100f800, | ||
| 406 | 0xb60a0417, | ||
| 407 | 0x1fd00614, | ||
| 408 | 0x0711f400, | ||
| 409 | 0x04d821f5, | ||
| 410 | /* 0x0508: ctx_xfer_not_load */ | ||
| 411 | 0x4afc17f1, | ||
| 412 | 0xf00213f0, | ||
| 413 | 0x12d00c27, | ||
| 414 | 0x1521f500, | ||
| 415 | 0xfc27f102, | ||
| 416 | 0x0223f047, | ||
| 417 | 0xf00020d0, | ||
| 418 | 0x20b6012c, | ||
| 419 | 0x0012d003, | ||
| 420 | 0xf001acf0, | ||
| 421 | 0xb7f002a5, | ||
| 422 | 0x50b3f000, | ||
| 423 | 0xb6040c98, | ||
| 424 | 0xbcbb0fc4, | ||
| 425 | 0x000c9800, | ||
| 426 | 0xf0010d98, | ||
| 427 | 0x21f500e7, | ||
| 428 | 0xacf00166, | ||
| 429 | 0x00b7f101, | ||
| 430 | 0x50b3f040, | ||
| 431 | 0xb6040c98, | ||
| 432 | 0xbcbb0fc4, | ||
| 433 | 0x010c9800, | ||
| 434 | 0x98020d98, | ||
| 435 | 0xe7f1060f, | ||
| 436 | 0x21f50800, | ||
| 437 | 0xacf00166, | ||
| 438 | 0x04a5f001, | ||
| 439 | 0x3000b7f1, | ||
| 440 | 0x9850b3f0, | 477 | 0x9850b3f0, |
| 441 | 0xc4b6040c, | 478 | 0xc4b6040c, |
| 442 | 0x00bcbb0f, | 479 | 0x00bcbb0f, |
| 443 | 0x98020c98, | 480 | 0x98000c98, |
| 444 | 0x0f98030d, | 481 | 0xe7f0010d, |
| 445 | 0x00e7f108, | 482 | 0x6f21f500, |
| 446 | 0x6621f502, | 483 | 0x01acf001, |
| 447 | 0x1521f501, | 484 | 0x4000b7f1, |
| 448 | 0x0601f402, | 485 | 0x9850b3f0, |
| 449 | /* 0x05a3: ctx_xfer_post */ | 486 | 0xc4b6040c, |
| 450 | 0xf11412f4, | 487 | 0x00bcbb0f, |
| 451 | 0xf04afc17, | 488 | 0x98010c98, |
| 452 | 0x27f00213, | 489 | 0x0f98020d, |
| 453 | 0x0012d00d, | 490 | 0x00e7f106, |
| 454 | 0x021521f5, | 491 | 0x6f21f508, |
| 455 | /* 0x05b4: ctx_xfer_done */ | 492 | 0x01acf001, |
| 456 | 0x04c321f5, | 493 | 0xf104a5f0, |
| 457 | 0x000000f8, | 494 | 0xf03000b7, |
| 495 | 0x0c9850b3, | ||
| 496 | 0x0fc4b604, | ||
| 497 | 0x9800bcbb, | ||
| 498 | 0x0d98020c, | ||
| 499 | 0x080f9803, | ||
| 500 | 0x0200e7f1, | ||
| 501 | 0x016f21f5, | ||
| 502 | 0x025e21f5, | ||
| 503 | 0xf40601f4, | ||
| 504 | /* 0x0686: ctx_xfer_post */ | ||
| 505 | 0x21f50712, | ||
| 506 | /* 0x068a: ctx_xfer_done */ | ||
| 507 | 0x21f5027f, | ||
| 508 | 0x00f80591, | ||
| 509 | 0x00000000, | ||
| 510 | 0x00000000, | ||
| 511 | 0x00000000, | ||
| 512 | 0x00000000, | ||
| 513 | 0x00000000, | ||
| 514 | 0x00000000, | ||
| 515 | 0x00000000, | ||
| 516 | 0x00000000, | ||
| 517 | 0x00000000, | ||
| 518 | 0x00000000, | ||
| 519 | 0x00000000, | ||
| 458 | 0x00000000, | 520 | 0x00000000, |
| 459 | 0x00000000, | 521 | 0x00000000, |
| 460 | 0x00000000, | 522 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h index 7ff5ef6b0804..b6da800ee9c2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h | |||
| @@ -41,14 +41,14 @@ uint32_t nve0_grgpc_data[] = { | |||
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | uint32_t nve0_grgpc_code[] = { | 43 | uint32_t nve0_grgpc_code[] = { |
| 44 | 0x03180ef5, | 44 | 0x03a10ef5, |
| 45 | /* 0x0004: queue_put */ | 45 | /* 0x0004: queue_put */ |
| 46 | 0x9800d898, | 46 | 0x9800d898, |
| 47 | 0x86f001d9, | 47 | 0x86f001d9, |
| 48 | 0x0489b808, | 48 | 0x0489b808, |
| 49 | 0xf00c1bf4, | 49 | 0xf00c1bf4, |
| 50 | 0x21f502f7, | 50 | 0x21f502f7, |
| 51 | 0x00f802fe, | 51 | 0x00f8037e, |
| 52 | /* 0x001c: queue_put_next */ | 52 | /* 0x001c: queue_put_next */ |
| 53 | 0xb60798c4, | 53 | 0xb60798c4, |
| 54 | 0x8dbb0384, | 54 | 0x8dbb0384, |
| @@ -72,184 +72,214 @@ uint32_t nve0_grgpc_code[] = { | |||
| 72 | /* 0x0066: queue_get_done */ | 72 | /* 0x0066: queue_get_done */ |
| 73 | 0x00f80132, | 73 | 0x00f80132, |
| 74 | /* 0x0068: nv_rd32 */ | 74 | /* 0x0068: nv_rd32 */ |
| 75 | 0x0728b7f1, | 75 | 0xf002ecb9, |
| 76 | 0xb906b4b6, | 76 | 0x07f11fc9, |
| 77 | 0xc9f002ec, | 77 | 0x03f0ca00, |
| 78 | 0x00bcd01f, | 78 | 0x000cd001, |
| 79 | /* 0x0078: nv_rd32_wait */ | 79 | /* 0x007a: nv_rd32_wait */ |
| 80 | 0xc800bccf, | 80 | 0xc7f104bd, |
| 81 | 0x1bf41fcc, | 81 | 0xc3f0ca00, |
| 82 | 0x06a7f0fa, | 82 | 0x00cccf01, |
| 83 | 0x010921f5, | 83 | 0xf41fccc8, |
| 84 | 0xf840bfcf, | 84 | 0xa7f0f31b, |
| 85 | /* 0x008d: nv_wr32 */ | 85 | 0x1021f506, |
| 86 | 0x28b7f100, | 86 | 0x00f7f101, |
| 87 | 0x06b4b607, | 87 | 0x01f3f0cb, |
| 88 | 0xb980bfd0, | 88 | 0xf800ffcf, |
| 89 | 0xc9f002ec, | 89 | /* 0x009d: nv_wr32 */ |
| 90 | 0x1ec9f01f, | 90 | 0x0007f100, |
| 91 | /* 0x00a3: nv_wr32_wait */ | 91 | 0x0103f0cc, |
| 92 | 0xcf00bcd0, | 92 | 0xbd000fd0, |
| 93 | 0xccc800bc, | 93 | 0x02ecb904, |
| 94 | 0xfa1bf41f, | 94 | 0xf01fc9f0, |
| 95 | /* 0x00ae: watchdog_reset */ | 95 | 0x07f11ec9, |
| 96 | 0x87f100f8, | 96 | 0x03f0ca00, |
| 97 | 0x84b60430, | 97 | 0x000cd001, |
| 98 | 0x1ff9f006, | 98 | /* 0x00be: nv_wr32_wait */ |
| 99 | 0xf8008fd0, | 99 | 0xc7f104bd, |
| 100 | /* 0x00bd: watchdog_clear */ | 100 | 0xc3f0ca00, |
| 101 | 0x3087f100, | 101 | 0x00cccf01, |
| 102 | 0x0684b604, | 102 | 0xf41fccc8, |
| 103 | 0xf80080d0, | 103 | 0x00f8f31b, |
| 104 | /* 0x00c9: wait_donez */ | 104 | /* 0x00d0: wait_donez */ |
| 105 | 0xf094bd00, | 105 | 0x99f094bd, |
| 106 | 0x07f10099, | 106 | 0x0007f100, |
| 107 | 0x03f00f00, | 107 | 0x0203f00f, |
| 108 | 0x0009d002, | 108 | 0xbd0009d0, |
| 109 | 0x07f104bd, | 109 | 0x0007f104, |
| 110 | 0x03f00600, | 110 | 0x0203f006, |
| 111 | 0x000ad002, | 111 | 0xbd000ad0, |
| 112 | /* 0x00e6: wait_donez_ne */ | 112 | /* 0x00ed: wait_donez_ne */ |
| 113 | 0x87f104bd, | 113 | 0x0087f104, |
| 114 | 0x83f00000, | 114 | 0x0183f000, |
| 115 | 0x0088cf01, | 115 | 0xff0088cf, |
| 116 | 0xf4888aff, | 116 | 0x1bf4888a, |
| 117 | 0x94bdf31b, | 117 | 0xf094bdf3, |
| 118 | 0xf10099f0, | ||
| 119 | 0xf0170007, | ||
| 120 | 0x09d00203, | ||
| 121 | 0xf804bd00, | ||
| 122 | /* 0x0109: wait_doneo */ | ||
| 123 | 0xf094bd00, | ||
| 124 | 0x07f10099, | 118 | 0x07f10099, |
| 125 | 0x03f00f00, | 119 | 0x03f01700, |
| 126 | 0x0009d002, | 120 | 0x0009d002, |
| 127 | 0x87f104bd, | 121 | 0x00f804bd, |
| 128 | 0x84b60818, | 122 | /* 0x0110: wait_doneo */ |
| 129 | 0x008ad006, | ||
| 130 | /* 0x0124: wait_doneo_e */ | ||
| 131 | 0x040087f1, | ||
| 132 | 0xcf0684b6, | ||
| 133 | 0x8aff0088, | ||
| 134 | 0xf30bf488, | ||
| 135 | 0x99f094bd, | 123 | 0x99f094bd, |
| 136 | 0x0007f100, | 124 | 0x0007f100, |
| 137 | 0x0203f017, | 125 | 0x0203f00f, |
| 138 | 0xbd0009d0, | 126 | 0xbd0009d0, |
| 139 | /* 0x0147: mmctx_size */ | 127 | 0x0007f104, |
| 140 | 0xbd00f804, | 128 | 0x0203f006, |
| 141 | /* 0x0149: nv_mmctx_size_loop */ | 129 | 0xbd000ad0, |
| 142 | 0x00e89894, | 130 | /* 0x012d: wait_doneo_e */ |
| 143 | 0xb61a85b6, | 131 | 0x0087f104, |
| 144 | 0x84b60180, | 132 | 0x0183f000, |
| 145 | 0x0098bb02, | 133 | 0xff0088cf, |
| 146 | 0xb804e0b6, | 134 | 0x0bf4888a, |
| 147 | 0x1bf404ef, | 135 | 0xf094bdf3, |
| 148 | 0x029fb9eb, | 136 | 0x07f10099, |
| 149 | /* 0x0166: mmctx_xfer */ | 137 | 0x03f01700, |
| 150 | 0x94bd00f8, | 138 | 0x0009d002, |
| 151 | 0xf10199f0, | 139 | 0x00f804bd, |
| 152 | 0xf00f0007, | 140 | /* 0x0150: mmctx_size */ |
| 153 | 0x09d00203, | 141 | /* 0x0152: nv_mmctx_size_loop */ |
| 154 | 0xf104bd00, | 142 | 0xe89894bd, |
| 155 | 0xb6071087, | 143 | 0x1a85b600, |
| 156 | 0x94bd0684, | 144 | 0xb60180b6, |
| 157 | 0xf405bbfd, | 145 | 0x98bb0284, |
| 158 | 0x8bd0090b, | 146 | 0x04e0b600, |
| 159 | 0x0099f000, | 147 | 0xf404efb8, |
| 160 | /* 0x018c: mmctx_base_disabled */ | 148 | 0x9fb9eb1b, |
| 161 | 0xf405eefd, | 149 | /* 0x016f: mmctx_xfer */ |
| 162 | 0x8ed00c0b, | 150 | 0xbd00f802, |
| 163 | 0xc08fd080, | 151 | 0x0199f094, |
| 164 | /* 0x019b: mmctx_multi_disabled */ | 152 | 0x0f0007f1, |
| 165 | 0xb70199f0, | 153 | 0xd00203f0, |
| 166 | 0xc8010080, | 154 | 0x04bd0009, |
| 155 | 0xbbfd94bd, | ||
| 156 | 0x120bf405, | ||
| 157 | 0xc40007f1, | ||
| 158 | 0xd00103f0, | ||
| 159 | 0x04bd000b, | ||
| 160 | /* 0x0197: mmctx_base_disabled */ | ||
| 161 | 0xfd0099f0, | ||
| 162 | 0x0bf405ee, | ||
| 163 | 0x0007f11e, | ||
| 164 | 0x0103f0c6, | ||
| 165 | 0xbd000ed0, | ||
| 166 | 0x0007f104, | ||
| 167 | 0x0103f0c7, | ||
| 168 | 0xbd000fd0, | ||
| 169 | 0x0199f004, | ||
| 170 | /* 0x01b8: mmctx_multi_disabled */ | ||
| 171 | 0xb600abc8, | ||
| 172 | 0xb9f010b4, | ||
| 173 | 0x01aec80c, | ||
| 174 | 0xfd11e4b6, | ||
| 175 | 0x07f105be, | ||
| 176 | 0x03f0c500, | ||
| 177 | 0x000bd001, | ||
| 178 | /* 0x01d6: mmctx_exec_loop */ | ||
| 179 | /* 0x01d6: mmctx_wait_free */ | ||
| 180 | 0xe7f104bd, | ||
| 181 | 0xe3f0c500, | ||
| 182 | 0x00eecf01, | ||
| 183 | 0xf41fe4f0, | ||
| 184 | 0xce98f30b, | ||
| 185 | 0x05e9fd00, | ||
| 186 | 0xc80007f1, | ||
| 187 | 0xd00103f0, | ||
| 188 | 0x04bd000e, | ||
| 189 | 0xb804c0b6, | ||
| 190 | 0x1bf404cd, | ||
| 191 | 0x02abc8d8, | ||
| 192 | /* 0x0207: mmctx_fini_wait */ | ||
| 193 | 0xf11f1bf4, | ||
| 194 | 0xf0c500b7, | ||
| 195 | 0xbbcf01b3, | ||
| 196 | 0x1fb4f000, | ||
| 197 | 0xf410b4b0, | ||
| 198 | 0xa7f0f01b, | ||
| 199 | 0xd021f402, | ||
| 200 | /* 0x0223: mmctx_stop */ | ||
| 201 | 0xc82b0ef4, | ||
| 167 | 0xb4b600ab, | 202 | 0xb4b600ab, |
| 168 | 0x0cb9f010, | 203 | 0x0cb9f010, |
| 169 | 0xb601aec8, | 204 | 0xf112b9f0, |
| 170 | 0xbefd11e4, | 205 | 0xf0c50007, |
| 171 | 0x008bd005, | 206 | 0x0bd00103, |
| 172 | /* 0x01b4: mmctx_exec_loop */ | 207 | /* 0x023b: mmctx_stop_wait */ |
| 173 | /* 0x01b4: mmctx_wait_free */ | 208 | 0xf104bd00, |
| 174 | 0xf0008ecf, | 209 | 0xf0c500b7, |
| 175 | 0x0bf41fe4, | 210 | 0xbbcf01b3, |
| 176 | 0x00ce98fa, | 211 | 0x12bbc800, |
| 177 | 0xd005e9fd, | 212 | /* 0x024b: mmctx_done */ |
| 178 | 0xc0b6c08e, | 213 | 0xbdf31bf4, |
| 179 | 0x04cdb804, | 214 | 0x0199f094, |
| 180 | 0xc8e81bf4, | 215 | 0x170007f1, |
| 181 | 0x1bf402ab, | 216 | 0xd00203f0, |
| 182 | /* 0x01d5: mmctx_fini_wait */ | 217 | 0x04bd0009, |
| 183 | 0x008bcf18, | 218 | /* 0x025e: strand_wait */ |
| 184 | 0xb01fb4f0, | 219 | 0xa0f900f8, |
| 185 | 0x1bf410b4, | 220 | 0xf402a7f0, |
| 186 | 0x02a7f0f7, | 221 | 0xa0fcd021, |
| 187 | 0xf4c921f4, | 222 | /* 0x026a: strand_pre */ |
| 188 | /* 0x01ea: mmctx_stop */ | 223 | 0x97f000f8, |
| 189 | 0xabc81b0e, | 224 | 0xfc07f10c, |
| 190 | 0x10b4b600, | 225 | 0x0203f04a, |
| 191 | 0xf00cb9f0, | 226 | 0xbd0009d0, |
| 192 | 0x8bd012b9, | 227 | 0x5e21f504, |
| 193 | /* 0x01f9: mmctx_stop_wait */ | 228 | /* 0x027f: strand_post */ |
| 194 | 0x008bcf00, | 229 | 0xf000f802, |
| 195 | 0xf412bbc8, | 230 | 0x07f10d97, |
| 196 | /* 0x0202: mmctx_done */ | 231 | 0x03f04afc, |
| 197 | 0x94bdfa1b, | ||
| 198 | 0xf10199f0, | ||
| 199 | 0xf0170007, | ||
| 200 | 0x09d00203, | ||
| 201 | 0xf804bd00, | ||
| 202 | /* 0x0215: strand_wait */ | ||
| 203 | 0xf0a0f900, | ||
| 204 | 0x21f402a7, | ||
| 205 | 0xf8a0fcc9, | ||
| 206 | /* 0x0221: strand_pre */ | ||
| 207 | 0xfc87f100, | ||
| 208 | 0x0283f04a, | ||
| 209 | 0xd00c97f0, | ||
| 210 | 0x21f50089, | ||
| 211 | 0x00f80215, | ||
| 212 | /* 0x0234: strand_post */ | ||
| 213 | 0x4afc87f1, | ||
| 214 | 0xf00283f0, | ||
| 215 | 0x89d00d97, | ||
| 216 | 0x1521f500, | ||
| 217 | /* 0x0247: strand_set */ | ||
| 218 | 0xf100f802, | ||
| 219 | 0xf04ffca7, | ||
| 220 | 0xaba202a3, | ||
| 221 | 0xc7f00500, | ||
| 222 | 0x00acd00f, | ||
| 223 | 0xd00bc7f0, | ||
| 224 | 0x21f500bc, | ||
| 225 | 0xaed00215, | ||
| 226 | 0x0ac7f000, | ||
| 227 | 0xf500bcd0, | ||
| 228 | 0xf8021521, | ||
| 229 | /* 0x0271: strand_ctx_init */ | ||
| 230 | 0xf094bd00, | ||
| 231 | 0x07f10399, | ||
| 232 | 0x03f00f00, | ||
| 233 | 0x0009d002, | 232 | 0x0009d002, |
| 234 | 0x21f504bd, | 233 | 0x21f504bd, |
| 235 | 0xe7f00221, | 234 | 0x00f8025e, |
| 236 | 0x4721f503, | 235 | /* 0x0294: strand_set */ |
| 237 | 0xfca7f102, | 236 | 0xf10fc7f0, |
| 238 | 0x02a3f046, | 237 | 0xf04ffc07, |
| 239 | 0x0400aba0, | 238 | 0x0cd00203, |
| 240 | 0xf040a0d0, | 239 | 0xf004bd00, |
| 241 | 0xbcd001c7, | 240 | 0x07f10bc7, |
| 242 | 0x1521f500, | 241 | 0x03f04afc, |
| 243 | 0x010c9202, | 242 | 0x000cd002, |
| 244 | 0xf000acd0, | 243 | 0x07f104bd, |
| 245 | 0xbcd002c7, | 244 | 0x03f04ffc, |
| 246 | 0x1521f500, | 245 | 0x000ed002, |
| 247 | 0x3421f502, | 246 | 0xc7f004bd, |
| 248 | 0x8087f102, | 247 | 0xfc07f10a, |
| 249 | 0x0684b608, | 248 | 0x0203f04a, |
| 250 | 0xb70089cf, | 249 | 0xbd000cd0, |
| 251 | 0x95220080, | 250 | 0x5e21f504, |
| 252 | /* 0x02ca: ctx_init_strand_loop */ | 251 | /* 0x02d3: strand_ctx_init */ |
| 252 | 0xbd00f802, | ||
| 253 | 0x0399f094, | ||
| 254 | 0x0f0007f1, | ||
| 255 | 0xd00203f0, | ||
| 256 | 0x04bd0009, | ||
| 257 | 0x026a21f5, | ||
| 258 | 0xf503e7f0, | ||
| 259 | 0xbd029421, | ||
| 260 | 0xfc07f1c4, | ||
| 261 | 0x0203f047, | ||
| 262 | 0xbd000cd0, | ||
| 263 | 0x01c7f004, | ||
| 264 | 0x4afc07f1, | ||
| 265 | 0xd00203f0, | ||
| 266 | 0x04bd000c, | ||
| 267 | 0x025e21f5, | ||
| 268 | 0xf1010c92, | ||
| 269 | 0xf046fc07, | ||
| 270 | 0x0cd00203, | ||
| 271 | 0xf004bd00, | ||
| 272 | 0x07f102c7, | ||
| 273 | 0x03f04afc, | ||
| 274 | 0x000cd002, | ||
| 275 | 0x21f504bd, | ||
| 276 | 0x21f5025e, | ||
| 277 | 0x87f1027f, | ||
| 278 | 0x83f04200, | ||
| 279 | 0x0097f102, | ||
| 280 | 0x0293f020, | ||
| 281 | 0x950099cf, | ||
| 282 | /* 0x034a: ctx_init_strand_loop */ | ||
| 253 | 0x8ed008fe, | 283 | 0x8ed008fe, |
| 254 | 0x408ed000, | 284 | 0x408ed000, |
| 255 | 0xb6808acf, | 285 | 0xb6808acf, |
| @@ -263,198 +293,230 @@ uint32_t nve0_grgpc_code[] = { | |||
| 263 | 0x170007f1, | 293 | 0x170007f1, |
| 264 | 0xd00203f0, | 294 | 0xd00203f0, |
| 265 | 0x04bd0009, | 295 | 0x04bd0009, |
| 266 | /* 0x02fe: error */ | 296 | /* 0x037e: error */ |
| 267 | 0xe0f900f8, | 297 | 0xe0f900f8, |
| 268 | 0x9814e7f1, | 298 | 0xf102ffb9, |
| 269 | 0xf440e3f0, | 299 | 0xf09814e7, |
| 270 | 0xe0b78d21, | 300 | 0x21f440e3, |
| 271 | 0xf7f0041c, | 301 | 0x01f7f09d, |
| 272 | 0x8d21f401, | 302 | 0xf102ffb9, |
| 273 | 0x00f8e0fc, | 303 | 0xf09c1ce7, |
| 274 | /* 0x0318: init */ | 304 | 0x21f440e3, |
| 275 | 0x04fe04bd, | 305 | 0xf8e0fc9d, |
| 276 | 0x0017f100, | 306 | /* 0x03a1: init */ |
| 277 | 0x0227f012, | 307 | 0xfe04bd00, |
| 278 | 0xf10012d0, | 308 | 0x27f00004, |
| 279 | 0xfe047017, | 309 | 0x0007f102, |
| 280 | 0x17f10010, | 310 | 0x0003f012, |
| 281 | 0x10d00400, | 311 | 0xbd0002d0, |
| 282 | 0x0427f0c0, | 312 | 0x1f17f104, |
| 283 | 0xf40012d0, | 313 | 0x0010fe05, |
| 284 | 0x17f11031, | 314 | 0x070007f1, |
| 285 | 0x14b60608, | 315 | 0xd00003f0, |
| 286 | 0x0012cf06, | 316 | 0x04bd0000, |
| 317 | 0xf10427f0, | ||
| 318 | 0xf0040007, | ||
| 319 | 0x02d00003, | ||
| 320 | 0xf404bd00, | ||
| 321 | 0x27f11031, | ||
| 322 | 0x23f08200, | ||
| 323 | 0x0022cf01, | ||
| 287 | 0xf00137f0, | 324 | 0xf00137f0, |
| 288 | 0x32bb1f24, | 325 | 0x32bb1f24, |
| 289 | 0x0132b604, | 326 | 0x0132b604, |
| 290 | 0x80050280, | 327 | 0x80050280, |
| 291 | 0x10b70603, | 328 | 0x27f10603, |
| 292 | 0x12cf0400, | 329 | 0x23f08600, |
| 293 | 0x04028000, | 330 | 0x0022cf01, |
| 294 | 0x0c30e7f1, | 331 | 0xf1040280, |
| 295 | 0xbd50e3f0, | 332 | 0xf00c30e7, |
| 296 | 0xbd34bd24, | 333 | 0x24bd50e3, |
| 297 | /* 0x0371: init_unk_loop */ | 334 | 0x44bd34bd, |
| 298 | 0x6821f444, | 335 | /* 0x0410: init_unk_loop */ |
| 299 | 0xf400f6b0, | 336 | 0xb06821f4, |
| 300 | 0xf7f00f0b, | 337 | 0x0bf400f6, |
| 301 | 0x04f2bb01, | 338 | 0x01f7f00f, |
| 302 | 0xb6054ffd, | 339 | 0xfd04f2bb, |
| 303 | /* 0x0386: init_unk_next */ | 340 | 0x30b6054f, |
| 304 | 0x20b60130, | 341 | /* 0x0425: init_unk_next */ |
| 305 | 0x04e0b601, | 342 | 0x0120b601, |
| 306 | 0xf40126b0, | 343 | 0xb004e0b6, |
| 307 | /* 0x0392: init_unk_done */ | 344 | 0x1bf40126, |
| 308 | 0x0380e21b, | 345 | /* 0x0431: init_unk_done */ |
| 309 | 0x08048007, | 346 | 0x070380e2, |
| 310 | 0x010027f1, | 347 | 0xf1080480, |
| 311 | 0xcf0223f0, | 348 | 0xf0010027, |
| 312 | 0x34bd0022, | 349 | 0x22cf0223, |
| 313 | 0x070047f1, | 350 | 0x9534bd00, |
| 314 | 0x950644b6, | 351 | 0x07f10825, |
| 315 | 0x45d00825, | 352 | 0x03f0c000, |
| 316 | 0x4045d000, | 353 | 0x0005d001, |
| 317 | 0x98000e98, | 354 | 0x07f104bd, |
| 318 | 0x21f5010f, | 355 | 0x03f0c100, |
| 319 | 0x2fbb0147, | 356 | 0x0005d001, |
| 320 | 0x003fbb00, | 357 | 0x0e9804bd, |
| 321 | 0x98010e98, | 358 | 0x010f9800, |
| 322 | 0x21f5020f, | 359 | 0x015021f5, |
| 323 | 0x0e980147, | 360 | 0xbb002fbb, |
| 324 | 0x00effd05, | 361 | 0x0e98003f, |
| 325 | 0xbb002ebb, | 362 | 0x020f9801, |
| 326 | 0x0e98003e, | 363 | 0x015021f5, |
| 327 | 0x030f9802, | 364 | 0xfd050e98, |
| 328 | 0x014721f5, | ||
| 329 | 0xfd070e98, | ||
| 330 | 0x2ebb00ef, | 365 | 0x2ebb00ef, |
| 331 | 0x003ebb00, | 366 | 0x003ebb00, |
| 332 | 0x130040b7, | 367 | 0x98020e98, |
| 333 | 0xd00235b6, | 368 | 0x21f5030f, |
| 334 | 0x25b60043, | 369 | 0x0e980150, |
| 335 | 0x0635b608, | 370 | 0x00effd07, |
| 336 | 0xb60120b6, | 371 | 0xbb002ebb, |
| 337 | 0x24b60130, | 372 | 0x35b6003e, |
| 338 | 0x0834b608, | 373 | 0x0007f102, |
| 339 | 0xf5022fb9, | 374 | 0x0103f0d3, |
| 340 | 0xbb027121, | 375 | 0xbd0003d0, |
| 341 | 0x07f1003f, | 376 | 0x0825b604, |
| 342 | 0x03f00100, | 377 | 0xb60635b6, |
| 343 | 0x0003d002, | 378 | 0x30b60120, |
| 344 | 0x24bd04bd, | 379 | 0x0824b601, |
| 345 | 0xf11f29f0, | 380 | 0xb90834b6, |
| 346 | 0xf0080007, | 381 | 0x21f5022f, |
| 347 | 0x02d00203, | 382 | 0x3fbb02d3, |
| 348 | /* 0x0433: main */ | 383 | 0x0007f100, |
| 384 | 0x0203f001, | ||
| 385 | 0xbd0003d0, | ||
| 386 | 0xf024bd04, | ||
| 387 | 0x07f11f29, | ||
| 388 | 0x03f00800, | ||
| 389 | 0x0002d002, | ||
| 390 | /* 0x04e2: main */ | ||
| 391 | 0x31f404bd, | ||
| 392 | 0x0028f400, | ||
| 393 | 0xf424d7f0, | ||
| 394 | 0x01f43921, | ||
| 395 | 0x04e4b0f4, | ||
| 396 | 0xfe1e18f4, | ||
| 397 | 0x27f00181, | ||
| 398 | 0xfd20bd06, | ||
| 399 | 0xe4b60412, | ||
| 400 | 0x051efd01, | ||
| 401 | 0xf50018fe, | ||
| 402 | 0xf405d721, | ||
| 403 | /* 0x0512: main_not_ctx_xfer */ | ||
| 404 | 0xef94d30e, | ||
| 405 | 0x01f5f010, | ||
| 406 | 0x037e21f5, | ||
| 407 | /* 0x051f: ih */ | ||
| 408 | 0xf9c60ef4, | ||
| 409 | 0x0188fe80, | ||
| 410 | 0x90f980f9, | ||
| 411 | 0xb0f9a0f9, | ||
| 412 | 0xe0f9d0f9, | ||
| 413 | 0x04bdf0f9, | ||
| 414 | 0x0200a7f1, | ||
| 415 | 0xcf00a3f0, | ||
| 416 | 0xabc400aa, | ||
| 417 | 0x2c0bf404, | ||
| 418 | 0xf124d7f0, | ||
| 419 | 0xf01a00e7, | ||
| 420 | 0xeecf00e3, | ||
| 421 | 0x00f7f100, | ||
| 422 | 0x00f3f019, | ||
| 423 | 0xf400ffcf, | ||
| 424 | 0xe7f00421, | ||
| 425 | 0x0007f101, | ||
| 426 | 0x0003f01d, | ||
| 427 | 0xbd000ed0, | ||
| 428 | /* 0x056d: ih_no_fifo */ | ||
| 429 | 0x0007f104, | ||
| 430 | 0x0003f001, | ||
| 431 | 0xbd000ad0, | ||
| 432 | 0xfcf0fc04, | ||
| 433 | 0xfcd0fce0, | ||
| 434 | 0xfca0fcb0, | ||
| 435 | 0xfe80fc90, | ||
| 436 | 0x80fc0088, | ||
| 437 | 0xf80032f4, | ||
| 438 | /* 0x0591: hub_barrier_done */ | ||
| 439 | 0x01f7f001, | ||
| 440 | 0xbb040e98, | ||
| 441 | 0xffb904fe, | ||
| 442 | 0x18e7f102, | ||
| 443 | 0x40e3f094, | ||
| 444 | 0xf89d21f4, | ||
| 445 | /* 0x05a9: ctx_redswitch */ | ||
| 446 | 0x20f7f000, | ||
| 447 | 0x850007f1, | ||
| 448 | 0xd00103f0, | ||
| 449 | 0x04bd000f, | ||
| 450 | /* 0x05bb: ctx_redswitch_delay */ | ||
| 451 | 0xb608e7f0, | ||
| 452 | 0x1bf401e2, | ||
| 453 | 0x00f5f1fd, | ||
| 454 | 0x00f5f108, | ||
| 455 | 0x0007f102, | ||
| 456 | 0x0103f085, | ||
| 457 | 0xbd000fd0, | ||
| 458 | /* 0x05d7: ctx_xfer */ | ||
| 459 | 0xf100f804, | ||
| 460 | 0xf0810007, | ||
| 461 | 0x0fd00203, | ||
| 349 | 0xf404bd00, | 462 | 0xf404bd00, |
| 350 | 0x28f40031, | 463 | 0x21f50711, |
| 351 | 0x24d7f000, | 464 | /* 0x05ea: ctx_xfer_not_load */ |
| 352 | 0xf43921f4, | 465 | 0x21f505a9, |
| 353 | 0xe4b0f401, | 466 | 0x24bd026a, |
| 354 | 0x1e18f404, | 467 | 0x47fc07f1, |
| 355 | 0xf00181fe, | 468 | 0xd00203f0, |
| 356 | 0x20bd0627, | 469 | 0x04bd0002, |
| 357 | 0xb60412fd, | 470 | 0xb6012cf0, |
| 358 | 0x1efd01e4, | 471 | 0x07f10320, |
| 359 | 0x0018fe05, | 472 | 0x03f04afc, |
| 360 | 0x04f721f5, | 473 | 0x0002d002, |
| 361 | /* 0x0463: main_not_ctx_xfer */ | 474 | 0xacf004bd, |
| 362 | 0x94d30ef4, | 475 | 0x02a5f001, |
| 363 | 0xf5f010ef, | 476 | 0x0000b7f1, |
| 364 | 0xfe21f501, | ||
| 365 | 0xc60ef402, | ||
| 366 | /* 0x0470: ih */ | ||
| 367 | 0x88fe80f9, | ||
| 368 | 0xf980f901, | ||
| 369 | 0xf9a0f990, | ||
| 370 | 0xf9d0f9b0, | ||
| 371 | 0xbdf0f9e0, | ||
| 372 | 0x800acf04, | ||
| 373 | 0xf404abc4, | ||
| 374 | 0xb7f11d0b, | ||
| 375 | 0xd7f01900, | ||
| 376 | 0x40becf24, | ||
| 377 | 0xf400bfcf, | ||
| 378 | 0xb0b70421, | ||
| 379 | 0xe7f00400, | ||
| 380 | 0x00bed001, | ||
| 381 | /* 0x04a8: ih_no_fifo */ | ||
| 382 | 0xfc400ad0, | ||
| 383 | 0xfce0fcf0, | ||
| 384 | 0xfcb0fcd0, | ||
| 385 | 0xfc90fca0, | ||
| 386 | 0x0088fe80, | ||
| 387 | 0x32f480fc, | ||
| 388 | /* 0x04c3: hub_barrier_done */ | ||
| 389 | 0xf001f800, | ||
| 390 | 0x0e9801f7, | ||
| 391 | 0x04febb04, | ||
| 392 | 0x9418e7f1, | ||
| 393 | 0xf440e3f0, | ||
| 394 | 0x00f88d21, | ||
| 395 | /* 0x04d8: ctx_redswitch */ | ||
| 396 | 0x0614e7f1, | ||
| 397 | 0xf006e4b6, | ||
| 398 | 0xefd020f7, | ||
| 399 | 0x08f7f000, | ||
| 400 | /* 0x04e8: ctx_redswitch_delay */ | ||
| 401 | 0xf401f2b6, | ||
| 402 | 0xf7f1fd1b, | ||
| 403 | 0xefd00a20, | ||
| 404 | /* 0x04f7: ctx_xfer */ | ||
| 405 | 0xf100f800, | ||
| 406 | 0xb60a0417, | ||
| 407 | 0x1fd00614, | ||
| 408 | 0x0711f400, | ||
| 409 | 0x04d821f5, | ||
| 410 | /* 0x0508: ctx_xfer_not_load */ | ||
| 411 | 0x4afc17f1, | ||
| 412 | 0xf00213f0, | ||
| 413 | 0x12d00c27, | ||
| 414 | 0x1521f500, | ||
| 415 | 0xfc27f102, | ||
| 416 | 0x0223f047, | ||
| 417 | 0xf00020d0, | ||
| 418 | 0x20b6012c, | ||
| 419 | 0x0012d003, | ||
| 420 | 0xf001acf0, | ||
| 421 | 0xb7f002a5, | ||
| 422 | 0x50b3f000, | ||
| 423 | 0xb6040c98, | ||
| 424 | 0xbcbb0fc4, | ||
| 425 | 0x000c9800, | ||
| 426 | 0xf0010d98, | ||
| 427 | 0x21f500e7, | ||
| 428 | 0xacf00166, | ||
| 429 | 0x00b7f101, | ||
| 430 | 0x50b3f040, | ||
| 431 | 0xb6040c98, | ||
| 432 | 0xbcbb0fc4, | ||
| 433 | 0x010c9800, | ||
| 434 | 0x98020d98, | ||
| 435 | 0xe7f1060f, | ||
| 436 | 0x21f50800, | ||
| 437 | 0xacf00166, | ||
| 438 | 0x04a5f001, | ||
| 439 | 0x3000b7f1, | ||
| 440 | 0x9850b3f0, | 477 | 0x9850b3f0, |
| 441 | 0xc4b6040c, | 478 | 0xc4b6040c, |
| 442 | 0x00bcbb0f, | 479 | 0x00bcbb0f, |
| 443 | 0x98020c98, | 480 | 0x98000c98, |
| 444 | 0x0f98030d, | 481 | 0xe7f0010d, |
| 445 | 0x00e7f108, | 482 | 0x6f21f500, |
| 446 | 0x6621f502, | 483 | 0x01acf001, |
| 447 | 0x1521f501, | 484 | 0x4000b7f1, |
| 448 | 0x0601f402, | 485 | 0x9850b3f0, |
| 449 | /* 0x05a3: ctx_xfer_post */ | 486 | 0xc4b6040c, |
| 450 | 0xf11412f4, | 487 | 0x00bcbb0f, |
| 451 | 0xf04afc17, | 488 | 0x98010c98, |
| 452 | 0x27f00213, | 489 | 0x0f98020d, |
| 453 | 0x0012d00d, | 490 | 0x00e7f106, |
| 454 | 0x021521f5, | 491 | 0x6f21f508, |
| 455 | /* 0x05b4: ctx_xfer_done */ | 492 | 0x01acf001, |
| 456 | 0x04c321f5, | 493 | 0xf104a5f0, |
| 457 | 0x000000f8, | 494 | 0xf03000b7, |
| 495 | 0x0c9850b3, | ||
| 496 | 0x0fc4b604, | ||
| 497 | 0x9800bcbb, | ||
| 498 | 0x0d98020c, | ||
| 499 | 0x080f9803, | ||
| 500 | 0x0200e7f1, | ||
| 501 | 0x016f21f5, | ||
| 502 | 0x025e21f5, | ||
| 503 | 0xf40601f4, | ||
| 504 | /* 0x0686: ctx_xfer_post */ | ||
| 505 | 0x21f50712, | ||
| 506 | /* 0x068a: ctx_xfer_done */ | ||
| 507 | 0x21f5027f, | ||
| 508 | 0x00f80591, | ||
| 509 | 0x00000000, | ||
| 510 | 0x00000000, | ||
| 511 | 0x00000000, | ||
| 512 | 0x00000000, | ||
| 513 | 0x00000000, | ||
| 514 | 0x00000000, | ||
| 515 | 0x00000000, | ||
| 516 | 0x00000000, | ||
| 517 | 0x00000000, | ||
| 518 | 0x00000000, | ||
| 519 | 0x00000000, | ||
| 458 | 0x00000000, | 520 | 0x00000000, |
| 459 | 0x00000000, | 521 | 0x00000000, |
| 460 | 0x00000000, | 522 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h index f870507be880..6316ebaf5d9a 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h | |||
| @@ -41,14 +41,14 @@ uint32_t nvf0_grgpc_data[] = { | |||
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | uint32_t nvf0_grgpc_code[] = { | 43 | uint32_t nvf0_grgpc_code[] = { |
| 44 | 0x03180ef5, | 44 | 0x03a10ef5, |
| 45 | /* 0x0004: queue_put */ | 45 | /* 0x0004: queue_put */ |
| 46 | 0x9800d898, | 46 | 0x9800d898, |
| 47 | 0x86f001d9, | 47 | 0x86f001d9, |
| 48 | 0x0489b808, | 48 | 0x0489b808, |
| 49 | 0xf00c1bf4, | 49 | 0xf00c1bf4, |
| 50 | 0x21f502f7, | 50 | 0x21f502f7, |
| 51 | 0x00f802fe, | 51 | 0x00f8037e, |
| 52 | /* 0x001c: queue_put_next */ | 52 | /* 0x001c: queue_put_next */ |
| 53 | 0xb60798c4, | 53 | 0xb60798c4, |
| 54 | 0x8dbb0384, | 54 | 0x8dbb0384, |
| @@ -72,184 +72,214 @@ uint32_t nvf0_grgpc_code[] = { | |||
| 72 | /* 0x0066: queue_get_done */ | 72 | /* 0x0066: queue_get_done */ |
| 73 | 0x00f80132, | 73 | 0x00f80132, |
| 74 | /* 0x0068: nv_rd32 */ | 74 | /* 0x0068: nv_rd32 */ |
| 75 | 0x0728b7f1, | 75 | 0xf002ecb9, |
| 76 | 0xb906b4b6, | 76 | 0x07f11fc9, |
| 77 | 0xc9f002ec, | 77 | 0x03f0ca00, |
| 78 | 0x00bcd01f, | 78 | 0x000cd001, |
| 79 | /* 0x0078: nv_rd32_wait */ | 79 | /* 0x007a: nv_rd32_wait */ |
| 80 | 0xc800bccf, | 80 | 0xc7f104bd, |
| 81 | 0x1bf41fcc, | 81 | 0xc3f0ca00, |
| 82 | 0x06a7f0fa, | 82 | 0x00cccf01, |
| 83 | 0x010921f5, | 83 | 0xf41fccc8, |
| 84 | 0xf840bfcf, | 84 | 0xa7f0f31b, |
| 85 | /* 0x008d: nv_wr32 */ | 85 | 0x1021f506, |
| 86 | 0x28b7f100, | 86 | 0x00f7f101, |
| 87 | 0x06b4b607, | 87 | 0x01f3f0cb, |
| 88 | 0xb980bfd0, | 88 | 0xf800ffcf, |
| 89 | 0xc9f002ec, | 89 | /* 0x009d: nv_wr32 */ |
| 90 | 0x1ec9f01f, | 90 | 0x0007f100, |
| 91 | /* 0x00a3: nv_wr32_wait */ | 91 | 0x0103f0cc, |
| 92 | 0xcf00bcd0, | 92 | 0xbd000fd0, |
| 93 | 0xccc800bc, | 93 | 0x02ecb904, |
| 94 | 0xfa1bf41f, | 94 | 0xf01fc9f0, |
| 95 | /* 0x00ae: watchdog_reset */ | 95 | 0x07f11ec9, |
| 96 | 0x87f100f8, | 96 | 0x03f0ca00, |
| 97 | 0x84b60430, | 97 | 0x000cd001, |
| 98 | 0x1ff9f006, | 98 | /* 0x00be: nv_wr32_wait */ |
| 99 | 0xf8008fd0, | 99 | 0xc7f104bd, |
| 100 | /* 0x00bd: watchdog_clear */ | 100 | 0xc3f0ca00, |
| 101 | 0x3087f100, | 101 | 0x00cccf01, |
| 102 | 0x0684b604, | 102 | 0xf41fccc8, |
| 103 | 0xf80080d0, | 103 | 0x00f8f31b, |
| 104 | /* 0x00c9: wait_donez */ | 104 | /* 0x00d0: wait_donez */ |
| 105 | 0xf094bd00, | 105 | 0x99f094bd, |
| 106 | 0x07f10099, | 106 | 0x0007f100, |
| 107 | 0x03f03700, | 107 | 0x0203f037, |
| 108 | 0x0009d002, | 108 | 0xbd0009d0, |
| 109 | 0x07f104bd, | 109 | 0x0007f104, |
| 110 | 0x03f00600, | 110 | 0x0203f006, |
| 111 | 0x000ad002, | 111 | 0xbd000ad0, |
| 112 | /* 0x00e6: wait_donez_ne */ | 112 | /* 0x00ed: wait_donez_ne */ |
| 113 | 0x87f104bd, | 113 | 0x0087f104, |
| 114 | 0x83f00000, | 114 | 0x0183f000, |
| 115 | 0x0088cf01, | 115 | 0xff0088cf, |
| 116 | 0xf4888aff, | 116 | 0x1bf4888a, |
| 117 | 0x94bdf31b, | 117 | 0xf094bdf3, |
| 118 | 0xf10099f0, | ||
| 119 | 0xf0170007, | ||
| 120 | 0x09d00203, | ||
| 121 | 0xf804bd00, | ||
| 122 | /* 0x0109: wait_doneo */ | ||
| 123 | 0xf094bd00, | ||
| 124 | 0x07f10099, | 118 | 0x07f10099, |
| 125 | 0x03f03700, | 119 | 0x03f01700, |
| 126 | 0x0009d002, | 120 | 0x0009d002, |
| 127 | 0x87f104bd, | 121 | 0x00f804bd, |
| 128 | 0x84b60818, | 122 | /* 0x0110: wait_doneo */ |
| 129 | 0x008ad006, | ||
| 130 | /* 0x0124: wait_doneo_e */ | ||
| 131 | 0x040087f1, | ||
| 132 | 0xcf0684b6, | ||
| 133 | 0x8aff0088, | ||
| 134 | 0xf30bf488, | ||
| 135 | 0x99f094bd, | 123 | 0x99f094bd, |
| 136 | 0x0007f100, | 124 | 0x0007f100, |
| 137 | 0x0203f017, | 125 | 0x0203f037, |
| 138 | 0xbd0009d0, | 126 | 0xbd0009d0, |
| 139 | /* 0x0147: mmctx_size */ | 127 | 0x0007f104, |
| 140 | 0xbd00f804, | 128 | 0x0203f006, |
| 141 | /* 0x0149: nv_mmctx_size_loop */ | 129 | 0xbd000ad0, |
| 142 | 0x00e89894, | 130 | /* 0x012d: wait_doneo_e */ |
| 143 | 0xb61a85b6, | 131 | 0x0087f104, |
| 144 | 0x84b60180, | 132 | 0x0183f000, |
| 145 | 0x0098bb02, | 133 | 0xff0088cf, |
| 146 | 0xb804e0b6, | 134 | 0x0bf4888a, |
| 147 | 0x1bf404ef, | 135 | 0xf094bdf3, |
| 148 | 0x029fb9eb, | 136 | 0x07f10099, |
| 149 | /* 0x0166: mmctx_xfer */ | 137 | 0x03f01700, |
| 150 | 0x94bd00f8, | 138 | 0x0009d002, |
| 151 | 0xf10199f0, | 139 | 0x00f804bd, |
| 152 | 0xf0370007, | 140 | /* 0x0150: mmctx_size */ |
| 153 | 0x09d00203, | 141 | /* 0x0152: nv_mmctx_size_loop */ |
| 154 | 0xf104bd00, | 142 | 0xe89894bd, |
| 155 | 0xb6071087, | 143 | 0x1a85b600, |
| 156 | 0x94bd0684, | 144 | 0xb60180b6, |
| 157 | 0xf405bbfd, | 145 | 0x98bb0284, |
| 158 | 0x8bd0090b, | 146 | 0x04e0b600, |
| 159 | 0x0099f000, | 147 | 0xf404efb8, |
| 160 | /* 0x018c: mmctx_base_disabled */ | 148 | 0x9fb9eb1b, |
| 161 | 0xf405eefd, | 149 | /* 0x016f: mmctx_xfer */ |
| 162 | 0x8ed00c0b, | 150 | 0xbd00f802, |
| 163 | 0xc08fd080, | 151 | 0x0199f094, |
| 164 | /* 0x019b: mmctx_multi_disabled */ | 152 | 0x370007f1, |
| 165 | 0xb70199f0, | 153 | 0xd00203f0, |
| 166 | 0xc8010080, | 154 | 0x04bd0009, |
| 155 | 0xbbfd94bd, | ||
| 156 | 0x120bf405, | ||
| 157 | 0xc40007f1, | ||
| 158 | 0xd00103f0, | ||
| 159 | 0x04bd000b, | ||
| 160 | /* 0x0197: mmctx_base_disabled */ | ||
| 161 | 0xfd0099f0, | ||
| 162 | 0x0bf405ee, | ||
| 163 | 0x0007f11e, | ||
| 164 | 0x0103f0c6, | ||
| 165 | 0xbd000ed0, | ||
| 166 | 0x0007f104, | ||
| 167 | 0x0103f0c7, | ||
| 168 | 0xbd000fd0, | ||
| 169 | 0x0199f004, | ||
| 170 | /* 0x01b8: mmctx_multi_disabled */ | ||
| 171 | 0xb600abc8, | ||
| 172 | 0xb9f010b4, | ||
| 173 | 0x01aec80c, | ||
| 174 | 0xfd11e4b6, | ||
| 175 | 0x07f105be, | ||
| 176 | 0x03f0c500, | ||
| 177 | 0x000bd001, | ||
| 178 | /* 0x01d6: mmctx_exec_loop */ | ||
| 179 | /* 0x01d6: mmctx_wait_free */ | ||
| 180 | 0xe7f104bd, | ||
| 181 | 0xe3f0c500, | ||
| 182 | 0x00eecf01, | ||
| 183 | 0xf41fe4f0, | ||
| 184 | 0xce98f30b, | ||
| 185 | 0x05e9fd00, | ||
| 186 | 0xc80007f1, | ||
| 187 | 0xd00103f0, | ||
| 188 | 0x04bd000e, | ||
| 189 | 0xb804c0b6, | ||
| 190 | 0x1bf404cd, | ||
| 191 | 0x02abc8d8, | ||
| 192 | /* 0x0207: mmctx_fini_wait */ | ||
| 193 | 0xf11f1bf4, | ||
| 194 | 0xf0c500b7, | ||
| 195 | 0xbbcf01b3, | ||
| 196 | 0x1fb4f000, | ||
| 197 | 0xf410b4b0, | ||
| 198 | 0xa7f0f01b, | ||
| 199 | 0xd021f402, | ||
| 200 | /* 0x0223: mmctx_stop */ | ||
| 201 | 0xc82b0ef4, | ||
| 167 | 0xb4b600ab, | 202 | 0xb4b600ab, |
| 168 | 0x0cb9f010, | 203 | 0x0cb9f010, |
| 169 | 0xb601aec8, | 204 | 0xf112b9f0, |
| 170 | 0xbefd11e4, | 205 | 0xf0c50007, |
| 171 | 0x008bd005, | 206 | 0x0bd00103, |
| 172 | /* 0x01b4: mmctx_exec_loop */ | 207 | /* 0x023b: mmctx_stop_wait */ |
| 173 | /* 0x01b4: mmctx_wait_free */ | 208 | 0xf104bd00, |
| 174 | 0xf0008ecf, | 209 | 0xf0c500b7, |
| 175 | 0x0bf41fe4, | 210 | 0xbbcf01b3, |
| 176 | 0x00ce98fa, | 211 | 0x12bbc800, |
| 177 | 0xd005e9fd, | 212 | /* 0x024b: mmctx_done */ |
| 178 | 0xc0b6c08e, | 213 | 0xbdf31bf4, |
| 179 | 0x04cdb804, | 214 | 0x0199f094, |
| 180 | 0xc8e81bf4, | 215 | 0x170007f1, |
| 181 | 0x1bf402ab, | 216 | 0xd00203f0, |
| 182 | /* 0x01d5: mmctx_fini_wait */ | 217 | 0x04bd0009, |
| 183 | 0x008bcf18, | 218 | /* 0x025e: strand_wait */ |
| 184 | 0xb01fb4f0, | 219 | 0xa0f900f8, |
| 185 | 0x1bf410b4, | 220 | 0xf402a7f0, |
| 186 | 0x02a7f0f7, | 221 | 0xa0fcd021, |
| 187 | 0xf4c921f4, | 222 | /* 0x026a: strand_pre */ |
| 188 | /* 0x01ea: mmctx_stop */ | 223 | 0x97f000f8, |
| 189 | 0xabc81b0e, | 224 | 0xfc07f10c, |
| 190 | 0x10b4b600, | 225 | 0x0203f04a, |
| 191 | 0xf00cb9f0, | 226 | 0xbd0009d0, |
| 192 | 0x8bd012b9, | 227 | 0x5e21f504, |
| 193 | /* 0x01f9: mmctx_stop_wait */ | 228 | /* 0x027f: strand_post */ |
| 194 | 0x008bcf00, | 229 | 0xf000f802, |
| 195 | 0xf412bbc8, | 230 | 0x07f10d97, |
| 196 | /* 0x0202: mmctx_done */ | 231 | 0x03f04afc, |
| 197 | 0x94bdfa1b, | ||
| 198 | 0xf10199f0, | ||
| 199 | 0xf0170007, | ||
| 200 | 0x09d00203, | ||
| 201 | 0xf804bd00, | ||
| 202 | /* 0x0215: strand_wait */ | ||
| 203 | 0xf0a0f900, | ||
| 204 | 0x21f402a7, | ||
| 205 | 0xf8a0fcc9, | ||
| 206 | /* 0x0221: strand_pre */ | ||
| 207 | 0xfc87f100, | ||
| 208 | 0x0283f04a, | ||
| 209 | 0xd00c97f0, | ||
| 210 | 0x21f50089, | ||
| 211 | 0x00f80215, | ||
| 212 | /* 0x0234: strand_post */ | ||
| 213 | 0x4afc87f1, | ||
| 214 | 0xf00283f0, | ||
| 215 | 0x89d00d97, | ||
| 216 | 0x1521f500, | ||
| 217 | /* 0x0247: strand_set */ | ||
| 218 | 0xf100f802, | ||
| 219 | 0xf04ffca7, | ||
| 220 | 0xaba202a3, | ||
| 221 | 0xc7f00500, | ||
| 222 | 0x00acd00f, | ||
| 223 | 0xd00bc7f0, | ||
| 224 | 0x21f500bc, | ||
| 225 | 0xaed00215, | ||
| 226 | 0x0ac7f000, | ||
| 227 | 0xf500bcd0, | ||
| 228 | 0xf8021521, | ||
| 229 | /* 0x0271: strand_ctx_init */ | ||
| 230 | 0xf094bd00, | ||
| 231 | 0x07f10399, | ||
| 232 | 0x03f03700, | ||
| 233 | 0x0009d002, | 232 | 0x0009d002, |
| 234 | 0x21f504bd, | 233 | 0x21f504bd, |
| 235 | 0xe7f00221, | 234 | 0x00f8025e, |
| 236 | 0x4721f503, | 235 | /* 0x0294: strand_set */ |
| 237 | 0xfca7f102, | 236 | 0xf10fc7f0, |
| 238 | 0x02a3f046, | 237 | 0xf04ffc07, |
| 239 | 0x0400aba0, | 238 | 0x0cd00203, |
| 240 | 0xf040a0d0, | 239 | 0xf004bd00, |
| 241 | 0xbcd001c7, | 240 | 0x07f10bc7, |
| 242 | 0x1521f500, | 241 | 0x03f04afc, |
| 243 | 0x010c9202, | 242 | 0x000cd002, |
| 244 | 0xf000acd0, | 243 | 0x07f104bd, |
| 245 | 0xbcd002c7, | 244 | 0x03f04ffc, |
| 246 | 0x1521f500, | 245 | 0x000ed002, |
| 247 | 0x3421f502, | 246 | 0xc7f004bd, |
| 248 | 0x8087f102, | 247 | 0xfc07f10a, |
| 249 | 0x0684b608, | 248 | 0x0203f04a, |
| 250 | 0xb70089cf, | 249 | 0xbd000cd0, |
| 251 | 0x95220080, | 250 | 0x5e21f504, |
| 252 | /* 0x02ca: ctx_init_strand_loop */ | 251 | /* 0x02d3: strand_ctx_init */ |
| 252 | 0xbd00f802, | ||
| 253 | 0x0399f094, | ||
| 254 | 0x370007f1, | ||
| 255 | 0xd00203f0, | ||
| 256 | 0x04bd0009, | ||
| 257 | 0x026a21f5, | ||
| 258 | 0xf503e7f0, | ||
| 259 | 0xbd029421, | ||
| 260 | 0xfc07f1c4, | ||
| 261 | 0x0203f047, | ||
| 262 | 0xbd000cd0, | ||
| 263 | 0x01c7f004, | ||
| 264 | 0x4afc07f1, | ||
| 265 | 0xd00203f0, | ||
| 266 | 0x04bd000c, | ||
| 267 | 0x025e21f5, | ||
| 268 | 0xf1010c92, | ||
| 269 | 0xf046fc07, | ||
| 270 | 0x0cd00203, | ||
| 271 | 0xf004bd00, | ||
| 272 | 0x07f102c7, | ||
| 273 | 0x03f04afc, | ||
| 274 | 0x000cd002, | ||
| 275 | 0x21f504bd, | ||
| 276 | 0x21f5025e, | ||
| 277 | 0x87f1027f, | ||
| 278 | 0x83f04200, | ||
| 279 | 0x0097f102, | ||
| 280 | 0x0293f020, | ||
| 281 | 0x950099cf, | ||
| 282 | /* 0x034a: ctx_init_strand_loop */ | ||
| 253 | 0x8ed008fe, | 283 | 0x8ed008fe, |
| 254 | 0x408ed000, | 284 | 0x408ed000, |
| 255 | 0xb6808acf, | 285 | 0xb6808acf, |
| @@ -263,198 +293,230 @@ uint32_t nvf0_grgpc_code[] = { | |||
| 263 | 0x170007f1, | 293 | 0x170007f1, |
| 264 | 0xd00203f0, | 294 | 0xd00203f0, |
| 265 | 0x04bd0009, | 295 | 0x04bd0009, |
| 266 | /* 0x02fe: error */ | 296 | /* 0x037e: error */ |
| 267 | 0xe0f900f8, | 297 | 0xe0f900f8, |
| 268 | 0x9814e7f1, | 298 | 0xf102ffb9, |
| 269 | 0xf440e3f0, | 299 | 0xf09814e7, |
| 270 | 0xe0b78d21, | 300 | 0x21f440e3, |
| 271 | 0xf7f0041c, | 301 | 0x01f7f09d, |
| 272 | 0x8d21f401, | 302 | 0xf102ffb9, |
| 273 | 0x00f8e0fc, | 303 | 0xf09c1ce7, |
| 274 | /* 0x0318: init */ | 304 | 0x21f440e3, |
| 275 | 0x04fe04bd, | 305 | 0xf8e0fc9d, |
| 276 | 0x0017f100, | 306 | /* 0x03a1: init */ |
| 277 | 0x0227f012, | 307 | 0xfe04bd00, |
| 278 | 0xf10012d0, | 308 | 0x27f00004, |
| 279 | 0xfe047017, | 309 | 0x0007f102, |
| 280 | 0x17f10010, | 310 | 0x0003f012, |
| 281 | 0x10d00400, | 311 | 0xbd0002d0, |
| 282 | 0x0427f0c0, | 312 | 0x1f17f104, |
| 283 | 0xf40012d0, | 313 | 0x0010fe05, |
| 284 | 0x17f11031, | 314 | 0x070007f1, |
| 285 | 0x14b60608, | 315 | 0xd00003f0, |
| 286 | 0x0012cf06, | 316 | 0x04bd0000, |
| 317 | 0xf10427f0, | ||
| 318 | 0xf0040007, | ||
| 319 | 0x02d00003, | ||
| 320 | 0xf404bd00, | ||
| 321 | 0x27f11031, | ||
| 322 | 0x23f08200, | ||
| 323 | 0x0022cf01, | ||
| 287 | 0xf00137f0, | 324 | 0xf00137f0, |
| 288 | 0x32bb1f24, | 325 | 0x32bb1f24, |
| 289 | 0x0132b604, | 326 | 0x0132b604, |
| 290 | 0x80050280, | 327 | 0x80050280, |
| 291 | 0x10b70603, | 328 | 0x27f10603, |
| 292 | 0x12cf0400, | 329 | 0x23f08600, |
| 293 | 0x04028000, | 330 | 0x0022cf01, |
| 294 | 0x0c30e7f1, | 331 | 0xf1040280, |
| 295 | 0xbd50e3f0, | 332 | 0xf00c30e7, |
| 296 | 0xbd34bd24, | 333 | 0x24bd50e3, |
| 297 | /* 0x0371: init_unk_loop */ | 334 | 0x44bd34bd, |
| 298 | 0x6821f444, | 335 | /* 0x0410: init_unk_loop */ |
| 299 | 0xf400f6b0, | 336 | 0xb06821f4, |
| 300 | 0xf7f00f0b, | 337 | 0x0bf400f6, |
| 301 | 0x04f2bb01, | 338 | 0x01f7f00f, |
| 302 | 0xb6054ffd, | 339 | 0xfd04f2bb, |
| 303 | /* 0x0386: init_unk_next */ | 340 | 0x30b6054f, |
| 304 | 0x20b60130, | 341 | /* 0x0425: init_unk_next */ |
| 305 | 0x04e0b601, | 342 | 0x0120b601, |
| 306 | 0xf40226b0, | 343 | 0xb004e0b6, |
| 307 | /* 0x0392: init_unk_done */ | 344 | 0x1bf40226, |
| 308 | 0x0380e21b, | 345 | /* 0x0431: init_unk_done */ |
| 309 | 0x08048007, | 346 | 0x070380e2, |
| 310 | 0x010027f1, | 347 | 0xf1080480, |
| 311 | 0xcf0223f0, | 348 | 0xf0010027, |
| 312 | 0x34bd0022, | 349 | 0x22cf0223, |
| 313 | 0x070047f1, | 350 | 0x9534bd00, |
| 314 | 0x950644b6, | 351 | 0x07f10825, |
| 315 | 0x45d00825, | 352 | 0x03f0c000, |
| 316 | 0x4045d000, | 353 | 0x0005d001, |
| 317 | 0x98000e98, | 354 | 0x07f104bd, |
| 318 | 0x21f5010f, | 355 | 0x03f0c100, |
| 319 | 0x2fbb0147, | 356 | 0x0005d001, |
| 320 | 0x003fbb00, | 357 | 0x0e9804bd, |
| 321 | 0x98010e98, | 358 | 0x010f9800, |
| 322 | 0x21f5020f, | 359 | 0x015021f5, |
| 323 | 0x0e980147, | 360 | 0xbb002fbb, |
| 324 | 0x00effd05, | 361 | 0x0e98003f, |
| 325 | 0xbb002ebb, | 362 | 0x020f9801, |
| 326 | 0x0e98003e, | 363 | 0x015021f5, |
| 327 | 0x030f9802, | 364 | 0xfd050e98, |
| 328 | 0x014721f5, | ||
| 329 | 0xfd070e98, | ||
| 330 | 0x2ebb00ef, | 365 | 0x2ebb00ef, |
| 331 | 0x003ebb00, | 366 | 0x003ebb00, |
| 332 | 0x130040b7, | 367 | 0x98020e98, |
| 333 | 0xd00235b6, | 368 | 0x21f5030f, |
| 334 | 0x25b60043, | 369 | 0x0e980150, |
| 335 | 0x0635b608, | 370 | 0x00effd07, |
| 336 | 0xb60120b6, | 371 | 0xbb002ebb, |
| 337 | 0x24b60130, | 372 | 0x35b6003e, |
| 338 | 0x0834b608, | 373 | 0x0007f102, |
| 339 | 0xf5022fb9, | 374 | 0x0103f0d3, |
| 340 | 0xbb027121, | 375 | 0xbd0003d0, |
| 341 | 0x07f1003f, | 376 | 0x0825b604, |
| 342 | 0x03f00100, | 377 | 0xb60635b6, |
| 343 | 0x0003d002, | 378 | 0x30b60120, |
| 344 | 0x24bd04bd, | 379 | 0x0824b601, |
| 345 | 0xf11f29f0, | 380 | 0xb90834b6, |
| 346 | 0xf0300007, | 381 | 0x21f5022f, |
| 347 | 0x02d00203, | 382 | 0x3fbb02d3, |
| 348 | /* 0x0433: main */ | 383 | 0x0007f100, |
| 384 | 0x0203f001, | ||
| 385 | 0xbd0003d0, | ||
| 386 | 0xf024bd04, | ||
| 387 | 0x07f11f29, | ||
| 388 | 0x03f03000, | ||
| 389 | 0x0002d002, | ||
| 390 | /* 0x04e2: main */ | ||
| 391 | 0x31f404bd, | ||
| 392 | 0x0028f400, | ||
| 393 | 0xf424d7f0, | ||
| 394 | 0x01f43921, | ||
| 395 | 0x04e4b0f4, | ||
| 396 | 0xfe1e18f4, | ||
| 397 | 0x27f00181, | ||
| 398 | 0xfd20bd06, | ||
| 399 | 0xe4b60412, | ||
| 400 | 0x051efd01, | ||
| 401 | 0xf50018fe, | ||
| 402 | 0xf405d721, | ||
| 403 | /* 0x0512: main_not_ctx_xfer */ | ||
| 404 | 0xef94d30e, | ||
| 405 | 0x01f5f010, | ||
| 406 | 0x037e21f5, | ||
| 407 | /* 0x051f: ih */ | ||
| 408 | 0xf9c60ef4, | ||
| 409 | 0x0188fe80, | ||
| 410 | 0x90f980f9, | ||
| 411 | 0xb0f9a0f9, | ||
| 412 | 0xe0f9d0f9, | ||
| 413 | 0x04bdf0f9, | ||
| 414 | 0x0200a7f1, | ||
| 415 | 0xcf00a3f0, | ||
| 416 | 0xabc400aa, | ||
| 417 | 0x2c0bf404, | ||
| 418 | 0xf124d7f0, | ||
| 419 | 0xf01a00e7, | ||
| 420 | 0xeecf00e3, | ||
| 421 | 0x00f7f100, | ||
| 422 | 0x00f3f019, | ||
| 423 | 0xf400ffcf, | ||
| 424 | 0xe7f00421, | ||
| 425 | 0x0007f101, | ||
| 426 | 0x0003f01d, | ||
| 427 | 0xbd000ed0, | ||
| 428 | /* 0x056d: ih_no_fifo */ | ||
| 429 | 0x0007f104, | ||
| 430 | 0x0003f001, | ||
| 431 | 0xbd000ad0, | ||
| 432 | 0xfcf0fc04, | ||
| 433 | 0xfcd0fce0, | ||
| 434 | 0xfca0fcb0, | ||
| 435 | 0xfe80fc90, | ||
| 436 | 0x80fc0088, | ||
| 437 | 0xf80032f4, | ||
| 438 | /* 0x0591: hub_barrier_done */ | ||
| 439 | 0x01f7f001, | ||
| 440 | 0xbb040e98, | ||
| 441 | 0xffb904fe, | ||
| 442 | 0x18e7f102, | ||
| 443 | 0x40e3f094, | ||
| 444 | 0xf89d21f4, | ||
| 445 | /* 0x05a9: ctx_redswitch */ | ||
| 446 | 0x20f7f000, | ||
| 447 | 0x850007f1, | ||
| 448 | 0xd00103f0, | ||
| 449 | 0x04bd000f, | ||
| 450 | /* 0x05bb: ctx_redswitch_delay */ | ||
| 451 | 0xb608e7f0, | ||
| 452 | 0x1bf401e2, | ||
| 453 | 0x00f5f1fd, | ||
| 454 | 0x00f5f108, | ||
| 455 | 0x0007f102, | ||
| 456 | 0x0103f085, | ||
| 457 | 0xbd000fd0, | ||
| 458 | /* 0x05d7: ctx_xfer */ | ||
| 459 | 0xf100f804, | ||
| 460 | 0xf0810007, | ||
| 461 | 0x0fd00203, | ||
| 349 | 0xf404bd00, | 462 | 0xf404bd00, |
| 350 | 0x28f40031, | 463 | 0x21f50711, |
| 351 | 0x24d7f000, | 464 | /* 0x05ea: ctx_xfer_not_load */ |
| 352 | 0xf43921f4, | 465 | 0x21f505a9, |
| 353 | 0xe4b0f401, | 466 | 0x24bd026a, |
| 354 | 0x1e18f404, | 467 | 0x47fc07f1, |
| 355 | 0xf00181fe, | 468 | 0xd00203f0, |
| 356 | 0x20bd0627, | 469 | 0x04bd0002, |
| 357 | 0xb60412fd, | 470 | 0xb6012cf0, |
| 358 | 0x1efd01e4, | 471 | 0x07f10320, |
| 359 | 0x0018fe05, | 472 | 0x03f04afc, |
| 360 | 0x04f721f5, | 473 | 0x0002d002, |
| 361 | /* 0x0463: main_not_ctx_xfer */ | 474 | 0xacf004bd, |
| 362 | 0x94d30ef4, | 475 | 0x02a5f001, |
| 363 | 0xf5f010ef, | 476 | 0x0000b7f1, |
| 364 | 0xfe21f501, | ||
| 365 | 0xc60ef402, | ||
| 366 | /* 0x0470: ih */ | ||
| 367 | 0x88fe80f9, | ||
| 368 | 0xf980f901, | ||
| 369 | 0xf9a0f990, | ||
| 370 | 0xf9d0f9b0, | ||
| 371 | 0xbdf0f9e0, | ||
| 372 | 0x800acf04, | ||
| 373 | 0xf404abc4, | ||
| 374 | 0xb7f11d0b, | ||
| 375 | 0xd7f01900, | ||
| 376 | 0x40becf24, | ||
| 377 | 0xf400bfcf, | ||
| 378 | 0xb0b70421, | ||
| 379 | 0xe7f00400, | ||
| 380 | 0x00bed001, | ||
| 381 | /* 0x04a8: ih_no_fifo */ | ||
| 382 | 0xfc400ad0, | ||
| 383 | 0xfce0fcf0, | ||
| 384 | 0xfcb0fcd0, | ||
| 385 | 0xfc90fca0, | ||
| 386 | 0x0088fe80, | ||
| 387 | 0x32f480fc, | ||
| 388 | /* 0x04c3: hub_barrier_done */ | ||
| 389 | 0xf001f800, | ||
| 390 | 0x0e9801f7, | ||
| 391 | 0x04febb04, | ||
| 392 | 0x9418e7f1, | ||
| 393 | 0xf440e3f0, | ||
| 394 | 0x00f88d21, | ||
| 395 | /* 0x04d8: ctx_redswitch */ | ||
| 396 | 0x0614e7f1, | ||
| 397 | 0xf006e4b6, | ||
| 398 | 0xefd020f7, | ||
| 399 | 0x08f7f000, | ||
| 400 | /* 0x04e8: ctx_redswitch_delay */ | ||
| 401 | 0xf401f2b6, | ||
| 402 | 0xf7f1fd1b, | ||
| 403 | 0xefd00a20, | ||
| 404 | /* 0x04f7: ctx_xfer */ | ||
| 405 | 0xf100f800, | ||
| 406 | 0xb60a0417, | ||
| 407 | 0x1fd00614, | ||
| 408 | 0x0711f400, | ||
| 409 | 0x04d821f5, | ||
| 410 | /* 0x0508: ctx_xfer_not_load */ | ||
| 411 | 0x4afc17f1, | ||
| 412 | 0xf00213f0, | ||
| 413 | 0x12d00c27, | ||
| 414 | 0x1521f500, | ||
| 415 | 0xfc27f102, | ||
| 416 | 0x0223f047, | ||
| 417 | 0xf00020d0, | ||
| 418 | 0x20b6012c, | ||
| 419 | 0x0012d003, | ||
| 420 | 0xf001acf0, | ||
| 421 | 0xb7f002a5, | ||
| 422 | 0x50b3f000, | ||
| 423 | 0xb6040c98, | ||
| 424 | 0xbcbb0fc4, | ||
| 425 | 0x000c9800, | ||
| 426 | 0xf0010d98, | ||
| 427 | 0x21f500e7, | ||
| 428 | 0xacf00166, | ||
| 429 | 0x00b7f101, | ||
| 430 | 0x50b3f040, | ||
| 431 | 0xb6040c98, | ||
| 432 | 0xbcbb0fc4, | ||
| 433 | 0x010c9800, | ||
| 434 | 0x98020d98, | ||
| 435 | 0xe7f1060f, | ||
| 436 | 0x21f50800, | ||
| 437 | 0xacf00166, | ||
| 438 | 0x04a5f001, | ||
| 439 | 0x3000b7f1, | ||
| 440 | 0x9850b3f0, | 477 | 0x9850b3f0, |
| 441 | 0xc4b6040c, | 478 | 0xc4b6040c, |
| 442 | 0x00bcbb0f, | 479 | 0x00bcbb0f, |
| 443 | 0x98020c98, | 480 | 0x98000c98, |
| 444 | 0x0f98030d, | 481 | 0xe7f0010d, |
| 445 | 0x00e7f108, | 482 | 0x6f21f500, |
| 446 | 0x6621f502, | 483 | 0x01acf001, |
| 447 | 0x1521f501, | 484 | 0x4000b7f1, |
| 448 | 0x0601f402, | 485 | 0x9850b3f0, |
| 449 | /* 0x05a3: ctx_xfer_post */ | 486 | 0xc4b6040c, |
| 450 | 0xf11412f4, | 487 | 0x00bcbb0f, |
| 451 | 0xf04afc17, | 488 | 0x98010c98, |
| 452 | 0x27f00213, | 489 | 0x0f98020d, |
| 453 | 0x0012d00d, | 490 | 0x00e7f106, |
| 454 | 0x021521f5, | 491 | 0x6f21f508, |
| 455 | /* 0x05b4: ctx_xfer_done */ | 492 | 0x01acf001, |
| 456 | 0x04c321f5, | 493 | 0xf104a5f0, |
| 457 | 0x000000f8, | 494 | 0xf03000b7, |
| 495 | 0x0c9850b3, | ||
| 496 | 0x0fc4b604, | ||
| 497 | 0x9800bcbb, | ||
| 498 | 0x0d98020c, | ||
| 499 | 0x080f9803, | ||
| 500 | 0x0200e7f1, | ||
| 501 | 0x016f21f5, | ||
| 502 | 0x025e21f5, | ||
| 503 | 0xf40601f4, | ||
| 504 | /* 0x0686: ctx_xfer_post */ | ||
| 505 | 0x21f50712, | ||
| 506 | /* 0x068a: ctx_xfer_done */ | ||
| 507 | 0x21f5027f, | ||
| 508 | 0x00f80591, | ||
| 509 | 0x00000000, | ||
| 510 | 0x00000000, | ||
| 511 | 0x00000000, | ||
| 512 | 0x00000000, | ||
| 513 | 0x00000000, | ||
| 514 | 0x00000000, | ||
| 515 | 0x00000000, | ||
| 516 | 0x00000000, | ||
| 517 | 0x00000000, | ||
| 518 | 0x00000000, | ||
| 519 | 0x00000000, | ||
| 458 | 0x00000000, | 520 | 0x00000000, |
| 459 | 0x00000000, | 521 | 0x00000000, |
| 460 | 0x00000000, | 522 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc index b82d2ae89917..c8ddb8d71b91 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc | |||
| @@ -68,60 +68,57 @@ error: | |||
| 68 | // | 68 | // |
| 69 | init: | 69 | init: |
| 70 | clear b32 $r0 | 70 | clear b32 $r0 |
| 71 | mov $sp $r0 | ||
| 72 | mov $xdbase $r0 | 71 | mov $xdbase $r0 |
| 73 | 72 | ||
| 73 | // setup stack | ||
| 74 | nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0) | ||
| 75 | extr $r1 $r1 9:17 | ||
| 76 | shl b32 $r1 8 | ||
| 77 | mov $sp $r1 | ||
| 78 | |||
| 74 | // enable fifo access | 79 | // enable fifo access |
| 75 | mov $r1 0x1200 | 80 | mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO |
| 76 | mov $r2 2 | 81 | nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2) |
| 77 | iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE | ||
| 78 | 82 | ||
| 79 | // setup i0 handler, and route all interrupts to it | 83 | // setup i0 handler, and route all interrupts to it |
| 80 | mov $r1 #ih | 84 | mov $r1 #ih |
| 81 | mov $iv0 $r1 | 85 | mov $iv0 $r1 |
| 82 | mov $r1 0x400 | ||
| 83 | iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH | ||
| 84 | 86 | ||
| 85 | // route HUB_CHANNEL_SWITCH to fuc interrupt 8 | 87 | clear b32 $r2 |
| 86 | mov $r3 0x404 | 88 | nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2) |
| 87 | shl b32 $r3 6 | 89 | |
| 88 | mov $r2 0x2003 // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8 | 90 | // route HUB_CHSW_PULSE to fuc interrupt 8 |
| 89 | iowr I[$r3 + 0x000] $r2 | 91 | mov $r2 0x2003 // { HUB_CHSW_PULSE, ZERO } -> intr 8 |
| 92 | nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2) | ||
| 90 | 93 | ||
| 91 | // not sure what these are, route them because NVIDIA does, and | 94 | // not sure what these are, route them because NVIDIA does, and |
| 92 | // the IRQ handler will signal the host if we ever get one.. we | 95 | // the IRQ handler will signal the host if we ever get one.. we |
| 93 | // may find out if/why we need to handle these if so.. | 96 | // may find out if/why we need to handle these if so.. |
| 94 | // | 97 | // |
| 95 | mov $r2 0x2004 | 98 | mov $r2 0x2004 // { 0x04, ZERO } -> intr 9 |
| 96 | iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9 | 99 | nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2) |
| 97 | mov $r2 0x200b | 100 | mov $r2 0x200b // { HUB_FIRMWARE_MTHD, ZERO } -> intr 10 |
| 98 | iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10 | 101 | nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2) |
| 99 | mov $r2 0x200c | 102 | mov $r2 0x200c // { 0x0c, ZERO } -> intr 15 |
| 100 | iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15 | 103 | nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2) |
| 101 | 104 | ||
| 102 | // enable all INTR_UP interrupts | 105 | // enable all INTR_UP interrupts |
| 103 | mov $r2 0xc24 | 106 | sub b32 $r3 $r0 1 |
| 104 | shl b32 $r2 6 | 107 | nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3) |
| 105 | not b32 $r3 $r0 | ||
| 106 | iowr I[$r2] $r3 | ||
| 107 | 108 | ||
| 108 | // enable fifo, ctxsw, 9, 10, 15 interrupts | 109 | // enable fifo, ctxsw, 9, fwmthd, 15 interrupts |
| 109 | mov $r2 -0x78fc // 0x8704 | 110 | imm32($r2, 0x8704) |
| 110 | sethi $r2 0 | 111 | nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2) |
| 111 | iowr I[$r1 + 0x000] $r2 // INTR_EN_SET | ||
| 112 | 112 | ||
| 113 | // fifo level triggered, rest edge | 113 | // fifo level triggered, rest edge |
| 114 | sub b32 $r1 0x100 | 114 | mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL |
| 115 | mov $r2 4 | 115 | nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2) |
| 116 | iowr I[$r1] $r2 | ||
| 117 | 116 | ||
| 118 | // enable interrupts | 117 | // enable interrupts |
| 119 | bset $flags ie0 | 118 | bset $flags ie0 |
| 120 | 119 | ||
| 121 | // fetch enabled GPC/ROP counts | 120 | // fetch enabled GPC/ROP counts |
| 122 | mov $r14 -0x69fc // 0x409604 | 121 | nv_rd32($r14, 0x409604) |
| 123 | sethi $r14 0x400000 | ||
| 124 | call #nv_rd32 | ||
| 125 | extr $r1 $r15 16:20 | 122 | extr $r1 $r15 16:20 |
| 126 | st b32 D[$r0 + #rop_count] $r1 | 123 | st b32 D[$r0 + #rop_count] $r1 |
| 127 | and $r15 0x1f | 124 | and $r15 0x1f |
| @@ -131,37 +128,40 @@ init: | |||
| 131 | mov $r1 1 | 128 | mov $r1 1 |
| 132 | shl b32 $r1 $r15 | 129 | shl b32 $r1 $r15 |
| 133 | sub b32 $r1 1 | 130 | sub b32 $r1 1 |
| 134 | mov $r2 0x40c | 131 | nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1) |
| 135 | shl b32 $r2 6 | 132 | nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1) |
| 136 | iowr I[$r2 + 0x000] $r1 | ||
| 137 | iowr I[$r2 + 0x100] $r1 | ||
| 138 | 133 | ||
| 139 | // context size calculation, reserve first 256 bytes for use by fuc | 134 | // context size calculation, reserve first 256 bytes for use by fuc |
| 140 | mov $r1 256 | 135 | mov $r1 256 |
| 141 | 136 | ||
| 137 | // | ||
| 138 | mov $r15 2 | ||
| 139 | call(ctx_4170s) | ||
| 140 | call(ctx_4170w) | ||
| 141 | mov $r15 0x10 | ||
| 142 | call(ctx_86c) | ||
| 143 | |||
| 142 | // calculate size of mmio context data | 144 | // calculate size of mmio context data |
| 143 | ld b32 $r14 D[$r0 + #hub_mmio_list_head] | 145 | ld b32 $r14 D[$r0 + #hub_mmio_list_head] |
| 144 | ld b32 $r15 D[$r0 + #hub_mmio_list_tail] | 146 | ld b32 $r15 D[$r0 + #hub_mmio_list_tail] |
| 145 | call #mmctx_size | 147 | call(mmctx_size) |
| 146 | 148 | ||
| 147 | // set mmctx base addresses now so we don't have to do it later, | 149 | // set mmctx base addresses now so we don't have to do it later, |
| 148 | // they don't (currently) ever change | 150 | // they don't (currently) ever change |
| 149 | mov $r3 0x700 | ||
| 150 | shl b32 $r3 6 | ||
| 151 | shr b32 $r4 $r1 8 | 151 | shr b32 $r4 $r1 8 |
| 152 | iowr I[$r3 + 0x000] $r4 // MMCTX_SAVE_SWBASE | 152 | nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4) |
| 153 | iowr I[$r3 + 0x100] $r4 // MMCTX_LOAD_SWBASE | 153 | nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4) |
| 154 | add b32 $r3 0x1300 | 154 | add b32 $r3 0x1300 |
| 155 | add b32 $r1 $r15 | 155 | add b32 $r1 $r15 |
| 156 | shr b32 $r15 2 | 156 | shr b32 $r15 2 |
| 157 | iowr I[$r3 + 0x000] $r15 // MMCTX_LOAD_COUNT, wtf for?!? | 157 | nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf?? |
| 158 | 158 | ||
| 159 | // strands, base offset needs to be aligned to 256 bytes | 159 | // strands, base offset needs to be aligned to 256 bytes |
| 160 | shr b32 $r1 8 | 160 | shr b32 $r1 8 |
| 161 | add b32 $r1 1 | 161 | add b32 $r1 1 |
| 162 | shl b32 $r1 8 | 162 | shl b32 $r1 8 |
| 163 | mov b32 $r15 $r1 | 163 | mov b32 $r15 $r1 |
| 164 | call #strand_ctx_init | 164 | call(strand_ctx_init) |
| 165 | add b32 $r1 $r15 | 165 | add b32 $r1 $r15 |
| 166 | 166 | ||
| 167 | // initialise each GPC in sequence by passing in the offset of its | 167 | // initialise each GPC in sequence by passing in the offset of its |
| @@ -173,30 +173,29 @@ init: | |||
| 173 | // in GPCn_CC_SCRATCH[1] | 173 | // in GPCn_CC_SCRATCH[1] |
| 174 | // | 174 | // |
| 175 | ld b32 $r3 D[$r0 + #gpc_count] | 175 | ld b32 $r3 D[$r0 + #gpc_count] |
| 176 | mov $r4 0x2000 | 176 | imm32($r4, 0x502000) |
| 177 | sethi $r4 0x500000 | ||
| 178 | init_gpc: | 177 | init_gpc: |
| 179 | // setup, and start GPC ucode running | 178 | // setup, and start GPC ucode running |
| 180 | add b32 $r14 $r4 0x804 | 179 | add b32 $r14 $r4 0x804 |
| 181 | mov b32 $r15 $r1 | 180 | mov b32 $r15 $r1 |
| 182 | call #nv_wr32 // CC_SCRATCH[1] = ctx offset | 181 | call(nv_wr32) // CC_SCRATCH[1] = ctx offset |
| 183 | add b32 $r14 $r4 0x10c | 182 | add b32 $r14 $r4 0x10c |
| 184 | clear b32 $r15 | 183 | clear b32 $r15 |
| 185 | call #nv_wr32 | 184 | call(nv_wr32) |
| 186 | add b32 $r14 $r4 0x104 | 185 | add b32 $r14 $r4 0x104 |
| 187 | call #nv_wr32 // ENTRY | 186 | call(nv_wr32) // ENTRY |
| 188 | add b32 $r14 $r4 0x100 | 187 | add b32 $r14 $r4 0x100 |
| 189 | mov $r15 2 // CTRL_START_TRIGGER | 188 | mov $r15 2 // CTRL_START_TRIGGER |
| 190 | call #nv_wr32 // CTRL | 189 | call(nv_wr32) // CTRL |
| 191 | 190 | ||
| 192 | // wait for it to complete, and adjust context size | 191 | // wait for it to complete, and adjust context size |
| 193 | add b32 $r14 $r4 0x800 | 192 | add b32 $r14 $r4 0x800 |
| 194 | init_gpc_wait: | 193 | init_gpc_wait: |
| 195 | call #nv_rd32 | 194 | call(nv_rd32) |
| 196 | xbit $r15 $r15 31 | 195 | xbit $r15 $r15 31 |
| 197 | bra e #init_gpc_wait | 196 | bra e #init_gpc_wait |
| 198 | add b32 $r14 $r4 0x804 | 197 | add b32 $r14 $r4 0x804 |
| 199 | call #nv_rd32 | 198 | call(nv_rd32) |
| 200 | add b32 $r1 $r15 | 199 | add b32 $r1 $r15 |
| 201 | 200 | ||
| 202 | // next! | 201 | // next! |
| @@ -204,6 +203,12 @@ init: | |||
| 204 | sub b32 $r3 1 | 203 | sub b32 $r3 1 |
| 205 | bra ne #init_gpc | 204 | bra ne #init_gpc |
| 206 | 205 | ||
| 206 | // | ||
| 207 | mov $r15 0 | ||
| 208 | call(ctx_86c) | ||
| 209 | mov $r15 0 | ||
| 210 | call(ctx_4170s) | ||
| 211 | |||
| 207 | // save context size, and tell host we're ready | 212 | // save context size, and tell host we're ready |
| 208 | nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1) | 213 | nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1) |
| 209 | clear b32 $r1 | 214 | clear b32 $r1 |
| @@ -218,17 +223,15 @@ main: | |||
| 218 | bset $flags $p0 | 223 | bset $flags $p0 |
| 219 | sleep $p0 | 224 | sleep $p0 |
| 220 | mov $r13 #cmd_queue | 225 | mov $r13 #cmd_queue |
| 221 | call #queue_get | 226 | call(queue_get) |
| 222 | bra $p1 #main | 227 | bra $p1 #main |
| 223 | 228 | ||
| 224 | // context switch, requested by GPU? | 229 | // context switch, requested by GPU? |
| 225 | cmpu b32 $r14 0x4001 | 230 | cmpu b32 $r14 0x4001 |
| 226 | bra ne #main_not_ctx_switch | 231 | bra ne #main_not_ctx_switch |
| 227 | trace_set(T_AUTO) | 232 | trace_set(T_AUTO) |
| 228 | mov $r1 0xb00 | 233 | nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0) |
| 229 | shl b32 $r1 6 | 234 | nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0) |
| 230 | iord $r2 I[$r1 + 0x100] // CHAN_NEXT | ||
| 231 | iord $r1 I[$r1 + 0x000] // CHAN_CUR | ||
| 232 | 235 | ||
| 233 | xbit $r3 $r1 31 | 236 | xbit $r3 $r1 31 |
| 234 | bra e #chsw_no_prev | 237 | bra e #chsw_no_prev |
| @@ -239,12 +242,12 @@ main: | |||
| 239 | trace_set(T_SAVE) | 242 | trace_set(T_SAVE) |
| 240 | bclr $flags $p1 | 243 | bclr $flags $p1 |
| 241 | bset $flags $p2 | 244 | bset $flags $p2 |
| 242 | call #ctx_xfer | 245 | call(ctx_xfer) |
| 243 | trace_clr(T_SAVE); | 246 | trace_clr(T_SAVE); |
| 244 | pop $r2 | 247 | pop $r2 |
| 245 | trace_set(T_LOAD); | 248 | trace_set(T_LOAD); |
| 246 | bset $flags $p1 | 249 | bset $flags $p1 |
| 247 | call #ctx_xfer | 250 | call(ctx_xfer) |
| 248 | trace_clr(T_LOAD); | 251 | trace_clr(T_LOAD); |
| 249 | bra #chsw_done | 252 | bra #chsw_done |
| 250 | chsw_prev_no_next: | 253 | chsw_prev_no_next: |
| @@ -252,25 +255,21 @@ main: | |||
| 252 | mov b32 $r2 $r1 | 255 | mov b32 $r2 $r1 |
| 253 | bclr $flags $p1 | 256 | bclr $flags $p1 |
| 254 | bclr $flags $p2 | 257 | bclr $flags $p2 |
| 255 | call #ctx_xfer | 258 | call(ctx_xfer) |
| 256 | pop $r2 | 259 | pop $r2 |
| 257 | mov $r1 0xb00 | 260 | nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) |
| 258 | shl b32 $r1 6 | ||
| 259 | iowr I[$r1] $r2 | ||
| 260 | bra #chsw_done | 261 | bra #chsw_done |
| 261 | chsw_no_prev: | 262 | chsw_no_prev: |
| 262 | xbit $r3 $r2 31 | 263 | xbit $r3 $r2 31 |
| 263 | bra e #chsw_done | 264 | bra e #chsw_done |
| 264 | bset $flags $p1 | 265 | bset $flags $p1 |
| 265 | bclr $flags $p2 | 266 | bclr $flags $p2 |
| 266 | call #ctx_xfer | 267 | call(ctx_xfer) |
| 267 | 268 | ||
| 268 | // ack the context switch request | 269 | // ack the context switch request |
| 269 | chsw_done: | 270 | chsw_done: |
| 270 | mov $r1 0xb0c | 271 | mov $r2 NV_PGRAPH_FECS_CHSW_ACK |
| 271 | shl b32 $r1 6 | 272 | nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2) |
| 272 | mov $r2 1 | ||
| 273 | iowr I[$r1 + 0x000] $r2 // 0x409b0c | ||
| 274 | trace_clr(T_AUTO) | 273 | trace_clr(T_AUTO) |
| 275 | bra #main | 274 | bra #main |
| 276 | 275 | ||
| @@ -279,7 +278,7 @@ main: | |||
| 279 | cmpu b32 $r14 0x0001 | 278 | cmpu b32 $r14 0x0001 |
| 280 | bra ne #main_not_ctx_chan | 279 | bra ne #main_not_ctx_chan |
| 281 | mov b32 $r2 $r15 | 280 | mov b32 $r2 $r15 |
| 282 | call #ctx_chan | 281 | call(ctx_chan) |
| 283 | bra #main_done | 282 | bra #main_done |
| 284 | 283 | ||
| 285 | // request to store current channel context? | 284 | // request to store current channel context? |
| @@ -289,14 +288,14 @@ main: | |||
| 289 | trace_set(T_SAVE) | 288 | trace_set(T_SAVE) |
| 290 | bclr $flags $p1 | 289 | bclr $flags $p1 |
| 291 | bclr $flags $p2 | 290 | bclr $flags $p2 |
| 292 | call #ctx_xfer | 291 | call(ctx_xfer) |
| 293 | trace_clr(T_SAVE) | 292 | trace_clr(T_SAVE) |
| 294 | bra #main_done | 293 | bra #main_done |
| 295 | 294 | ||
| 296 | main_not_ctx_save: | 295 | main_not_ctx_save: |
| 297 | shl b32 $r15 $r14 16 | 296 | shl b32 $r15 $r14 16 |
| 298 | or $r15 E_BAD_COMMAND | 297 | or $r15 E_BAD_COMMAND |
| 299 | call #error | 298 | call(error) |
| 300 | bra #main | 299 | bra #main |
| 301 | 300 | ||
| 302 | main_done: | 301 | main_done: |
| @@ -319,41 +318,46 @@ ih: | |||
| 319 | clear b32 $r0 | 318 | clear b32 $r0 |
| 320 | 319 | ||
| 321 | // incoming fifo command? | 320 | // incoming fifo command? |
| 322 | iord $r10 I[$r0 + 0x200] // INTR | 321 | nv_iord($r10, NV_PGRAPH_FECS_INTR, 0) |
| 323 | and $r11 $r10 0x00000004 | 322 | and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO |
| 324 | bra e #ih_no_fifo | 323 | bra e #ih_no_fifo |
| 325 | // queue incoming fifo command for later processing | 324 | // queue incoming fifo command for later processing |
| 326 | mov $r11 0x1900 | ||
| 327 | mov $r13 #cmd_queue | 325 | mov $r13 #cmd_queue |
| 328 | iord $r14 I[$r11 + 0x100] // FIFO_CMD | 326 | nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0) |
| 329 | iord $r15 I[$r11 + 0x000] // FIFO_DATA | 327 | nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0) |
| 330 | call #queue_put | 328 | call(queue_put) |
| 331 | add b32 $r11 0x400 | 329 | add b32 $r11 0x400 |
| 332 | mov $r14 1 | 330 | mov $r14 1 |
| 333 | iowr I[$r11 + 0x000] $r14 // FIFO_ACK | 331 | nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14) |
| 334 | 332 | ||
| 335 | // context switch request? | 333 | // context switch request? |
| 336 | ih_no_fifo: | 334 | ih_no_fifo: |
| 337 | and $r11 $r10 0x00000100 | 335 | and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW |
| 338 | bra e #ih_no_ctxsw | 336 | bra e #ih_no_ctxsw |
| 339 | // enqueue a context switch for later processing | 337 | // enqueue a context switch for later processing |
| 340 | mov $r13 #cmd_queue | 338 | mov $r13 #cmd_queue |
| 341 | mov $r14 0x4001 | 339 | mov $r14 0x4001 |
| 342 | call #queue_put | 340 | call(queue_put) |
| 343 | 341 | ||
| 344 | // anything we didn't handle, bring it to the host's attention | 342 | // firmware method? |
| 345 | ih_no_ctxsw: | 343 | ih_no_ctxsw: |
| 346 | mov $r11 0x104 | 344 | and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD |
| 345 | bra e #ih_no_fwmthd | ||
| 346 | // none we handle, ack, and fall-through to unhandled | ||
| 347 | mov $r11 0x100 | ||
| 348 | nv_wr32(0x400144, $r11) | ||
| 349 | |||
| 350 | // anything we didn't handle, bring it to the host's attention | ||
| 351 | ih_no_fwmthd: | ||
| 352 | mov $r11 0x104 // FIFO | CHSW | ||
| 347 | not b32 $r11 | 353 | not b32 $r11 |
| 348 | and $r11 $r10 $r11 | 354 | and $r11 $r10 $r11 |
| 349 | bra e #ih_no_other | 355 | bra e #ih_no_other |
| 350 | mov $r10 0xc1c | 356 | nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11) |
| 351 | shl b32 $r10 6 | ||
| 352 | iowr I[$r10] $r11 // INTR_UP_SET | ||
| 353 | 357 | ||
| 354 | // ack, and wake up main() | 358 | // ack, and wake up main() |
| 355 | ih_no_other: | 359 | ih_no_other: |
| 356 | iowr I[$r0 + 0x100] $r10 // INTR_ACK | 360 | nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10) |
| 357 | 361 | ||
| 358 | pop $r15 | 362 | pop $r15 |
| 359 | pop $r14 | 363 | pop $r14 |
| @@ -370,12 +374,10 @@ ih: | |||
| 370 | #if CHIPSET < GK100 | 374 | #if CHIPSET < GK100 |
| 371 | // Not real sure, but, MEM_CMD 7 will hang forever if this isn't done | 375 | // Not real sure, but, MEM_CMD 7 will hang forever if this isn't done |
| 372 | ctx_4160s: | 376 | ctx_4160s: |
| 373 | mov $r14 0x4160 | ||
| 374 | sethi $r14 0x400000 | ||
| 375 | mov $r15 1 | 377 | mov $r15 1 |
| 376 | call #nv_wr32 | 378 | nv_wr32(0x404160, $r15) |
| 377 | ctx_4160s_wait: | 379 | ctx_4160s_wait: |
| 378 | call #nv_rd32 | 380 | nv_rd32($r15, 0x404160) |
| 379 | xbit $r15 $r15 4 | 381 | xbit $r15 $r15 4 |
| 380 | bra e #ctx_4160s_wait | 382 | bra e #ctx_4160s_wait |
| 381 | ret | 383 | ret |
| @@ -384,10 +386,8 @@ ctx_4160s: | |||
| 384 | // to hang with STATUS=0x00000007 until it's cleared.. fbcon can | 386 | // to hang with STATUS=0x00000007 until it's cleared.. fbcon can |
| 385 | // still function with it set however... | 387 | // still function with it set however... |
| 386 | ctx_4160c: | 388 | ctx_4160c: |
| 387 | mov $r14 0x4160 | ||
| 388 | sethi $r14 0x400000 | ||
| 389 | clear b32 $r15 | 389 | clear b32 $r15 |
| 390 | call #nv_wr32 | 390 | nv_wr32(0x404160, $r15) |
| 391 | ret | 391 | ret |
| 392 | #endif | 392 | #endif |
| 393 | 393 | ||
| @@ -396,18 +396,14 @@ ctx_4160c: | |||
| 396 | // In: $r15 value to set 0x404170 to | 396 | // In: $r15 value to set 0x404170 to |
| 397 | // | 397 | // |
| 398 | ctx_4170s: | 398 | ctx_4170s: |
| 399 | mov $r14 0x4170 | ||
| 400 | sethi $r14 0x400000 | ||
| 401 | or $r15 0x10 | 399 | or $r15 0x10 |
| 402 | call #nv_wr32 | 400 | nv_wr32(0x404170, $r15) |
| 403 | ret | 401 | ret |
| 404 | 402 | ||
| 405 | // Waits for a ctx_4170s() call to complete | 403 | // Waits for a ctx_4170s() call to complete |
| 406 | // | 404 | // |
| 407 | ctx_4170w: | 405 | ctx_4170w: |
| 408 | mov $r14 0x4170 | 406 | nv_rd32($r15, 0x404170) |
| 409 | sethi $r14 0x400000 | ||
| 410 | call #nv_rd32 | ||
| 411 | and $r15 0x10 | 407 | and $r15 0x10 |
| 412 | bra ne #ctx_4170w | 408 | bra ne #ctx_4170w |
| 413 | ret | 409 | ret |
| @@ -419,16 +415,18 @@ ctx_4170w: | |||
| 419 | // funny things happen. | 415 | // funny things happen. |
| 420 | // | 416 | // |
| 421 | ctx_redswitch: | 417 | ctx_redswitch: |
| 422 | mov $r14 0x614 | 418 | mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC |
| 423 | shl b32 $r14 6 | 419 | or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP |
| 424 | mov $r15 0x270 | 420 | or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC |
| 425 | iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_GPC, POWER_ALL | 421 | or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN |
| 422 | nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) | ||
| 426 | mov $r15 8 | 423 | mov $r15 8 |
| 427 | ctx_redswitch_delay: | 424 | ctx_redswitch_delay: |
| 428 | sub b32 $r15 1 | 425 | sub b32 $r15 1 |
| 429 | bra ne #ctx_redswitch_delay | 426 | bra ne #ctx_redswitch_delay |
| 430 | mov $r15 0x770 | 427 | or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP |
| 431 | iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL | 428 | or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN |
| 429 | nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) | ||
| 432 | ret | 430 | ret |
| 433 | 431 | ||
| 434 | // Not a clue what this is for, except that unless the value is 0x10, the | 432 | // Not a clue what this is for, except that unless the value is 0x10, the |
| @@ -437,15 +435,18 @@ ctx_redswitch: | |||
| 437 | // In: $r15 value to set to (0x00/0x10 are used) | 435 | // In: $r15 value to set to (0x00/0x10 are used) |
| 438 | // | 436 | // |
| 439 | ctx_86c: | 437 | ctx_86c: |
| 440 | mov $r14 0x86c | 438 | nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15) |
| 441 | shl b32 $r14 6 | 439 | nv_wr32(0x408a14, $r15) |
| 442 | iowr I[$r14] $r15 // HUB(0x86c) = val | 440 | nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15) |
| 443 | mov $r14 -0x75ec | 441 | ret |
| 444 | sethi $r14 0x400000 | 442 | |
| 445 | call #nv_wr32 // ROP(0xa14) = val | 443 | // In: $r15 NV_PGRAPH_FECS_MEM_CMD_* |
| 446 | mov $r14 -0x5794 | 444 | ctx_mem: |
| 447 | sethi $r14 0x410000 | 445 | nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15) |
| 448 | call #nv_wr32 // GPC(0x86c) = val | 446 | ctx_mem_wait: |
| 447 | nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0) | ||
| 448 | or $r15 $r15 | ||
| 449 | bra ne #ctx_mem_wait | ||
| 449 | ret | 450 | ret |
| 450 | 451 | ||
| 451 | // ctx_load - load's a channel's ctxctl data, and selects its vm | 452 | // ctx_load - load's a channel's ctxctl data, and selects its vm |
| @@ -457,23 +458,14 @@ ctx_load: | |||
| 457 | 458 | ||
| 458 | // switch to channel, somewhat magic in parts.. | 459 | // switch to channel, somewhat magic in parts.. |
| 459 | mov $r10 12 // DONE_UNK12 | 460 | mov $r10 12 // DONE_UNK12 |
| 460 | call #wait_donez | 461 | call(wait_donez) |
| 461 | mov $r1 0xa24 | 462 | clear b32 $r15 |
| 462 | shl b32 $r1 6 | 463 | nv_iowr(0x409a24, 0, $r15) |
| 463 | iowr I[$r1 + 0x000] $r0 // 0x409a24 | 464 | nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2) |
| 464 | mov $r3 0xb00 | 465 | nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2) |
| 465 | shl b32 $r3 6 | 466 | mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN |
| 466 | iowr I[$r3 + 0x100] $r2 // CHAN_NEXT | 467 | call(ctx_mem) |
| 467 | mov $r1 0xa0c | 468 | nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) |
| 468 | shl b32 $r1 6 | ||
| 469 | mov $r4 7 | ||
| 470 | iowr I[$r1 + 0x000] $r2 // MEM_CHAN | ||
| 471 | iowr I[$r1 + 0x100] $r4 // MEM_CMD | ||
| 472 | ctx_chan_wait_0: | ||
| 473 | iord $r4 I[$r1 + 0x100] | ||
| 474 | and $r4 0x1f | ||
| 475 | bra ne #ctx_chan_wait_0 | ||
| 476 | iowr I[$r3 + 0x000] $r2 // CHAN_CUR | ||
| 477 | 469 | ||
| 478 | // load channel header, fetch PGRAPH context pointer | 470 | // load channel header, fetch PGRAPH context pointer |
| 479 | mov $xtargets $r0 | 471 | mov $xtargets $r0 |
| @@ -482,14 +474,10 @@ ctx_load: | |||
| 482 | add b32 $r2 2 | 474 | add b32 $r2 2 |
| 483 | 475 | ||
| 484 | trace_set(T_LCHAN) | 476 | trace_set(T_LCHAN) |
| 485 | mov $r1 0xa04 | 477 | nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2) |
| 486 | shl b32 $r1 6 | 478 | imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31) |
| 487 | iowr I[$r1 + 0x000] $r2 // MEM_BASE | 479 | or $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM |
| 488 | mov $r1 0xa20 | 480 | nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) |
| 489 | shl b32 $r1 6 | ||
| 490 | mov $r2 0x0002 | ||
| 491 | sethi $r2 0x80000000 | ||
| 492 | iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vram | ||
| 493 | mov $r1 0x10 // chan + 0x0210 | 481 | mov $r1 0x10 // chan + 0x0210 |
| 494 | mov $r2 #xfer_data | 482 | mov $r2 #xfer_data |
| 495 | sethi $r2 0x00020000 // 16 bytes | 483 | sethi $r2 0x00020000 // 16 bytes |
| @@ -507,13 +495,9 @@ ctx_load: | |||
| 507 | 495 | ||
| 508 | // set transfer base to start of context, and fetch context header | 496 | // set transfer base to start of context, and fetch context header |
| 509 | trace_set(T_LCTXH) | 497 | trace_set(T_LCTXH) |
| 510 | mov $r2 0xa04 | 498 | nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1) |
| 511 | shl b32 $r2 6 | 499 | mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM |
| 512 | iowr I[$r2 + 0x000] $r1 // MEM_BASE | 500 | nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) |
| 513 | mov $r2 1 | ||
| 514 | mov $r1 0xa20 | ||
| 515 | shl b32 $r1 6 | ||
| 516 | iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vm | ||
| 517 | mov $r1 #chan_data | 501 | mov $r1 #chan_data |
| 518 | sethi $r1 0x00060000 // 256 bytes | 502 | sethi $r1 0x00060000 // 256 bytes |
| 519 | xdld $r0 $r1 | 503 | xdld $r0 $r1 |
| @@ -532,21 +516,15 @@ ctx_load: | |||
| 532 | // | 516 | // |
| 533 | ctx_chan: | 517 | ctx_chan: |
| 534 | #if CHIPSET < GK100 | 518 | #if CHIPSET < GK100 |
| 535 | call #ctx_4160s | 519 | call(ctx_4160s) |
| 536 | #endif | 520 | #endif |
| 537 | call #ctx_load | 521 | call(ctx_load) |
| 538 | mov $r10 12 // DONE_UNK12 | 522 | mov $r10 12 // DONE_UNK12 |
| 539 | call #wait_donez | 523 | call(wait_donez) |
| 540 | mov $r1 0xa10 | 524 | mov $r15 5 // MEM_CMD 5 ??? |
| 541 | shl b32 $r1 6 | 525 | call(ctx_mem) |
| 542 | mov $r2 5 | ||
| 543 | iowr I[$r1 + 0x000] $r2 // MEM_CMD = 5 (???) | ||
| 544 | ctx_chan_wait: | ||
| 545 | iord $r2 I[$r1 + 0x000] | ||
| 546 | or $r2 $r2 | ||
| 547 | bra ne #ctx_chan_wait | ||
| 548 | #if CHIPSET < GK100 | 526 | #if CHIPSET < GK100 |
| 549 | call #ctx_4160c | 527 | call(ctx_4160c) |
| 550 | #endif | 528 | #endif |
| 551 | ret | 529 | ret |
| 552 | 530 | ||
| @@ -562,9 +540,7 @@ ctx_chan: | |||
| 562 | ctx_mmio_exec: | 540 | ctx_mmio_exec: |
| 563 | // set transfer base to be the mmio list | 541 | // set transfer base to be the mmio list |
| 564 | ld b32 $r3 D[$r0 + #chan_mmio_address] | 542 | ld b32 $r3 D[$r0 + #chan_mmio_address] |
| 565 | mov $r2 0xa04 | 543 | nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) |
| 566 | shl b32 $r2 6 | ||
| 567 | iowr I[$r2 + 0x000] $r3 // MEM_BASE | ||
| 568 | 544 | ||
| 569 | clear b32 $r3 | 545 | clear b32 $r3 |
| 570 | ctx_mmio_loop: | 546 | ctx_mmio_loop: |
| @@ -580,7 +556,7 @@ ctx_mmio_exec: | |||
| 580 | ctx_mmio_pull: | 556 | ctx_mmio_pull: |
| 581 | ld b32 $r14 D[$r4 + #xfer_data + 0x00] | 557 | ld b32 $r14 D[$r4 + #xfer_data + 0x00] |
| 582 | ld b32 $r15 D[$r4 + #xfer_data + 0x04] | 558 | ld b32 $r15 D[$r4 + #xfer_data + 0x04] |
| 583 | call #nv_wr32 | 559 | call(nv_wr32) |
| 584 | 560 | ||
| 585 | // next! | 561 | // next! |
| 586 | add b32 $r3 8 | 562 | add b32 $r3 8 |
| @@ -590,7 +566,7 @@ ctx_mmio_exec: | |||
| 590 | // set transfer base back to the current context | 566 | // set transfer base back to the current context |
| 591 | ctx_mmio_done: | 567 | ctx_mmio_done: |
| 592 | ld b32 $r3 D[$r0 + #ctx_current] | 568 | ld b32 $r3 D[$r0 + #ctx_current] |
| 593 | iowr I[$r2 + 0x000] $r3 // MEM_BASE | 569 | nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) |
| 594 | 570 | ||
| 595 | // disable the mmio list now, we don't need/want to execute it again | 571 | // disable the mmio list now, we don't need/want to execute it again |
| 596 | st b32 D[$r0 + #chan_mmio_count] $r0 | 572 | st b32 D[$r0 + #chan_mmio_count] $r0 |
| @@ -610,12 +586,10 @@ ctx_mmio_exec: | |||
| 610 | // | 586 | // |
| 611 | ctx_xfer: | 587 | ctx_xfer: |
| 612 | // according to mwk, some kind of wait for idle | 588 | // according to mwk, some kind of wait for idle |
| 613 | mov $r15 0xc00 | ||
| 614 | shl b32 $r15 6 | ||
| 615 | mov $r14 4 | 589 | mov $r14 4 |
| 616 | iowr I[$r15 + 0x200] $r14 | 590 | nv_iowr(0x409c08, 0, $r14) |
| 617 | ctx_xfer_idle: | 591 | ctx_xfer_idle: |
| 618 | iord $r14 I[$r15 + 0x000] | 592 | nv_iord($r14, 0x409c00, 0) |
| 619 | and $r14 0x2000 | 593 | and $r14 0x2000 |
| 620 | bra ne #ctx_xfer_idle | 594 | bra ne #ctx_xfer_idle |
| 621 | 595 | ||
| @@ -623,50 +597,42 @@ ctx_xfer: | |||
| 623 | bra $p2 #ctx_xfer_pre_load | 597 | bra $p2 #ctx_xfer_pre_load |
| 624 | ctx_xfer_pre: | 598 | ctx_xfer_pre: |
| 625 | mov $r15 0x10 | 599 | mov $r15 0x10 |
| 626 | call #ctx_86c | 600 | call(ctx_86c) |
| 627 | #if CHIPSET < GK100 | 601 | #if CHIPSET < GK100 |
| 628 | call #ctx_4160s | 602 | call(ctx_4160s) |
| 629 | #endif | 603 | #endif |
| 630 | bra not $p1 #ctx_xfer_exec | 604 | bra not $p1 #ctx_xfer_exec |
| 631 | 605 | ||
| 632 | ctx_xfer_pre_load: | 606 | ctx_xfer_pre_load: |
| 633 | mov $r15 2 | 607 | mov $r15 2 |
| 634 | call #ctx_4170s | 608 | call(ctx_4170s) |
| 635 | call #ctx_4170w | 609 | call(ctx_4170w) |
| 636 | call #ctx_redswitch | 610 | call(ctx_redswitch) |
| 637 | clear b32 $r15 | 611 | clear b32 $r15 |
| 638 | call #ctx_4170s | 612 | call(ctx_4170s) |
| 639 | call #ctx_load | 613 | call(ctx_load) |
| 640 | 614 | ||
| 641 | // fetch context pointer, and initiate xfer on all GPCs | 615 | // fetch context pointer, and initiate xfer on all GPCs |
| 642 | ctx_xfer_exec: | 616 | ctx_xfer_exec: |
| 643 | ld b32 $r1 D[$r0 + #ctx_current] | 617 | ld b32 $r1 D[$r0 + #ctx_current] |
| 644 | mov $r2 0x414 | 618 | |
| 645 | shl b32 $r2 6 | 619 | clear b32 $r2 |
| 646 | iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset | 620 | nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2) |
| 647 | mov $r14 -0x5b00 | 621 | |
| 648 | sethi $r14 0x410000 | 622 | nv_wr32(0x41a500, $r1) // GPC_BCAST_WRCMD_DATA = ctx pointer |
| 649 | mov b32 $r15 $r1 | ||
| 650 | call #nv_wr32 // GPC_BCAST_WRCMD_DATA = ctx pointer | ||
| 651 | add b32 $r14 4 | ||
| 652 | xbit $r15 $flags $p1 | 623 | xbit $r15 $flags $p1 |
| 653 | xbit $r2 $flags $p2 | 624 | xbit $r2 $flags $p2 |
| 654 | shl b32 $r2 1 | 625 | shl b32 $r2 1 |
| 655 | or $r15 $r2 | 626 | or $r15 $r2 |
| 656 | call #nv_wr32 // GPC_BCAST_WRCMD_CMD = GPC_XFER(type) | 627 | nv_wr32(0x41a504, $r15) // GPC_BCAST_WRCMD_CMD = GPC_XFER(type) |
| 657 | 628 | ||
| 658 | // strands | 629 | // strands |
| 659 | mov $r1 0x4afc | 630 | call(strand_pre) |
| 660 | sethi $r1 0x20000 | 631 | clear b32 $r2 |
| 661 | mov $r2 0xc | 632 | nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2) |
| 662 | iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c | 633 | xbit $r2 $flags $p1 // SAVE/LOAD |
| 663 | call #strand_wait | 634 | add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE |
| 664 | mov $r2 0x47fc | 635 | nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2) |
| 665 | sethi $r2 0x20000 | ||
| 666 | iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00 | ||
| 667 | xbit $r2 $flags $p1 | ||
| 668 | add b32 $r2 3 | ||
| 669 | iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD) | ||
| 670 | 636 | ||
| 671 | // mmio context | 637 | // mmio context |
| 672 | xbit $r10 $flags $p1 // direction | 638 | xbit $r10 $flags $p1 // direction |
| @@ -675,48 +641,42 @@ ctx_xfer: | |||
| 675 | ld b32 $r12 D[$r0 + #hub_mmio_list_head] | 641 | ld b32 $r12 D[$r0 + #hub_mmio_list_head] |
| 676 | ld b32 $r13 D[$r0 + #hub_mmio_list_tail] | 642 | ld b32 $r13 D[$r0 + #hub_mmio_list_tail] |
| 677 | mov $r14 0 // not multi | 643 | mov $r14 0 // not multi |
| 678 | call #mmctx_xfer | 644 | call(mmctx_xfer) |
| 679 | 645 | ||
| 680 | // wait for GPCs to all complete | 646 | // wait for GPCs to all complete |
| 681 | mov $r10 8 // DONE_BAR | 647 | mov $r10 8 // DONE_BAR |
| 682 | call #wait_doneo | 648 | call(wait_doneo) |
| 683 | 649 | ||
| 684 | // wait for strand xfer to complete | 650 | // wait for strand xfer to complete |
| 685 | call #strand_wait | 651 | call(strand_wait) |
| 686 | 652 | ||
| 687 | // post-op | 653 | // post-op |
| 688 | bra $p1 #ctx_xfer_post | 654 | bra $p1 #ctx_xfer_post |
| 689 | mov $r10 12 // DONE_UNK12 | 655 | mov $r10 12 // DONE_UNK12 |
| 690 | call #wait_donez | 656 | call(wait_donez) |
| 691 | mov $r1 0xa10 | 657 | mov $r15 5 // MEM_CMD 5 ??? |
| 692 | shl b32 $r1 6 | 658 | call(ctx_mem) |
| 693 | mov $r2 5 | ||
| 694 | iowr I[$r1] $r2 // MEM_CMD | ||
| 695 | ctx_xfer_post_save_wait: | ||
| 696 | iord $r2 I[$r1] | ||
| 697 | or $r2 $r2 | ||
| 698 | bra ne #ctx_xfer_post_save_wait | ||
| 699 | 659 | ||
| 700 | bra $p2 #ctx_xfer_done | 660 | bra $p2 #ctx_xfer_done |
| 701 | ctx_xfer_post: | 661 | ctx_xfer_post: |
| 702 | mov $r15 2 | 662 | mov $r15 2 |
| 703 | call #ctx_4170s | 663 | call(ctx_4170s) |
| 704 | clear b32 $r15 | 664 | clear b32 $r15 |
| 705 | call #ctx_86c | 665 | call(ctx_86c) |
| 706 | call #strand_post | 666 | call(strand_post) |
| 707 | call #ctx_4170w | 667 | call(ctx_4170w) |
| 708 | clear b32 $r15 | 668 | clear b32 $r15 |
| 709 | call #ctx_4170s | 669 | call(ctx_4170s) |
| 710 | 670 | ||
| 711 | bra not $p1 #ctx_xfer_no_post_mmio | 671 | bra not $p1 #ctx_xfer_no_post_mmio |
| 712 | ld b32 $r1 D[$r0 + #chan_mmio_count] | 672 | ld b32 $r1 D[$r0 + #chan_mmio_count] |
| 713 | or $r1 $r1 | 673 | or $r1 $r1 |
| 714 | bra e #ctx_xfer_no_post_mmio | 674 | bra e #ctx_xfer_no_post_mmio |
| 715 | call #ctx_mmio_exec | 675 | call(ctx_mmio_exec) |
| 716 | 676 | ||
| 717 | ctx_xfer_no_post_mmio: | 677 | ctx_xfer_no_post_mmio: |
| 718 | #if CHIPSET < GK100 | 678 | #if CHIPSET < GK100 |
| 719 | call #ctx_4160c | 679 | call(ctx_4160c) |
| 720 | #endif | 680 | #endif |
| 721 | 681 | ||
| 722 | ctx_xfer_done: | 682 | ctx_xfer_done: |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 new file mode 100644 index 000000000000..7c5d25630fa8 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define CHIPSET GK208 | ||
| 26 | #include "macros.fuc" | ||
| 27 | |||
| 28 | .section #nv108_grhub_data | ||
| 29 | #define INCLUDE_DATA | ||
| 30 | #include "com.fuc" | ||
| 31 | #include "hub.fuc" | ||
| 32 | #undef INCLUDE_DATA | ||
| 33 | |||
| 34 | .section #nv108_grhub_code | ||
| 35 | #define INCLUDE_CODE | ||
| 36 | bra #init | ||
| 37 | #include "com.fuc" | ||
| 38 | #include "hub.fuc" | ||
| 39 | .align 256 | ||
| 40 | #undef INCLUDE_CODE | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h new file mode 100644 index 000000000000..4750984bf380 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h | |||
| @@ -0,0 +1,916 @@ | |||
| 1 | uint32_t nv108_grhub_data[] = { | ||
| 2 | /* 0x0000: hub_mmio_list_head */ | ||
| 3 | 0x00000300, | ||
| 4 | /* 0x0004: hub_mmio_list_tail */ | ||
| 5 | 0x00000304, | ||
| 6 | /* 0x0008: gpc_count */ | ||
| 7 | 0x00000000, | ||
| 8 | /* 0x000c: rop_count */ | ||
| 9 | 0x00000000, | ||
| 10 | /* 0x0010: cmd_queue */ | ||
| 11 | 0x00000000, | ||
| 12 | 0x00000000, | ||
| 13 | 0x00000000, | ||
| 14 | 0x00000000, | ||
| 15 | 0x00000000, | ||
| 16 | 0x00000000, | ||
| 17 | 0x00000000, | ||
| 18 | 0x00000000, | ||
| 19 | 0x00000000, | ||
| 20 | 0x00000000, | ||
| 21 | 0x00000000, | ||
| 22 | 0x00000000, | ||
| 23 | 0x00000000, | ||
| 24 | 0x00000000, | ||
| 25 | 0x00000000, | ||
| 26 | 0x00000000, | ||
| 27 | 0x00000000, | ||
| 28 | 0x00000000, | ||
| 29 | /* 0x0058: ctx_current */ | ||
| 30 | 0x00000000, | ||
| 31 | 0x00000000, | ||
| 32 | 0x00000000, | ||
| 33 | 0x00000000, | ||
| 34 | 0x00000000, | ||
| 35 | 0x00000000, | ||
| 36 | 0x00000000, | ||
| 37 | 0x00000000, | ||
| 38 | 0x00000000, | ||
| 39 | 0x00000000, | ||
| 40 | 0x00000000, | ||
| 41 | 0x00000000, | ||
| 42 | 0x00000000, | ||
| 43 | 0x00000000, | ||
| 44 | 0x00000000, | ||
| 45 | 0x00000000, | ||
| 46 | 0x00000000, | ||
| 47 | 0x00000000, | ||
| 48 | 0x00000000, | ||
| 49 | 0x00000000, | ||
| 50 | 0x00000000, | ||
| 51 | 0x00000000, | ||
| 52 | 0x00000000, | ||
| 53 | 0x00000000, | ||
| 54 | 0x00000000, | ||
| 55 | 0x00000000, | ||
| 56 | 0x00000000, | ||
| 57 | 0x00000000, | ||
| 58 | 0x00000000, | ||
| 59 | 0x00000000, | ||
| 60 | 0x00000000, | ||
| 61 | 0x00000000, | ||
| 62 | 0x00000000, | ||
| 63 | 0x00000000, | ||
| 64 | 0x00000000, | ||
| 65 | 0x00000000, | ||
| 66 | 0x00000000, | ||
| 67 | 0x00000000, | ||
| 68 | 0x00000000, | ||
| 69 | 0x00000000, | ||
| 70 | 0x00000000, | ||
| 71 | 0x00000000, | ||
| 72 | /* 0x0100: chan_data */ | ||
| 73 | /* 0x0100: chan_mmio_count */ | ||
| 74 | 0x00000000, | ||
| 75 | /* 0x0104: chan_mmio_address */ | ||
| 76 | 0x00000000, | ||
| 77 | 0x00000000, | ||
| 78 | 0x00000000, | ||
| 79 | 0x00000000, | ||
| 80 | 0x00000000, | ||
| 81 | 0x00000000, | ||
| 82 | 0x00000000, | ||
| 83 | 0x00000000, | ||
| 84 | 0x00000000, | ||
| 85 | 0x00000000, | ||
| 86 | 0x00000000, | ||
| 87 | 0x00000000, | ||
| 88 | 0x00000000, | ||
| 89 | 0x00000000, | ||
| 90 | 0x00000000, | ||
| 91 | 0x00000000, | ||
| 92 | 0x00000000, | ||
| 93 | 0x00000000, | ||
| 94 | 0x00000000, | ||
| 95 | 0x00000000, | ||
| 96 | 0x00000000, | ||
| 97 | 0x00000000, | ||
| 98 | 0x00000000, | ||
| 99 | 0x00000000, | ||
| 100 | 0x00000000, | ||
| 101 | 0x00000000, | ||
| 102 | 0x00000000, | ||
| 103 | 0x00000000, | ||
| 104 | 0x00000000, | ||
| 105 | 0x00000000, | ||
| 106 | 0x00000000, | ||
| 107 | 0x00000000, | ||
| 108 | 0x00000000, | ||
| 109 | 0x00000000, | ||
| 110 | 0x00000000, | ||
| 111 | 0x00000000, | ||
| 112 | 0x00000000, | ||
| 113 | 0x00000000, | ||
| 114 | 0x00000000, | ||
| 115 | 0x00000000, | ||
| 116 | 0x00000000, | ||
| 117 | 0x00000000, | ||
| 118 | 0x00000000, | ||
| 119 | 0x00000000, | ||
| 120 | 0x00000000, | ||
| 121 | 0x00000000, | ||
| 122 | 0x00000000, | ||
| 123 | 0x00000000, | ||
| 124 | 0x00000000, | ||
| 125 | 0x00000000, | ||
| 126 | 0x00000000, | ||
| 127 | 0x00000000, | ||
| 128 | 0x00000000, | ||
| 129 | 0x00000000, | ||
| 130 | 0x00000000, | ||
| 131 | 0x00000000, | ||
| 132 | 0x00000000, | ||
| 133 | 0x00000000, | ||
| 134 | 0x00000000, | ||
| 135 | 0x00000000, | ||
| 136 | 0x00000000, | ||
| 137 | 0x00000000, | ||
| 138 | 0x00000000, | ||
| 139 | /* 0x0200: xfer_data */ | ||
| 140 | 0x00000000, | ||
| 141 | 0x00000000, | ||
| 142 | 0x00000000, | ||
| 143 | 0x00000000, | ||
| 144 | 0x00000000, | ||
| 145 | 0x00000000, | ||
| 146 | 0x00000000, | ||
| 147 | 0x00000000, | ||
| 148 | 0x00000000, | ||
| 149 | 0x00000000, | ||
| 150 | 0x00000000, | ||
| 151 | 0x00000000, | ||
| 152 | 0x00000000, | ||
| 153 | 0x00000000, | ||
| 154 | 0x00000000, | ||
| 155 | 0x00000000, | ||
| 156 | 0x00000000, | ||
| 157 | 0x00000000, | ||
| 158 | 0x00000000, | ||
| 159 | 0x00000000, | ||
| 160 | 0x00000000, | ||
| 161 | 0x00000000, | ||
| 162 | 0x00000000, | ||
| 163 | 0x00000000, | ||
| 164 | 0x00000000, | ||
| 165 | 0x00000000, | ||
| 166 | 0x00000000, | ||
| 167 | 0x00000000, | ||
| 168 | 0x00000000, | ||
| 169 | 0x00000000, | ||
| 170 | 0x00000000, | ||
| 171 | 0x00000000, | ||
| 172 | 0x00000000, | ||
| 173 | 0x00000000, | ||
| 174 | 0x00000000, | ||
| 175 | 0x00000000, | ||
| 176 | 0x00000000, | ||
| 177 | 0x00000000, | ||
| 178 | 0x00000000, | ||
| 179 | 0x00000000, | ||
| 180 | 0x00000000, | ||
| 181 | 0x00000000, | ||
| 182 | 0x00000000, | ||
| 183 | 0x00000000, | ||
| 184 | 0x00000000, | ||
| 185 | 0x00000000, | ||
| 186 | 0x00000000, | ||
| 187 | 0x00000000, | ||
| 188 | 0x00000000, | ||
| 189 | 0x00000000, | ||
| 190 | 0x00000000, | ||
| 191 | 0x00000000, | ||
| 192 | 0x00000000, | ||
| 193 | 0x00000000, | ||
| 194 | 0x00000000, | ||
| 195 | 0x00000000, | ||
| 196 | 0x00000000, | ||
| 197 | 0x00000000, | ||
| 198 | 0x00000000, | ||
| 199 | 0x00000000, | ||
| 200 | 0x00000000, | ||
| 201 | 0x00000000, | ||
| 202 | 0x00000000, | ||
| 203 | 0x00000000, | ||
| 204 | /* 0x0300: hub_mmio_list_base */ | ||
| 205 | 0x0417e91c, | ||
| 206 | }; | ||
| 207 | |||
| 208 | uint32_t nv108_grhub_code[] = { | ||
| 209 | 0x030e0ef5, | ||
| 210 | /* 0x0004: queue_put */ | ||
| 211 | 0x9800d898, | ||
| 212 | 0x86f001d9, | ||
| 213 | 0xf489a408, | ||
| 214 | 0x020f0b1b, | ||
| 215 | 0x0002f87e, | ||
| 216 | /* 0x001a: queue_put_next */ | ||
| 217 | 0x98c400f8, | ||
| 218 | 0x0384b607, | ||
| 219 | 0xb6008dbb, | ||
| 220 | 0x8eb50880, | ||
| 221 | 0x018fb500, | ||
| 222 | 0xf00190b6, | ||
| 223 | 0xd9b50f94, | ||
| 224 | /* 0x0037: queue_get */ | ||
| 225 | 0xf400f801, | ||
| 226 | 0xd8980131, | ||
| 227 | 0x01d99800, | ||
| 228 | 0x0bf489a4, | ||
| 229 | 0x0789c421, | ||
| 230 | 0xbb0394b6, | ||
| 231 | 0x90b6009d, | ||
| 232 | 0x009e9808, | ||
| 233 | 0xb6019f98, | ||
| 234 | 0x84f00180, | ||
| 235 | 0x00d8b50f, | ||
| 236 | /* 0x0063: queue_get_done */ | ||
| 237 | 0xf80132f4, | ||
| 238 | /* 0x0065: nv_rd32 */ | ||
| 239 | 0xf0ecb200, | ||
| 240 | 0x00801fc9, | ||
| 241 | 0x0cf601ca, | ||
| 242 | /* 0x0073: nv_rd32_wait */ | ||
| 243 | 0x8c04bd00, | ||
| 244 | 0xcf01ca00, | ||
| 245 | 0xccc800cc, | ||
| 246 | 0xf61bf41f, | ||
| 247 | 0xec7e060a, | ||
| 248 | 0x008f0000, | ||
| 249 | 0xffcf01cb, | ||
| 250 | /* 0x008f: nv_wr32 */ | ||
| 251 | 0x8000f800, | ||
| 252 | 0xf601cc00, | ||
| 253 | 0x04bd000f, | ||
| 254 | 0xc9f0ecb2, | ||
| 255 | 0x1ec9f01f, | ||
| 256 | 0x01ca0080, | ||
| 257 | 0xbd000cf6, | ||
| 258 | /* 0x00a9: nv_wr32_wait */ | ||
| 259 | 0xca008c04, | ||
| 260 | 0x00cccf01, | ||
| 261 | 0xf41fccc8, | ||
| 262 | 0x00f8f61b, | ||
| 263 | /* 0x00b8: wait_donez */ | ||
| 264 | 0x99f094bd, | ||
| 265 | 0x37008000, | ||
| 266 | 0x0009f602, | ||
| 267 | 0x008004bd, | ||
| 268 | 0x0af60206, | ||
| 269 | /* 0x00cf: wait_donez_ne */ | ||
| 270 | 0x8804bd00, | ||
| 271 | 0xcf010000, | ||
| 272 | 0x8aff0088, | ||
| 273 | 0xf61bf488, | ||
| 274 | 0x99f094bd, | ||
| 275 | 0x17008000, | ||
| 276 | 0x0009f602, | ||
| 277 | 0x00f804bd, | ||
| 278 | /* 0x00ec: wait_doneo */ | ||
| 279 | 0x99f094bd, | ||
| 280 | 0x37008000, | ||
| 281 | 0x0009f602, | ||
| 282 | 0x008004bd, | ||
| 283 | 0x0af60206, | ||
| 284 | /* 0x0103: wait_doneo_e */ | ||
| 285 | 0x8804bd00, | ||
| 286 | 0xcf010000, | ||
| 287 | 0x8aff0088, | ||
| 288 | 0xf60bf488, | ||
| 289 | 0x99f094bd, | ||
| 290 | 0x17008000, | ||
| 291 | 0x0009f602, | ||
| 292 | 0x00f804bd, | ||
| 293 | /* 0x0120: mmctx_size */ | ||
| 294 | /* 0x0122: nv_mmctx_size_loop */ | ||
| 295 | 0xe89894bd, | ||
| 296 | 0x1a85b600, | ||
| 297 | 0xb60180b6, | ||
| 298 | 0x98bb0284, | ||
| 299 | 0x04e0b600, | ||
| 300 | 0x1bf4efa4, | ||
| 301 | 0xf89fb2ec, | ||
| 302 | /* 0x013d: mmctx_xfer */ | ||
| 303 | 0xf094bd00, | ||
| 304 | 0x00800199, | ||
| 305 | 0x09f60237, | ||
| 306 | 0xbd04bd00, | ||
| 307 | 0x05bbfd94, | ||
| 308 | 0x800f0bf4, | ||
| 309 | 0xf601c400, | ||
| 310 | 0x04bd000b, | ||
| 311 | /* 0x015f: mmctx_base_disabled */ | ||
| 312 | 0xfd0099f0, | ||
| 313 | 0x0bf405ee, | ||
| 314 | 0xc6008018, | ||
| 315 | 0x000ef601, | ||
| 316 | 0x008004bd, | ||
| 317 | 0x0ff601c7, | ||
| 318 | 0xf004bd00, | ||
| 319 | /* 0x017a: mmctx_multi_disabled */ | ||
| 320 | 0xabc80199, | ||
| 321 | 0x10b4b600, | ||
| 322 | 0xc80cb9f0, | ||
| 323 | 0xe4b601ae, | ||
| 324 | 0x05befd11, | ||
| 325 | 0x01c50080, | ||
| 326 | 0xbd000bf6, | ||
| 327 | /* 0x0195: mmctx_exec_loop */ | ||
| 328 | /* 0x0195: mmctx_wait_free */ | ||
| 329 | 0xc5008e04, | ||
| 330 | 0x00eecf01, | ||
| 331 | 0xf41fe4f0, | ||
| 332 | 0xce98f60b, | ||
| 333 | 0x05e9fd00, | ||
| 334 | 0x01c80080, | ||
| 335 | 0xbd000ef6, | ||
| 336 | 0x04c0b604, | ||
| 337 | 0x1bf4cda4, | ||
| 338 | 0x02abc8df, | ||
| 339 | /* 0x01bf: mmctx_fini_wait */ | ||
| 340 | 0x8b1c1bf4, | ||
| 341 | 0xcf01c500, | ||
| 342 | 0xb4f000bb, | ||
| 343 | 0x10b4b01f, | ||
| 344 | 0x0af31bf4, | ||
| 345 | 0x00b87e02, | ||
| 346 | 0x250ef400, | ||
| 347 | /* 0x01d8: mmctx_stop */ | ||
| 348 | 0xb600abc8, | ||
| 349 | 0xb9f010b4, | ||
| 350 | 0x12b9f00c, | ||
| 351 | 0x01c50080, | ||
| 352 | 0xbd000bf6, | ||
| 353 | /* 0x01ed: mmctx_stop_wait */ | ||
| 354 | 0xc5008b04, | ||
| 355 | 0x00bbcf01, | ||
| 356 | 0xf412bbc8, | ||
| 357 | /* 0x01fa: mmctx_done */ | ||
| 358 | 0x94bdf61b, | ||
| 359 | 0x800199f0, | ||
| 360 | 0xf6021700, | ||
| 361 | 0x04bd0009, | ||
| 362 | /* 0x020a: strand_wait */ | ||
| 363 | 0xa0f900f8, | ||
| 364 | 0xb87e020a, | ||
| 365 | 0xa0fc0000, | ||
| 366 | /* 0x0216: strand_pre */ | ||
| 367 | 0x0c0900f8, | ||
| 368 | 0x024afc80, | ||
| 369 | 0xbd0009f6, | ||
| 370 | 0x020a7e04, | ||
| 371 | /* 0x0227: strand_post */ | ||
| 372 | 0x0900f800, | ||
| 373 | 0x4afc800d, | ||
| 374 | 0x0009f602, | ||
| 375 | 0x0a7e04bd, | ||
| 376 | 0x00f80002, | ||
| 377 | /* 0x0238: strand_set */ | ||
| 378 | 0xfc800f0c, | ||
| 379 | 0x0cf6024f, | ||
| 380 | 0x0c04bd00, | ||
| 381 | 0x4afc800b, | ||
| 382 | 0x000cf602, | ||
| 383 | 0xfc8004bd, | ||
| 384 | 0x0ef6024f, | ||
| 385 | 0x0c04bd00, | ||
| 386 | 0x4afc800a, | ||
| 387 | 0x000cf602, | ||
| 388 | 0x0a7e04bd, | ||
| 389 | 0x00f80002, | ||
| 390 | /* 0x0268: strand_ctx_init */ | ||
| 391 | 0x99f094bd, | ||
| 392 | 0x37008003, | ||
| 393 | 0x0009f602, | ||
| 394 | 0x167e04bd, | ||
| 395 | 0x030e0002, | ||
| 396 | 0x0002387e, | ||
| 397 | 0xfc80c4bd, | ||
| 398 | 0x0cf60247, | ||
| 399 | 0x0c04bd00, | ||
| 400 | 0x4afc8001, | ||
| 401 | 0x000cf602, | ||
| 402 | 0x0a7e04bd, | ||
| 403 | 0x0c920002, | ||
| 404 | 0x46fc8001, | ||
| 405 | 0x000cf602, | ||
| 406 | 0x020c04bd, | ||
| 407 | 0x024afc80, | ||
| 408 | 0xbd000cf6, | ||
| 409 | 0x020a7e04, | ||
| 410 | 0x02277e00, | ||
| 411 | 0x42008800, | ||
| 412 | 0x20008902, | ||
| 413 | 0x0099cf02, | ||
| 414 | /* 0x02c7: ctx_init_strand_loop */ | ||
| 415 | 0xf608fe95, | ||
| 416 | 0x8ef6008e, | ||
| 417 | 0x808acf40, | ||
| 418 | 0xb606a5b6, | ||
| 419 | 0xeabb01a0, | ||
| 420 | 0x0480b600, | ||
| 421 | 0xf40192b6, | ||
| 422 | 0xe4b6e81b, | ||
| 423 | 0xf2efbc08, | ||
| 424 | 0x99f094bd, | ||
| 425 | 0x17008003, | ||
| 426 | 0x0009f602, | ||
| 427 | 0x00f804bd, | ||
| 428 | /* 0x02f8: error */ | ||
| 429 | 0x02050080, | ||
| 430 | 0xbd000ff6, | ||
| 431 | 0x80010f04, | ||
| 432 | 0xf6030700, | ||
| 433 | 0x04bd000f, | ||
| 434 | /* 0x030e: init */ | ||
| 435 | 0x04bd00f8, | ||
| 436 | 0x410007fe, | ||
| 437 | 0x11cf4200, | ||
| 438 | 0x0911e700, | ||
| 439 | 0x0814b601, | ||
| 440 | 0x020014fe, | ||
| 441 | 0x12004002, | ||
| 442 | 0xbd0002f6, | ||
| 443 | 0x05c94104, | ||
| 444 | 0xbd0010fe, | ||
| 445 | 0x07004024, | ||
| 446 | 0xbd0002f6, | ||
| 447 | 0x20034204, | ||
| 448 | 0x01010080, | ||
| 449 | 0xbd0002f6, | ||
| 450 | 0x20044204, | ||
| 451 | 0x01010480, | ||
| 452 | 0xbd0002f6, | ||
| 453 | 0x200b4204, | ||
| 454 | 0x01010880, | ||
| 455 | 0xbd0002f6, | ||
| 456 | 0x200c4204, | ||
| 457 | 0x01011c80, | ||
| 458 | 0xbd0002f6, | ||
| 459 | 0x01039204, | ||
| 460 | 0x03090080, | ||
| 461 | 0xbd0003f6, | ||
| 462 | 0x87044204, | ||
| 463 | 0xf6040040, | ||
| 464 | 0x04bd0002, | ||
| 465 | 0x00400402, | ||
| 466 | 0x0002f603, | ||
| 467 | 0x31f404bd, | ||
| 468 | 0x96048e10, | ||
| 469 | 0x00657e40, | ||
| 470 | 0xc7feb200, | ||
| 471 | 0x01b590f1, | ||
| 472 | 0x1ff4f003, | ||
| 473 | 0x01020fb5, | ||
| 474 | 0x041fbb01, | ||
| 475 | 0x800112b6, | ||
| 476 | 0xf6010300, | ||
| 477 | 0x04bd0001, | ||
| 478 | 0x01040080, | ||
| 479 | 0xbd0001f6, | ||
| 480 | 0x01004104, | ||
| 481 | 0x627e020f, | ||
| 482 | 0x717e0006, | ||
| 483 | 0x100f0006, | ||
| 484 | 0x0006b37e, | ||
| 485 | 0x98000e98, | ||
| 486 | 0x207e010f, | ||
| 487 | 0x14950001, | ||
| 488 | 0xc0008008, | ||
| 489 | 0x0004f601, | ||
| 490 | 0x008004bd, | ||
| 491 | 0x04f601c1, | ||
| 492 | 0xb704bd00, | ||
| 493 | 0xbb130030, | ||
| 494 | 0xf5b6001f, | ||
| 495 | 0xd3008002, | ||
| 496 | 0x000ff601, | ||
| 497 | 0x15b604bd, | ||
| 498 | 0x0110b608, | ||
| 499 | 0xb20814b6, | ||
| 500 | 0x02687e1f, | ||
| 501 | 0x001fbb00, | ||
| 502 | 0x84020398, | ||
| 503 | /* 0x041f: init_gpc */ | ||
| 504 | 0xb8502000, | ||
| 505 | 0x0008044e, | ||
| 506 | 0x8f7e1fb2, | ||
| 507 | 0x4eb80000, | ||
| 508 | 0xbd00010c, | ||
| 509 | 0x008f7ef4, | ||
| 510 | 0x044eb800, | ||
| 511 | 0x8f7e0001, | ||
| 512 | 0x4eb80000, | ||
| 513 | 0x0f000100, | ||
| 514 | 0x008f7e02, | ||
| 515 | 0x004eb800, | ||
| 516 | /* 0x044e: init_gpc_wait */ | ||
| 517 | 0x657e0008, | ||
| 518 | 0xffc80000, | ||
| 519 | 0xf90bf41f, | ||
| 520 | 0x08044eb8, | ||
| 521 | 0x00657e00, | ||
| 522 | 0x001fbb00, | ||
| 523 | 0x800040b7, | ||
| 524 | 0xf40132b6, | ||
| 525 | 0x000fb41b, | ||
| 526 | 0x0006b37e, | ||
| 527 | 0x627e000f, | ||
| 528 | 0x00800006, | ||
| 529 | 0x01f60201, | ||
| 530 | 0xbd04bd00, | ||
| 531 | 0x1f19f014, | ||
| 532 | 0x02300080, | ||
| 533 | 0xbd0001f6, | ||
| 534 | /* 0x0491: main */ | ||
| 535 | 0x0031f404, | ||
| 536 | 0x0d0028f4, | ||
| 537 | 0x00377e10, | ||
| 538 | 0xf401f400, | ||
| 539 | 0x4001e4b1, | ||
| 540 | 0x00c71bf5, | ||
| 541 | 0x99f094bd, | ||
| 542 | 0x37008004, | ||
| 543 | 0x0009f602, | ||
| 544 | 0x008104bd, | ||
| 545 | 0x11cf02c0, | ||
| 546 | 0xc1008200, | ||
| 547 | 0x0022cf02, | ||
| 548 | 0xf41f13c8, | ||
| 549 | 0x23c8770b, | ||
| 550 | 0x550bf41f, | ||
| 551 | 0x12b220f9, | ||
| 552 | 0x99f094bd, | ||
| 553 | 0x37008007, | ||
| 554 | 0x0009f602, | ||
| 555 | 0x32f404bd, | ||
| 556 | 0x0231f401, | ||
| 557 | 0x0008367e, | ||
| 558 | 0x99f094bd, | ||
| 559 | 0x17008007, | ||
| 560 | 0x0009f602, | ||
| 561 | 0x20fc04bd, | ||
| 562 | 0x99f094bd, | ||
| 563 | 0x37008006, | ||
| 564 | 0x0009f602, | ||
| 565 | 0x31f404bd, | ||
| 566 | 0x08367e01, | ||
| 567 | 0xf094bd00, | ||
| 568 | 0x00800699, | ||
| 569 | 0x09f60217, | ||
| 570 | 0xf404bd00, | ||
| 571 | /* 0x0522: chsw_prev_no_next */ | ||
| 572 | 0x20f92f0e, | ||
| 573 | 0x32f412b2, | ||
| 574 | 0x0232f401, | ||
| 575 | 0x0008367e, | ||
| 576 | 0x008020fc, | ||
| 577 | 0x02f602c0, | ||
| 578 | 0xf404bd00, | ||
| 579 | /* 0x053e: chsw_no_prev */ | ||
| 580 | 0x23c8130e, | ||
| 581 | 0x0d0bf41f, | ||
| 582 | 0xf40131f4, | ||
| 583 | 0x367e0232, | ||
| 584 | /* 0x054e: chsw_done */ | ||
| 585 | 0x01020008, | ||
| 586 | 0x02c30080, | ||
| 587 | 0xbd0002f6, | ||
| 588 | 0xf094bd04, | ||
| 589 | 0x00800499, | ||
| 590 | 0x09f60217, | ||
| 591 | 0xf504bd00, | ||
| 592 | /* 0x056b: main_not_ctx_switch */ | ||
| 593 | 0xb0ff2a0e, | ||
| 594 | 0x1bf401e4, | ||
| 595 | 0x7ef2b20c, | ||
| 596 | 0xf40007d6, | ||
| 597 | /* 0x057a: main_not_ctx_chan */ | ||
| 598 | 0xe4b0400e, | ||
| 599 | 0x2c1bf402, | ||
| 600 | 0x99f094bd, | ||
| 601 | 0x37008007, | ||
| 602 | 0x0009f602, | ||
| 603 | 0x32f404bd, | ||
| 604 | 0x0232f401, | ||
| 605 | 0x0008367e, | ||
| 606 | 0x99f094bd, | ||
| 607 | 0x17008007, | ||
| 608 | 0x0009f602, | ||
| 609 | 0x0ef404bd, | ||
| 610 | /* 0x05a9: main_not_ctx_save */ | ||
| 611 | 0x10ef9411, | ||
| 612 | 0x7e01f5f0, | ||
| 613 | 0xf50002f8, | ||
| 614 | /* 0x05b7: main_done */ | ||
| 615 | 0xbdfede0e, | ||
| 616 | 0x1f29f024, | ||
| 617 | 0x02300080, | ||
| 618 | 0xbd0002f6, | ||
| 619 | 0xcc0ef504, | ||
| 620 | /* 0x05c9: ih */ | ||
| 621 | 0xfe80f9fe, | ||
| 622 | 0x80f90188, | ||
| 623 | 0xa0f990f9, | ||
| 624 | 0xd0f9b0f9, | ||
| 625 | 0xf0f9e0f9, | ||
| 626 | 0x004a04bd, | ||
| 627 | 0x00aacf02, | ||
| 628 | 0xf404abc4, | ||
| 629 | 0x100d230b, | ||
| 630 | 0xcf1a004e, | ||
| 631 | 0x004f00ee, | ||
| 632 | 0x00ffcf19, | ||
| 633 | 0x0000047e, | ||
| 634 | 0x0400b0b7, | ||
| 635 | 0x0040010e, | ||
| 636 | 0x000ef61d, | ||
| 637 | /* 0x060a: ih_no_fifo */ | ||
| 638 | 0xabe404bd, | ||
| 639 | 0x0bf40100, | ||
| 640 | 0x4e100d0c, | ||
| 641 | 0x047e4001, | ||
| 642 | /* 0x061a: ih_no_ctxsw */ | ||
| 643 | 0xabe40000, | ||
| 644 | 0x0bf40400, | ||
| 645 | 0x01004b10, | ||
| 646 | 0x448ebfb2, | ||
| 647 | 0x8f7e4001, | ||
| 648 | /* 0x062e: ih_no_fwmthd */ | ||
| 649 | 0x044b0000, | ||
| 650 | 0xffb0bd01, | ||
| 651 | 0x0bf4b4ab, | ||
| 652 | 0x0700800c, | ||
| 653 | 0x000bf603, | ||
| 654 | /* 0x0642: ih_no_other */ | ||
| 655 | 0x004004bd, | ||
| 656 | 0x000af601, | ||
| 657 | 0xf0fc04bd, | ||
| 658 | 0xd0fce0fc, | ||
| 659 | 0xa0fcb0fc, | ||
| 660 | 0x80fc90fc, | ||
| 661 | 0xfc0088fe, | ||
| 662 | 0x0032f480, | ||
| 663 | /* 0x0662: ctx_4170s */ | ||
| 664 | 0xf5f001f8, | ||
| 665 | 0x8effb210, | ||
| 666 | 0x7e404170, | ||
| 667 | 0xf800008f, | ||
| 668 | /* 0x0671: ctx_4170w */ | ||
| 669 | 0x41708e00, | ||
| 670 | 0x00657e40, | ||
| 671 | 0xf0ffb200, | ||
| 672 | 0x1bf410f4, | ||
| 673 | /* 0x0683: ctx_redswitch */ | ||
| 674 | 0x4e00f8f3, | ||
| 675 | 0xe5f00200, | ||
| 676 | 0x20e5f040, | ||
| 677 | 0x8010e5f0, | ||
| 678 | 0xf6018500, | ||
| 679 | 0x04bd000e, | ||
| 680 | /* 0x069a: ctx_redswitch_delay */ | ||
| 681 | 0xf2b6080f, | ||
| 682 | 0xfd1bf401, | ||
| 683 | 0x0400e5f1, | ||
| 684 | 0x0100e5f1, | ||
| 685 | 0x01850080, | ||
| 686 | 0xbd000ef6, | ||
| 687 | /* 0x06b3: ctx_86c */ | ||
| 688 | 0x8000f804, | ||
| 689 | 0xf6022300, | ||
| 690 | 0x04bd000f, | ||
| 691 | 0x148effb2, | ||
| 692 | 0x8f7e408a, | ||
| 693 | 0xffb20000, | ||
| 694 | 0x41a88c8e, | ||
| 695 | 0x00008f7e, | ||
| 696 | /* 0x06d2: ctx_mem */ | ||
| 697 | 0x008000f8, | ||
| 698 | 0x0ff60284, | ||
| 699 | /* 0x06db: ctx_mem_wait */ | ||
| 700 | 0x8f04bd00, | ||
| 701 | 0xcf028400, | ||
| 702 | 0xfffd00ff, | ||
| 703 | 0xf61bf405, | ||
| 704 | /* 0x06ea: ctx_load */ | ||
| 705 | 0x94bd00f8, | ||
| 706 | 0x800599f0, | ||
| 707 | 0xf6023700, | ||
| 708 | 0x04bd0009, | ||
| 709 | 0xb87e0c0a, | ||
| 710 | 0xf4bd0000, | ||
| 711 | 0x02890080, | ||
| 712 | 0xbd000ff6, | ||
| 713 | 0xc1008004, | ||
| 714 | 0x0002f602, | ||
| 715 | 0x008004bd, | ||
| 716 | 0x02f60283, | ||
| 717 | 0x0f04bd00, | ||
| 718 | 0x06d27e07, | ||
| 719 | 0xc0008000, | ||
| 720 | 0x0002f602, | ||
| 721 | 0x0bfe04bd, | ||
| 722 | 0x1f2af000, | ||
| 723 | 0xb60424b6, | ||
| 724 | 0x94bd0220, | ||
| 725 | 0x800899f0, | ||
| 726 | 0xf6023700, | ||
| 727 | 0x04bd0009, | ||
| 728 | 0x02810080, | ||
| 729 | 0xbd0002f6, | ||
| 730 | 0x0000d204, | ||
| 731 | 0x25f08000, | ||
| 732 | 0x88008002, | ||
| 733 | 0x0002f602, | ||
| 734 | 0x100104bd, | ||
| 735 | 0xf0020042, | ||
| 736 | 0x12fa0223, | ||
| 737 | 0xbd03f805, | ||
| 738 | 0x0899f094, | ||
| 739 | 0x02170080, | ||
| 740 | 0xbd0009f6, | ||
| 741 | 0x81019804, | ||
| 742 | 0x981814b6, | ||
| 743 | 0x25b68002, | ||
| 744 | 0x0512fd08, | ||
| 745 | 0xbd1601b5, | ||
| 746 | 0x0999f094, | ||
| 747 | 0x02370080, | ||
| 748 | 0xbd0009f6, | ||
| 749 | 0x81008004, | ||
| 750 | 0x0001f602, | ||
| 751 | 0x010204bd, | ||
| 752 | 0x02880080, | ||
| 753 | 0xbd0002f6, | ||
| 754 | 0x01004104, | ||
| 755 | 0xfa0613f0, | ||
| 756 | 0x03f80501, | ||
| 757 | 0x99f094bd, | ||
| 758 | 0x17008009, | ||
| 759 | 0x0009f602, | ||
| 760 | 0x94bd04bd, | ||
| 761 | 0x800599f0, | ||
| 762 | 0xf6021700, | ||
| 763 | 0x04bd0009, | ||
| 764 | /* 0x07d6: ctx_chan */ | ||
| 765 | 0xea7e00f8, | ||
| 766 | 0x0c0a0006, | ||
| 767 | 0x0000b87e, | ||
| 768 | 0xd27e050f, | ||
| 769 | 0x00f80006, | ||
| 770 | /* 0x07e8: ctx_mmio_exec */ | ||
| 771 | 0x80410398, | ||
| 772 | 0xf6028100, | ||
| 773 | 0x04bd0003, | ||
| 774 | /* 0x07f6: ctx_mmio_loop */ | ||
| 775 | 0x34c434bd, | ||
| 776 | 0x0e1bf4ff, | ||
| 777 | 0xf0020045, | ||
| 778 | 0x35fa0653, | ||
| 779 | /* 0x0807: ctx_mmio_pull */ | ||
| 780 | 0x9803f805, | ||
| 781 | 0x4f98804e, | ||
| 782 | 0x008f7e81, | ||
| 783 | 0x0830b600, | ||
| 784 | 0xf40112b6, | ||
| 785 | /* 0x081a: ctx_mmio_done */ | ||
| 786 | 0x0398df1b, | ||
| 787 | 0x81008016, | ||
| 788 | 0x0003f602, | ||
| 789 | 0x00b504bd, | ||
| 790 | 0x01004140, | ||
| 791 | 0xfa0613f0, | ||
| 792 | 0x03f80601, | ||
| 793 | /* 0x0836: ctx_xfer */ | ||
| 794 | 0x040e00f8, | ||
| 795 | 0x03020080, | ||
| 796 | 0xbd000ef6, | ||
| 797 | /* 0x0841: ctx_xfer_idle */ | ||
| 798 | 0x00008e04, | ||
| 799 | 0x00eecf03, | ||
| 800 | 0x2000e4f1, | ||
| 801 | 0xf4f51bf4, | ||
| 802 | 0x02f40611, | ||
| 803 | /* 0x0855: ctx_xfer_pre */ | ||
| 804 | 0x7e100f0c, | ||
| 805 | 0xf40006b3, | ||
| 806 | /* 0x085e: ctx_xfer_pre_load */ | ||
| 807 | 0x020f1b11, | ||
| 808 | 0x0006627e, | ||
| 809 | 0x0006717e, | ||
| 810 | 0x0006837e, | ||
| 811 | 0x627ef4bd, | ||
| 812 | 0xea7e0006, | ||
| 813 | /* 0x0876: ctx_xfer_exec */ | ||
| 814 | 0x01980006, | ||
| 815 | 0x8024bd16, | ||
| 816 | 0xf6010500, | ||
| 817 | 0x04bd0002, | ||
| 818 | 0x008e1fb2, | ||
| 819 | 0x8f7e41a5, | ||
| 820 | 0xfcf00000, | ||
| 821 | 0x022cf001, | ||
| 822 | 0xfd0124b6, | ||
| 823 | 0xffb205f2, | ||
| 824 | 0x41a5048e, | ||
| 825 | 0x00008f7e, | ||
| 826 | 0x0002167e, | ||
| 827 | 0xfc8024bd, | ||
| 828 | 0x02f60247, | ||
| 829 | 0xf004bd00, | ||
| 830 | 0x20b6012c, | ||
| 831 | 0x4afc8003, | ||
| 832 | 0x0002f602, | ||
| 833 | 0xacf004bd, | ||
| 834 | 0x06a5f001, | ||
| 835 | 0x0c98000b, | ||
| 836 | 0x010d9800, | ||
| 837 | 0x3d7e000e, | ||
| 838 | 0x080a0001, | ||
| 839 | 0x0000ec7e, | ||
| 840 | 0x00020a7e, | ||
| 841 | 0x0a1201f4, | ||
| 842 | 0x00b87e0c, | ||
| 843 | 0x7e050f00, | ||
| 844 | 0xf40006d2, | ||
| 845 | /* 0x08f2: ctx_xfer_post */ | ||
| 846 | 0x020f2d02, | ||
| 847 | 0x0006627e, | ||
| 848 | 0xb37ef4bd, | ||
| 849 | 0x277e0006, | ||
| 850 | 0x717e0002, | ||
| 851 | 0xf4bd0006, | ||
| 852 | 0x0006627e, | ||
| 853 | 0x981011f4, | ||
| 854 | 0x11fd4001, | ||
| 855 | 0x070bf405, | ||
| 856 | 0x0007e87e, | ||
| 857 | /* 0x091c: ctx_xfer_no_post_mmio */ | ||
| 858 | /* 0x091c: ctx_xfer_done */ | ||
| 859 | 0x000000f8, | ||
| 860 | 0x00000000, | ||
| 861 | 0x00000000, | ||
| 862 | 0x00000000, | ||
| 863 | 0x00000000, | ||
| 864 | 0x00000000, | ||
| 865 | 0x00000000, | ||
| 866 | 0x00000000, | ||
| 867 | 0x00000000, | ||
| 868 | 0x00000000, | ||
| 869 | 0x00000000, | ||
| 870 | 0x00000000, | ||
| 871 | 0x00000000, | ||
| 872 | 0x00000000, | ||
| 873 | 0x00000000, | ||
| 874 | 0x00000000, | ||
| 875 | 0x00000000, | ||
| 876 | 0x00000000, | ||
| 877 | 0x00000000, | ||
| 878 | 0x00000000, | ||
| 879 | 0x00000000, | ||
| 880 | 0x00000000, | ||
| 881 | 0x00000000, | ||
| 882 | 0x00000000, | ||
| 883 | 0x00000000, | ||
| 884 | 0x00000000, | ||
| 885 | 0x00000000, | ||
| 886 | 0x00000000, | ||
| 887 | 0x00000000, | ||
| 888 | 0x00000000, | ||
| 889 | 0x00000000, | ||
| 890 | 0x00000000, | ||
| 891 | 0x00000000, | ||
| 892 | 0x00000000, | ||
| 893 | 0x00000000, | ||
| 894 | 0x00000000, | ||
| 895 | 0x00000000, | ||
| 896 | 0x00000000, | ||
| 897 | 0x00000000, | ||
| 898 | 0x00000000, | ||
| 899 | 0x00000000, | ||
| 900 | 0x00000000, | ||
| 901 | 0x00000000, | ||
| 902 | 0x00000000, | ||
| 903 | 0x00000000, | ||
| 904 | 0x00000000, | ||
| 905 | 0x00000000, | ||
| 906 | 0x00000000, | ||
| 907 | 0x00000000, | ||
| 908 | 0x00000000, | ||
| 909 | 0x00000000, | ||
| 910 | 0x00000000, | ||
| 911 | 0x00000000, | ||
| 912 | 0x00000000, | ||
| 913 | 0x00000000, | ||
| 914 | 0x00000000, | ||
| 915 | 0x00000000, | ||
| 916 | }; | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h index b59f694c0423..132f684b1946 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h | |||
| @@ -206,14 +206,14 @@ uint32_t nvc0_grhub_data[] = { | |||
| 206 | }; | 206 | }; |
| 207 | 207 | ||
| 208 | uint32_t nvc0_grhub_code[] = { | 208 | uint32_t nvc0_grhub_code[] = { |
| 209 | 0x031b0ef5, | 209 | 0x039b0ef5, |
| 210 | /* 0x0004: queue_put */ | 210 | /* 0x0004: queue_put */ |
| 211 | 0x9800d898, | 211 | 0x9800d898, |
| 212 | 0x86f001d9, | 212 | 0x86f001d9, |
| 213 | 0x0489b808, | 213 | 0x0489b808, |
| 214 | 0xf00c1bf4, | 214 | 0xf00c1bf4, |
| 215 | 0x21f502f7, | 215 | 0x21f502f7, |
| 216 | 0x00f802fe, | 216 | 0x00f8037e, |
| 217 | /* 0x001c: queue_put_next */ | 217 | /* 0x001c: queue_put_next */ |
| 218 | 0xb60798c4, | 218 | 0xb60798c4, |
| 219 | 0x8dbb0384, | 219 | 0x8dbb0384, |
| @@ -237,184 +237,214 @@ uint32_t nvc0_grhub_code[] = { | |||
| 237 | /* 0x0066: queue_get_done */ | 237 | /* 0x0066: queue_get_done */ |
| 238 | 0x00f80132, | 238 | 0x00f80132, |
| 239 | /* 0x0068: nv_rd32 */ | 239 | /* 0x0068: nv_rd32 */ |
| 240 | 0x0728b7f1, | 240 | 0xf002ecb9, |
| 241 | 0xb906b4b6, | 241 | 0x07f11fc9, |
| 242 | 0xc9f002ec, | 242 | 0x03f0ca00, |
| 243 | 0x00bcd01f, | 243 | 0x000cd001, |
| 244 | /* 0x0078: nv_rd32_wait */ | 244 | /* 0x007a: nv_rd32_wait */ |
| 245 | 0xc800bccf, | 245 | 0xc7f104bd, |
| 246 | 0x1bf41fcc, | 246 | 0xc3f0ca00, |
| 247 | 0x06a7f0fa, | 247 | 0x00cccf01, |
| 248 | 0x010921f5, | 248 | 0xf41fccc8, |
| 249 | 0xf840bfcf, | 249 | 0xa7f0f31b, |
| 250 | /* 0x008d: nv_wr32 */ | 250 | 0x1021f506, |
| 251 | 0x28b7f100, | 251 | 0x00f7f101, |
| 252 | 0x06b4b607, | 252 | 0x01f3f0cb, |
| 253 | 0xb980bfd0, | 253 | 0xf800ffcf, |
| 254 | 0xc9f002ec, | 254 | /* 0x009d: nv_wr32 */ |
| 255 | 0x1ec9f01f, | 255 | 0x0007f100, |
| 256 | /* 0x00a3: nv_wr32_wait */ | 256 | 0x0103f0cc, |
| 257 | 0xcf00bcd0, | 257 | 0xbd000fd0, |
| 258 | 0xccc800bc, | 258 | 0x02ecb904, |
| 259 | 0xfa1bf41f, | 259 | 0xf01fc9f0, |
| 260 | /* 0x00ae: watchdog_reset */ | 260 | 0x07f11ec9, |
| 261 | 0x87f100f8, | 261 | 0x03f0ca00, |
| 262 | 0x84b60430, | 262 | 0x000cd001, |
| 263 | 0x1ff9f006, | 263 | /* 0x00be: nv_wr32_wait */ |
| 264 | 0xf8008fd0, | 264 | 0xc7f104bd, |
| 265 | /* 0x00bd: watchdog_clear */ | 265 | 0xc3f0ca00, |
| 266 | 0x3087f100, | 266 | 0x00cccf01, |
| 267 | 0x0684b604, | 267 | 0xf41fccc8, |
| 268 | 0xf80080d0, | 268 | 0x00f8f31b, |
| 269 | /* 0x00c9: wait_donez */ | 269 | /* 0x00d0: wait_donez */ |
| 270 | 0xf094bd00, | 270 | 0x99f094bd, |
| 271 | 0x07f10099, | 271 | 0x0007f100, |
| 272 | 0x03f00f00, | 272 | 0x0203f00f, |
| 273 | 0x0009d002, | 273 | 0xbd0009d0, |
| 274 | 0x07f104bd, | 274 | 0x0007f104, |
| 275 | 0x03f00600, | 275 | 0x0203f006, |
| 276 | 0x000ad002, | 276 | 0xbd000ad0, |
| 277 | /* 0x00e6: wait_donez_ne */ | 277 | /* 0x00ed: wait_donez_ne */ |
| 278 | 0x87f104bd, | 278 | 0x0087f104, |
| 279 | 0x83f00000, | 279 | 0x0183f000, |
| 280 | 0x0088cf01, | 280 | 0xff0088cf, |
| 281 | 0xf4888aff, | 281 | 0x1bf4888a, |
| 282 | 0x94bdf31b, | 282 | 0xf094bdf3, |
| 283 | 0xf10099f0, | ||
| 284 | 0xf0170007, | ||
| 285 | 0x09d00203, | ||
| 286 | 0xf804bd00, | ||
| 287 | /* 0x0109: wait_doneo */ | ||
| 288 | 0xf094bd00, | ||
| 289 | 0x07f10099, | 283 | 0x07f10099, |
| 290 | 0x03f00f00, | 284 | 0x03f01700, |
| 291 | 0x0009d002, | 285 | 0x0009d002, |
| 292 | 0x87f104bd, | 286 | 0x00f804bd, |
| 293 | 0x84b60818, | 287 | /* 0x0110: wait_doneo */ |
| 294 | 0x008ad006, | ||
| 295 | /* 0x0124: wait_doneo_e */ | ||
| 296 | 0x040087f1, | ||
| 297 | 0xcf0684b6, | ||
| 298 | 0x8aff0088, | ||
| 299 | 0xf30bf488, | ||
| 300 | 0x99f094bd, | 288 | 0x99f094bd, |
| 301 | 0x0007f100, | 289 | 0x0007f100, |
| 302 | 0x0203f017, | 290 | 0x0203f00f, |
| 303 | 0xbd0009d0, | 291 | 0xbd0009d0, |
| 304 | /* 0x0147: mmctx_size */ | 292 | 0x0007f104, |
| 305 | 0xbd00f804, | 293 | 0x0203f006, |
| 306 | /* 0x0149: nv_mmctx_size_loop */ | 294 | 0xbd000ad0, |
| 307 | 0x00e89894, | 295 | /* 0x012d: wait_doneo_e */ |
| 308 | 0xb61a85b6, | 296 | 0x0087f104, |
| 309 | 0x84b60180, | 297 | 0x0183f000, |
| 310 | 0x0098bb02, | 298 | 0xff0088cf, |
| 311 | 0xb804e0b6, | 299 | 0x0bf4888a, |
| 312 | 0x1bf404ef, | 300 | 0xf094bdf3, |
| 313 | 0x029fb9eb, | 301 | 0x07f10099, |
| 314 | /* 0x0166: mmctx_xfer */ | 302 | 0x03f01700, |
| 315 | 0x94bd00f8, | 303 | 0x0009d002, |
| 316 | 0xf10199f0, | 304 | 0x00f804bd, |
| 317 | 0xf00f0007, | 305 | /* 0x0150: mmctx_size */ |
| 318 | 0x09d00203, | 306 | /* 0x0152: nv_mmctx_size_loop */ |
| 319 | 0xf104bd00, | 307 | 0xe89894bd, |
| 320 | 0xb6071087, | 308 | 0x1a85b600, |
| 321 | 0x94bd0684, | 309 | 0xb60180b6, |
| 322 | 0xf405bbfd, | 310 | 0x98bb0284, |
| 323 | 0x8bd0090b, | 311 | 0x04e0b600, |
| 324 | 0x0099f000, | 312 | 0xf404efb8, |
| 325 | /* 0x018c: mmctx_base_disabled */ | 313 | 0x9fb9eb1b, |
| 326 | 0xf405eefd, | 314 | /* 0x016f: mmctx_xfer */ |
| 327 | 0x8ed00c0b, | 315 | 0xbd00f802, |
| 328 | 0xc08fd080, | 316 | 0x0199f094, |
| 329 | /* 0x019b: mmctx_multi_disabled */ | 317 | 0x0f0007f1, |
| 330 | 0xb70199f0, | 318 | 0xd00203f0, |
| 331 | 0xc8010080, | 319 | 0x04bd0009, |
| 320 | 0xbbfd94bd, | ||
| 321 | 0x120bf405, | ||
| 322 | 0xc40007f1, | ||
| 323 | 0xd00103f0, | ||
| 324 | 0x04bd000b, | ||
| 325 | /* 0x0197: mmctx_base_disabled */ | ||
| 326 | 0xfd0099f0, | ||
| 327 | 0x0bf405ee, | ||
| 328 | 0x0007f11e, | ||
| 329 | 0x0103f0c6, | ||
| 330 | 0xbd000ed0, | ||
| 331 | 0x0007f104, | ||
| 332 | 0x0103f0c7, | ||
| 333 | 0xbd000fd0, | ||
| 334 | 0x0199f004, | ||
| 335 | /* 0x01b8: mmctx_multi_disabled */ | ||
| 336 | 0xb600abc8, | ||
| 337 | 0xb9f010b4, | ||
| 338 | 0x01aec80c, | ||
| 339 | 0xfd11e4b6, | ||
| 340 | 0x07f105be, | ||
| 341 | 0x03f0c500, | ||
| 342 | 0x000bd001, | ||
| 343 | /* 0x01d6: mmctx_exec_loop */ | ||
| 344 | /* 0x01d6: mmctx_wait_free */ | ||
| 345 | 0xe7f104bd, | ||
| 346 | 0xe3f0c500, | ||
| 347 | 0x00eecf01, | ||
| 348 | 0xf41fe4f0, | ||
| 349 | 0xce98f30b, | ||
| 350 | 0x05e9fd00, | ||
| 351 | 0xc80007f1, | ||
| 352 | 0xd00103f0, | ||
| 353 | 0x04bd000e, | ||
| 354 | 0xb804c0b6, | ||
| 355 | 0x1bf404cd, | ||
| 356 | 0x02abc8d8, | ||
| 357 | /* 0x0207: mmctx_fini_wait */ | ||
| 358 | 0xf11f1bf4, | ||
| 359 | 0xf0c500b7, | ||
| 360 | 0xbbcf01b3, | ||
| 361 | 0x1fb4f000, | ||
| 362 | 0xf410b4b0, | ||
| 363 | 0xa7f0f01b, | ||
| 364 | 0xd021f402, | ||
| 365 | /* 0x0223: mmctx_stop */ | ||
| 366 | 0xc82b0ef4, | ||
| 332 | 0xb4b600ab, | 367 | 0xb4b600ab, |
| 333 | 0x0cb9f010, | 368 | 0x0cb9f010, |
| 334 | 0xb601aec8, | 369 | 0xf112b9f0, |
| 335 | 0xbefd11e4, | 370 | 0xf0c50007, |
| 336 | 0x008bd005, | 371 | 0x0bd00103, |
| 337 | /* 0x01b4: mmctx_exec_loop */ | 372 | /* 0x023b: mmctx_stop_wait */ |
| 338 | /* 0x01b4: mmctx_wait_free */ | 373 | 0xf104bd00, |
| 339 | 0xf0008ecf, | 374 | 0xf0c500b7, |
| 340 | 0x0bf41fe4, | 375 | 0xbbcf01b3, |
| 341 | 0x00ce98fa, | 376 | 0x12bbc800, |
| 342 | 0xd005e9fd, | 377 | /* 0x024b: mmctx_done */ |
| 343 | 0xc0b6c08e, | 378 | 0xbdf31bf4, |
| 344 | 0x04cdb804, | 379 | 0x0199f094, |
| 345 | 0xc8e81bf4, | 380 | 0x170007f1, |
| 346 | 0x1bf402ab, | 381 | 0xd00203f0, |
| 347 | /* 0x01d5: mmctx_fini_wait */ | 382 | 0x04bd0009, |
| 348 | 0x008bcf18, | 383 | /* 0x025e: strand_wait */ |
| 349 | 0xb01fb4f0, | 384 | 0xa0f900f8, |
| 350 | 0x1bf410b4, | 385 | 0xf402a7f0, |
| 351 | 0x02a7f0f7, | 386 | 0xa0fcd021, |
| 352 | 0xf4c921f4, | 387 | /* 0x026a: strand_pre */ |
| 353 | /* 0x01ea: mmctx_stop */ | 388 | 0x97f000f8, |
| 354 | 0xabc81b0e, | 389 | 0xfc07f10c, |
| 355 | 0x10b4b600, | 390 | 0x0203f04a, |
| 356 | 0xf00cb9f0, | 391 | 0xbd0009d0, |
| 357 | 0x8bd012b9, | 392 | 0x5e21f504, |
| 358 | /* 0x01f9: mmctx_stop_wait */ | 393 | /* 0x027f: strand_post */ |
| 359 | 0x008bcf00, | 394 | 0xf000f802, |
| 360 | 0xf412bbc8, | 395 | 0x07f10d97, |
| 361 | /* 0x0202: mmctx_done */ | 396 | 0x03f04afc, |
| 362 | 0x94bdfa1b, | ||
| 363 | 0xf10199f0, | ||
| 364 | 0xf0170007, | ||
| 365 | 0x09d00203, | ||
| 366 | 0xf804bd00, | ||
| 367 | /* 0x0215: strand_wait */ | ||
| 368 | 0xf0a0f900, | ||
| 369 | 0x21f402a7, | ||
| 370 | 0xf8a0fcc9, | ||
| 371 | /* 0x0221: strand_pre */ | ||
| 372 | 0xfc87f100, | ||
| 373 | 0x0283f04a, | ||
| 374 | 0xd00c97f0, | ||
| 375 | 0x21f50089, | ||
| 376 | 0x00f80215, | ||
| 377 | /* 0x0234: strand_post */ | ||
| 378 | 0x4afc87f1, | ||
| 379 | 0xf00283f0, | ||
| 380 | 0x89d00d97, | ||
| 381 | 0x1521f500, | ||
| 382 | /* 0x0247: strand_set */ | ||
| 383 | 0xf100f802, | ||
| 384 | 0xf04ffca7, | ||
| 385 | 0xaba202a3, | ||
| 386 | 0xc7f00500, | ||
| 387 | 0x00acd00f, | ||
| 388 | 0xd00bc7f0, | ||
| 389 | 0x21f500bc, | ||
| 390 | 0xaed00215, | ||
| 391 | 0x0ac7f000, | ||
| 392 | 0xf500bcd0, | ||
| 393 | 0xf8021521, | ||
| 394 | /* 0x0271: strand_ctx_init */ | ||
| 395 | 0xf094bd00, | ||
| 396 | 0x07f10399, | ||
| 397 | 0x03f00f00, | ||
| 398 | 0x0009d002, | 397 | 0x0009d002, |
| 399 | 0x21f504bd, | 398 | 0x21f504bd, |
| 400 | 0xe7f00221, | 399 | 0x00f8025e, |
| 401 | 0x4721f503, | 400 | /* 0x0294: strand_set */ |
| 402 | 0xfca7f102, | 401 | 0xf10fc7f0, |
| 403 | 0x02a3f046, | 402 | 0xf04ffc07, |
| 404 | 0x0400aba0, | 403 | 0x0cd00203, |
| 405 | 0xf040a0d0, | 404 | 0xf004bd00, |
| 406 | 0xbcd001c7, | 405 | 0x07f10bc7, |
| 407 | 0x1521f500, | 406 | 0x03f04afc, |
| 408 | 0x010c9202, | 407 | 0x000cd002, |
| 409 | 0xf000acd0, | 408 | 0x07f104bd, |
| 410 | 0xbcd002c7, | 409 | 0x03f04ffc, |
| 411 | 0x1521f500, | 410 | 0x000ed002, |
| 412 | 0x3421f502, | 411 | 0xc7f004bd, |
| 413 | 0x8087f102, | 412 | 0xfc07f10a, |
| 414 | 0x0684b608, | 413 | 0x0203f04a, |
| 415 | 0xb70089cf, | 414 | 0xbd000cd0, |
| 416 | 0x95220080, | 415 | 0x5e21f504, |
| 417 | /* 0x02ca: ctx_init_strand_loop */ | 416 | /* 0x02d3: strand_ctx_init */ |
| 417 | 0xbd00f802, | ||
| 418 | 0x0399f094, | ||
| 419 | 0x0f0007f1, | ||
| 420 | 0xd00203f0, | ||
| 421 | 0x04bd0009, | ||
| 422 | 0x026a21f5, | ||
| 423 | 0xf503e7f0, | ||
| 424 | 0xbd029421, | ||
| 425 | 0xfc07f1c4, | ||
| 426 | 0x0203f047, | ||
| 427 | 0xbd000cd0, | ||
| 428 | 0x01c7f004, | ||
| 429 | 0x4afc07f1, | ||
| 430 | 0xd00203f0, | ||
| 431 | 0x04bd000c, | ||
| 432 | 0x025e21f5, | ||
| 433 | 0xf1010c92, | ||
| 434 | 0xf046fc07, | ||
| 435 | 0x0cd00203, | ||
| 436 | 0xf004bd00, | ||
| 437 | 0x07f102c7, | ||
| 438 | 0x03f04afc, | ||
| 439 | 0x000cd002, | ||
| 440 | 0x21f504bd, | ||
| 441 | 0x21f5025e, | ||
| 442 | 0x87f1027f, | ||
| 443 | 0x83f04200, | ||
| 444 | 0x0097f102, | ||
| 445 | 0x0293f020, | ||
| 446 | 0x950099cf, | ||
| 447 | /* 0x034a: ctx_init_strand_loop */ | ||
| 418 | 0x8ed008fe, | 448 | 0x8ed008fe, |
| 419 | 0x408ed000, | 449 | 0x408ed000, |
| 420 | 0xb6808acf, | 450 | 0xb6808acf, |
| @@ -428,7 +458,7 @@ uint32_t nvc0_grhub_code[] = { | |||
| 428 | 0x170007f1, | 458 | 0x170007f1, |
| 429 | 0xd00203f0, | 459 | 0xd00203f0, |
| 430 | 0x04bd0009, | 460 | 0x04bd0009, |
| 431 | /* 0x02fe: error */ | 461 | /* 0x037e: error */ |
| 432 | 0x07f100f8, | 462 | 0x07f100f8, |
| 433 | 0x03f00500, | 463 | 0x03f00500, |
| 434 | 0x000fd002, | 464 | 0x000fd002, |
| @@ -436,82 +466,117 @@ uint32_t nvc0_grhub_code[] = { | |||
| 436 | 0x0007f101, | 466 | 0x0007f101, |
| 437 | 0x0303f007, | 467 | 0x0303f007, |
| 438 | 0xbd000fd0, | 468 | 0xbd000fd0, |
| 439 | /* 0x031b: init */ | 469 | /* 0x039b: init */ |
| 440 | 0xbd00f804, | 470 | 0xbd00f804, |
| 441 | 0x0004fe04, | 471 | 0x0007fe04, |
| 442 | 0xf10007fe, | 472 | 0x420017f1, |
| 443 | 0xf0120017, | 473 | 0xcf0013f0, |
| 444 | 0x12d00227, | 474 | 0x11e70011, |
| 445 | 0xb117f100, | 475 | 0x14b60109, |
| 446 | 0x0010fe05, | 476 | 0x0014fe08, |
| 447 | 0x040017f1, | 477 | 0xf10227f0, |
| 448 | 0xf1c010d0, | 478 | 0xf0120007, |
| 449 | 0xb6040437, | 479 | 0x02d00003, |
| 450 | 0x27f10634, | 480 | 0xf104bd00, |
| 451 | 0x32d02003, | 481 | 0xfe06c817, |
| 452 | 0x0427f100, | 482 | 0x24bd0010, |
| 453 | 0x0132d020, | 483 | 0x070007f1, |
| 484 | 0xd00003f0, | ||
| 485 | 0x04bd0002, | ||
| 486 | 0x200327f1, | ||
| 487 | 0x010007f1, | ||
| 488 | 0xd00103f0, | ||
| 489 | 0x04bd0002, | ||
| 490 | 0x200427f1, | ||
| 491 | 0x010407f1, | ||
| 492 | 0xd00103f0, | ||
| 493 | 0x04bd0002, | ||
| 454 | 0x200b27f1, | 494 | 0x200b27f1, |
| 455 | 0xf10232d0, | 495 | 0x010807f1, |
| 456 | 0xd0200c27, | 496 | 0xd00103f0, |
| 457 | 0x27f10732, | 497 | 0x04bd0002, |
| 458 | 0x24b60c24, | 498 | 0x200c27f1, |
| 459 | 0x0003b906, | 499 | 0x011c07f1, |
| 460 | 0xf10023d0, | 500 | 0xd00103f0, |
| 501 | 0x04bd0002, | ||
| 502 | 0xf1010392, | ||
| 503 | 0xf0090007, | ||
| 504 | 0x03d00303, | ||
| 505 | 0xf104bd00, | ||
| 461 | 0xf0870427, | 506 | 0xf0870427, |
| 462 | 0x12d00023, | 507 | 0x07f10023, |
| 463 | 0x0012b700, | 508 | 0x03f00400, |
| 464 | 0x0427f001, | 509 | 0x0002d000, |
| 465 | 0xf40012d0, | 510 | 0x27f004bd, |
| 466 | 0xe7f11031, | 511 | 0x0007f104, |
| 467 | 0xe3f09604, | 512 | 0x0003f003, |
| 468 | 0x6821f440, | 513 | 0xbd0002d0, |
| 469 | 0x8090f1c7, | 514 | 0x1031f404, |
| 470 | 0xf4f00301, | 515 | 0x9604e7f1, |
| 471 | 0x020f801f, | 516 | 0xf440e3f0, |
| 472 | 0xbb0117f0, | 517 | 0xfeb96821, |
| 473 | 0x12b6041f, | 518 | 0x90f1c702, |
| 474 | 0x0c27f101, | 519 | 0xf0030180, |
| 475 | 0x0624b604, | 520 | 0x0f801ff4, |
| 476 | 0xd00021d0, | 521 | 0x0117f002, |
| 477 | 0x17f14021, | 522 | 0xb6041fbb, |
| 478 | 0x0e980100, | 523 | 0x07f10112, |
| 479 | 0x010f9800, | 524 | 0x03f00300, |
| 480 | 0x014721f5, | 525 | 0x0001d001, |
| 481 | 0x070037f1, | 526 | 0x07f104bd, |
| 482 | 0x950634b6, | 527 | 0x03f00400, |
| 483 | 0x34d00814, | 528 | 0x0001d001, |
| 484 | 0x4034d000, | 529 | 0x17f104bd, |
| 485 | 0x130030b7, | 530 | 0xf7f00100, |
| 486 | 0xb6001fbb, | 531 | 0xb521f502, |
| 487 | 0x3fd002f5, | 532 | 0xc721f507, |
| 488 | 0x0815b600, | 533 | 0x10f7f007, |
| 489 | 0xb60110b6, | 534 | 0x081421f5, |
| 490 | 0x1fb90814, | 535 | 0x98000e98, |
| 491 | 0x7121f502, | 536 | 0x21f5010f, |
| 492 | 0x001fbb02, | 537 | 0x14950150, |
| 493 | 0xf1020398, | 538 | 0x0007f108, |
| 494 | 0xf0200047, | 539 | 0x0103f0c0, |
| 495 | /* 0x03f6: init_gpc */ | 540 | 0xbd0004d0, |
| 496 | 0x4ea05043, | 541 | 0x0007f104, |
| 497 | 0x1fb90804, | 542 | 0x0103f0c1, |
| 498 | 0x8d21f402, | 543 | 0xbd0004d0, |
| 499 | 0x010c4ea0, | 544 | 0x0030b704, |
| 500 | 0x21f4f4bd, | 545 | 0x001fbb13, |
| 501 | 0x044ea08d, | 546 | 0xf102f5b6, |
| 502 | 0x8d21f401, | 547 | 0xf0d30007, |
| 503 | 0x01004ea0, | 548 | 0x0fd00103, |
| 504 | 0xf402f7f0, | 549 | 0xb604bd00, |
| 505 | 0x4ea08d21, | 550 | 0x10b60815, |
| 506 | /* 0x041e: init_gpc_wait */ | 551 | 0x0814b601, |
| 507 | 0x21f40800, | 552 | 0xf5021fb9, |
| 508 | 0x1fffc868, | 553 | 0xbb02d321, |
| 509 | 0xa0fa0bf4, | 554 | 0x0398001f, |
| 510 | 0xf408044e, | 555 | 0x0047f102, |
| 511 | 0x1fbb6821, | 556 | 0x5043f020, |
| 512 | 0x0040b700, | 557 | /* 0x04f4: init_gpc */ |
| 513 | 0x0132b680, | 558 | 0x08044ea0, |
| 514 | 0xf1be1bf4, | 559 | 0xf4021fb9, |
| 560 | 0x4ea09d21, | ||
| 561 | 0xf4bd010c, | ||
| 562 | 0xa09d21f4, | ||
| 563 | 0xf401044e, | ||
| 564 | 0x4ea09d21, | ||
| 565 | 0xf7f00100, | ||
| 566 | 0x9d21f402, | ||
| 567 | 0x08004ea0, | ||
| 568 | /* 0x051c: init_gpc_wait */ | ||
| 569 | 0xc86821f4, | ||
| 570 | 0x0bf41fff, | ||
| 571 | 0x044ea0fa, | ||
| 572 | 0x6821f408, | ||
| 573 | 0xb7001fbb, | ||
| 574 | 0xb6800040, | ||
| 575 | 0x1bf40132, | ||
| 576 | 0x00f7f0be, | ||
| 577 | 0x081421f5, | ||
| 578 | 0xf500f7f0, | ||
| 579 | 0xf107b521, | ||
| 515 | 0xf0010007, | 580 | 0xf0010007, |
| 516 | 0x01d00203, | 581 | 0x01d00203, |
| 517 | 0xbd04bd00, | 582 | 0xbd04bd00, |
| @@ -519,402 +584,399 @@ uint32_t nvc0_grhub_code[] = { | |||
| 519 | 0x080007f1, | 584 | 0x080007f1, |
| 520 | 0xd00203f0, | 585 | 0xd00203f0, |
| 521 | 0x04bd0001, | 586 | 0x04bd0001, |
| 522 | /* 0x0458: main */ | 587 | /* 0x0564: main */ |
| 523 | 0xf40031f4, | 588 | 0xf40031f4, |
| 524 | 0xd7f00028, | 589 | 0xd7f00028, |
| 525 | 0x3921f410, | 590 | 0x3921f410, |
| 526 | 0xb1f401f4, | 591 | 0xb1f401f4, |
| 527 | 0xf54001e4, | 592 | 0xf54001e4, |
| 528 | 0xbd00de1b, | 593 | 0xbd00e91b, |
| 529 | 0x0499f094, | 594 | 0x0499f094, |
| 530 | 0x0f0007f1, | 595 | 0x0f0007f1, |
| 531 | 0xd00203f0, | 596 | 0xd00203f0, |
| 532 | 0x04bd0009, | 597 | 0x04bd0009, |
| 533 | 0x0b0017f1, | 598 | 0xc00017f1, |
| 534 | 0xcf0614b6, | 599 | 0xcf0213f0, |
| 535 | 0x11cf4012, | 600 | 0x27f10011, |
| 536 | 0x1f13c800, | 601 | 0x23f0c100, |
| 537 | 0x00870bf5, | 602 | 0x0022cf02, |
| 538 | 0xf41f23c8, | 603 | 0xf51f13c8, |
| 539 | 0x20f9620b, | 604 | 0xc800890b, |
| 540 | 0xbd0212b9, | 605 | 0x0bf41f23, |
| 541 | 0x0799f094, | 606 | 0xb920f962, |
| 542 | 0x0f0007f1, | 607 | 0x94bd0212, |
| 543 | 0xd00203f0, | ||
| 544 | 0x04bd0009, | ||
| 545 | 0xf40132f4, | ||
| 546 | 0x21f50231, | ||
| 547 | 0x94bd082f, | ||
| 548 | 0xf10799f0, | 608 | 0xf10799f0, |
| 549 | 0xf0170007, | 609 | 0xf00f0007, |
| 550 | 0x09d00203, | 610 | 0x09d00203, |
| 551 | 0xfc04bd00, | 611 | 0xf404bd00, |
| 552 | 0xf094bd20, | 612 | 0x31f40132, |
| 553 | 0x07f10699, | 613 | 0xe821f502, |
| 554 | 0x03f00f00, | 614 | 0xf094bd09, |
| 555 | 0x0009d002, | 615 | 0x07f10799, |
| 556 | 0x31f404bd, | ||
| 557 | 0x2f21f501, | ||
| 558 | 0xf094bd08, | ||
| 559 | 0x07f10699, | ||
| 560 | 0x03f01700, | 616 | 0x03f01700, |
| 561 | 0x0009d002, | 617 | 0x0009d002, |
| 562 | 0x0ef404bd, | 618 | 0x20fc04bd, |
| 563 | /* 0x04f9: chsw_prev_no_next */ | ||
| 564 | 0xb920f931, | ||
| 565 | 0x32f40212, | ||
| 566 | 0x0232f401, | ||
| 567 | 0x082f21f5, | ||
| 568 | 0x17f120fc, | ||
| 569 | 0x14b60b00, | ||
| 570 | 0x0012d006, | ||
| 571 | /* 0x0517: chsw_no_prev */ | ||
| 572 | 0xc8130ef4, | ||
| 573 | 0x0bf41f23, | ||
| 574 | 0x0131f40d, | ||
| 575 | 0xf50232f4, | ||
| 576 | /* 0x0527: chsw_done */ | ||
| 577 | 0xf1082f21, | ||
| 578 | 0xb60b0c17, | ||
| 579 | 0x27f00614, | ||
| 580 | 0x0012d001, | ||
| 581 | 0x99f094bd, | 619 | 0x99f094bd, |
| 582 | 0x0007f104, | 620 | 0x0007f106, |
| 621 | 0x0203f00f, | ||
| 622 | 0xbd0009d0, | ||
| 623 | 0x0131f404, | ||
| 624 | 0x09e821f5, | ||
| 625 | 0x99f094bd, | ||
| 626 | 0x0007f106, | ||
| 583 | 0x0203f017, | 627 | 0x0203f017, |
| 584 | 0xbd0009d0, | 628 | 0xbd0009d0, |
| 585 | 0x130ef504, | 629 | 0x330ef404, |
| 586 | /* 0x0549: main_not_ctx_switch */ | 630 | /* 0x060c: chsw_prev_no_next */ |
| 587 | 0x01e4b0ff, | 631 | 0x12b920f9, |
| 588 | 0xb90d1bf4, | 632 | 0x0132f402, |
| 589 | 0x21f502f2, | 633 | 0xf50232f4, |
| 590 | 0x0ef407bb, | 634 | 0xfc09e821, |
| 591 | /* 0x0559: main_not_ctx_chan */ | 635 | 0x0007f120, |
| 592 | 0x02e4b046, | 636 | 0x0203f0c0, |
| 593 | 0xbd321bf4, | 637 | 0xbd0002d0, |
| 594 | 0x0799f094, | 638 | 0x130ef404, |
| 595 | 0x0f0007f1, | 639 | /* 0x062c: chsw_no_prev */ |
| 640 | 0xf41f23c8, | ||
| 641 | 0x31f40d0b, | ||
| 642 | 0x0232f401, | ||
| 643 | 0x09e821f5, | ||
| 644 | /* 0x063c: chsw_done */ | ||
| 645 | 0xf10127f0, | ||
| 646 | 0xf0c30007, | ||
| 647 | 0x02d00203, | ||
| 648 | 0xbd04bd00, | ||
| 649 | 0x0499f094, | ||
| 650 | 0x170007f1, | ||
| 596 | 0xd00203f0, | 651 | 0xd00203f0, |
| 597 | 0x04bd0009, | 652 | 0x04bd0009, |
| 598 | 0xf40132f4, | 653 | 0xff080ef5, |
| 599 | 0x21f50232, | 654 | /* 0x0660: main_not_ctx_switch */ |
| 600 | 0x94bd082f, | 655 | 0xf401e4b0, |
| 656 | 0xf2b90d1b, | ||
| 657 | 0x7821f502, | ||
| 658 | 0x460ef409, | ||
| 659 | /* 0x0670: main_not_ctx_chan */ | ||
| 660 | 0xf402e4b0, | ||
| 661 | 0x94bd321b, | ||
| 601 | 0xf10799f0, | 662 | 0xf10799f0, |
| 602 | 0xf0170007, | 663 | 0xf00f0007, |
| 603 | 0x09d00203, | 664 | 0x09d00203, |
| 604 | 0xf404bd00, | 665 | 0xf404bd00, |
| 605 | /* 0x058e: main_not_ctx_save */ | 666 | 0x32f40132, |
| 606 | 0xef94110e, | 667 | 0xe821f502, |
| 607 | 0x01f5f010, | 668 | 0xf094bd09, |
| 608 | 0x02fe21f5, | 669 | 0x07f10799, |
| 609 | 0xfec00ef5, | 670 | 0x03f01700, |
| 610 | /* 0x059c: main_done */ | 671 | 0x0009d002, |
| 611 | 0x29f024bd, | 672 | 0x0ef404bd, |
| 612 | 0x0007f11f, | 673 | /* 0x06a5: main_not_ctx_save */ |
| 613 | 0x0203f008, | 674 | 0x10ef9411, |
| 614 | 0xbd0002d0, | 675 | 0xf501f5f0, |
| 615 | 0xab0ef504, | 676 | 0xf5037e21, |
| 616 | /* 0x05b1: ih */ | 677 | /* 0x06b3: main_done */ |
| 617 | 0xfe80f9fe, | 678 | 0xbdfeb50e, |
| 618 | 0x80f90188, | 679 | 0x1f29f024, |
| 619 | 0xa0f990f9, | 680 | 0x080007f1, |
| 620 | 0xd0f9b0f9, | 681 | 0xd00203f0, |
| 621 | 0xf0f9e0f9, | 682 | 0x04bd0002, |
| 622 | 0x0acf04bd, | 683 | 0xfea00ef5, |
| 623 | 0x04abc480, | 684 | /* 0x06c8: ih */ |
| 624 | 0xf11d0bf4, | 685 | 0x88fe80f9, |
| 625 | 0xf01900b7, | 686 | 0xf980f901, |
| 626 | 0xbecf10d7, | 687 | 0xf9a0f990, |
| 627 | 0x00bfcf40, | 688 | 0xf9d0f9b0, |
| 689 | 0xbdf0f9e0, | ||
| 690 | 0x00a7f104, | ||
| 691 | 0x00a3f002, | ||
| 692 | 0xc400aacf, | ||
| 693 | 0x0bf404ab, | ||
| 694 | 0x10d7f030, | ||
| 695 | 0x1a00e7f1, | ||
| 696 | 0xcf00e3f0, | ||
| 697 | 0xf7f100ee, | ||
| 698 | 0xf3f01900, | ||
| 699 | 0x00ffcf00, | ||
| 628 | 0xb70421f4, | 700 | 0xb70421f4, |
| 629 | 0xf00400b0, | 701 | 0xf00400b0, |
| 630 | 0xbed001e7, | 702 | 0x07f101e7, |
| 631 | /* 0x05e9: ih_no_fifo */ | 703 | 0x03f01d00, |
| 632 | 0x00abe400, | 704 | 0x000ed000, |
| 633 | 0x0d0bf401, | 705 | /* 0x071a: ih_no_fifo */ |
| 634 | 0xf110d7f0, | 706 | 0xabe404bd, |
| 635 | 0xf44001e7, | 707 | 0x0bf40100, |
| 636 | /* 0x05fa: ih_no_ctxsw */ | 708 | 0x10d7f00d, |
| 637 | 0xb7f10421, | 709 | 0x4001e7f1, |
| 638 | 0xb0bd0104, | 710 | /* 0x072b: ih_no_ctxsw */ |
| 639 | 0xf4b4abff, | 711 | 0xe40421f4, |
| 640 | 0xa7f10d0b, | 712 | 0xf40400ab, |
| 641 | 0xa4b60c1c, | 713 | 0xb7f1140b, |
| 642 | 0x00abd006, | 714 | 0xbfb90100, |
| 643 | /* 0x0610: ih_no_other */ | 715 | 0x44e7f102, |
| 644 | 0xfc400ad0, | 716 | 0x40e3f001, |
| 717 | /* 0x0743: ih_no_fwmthd */ | ||
| 718 | 0xf19d21f4, | ||
| 719 | 0xbd0104b7, | ||
| 720 | 0xb4abffb0, | ||
| 721 | 0xf10f0bf4, | ||
| 722 | 0xf0070007, | ||
| 723 | 0x0bd00303, | ||
| 724 | /* 0x075b: ih_no_other */ | ||
| 725 | 0xf104bd00, | ||
| 726 | 0xf0010007, | ||
| 727 | 0x0ad00003, | ||
| 728 | 0xfc04bd00, | ||
| 645 | 0xfce0fcf0, | 729 | 0xfce0fcf0, |
| 646 | 0xfcb0fcd0, | 730 | 0xfcb0fcd0, |
| 647 | 0xfc90fca0, | 731 | 0xfc90fca0, |
| 648 | 0x0088fe80, | 732 | 0x0088fe80, |
| 649 | 0x32f480fc, | 733 | 0x32f480fc, |
| 650 | /* 0x062b: ctx_4160s */ | 734 | /* 0x077f: ctx_4160s */ |
| 651 | 0xf101f800, | 735 | 0xf001f800, |
| 652 | 0xf04160e7, | 736 | 0xffb901f7, |
| 653 | 0xf7f040e3, | 737 | 0x60e7f102, |
| 654 | 0x8d21f401, | 738 | 0x40e3f041, |
| 655 | /* 0x0638: ctx_4160s_wait */ | 739 | /* 0x078f: ctx_4160s_wait */ |
| 656 | 0xc86821f4, | 740 | 0xf19d21f4, |
| 657 | 0x0bf404ff, | ||
| 658 | /* 0x0643: ctx_4160c */ | ||
| 659 | 0xf100f8fa, | ||
| 660 | 0xf04160e7, | 741 | 0xf04160e7, |
| 661 | 0xf4bd40e3, | 742 | 0x21f440e3, |
| 662 | 0xf88d21f4, | 743 | 0x02ffb968, |
| 663 | /* 0x0651: ctx_4170s */ | 744 | 0xf404ffc8, |
| 664 | 0x70e7f100, | 745 | 0x00f8f00b, |
| 746 | /* 0x07a4: ctx_4160c */ | ||
| 747 | 0xffb9f4bd, | ||
| 748 | 0x60e7f102, | ||
| 665 | 0x40e3f041, | 749 | 0x40e3f041, |
| 666 | 0xf410f5f0, | 750 | 0xf89d21f4, |
| 667 | 0x00f88d21, | 751 | /* 0x07b5: ctx_4170s */ |
| 668 | /* 0x0660: ctx_4170w */ | 752 | 0x10f5f000, |
| 669 | 0x4170e7f1, | 753 | 0xf102ffb9, |
| 670 | 0xf440e3f0, | 754 | 0xf04170e7, |
| 671 | 0xf4f06821, | 755 | 0x21f440e3, |
| 672 | 0xf31bf410, | 756 | /* 0x07c7: ctx_4170w */ |
| 673 | /* 0x0672: ctx_redswitch */ | 757 | 0xf100f89d, |
| 674 | 0xe7f100f8, | 758 | 0xf04170e7, |
| 675 | 0xe4b60614, | 759 | 0x21f440e3, |
| 676 | 0x70f7f106, | 760 | 0x02ffb968, |
| 677 | 0x00efd002, | 761 | 0xf410f4f0, |
| 678 | /* 0x0683: ctx_redswitch_delay */ | 762 | 0x00f8f01b, |
| 679 | 0xb608f7f0, | 763 | /* 0x07dc: ctx_redswitch */ |
| 680 | 0x1bf401f2, | 764 | 0x0200e7f1, |
| 681 | 0x70f7f1fd, | 765 | 0xf040e5f0, |
| 682 | 0x00efd007, | 766 | 0xe5f020e5, |
| 683 | /* 0x0692: ctx_86c */ | 767 | 0x0007f110, |
| 684 | 0xe7f100f8, | 768 | 0x0103f085, |
| 685 | 0xe4b6086c, | 769 | 0xbd000ed0, |
| 686 | 0x00efd006, | 770 | 0x08f7f004, |
| 687 | 0x8a14e7f1, | 771 | /* 0x07f8: ctx_redswitch_delay */ |
| 688 | 0xf440e3f0, | 772 | 0xf401f2b6, |
| 689 | 0xe7f18d21, | 773 | 0xe5f1fd1b, |
| 690 | 0xe3f0a86c, | 774 | 0xe5f10400, |
| 691 | 0x8d21f441, | 775 | 0x07f10100, |
| 692 | /* 0x06b2: ctx_load */ | 776 | 0x03f08500, |
| 777 | 0x000ed001, | ||
| 778 | 0x00f804bd, | ||
| 779 | /* 0x0814: ctx_86c */ | ||
| 780 | 0x1b0007f1, | ||
| 781 | 0xd00203f0, | ||
| 782 | 0x04bd000f, | ||
| 783 | 0xf102ffb9, | ||
| 784 | 0xf08a14e7, | ||
| 785 | 0x21f440e3, | ||
| 786 | 0x02ffb99d, | ||
| 787 | 0xa86ce7f1, | ||
| 788 | 0xf441e3f0, | ||
| 789 | 0x00f89d21, | ||
| 790 | /* 0x083c: ctx_mem */ | ||
| 791 | 0x840007f1, | ||
| 792 | 0xd00203f0, | ||
| 793 | 0x04bd000f, | ||
| 794 | /* 0x0848: ctx_mem_wait */ | ||
| 795 | 0x8400f7f1, | ||
| 796 | 0xcf02f3f0, | ||
| 797 | 0xfffd00ff, | ||
| 798 | 0xf31bf405, | ||
| 799 | /* 0x085a: ctx_load */ | ||
| 693 | 0x94bd00f8, | 800 | 0x94bd00f8, |
| 694 | 0xf10599f0, | 801 | 0xf10599f0, |
| 695 | 0xf00f0007, | 802 | 0xf00f0007, |
| 696 | 0x09d00203, | 803 | 0x09d00203, |
| 697 | 0xf004bd00, | 804 | 0xf004bd00, |
| 698 | 0x21f40ca7, | 805 | 0x21f40ca7, |
| 699 | 0x2417f1c9, | 806 | 0xf1f4bdd0, |
| 700 | 0x0614b60a, | 807 | 0xf0890007, |
| 701 | 0xf10010d0, | 808 | 0x0fd00203, |
| 702 | 0xb60b0037, | 809 | 0xf104bd00, |
| 703 | 0x32d00634, | 810 | 0xf0c10007, |
| 704 | 0x0c17f140, | 811 | 0x02d00203, |
| 705 | 0x0614b60a, | 812 | 0xf104bd00, |
| 706 | 0xd00747f0, | 813 | 0xf0830007, |
| 707 | 0x14d00012, | 814 | 0x02d00203, |
| 708 | /* 0x06ed: ctx_chan_wait_0 */ | 815 | 0xf004bd00, |
| 709 | 0x4014cf40, | 816 | 0x21f507f7, |
| 710 | 0xf41f44f0, | 817 | 0x07f1083c, |
| 711 | 0x32d0fa1b, | 818 | 0x03f0c000, |
| 712 | 0x000bfe00, | 819 | 0x0002d002, |
| 713 | 0xb61f2af0, | 820 | 0x0bfe04bd, |
| 714 | 0x20b60424, | 821 | 0x1f2af000, |
| 715 | 0xf094bd02, | 822 | 0xb60424b6, |
| 823 | 0x94bd0220, | ||
| 824 | 0xf10899f0, | ||
| 825 | 0xf00f0007, | ||
| 826 | 0x09d00203, | ||
| 827 | 0xf104bd00, | ||
| 828 | 0xf0810007, | ||
| 829 | 0x02d00203, | ||
| 830 | 0xf104bd00, | ||
| 831 | 0xf1000027, | ||
| 832 | 0xf0800023, | ||
| 833 | 0x07f10225, | ||
| 834 | 0x03f08800, | ||
| 835 | 0x0002d002, | ||
| 836 | 0x17f004bd, | ||
| 837 | 0x0027f110, | ||
| 838 | 0x0223f002, | ||
| 839 | 0xf80512fa, | ||
| 840 | 0xf094bd03, | ||
| 716 | 0x07f10899, | 841 | 0x07f10899, |
| 717 | 0x03f00f00, | 842 | 0x03f01700, |
| 718 | 0x0009d002, | 843 | 0x0009d002, |
| 719 | 0x17f104bd, | 844 | 0x019804bd, |
| 720 | 0x14b60a04, | 845 | 0x1814b681, |
| 721 | 0x0012d006, | 846 | 0xb6800298, |
| 722 | 0x0a2017f1, | 847 | 0x12fd0825, |
| 723 | 0xf00614b6, | 848 | 0x16018005, |
| 724 | 0x23f10227, | ||
| 725 | 0x12d08000, | ||
| 726 | 0x1017f000, | ||
| 727 | 0x020027f1, | ||
| 728 | 0xfa0223f0, | ||
| 729 | 0x03f80512, | ||
| 730 | 0x99f094bd, | 849 | 0x99f094bd, |
| 731 | 0x0007f108, | 850 | 0x0007f109, |
| 732 | 0x0203f017, | 851 | 0x0203f00f, |
| 733 | 0xbd0009d0, | 852 | 0xbd0009d0, |
| 734 | 0x81019804, | 853 | 0x0007f104, |
| 735 | 0x981814b6, | 854 | 0x0203f081, |
| 736 | 0x25b68002, | 855 | 0xbd0001d0, |
| 737 | 0x0512fd08, | 856 | 0x0127f004, |
| 738 | 0xbd160180, | 857 | 0x880007f1, |
| 739 | 0x0999f094, | ||
| 740 | 0x0f0007f1, | ||
| 741 | 0xd00203f0, | ||
| 742 | 0x04bd0009, | ||
| 743 | 0x0a0427f1, | ||
| 744 | 0xd00624b6, | ||
| 745 | 0x27f00021, | ||
| 746 | 0x2017f101, | ||
| 747 | 0x0614b60a, | ||
| 748 | 0xf10012d0, | ||
| 749 | 0xf0010017, | ||
| 750 | 0x01fa0613, | ||
| 751 | 0xbd03f805, | ||
| 752 | 0x0999f094, | ||
| 753 | 0x170007f1, | ||
| 754 | 0xd00203f0, | 858 | 0xd00203f0, |
| 755 | 0x04bd0009, | 859 | 0x04bd0002, |
| 860 | 0x010017f1, | ||
| 861 | 0xfa0613f0, | ||
| 862 | 0x03f80501, | ||
| 756 | 0x99f094bd, | 863 | 0x99f094bd, |
| 757 | 0x0007f105, | 864 | 0x0007f109, |
| 758 | 0x0203f017, | 865 | 0x0203f017, |
| 759 | 0xbd0009d0, | 866 | 0xbd0009d0, |
| 760 | /* 0x07bb: ctx_chan */ | 867 | 0xf094bd04, |
| 761 | 0xf500f804, | 868 | 0x07f10599, |
| 762 | 0xf5062b21, | 869 | 0x03f01700, |
| 763 | 0xf006b221, | 870 | 0x0009d002, |
| 764 | 0x21f40ca7, | 871 | 0x00f804bd, |
| 765 | 0x1017f1c9, | 872 | /* 0x0978: ctx_chan */ |
| 766 | 0x0614b60a, | 873 | 0x077f21f5, |
| 767 | 0xd00527f0, | 874 | 0x085a21f5, |
| 768 | /* 0x07d6: ctx_chan_wait */ | 875 | 0xf40ca7f0, |
| 769 | 0x12cf0012, | 876 | 0xf7f0d021, |
| 770 | 0x0522fd00, | 877 | 0x3c21f505, |
| 771 | 0xf5fa1bf4, | 878 | 0xa421f508, |
| 772 | 0xf8064321, | 879 | /* 0x0993: ctx_mmio_exec */ |
| 773 | /* 0x07e5: ctx_mmio_exec */ | 880 | 0x9800f807, |
| 774 | 0x41039800, | 881 | 0x07f14103, |
| 775 | 0x0a0427f1, | 882 | 0x03f08100, |
| 776 | 0xd00624b6, | 883 | 0x0003d002, |
| 777 | 0x34bd0023, | 884 | 0x34bd04bd, |
| 778 | /* 0x07f4: ctx_mmio_loop */ | 885 | /* 0x09a4: ctx_mmio_loop */ |
| 779 | 0xf4ff34c4, | 886 | 0xf4ff34c4, |
| 780 | 0x57f10f1b, | 887 | 0x57f10f1b, |
| 781 | 0x53f00200, | 888 | 0x53f00200, |
| 782 | 0x0535fa06, | 889 | 0x0535fa06, |
| 783 | /* 0x0806: ctx_mmio_pull */ | 890 | /* 0x09b6: ctx_mmio_pull */ |
| 784 | 0x4e9803f8, | 891 | 0x4e9803f8, |
| 785 | 0x814f9880, | 892 | 0x814f9880, |
| 786 | 0xb68d21f4, | 893 | 0xb69d21f4, |
| 787 | 0x12b60830, | 894 | 0x12b60830, |
| 788 | 0xdf1bf401, | 895 | 0xdf1bf401, |
| 789 | /* 0x0818: ctx_mmio_done */ | 896 | /* 0x09c8: ctx_mmio_done */ |
| 790 | 0xd0160398, | 897 | 0xf1160398, |
| 791 | 0x00800023, | 898 | 0xf0810007, |
| 792 | 0x0017f140, | 899 | 0x03d00203, |
| 793 | 0x0613f001, | 900 | 0x8004bd00, |
| 794 | 0xf80601fa, | 901 | 0x17f14000, |
| 795 | /* 0x082f: ctx_xfer */ | 902 | 0x13f00100, |
| 796 | 0xf100f803, | 903 | 0x0601fa06, |
| 797 | 0xb60c00f7, | 904 | 0x00f803f8, |
| 798 | 0xe7f006f4, | 905 | /* 0x09e8: ctx_xfer */ |
| 799 | 0x80fed004, | 906 | 0xf104e7f0, |
| 800 | /* 0x083c: ctx_xfer_idle */ | 907 | 0xf0020007, |
| 801 | 0xf100fecf, | 908 | 0x0ed00303, |
| 802 | 0xf42000e4, | 909 | /* 0x09f7: ctx_xfer_idle */ |
| 803 | 0x11f4f91b, | 910 | 0xf104bd00, |
| 804 | 0x1102f406, | 911 | 0xf00000e7, |
| 805 | /* 0x084c: ctx_xfer_pre */ | 912 | 0xeecf03e3, |
| 806 | 0xf510f7f0, | 913 | 0x00e4f100, |
| 807 | 0xf5069221, | 914 | 0xf21bf420, |
| 808 | 0xf4062b21, | 915 | 0xf40611f4, |
| 809 | /* 0x085a: ctx_xfer_pre_load */ | 916 | /* 0x0a0e: ctx_xfer_pre */ |
| 810 | 0xf7f01c11, | 917 | 0xf7f01102, |
| 811 | 0x5121f502, | 918 | 0x1421f510, |
| 812 | 0x6021f506, | 919 | 0x7f21f508, |
| 813 | 0x7221f506, | 920 | 0x1c11f407, |
| 814 | 0xf5f4bd06, | 921 | /* 0x0a1c: ctx_xfer_pre_load */ |
| 815 | 0xf5065121, | 922 | 0xf502f7f0, |
| 816 | /* 0x0873: ctx_xfer_exec */ | 923 | 0xf507b521, |
| 817 | 0x9806b221, | 924 | 0xf507c721, |
| 818 | 0x27f11601, | 925 | 0xbd07dc21, |
| 819 | 0x24b60414, | 926 | 0xb521f5f4, |
| 820 | 0x0020d006, | 927 | 0x5a21f507, |
| 821 | 0xa500e7f1, | 928 | /* 0x0a35: ctx_xfer_exec */ |
| 822 | 0xb941e3f0, | 929 | 0x16019808, |
| 823 | 0x21f4021f, | 930 | 0x07f124bd, |
| 824 | 0x04e0b68d, | 931 | 0x03f00500, |
| 825 | 0xf001fcf0, | 932 | 0x0002d001, |
| 826 | 0x24b6022c, | 933 | 0x1fb904bd, |
| 827 | 0x05f2fd01, | 934 | 0x00e7f102, |
| 828 | 0xf18d21f4, | 935 | 0x41e3f0a5, |
| 829 | 0xf04afc17, | 936 | 0xf09d21f4, |
| 830 | 0x27f00213, | 937 | 0x2cf001fc, |
| 831 | 0x0012d00c, | 938 | 0x0124b602, |
| 832 | 0x021521f5, | 939 | 0xb905f2fd, |
| 833 | 0x47fc27f1, | 940 | 0xe7f102ff, |
| 834 | 0xd00223f0, | 941 | 0xe3f0a504, |
| 835 | 0x2cf00020, | 942 | 0x9d21f441, |
| 943 | 0x026a21f5, | ||
| 944 | 0x07f124bd, | ||
| 945 | 0x03f047fc, | ||
| 946 | 0x0002d002, | ||
| 947 | 0x2cf004bd, | ||
| 836 | 0x0320b601, | 948 | 0x0320b601, |
| 837 | 0xf00012d0, | 949 | 0x4afc07f1, |
| 838 | 0xa5f001ac, | 950 | 0xd00203f0, |
| 839 | 0x00b7f006, | 951 | 0x04bd0002, |
| 840 | 0x98000c98, | 952 | 0xf001acf0, |
| 841 | 0xe7f0010d, | 953 | 0xb7f006a5, |
| 842 | 0x6621f500, | 954 | 0x000c9800, |
| 843 | 0x08a7f001, | 955 | 0xf0010d98, |
| 844 | 0x010921f5, | 956 | 0x21f500e7, |
| 845 | 0x021521f5, | 957 | 0xa7f0016f, |
| 846 | 0xf02201f4, | 958 | 0x1021f508, |
| 847 | 0x21f40ca7, | 959 | 0x5e21f501, |
| 848 | 0x1017f1c9, | 960 | 0x1301f402, |
| 849 | 0x0614b60a, | 961 | 0xf40ca7f0, |
| 850 | 0xd00527f0, | 962 | 0xf7f0d021, |
| 851 | /* 0x08fa: ctx_xfer_post_save_wait */ | 963 | 0x3c21f505, |
| 852 | 0x12cf0012, | 964 | 0x3202f408, |
| 853 | 0x0522fd00, | 965 | /* 0x0ac4: ctx_xfer_post */ |
| 854 | 0xf4fa1bf4, | 966 | 0xf502f7f0, |
| 855 | /* 0x0906: ctx_xfer_post */ | 967 | 0xbd07b521, |
| 856 | 0xf7f03202, | 968 | 0x1421f5f4, |
| 857 | 0x5121f502, | 969 | 0x7f21f508, |
| 858 | 0xf5f4bd06, | 970 | 0xc721f502, |
| 859 | 0xf5069221, | 971 | 0xf5f4bd07, |
| 860 | 0xf5023421, | 972 | 0xf407b521, |
| 861 | 0xbd066021, | 973 | 0x01981011, |
| 862 | 0x5121f5f4, | 974 | 0x0511fd40, |
| 863 | 0x1011f406, | 975 | 0xf5070bf4, |
| 864 | 0xfd400198, | 976 | /* 0x0aef: ctx_xfer_no_post_mmio */ |
| 865 | 0x0bf40511, | 977 | 0xf5099321, |
| 866 | 0xe521f507, | 978 | /* 0x0af3: ctx_xfer_done */ |
| 867 | /* 0x0931: ctx_xfer_no_post_mmio */ | 979 | 0xf807a421, |
| 868 | 0x4321f507, | ||
| 869 | /* 0x0935: ctx_xfer_done */ | ||
| 870 | 0x0000f806, | ||
| 871 | 0x00000000, | ||
| 872 | 0x00000000, | ||
| 873 | 0x00000000, | ||
| 874 | 0x00000000, | ||
| 875 | 0x00000000, | ||
| 876 | 0x00000000, | ||
| 877 | 0x00000000, | ||
| 878 | 0x00000000, | ||
| 879 | 0x00000000, | ||
| 880 | 0x00000000, | ||
| 881 | 0x00000000, | ||
| 882 | 0x00000000, | ||
| 883 | 0x00000000, | ||
| 884 | 0x00000000, | ||
| 885 | 0x00000000, | ||
| 886 | 0x00000000, | ||
| 887 | 0x00000000, | ||
| 888 | 0x00000000, | ||
| 889 | 0x00000000, | ||
| 890 | 0x00000000, | ||
| 891 | 0x00000000, | ||
| 892 | 0x00000000, | ||
| 893 | 0x00000000, | ||
| 894 | 0x00000000, | ||
| 895 | 0x00000000, | ||
| 896 | 0x00000000, | ||
| 897 | 0x00000000, | ||
| 898 | 0x00000000, | ||
| 899 | 0x00000000, | ||
| 900 | 0x00000000, | ||
| 901 | 0x00000000, | ||
| 902 | 0x00000000, | ||
| 903 | 0x00000000, | ||
| 904 | 0x00000000, | ||
| 905 | 0x00000000, | ||
| 906 | 0x00000000, | ||
| 907 | 0x00000000, | ||
| 908 | 0x00000000, | ||
| 909 | 0x00000000, | ||
| 910 | 0x00000000, | ||
| 911 | 0x00000000, | ||
| 912 | 0x00000000, | ||
| 913 | 0x00000000, | ||
| 914 | 0x00000000, | ||
| 915 | 0x00000000, | ||
| 916 | 0x00000000, | ||
| 917 | 0x00000000, | ||
| 918 | 0x00000000, | 980 | 0x00000000, |
| 919 | 0x00000000, | 981 | 0x00000000, |
| 920 | 0x00000000, | 982 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h index a1b9f763996a..84af82418987 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h | |||
| @@ -206,14 +206,14 @@ uint32_t nvd7_grhub_data[] = { | |||
| 206 | }; | 206 | }; |
| 207 | 207 | ||
| 208 | uint32_t nvd7_grhub_code[] = { | 208 | uint32_t nvd7_grhub_code[] = { |
| 209 | 0x031b0ef5, | 209 | 0x039b0ef5, |
| 210 | /* 0x0004: queue_put */ | 210 | /* 0x0004: queue_put */ |
| 211 | 0x9800d898, | 211 | 0x9800d898, |
| 212 | 0x86f001d9, | 212 | 0x86f001d9, |
| 213 | 0x0489b808, | 213 | 0x0489b808, |
| 214 | 0xf00c1bf4, | 214 | 0xf00c1bf4, |
| 215 | 0x21f502f7, | 215 | 0x21f502f7, |
| 216 | 0x00f802fe, | 216 | 0x00f8037e, |
| 217 | /* 0x001c: queue_put_next */ | 217 | /* 0x001c: queue_put_next */ |
| 218 | 0xb60798c4, | 218 | 0xb60798c4, |
| 219 | 0x8dbb0384, | 219 | 0x8dbb0384, |
| @@ -237,184 +237,214 @@ uint32_t nvd7_grhub_code[] = { | |||
| 237 | /* 0x0066: queue_get_done */ | 237 | /* 0x0066: queue_get_done */ |
| 238 | 0x00f80132, | 238 | 0x00f80132, |
| 239 | /* 0x0068: nv_rd32 */ | 239 | /* 0x0068: nv_rd32 */ |
| 240 | 0x0728b7f1, | 240 | 0xf002ecb9, |
| 241 | 0xb906b4b6, | 241 | 0x07f11fc9, |
| 242 | 0xc9f002ec, | 242 | 0x03f0ca00, |
| 243 | 0x00bcd01f, | 243 | 0x000cd001, |
| 244 | /* 0x0078: nv_rd32_wait */ | 244 | /* 0x007a: nv_rd32_wait */ |
| 245 | 0xc800bccf, | 245 | 0xc7f104bd, |
| 246 | 0x1bf41fcc, | 246 | 0xc3f0ca00, |
| 247 | 0x06a7f0fa, | 247 | 0x00cccf01, |
| 248 | 0x010921f5, | 248 | 0xf41fccc8, |
| 249 | 0xf840bfcf, | 249 | 0xa7f0f31b, |
| 250 | /* 0x008d: nv_wr32 */ | 250 | 0x1021f506, |
| 251 | 0x28b7f100, | 251 | 0x00f7f101, |
| 252 | 0x06b4b607, | 252 | 0x01f3f0cb, |
| 253 | 0xb980bfd0, | 253 | 0xf800ffcf, |
| 254 | 0xc9f002ec, | 254 | /* 0x009d: nv_wr32 */ |
| 255 | 0x1ec9f01f, | 255 | 0x0007f100, |
| 256 | /* 0x00a3: nv_wr32_wait */ | 256 | 0x0103f0cc, |
| 257 | 0xcf00bcd0, | 257 | 0xbd000fd0, |
| 258 | 0xccc800bc, | 258 | 0x02ecb904, |
| 259 | 0xfa1bf41f, | 259 | 0xf01fc9f0, |
| 260 | /* 0x00ae: watchdog_reset */ | 260 | 0x07f11ec9, |
| 261 | 0x87f100f8, | 261 | 0x03f0ca00, |
| 262 | 0x84b60430, | 262 | 0x000cd001, |
| 263 | 0x1ff9f006, | 263 | /* 0x00be: nv_wr32_wait */ |
| 264 | 0xf8008fd0, | 264 | 0xc7f104bd, |
| 265 | /* 0x00bd: watchdog_clear */ | 265 | 0xc3f0ca00, |
| 266 | 0x3087f100, | 266 | 0x00cccf01, |
| 267 | 0x0684b604, | 267 | 0xf41fccc8, |
| 268 | 0xf80080d0, | 268 | 0x00f8f31b, |
| 269 | /* 0x00c9: wait_donez */ | 269 | /* 0x00d0: wait_donez */ |
| 270 | 0xf094bd00, | 270 | 0x99f094bd, |
| 271 | 0x07f10099, | 271 | 0x0007f100, |
| 272 | 0x03f00f00, | 272 | 0x0203f00f, |
| 273 | 0x0009d002, | 273 | 0xbd0009d0, |
| 274 | 0x07f104bd, | 274 | 0x0007f104, |
| 275 | 0x03f00600, | 275 | 0x0203f006, |
| 276 | 0x000ad002, | 276 | 0xbd000ad0, |
| 277 | /* 0x00e6: wait_donez_ne */ | 277 | /* 0x00ed: wait_donez_ne */ |
| 278 | 0x87f104bd, | 278 | 0x0087f104, |
| 279 | 0x83f00000, | 279 | 0x0183f000, |
| 280 | 0x0088cf01, | 280 | 0xff0088cf, |
| 281 | 0xf4888aff, | 281 | 0x1bf4888a, |
| 282 | 0x94bdf31b, | 282 | 0xf094bdf3, |
| 283 | 0xf10099f0, | ||
| 284 | 0xf0170007, | ||
| 285 | 0x09d00203, | ||
| 286 | 0xf804bd00, | ||
| 287 | /* 0x0109: wait_doneo */ | ||
| 288 | 0xf094bd00, | ||
| 289 | 0x07f10099, | 283 | 0x07f10099, |
| 290 | 0x03f00f00, | 284 | 0x03f01700, |
| 291 | 0x0009d002, | 285 | 0x0009d002, |
| 292 | 0x87f104bd, | 286 | 0x00f804bd, |
| 293 | 0x84b60818, | 287 | /* 0x0110: wait_doneo */ |
| 294 | 0x008ad006, | ||
| 295 | /* 0x0124: wait_doneo_e */ | ||
| 296 | 0x040087f1, | ||
| 297 | 0xcf0684b6, | ||
| 298 | 0x8aff0088, | ||
| 299 | 0xf30bf488, | ||
| 300 | 0x99f094bd, | 288 | 0x99f094bd, |
| 301 | 0x0007f100, | 289 | 0x0007f100, |
| 302 | 0x0203f017, | 290 | 0x0203f00f, |
| 303 | 0xbd0009d0, | 291 | 0xbd0009d0, |
| 304 | /* 0x0147: mmctx_size */ | 292 | 0x0007f104, |
| 305 | 0xbd00f804, | 293 | 0x0203f006, |
| 306 | /* 0x0149: nv_mmctx_size_loop */ | 294 | 0xbd000ad0, |
| 307 | 0x00e89894, | 295 | /* 0x012d: wait_doneo_e */ |
| 308 | 0xb61a85b6, | 296 | 0x0087f104, |
| 309 | 0x84b60180, | 297 | 0x0183f000, |
| 310 | 0x0098bb02, | 298 | 0xff0088cf, |
| 311 | 0xb804e0b6, | 299 | 0x0bf4888a, |
| 312 | 0x1bf404ef, | 300 | 0xf094bdf3, |
| 313 | 0x029fb9eb, | 301 | 0x07f10099, |
| 314 | /* 0x0166: mmctx_xfer */ | 302 | 0x03f01700, |
| 315 | 0x94bd00f8, | 303 | 0x0009d002, |
| 316 | 0xf10199f0, | 304 | 0x00f804bd, |
| 317 | 0xf00f0007, | 305 | /* 0x0150: mmctx_size */ |
| 318 | 0x09d00203, | 306 | /* 0x0152: nv_mmctx_size_loop */ |
| 319 | 0xf104bd00, | 307 | 0xe89894bd, |
| 320 | 0xb6071087, | 308 | 0x1a85b600, |
| 321 | 0x94bd0684, | 309 | 0xb60180b6, |
| 322 | 0xf405bbfd, | 310 | 0x98bb0284, |
| 323 | 0x8bd0090b, | 311 | 0x04e0b600, |
| 324 | 0x0099f000, | 312 | 0xf404efb8, |
| 325 | /* 0x018c: mmctx_base_disabled */ | 313 | 0x9fb9eb1b, |
| 326 | 0xf405eefd, | 314 | /* 0x016f: mmctx_xfer */ |
| 327 | 0x8ed00c0b, | 315 | 0xbd00f802, |
| 328 | 0xc08fd080, | 316 | 0x0199f094, |
| 329 | /* 0x019b: mmctx_multi_disabled */ | 317 | 0x0f0007f1, |
| 330 | 0xb70199f0, | 318 | 0xd00203f0, |
| 331 | 0xc8010080, | 319 | 0x04bd0009, |
| 320 | 0xbbfd94bd, | ||
| 321 | 0x120bf405, | ||
| 322 | 0xc40007f1, | ||
| 323 | 0xd00103f0, | ||
| 324 | 0x04bd000b, | ||
| 325 | /* 0x0197: mmctx_base_disabled */ | ||
| 326 | 0xfd0099f0, | ||
| 327 | 0x0bf405ee, | ||
| 328 | 0x0007f11e, | ||
| 329 | 0x0103f0c6, | ||
| 330 | 0xbd000ed0, | ||
| 331 | 0x0007f104, | ||
| 332 | 0x0103f0c7, | ||
| 333 | 0xbd000fd0, | ||
| 334 | 0x0199f004, | ||
| 335 | /* 0x01b8: mmctx_multi_disabled */ | ||
| 336 | 0xb600abc8, | ||
| 337 | 0xb9f010b4, | ||
| 338 | 0x01aec80c, | ||
| 339 | 0xfd11e4b6, | ||
| 340 | 0x07f105be, | ||
| 341 | 0x03f0c500, | ||
| 342 | 0x000bd001, | ||
| 343 | /* 0x01d6: mmctx_exec_loop */ | ||
| 344 | /* 0x01d6: mmctx_wait_free */ | ||
| 345 | 0xe7f104bd, | ||
| 346 | 0xe3f0c500, | ||
| 347 | 0x00eecf01, | ||
| 348 | 0xf41fe4f0, | ||
| 349 | 0xce98f30b, | ||
| 350 | 0x05e9fd00, | ||
| 351 | 0xc80007f1, | ||
| 352 | 0xd00103f0, | ||
| 353 | 0x04bd000e, | ||
| 354 | 0xb804c0b6, | ||
| 355 | 0x1bf404cd, | ||
| 356 | 0x02abc8d8, | ||
| 357 | /* 0x0207: mmctx_fini_wait */ | ||
| 358 | 0xf11f1bf4, | ||
| 359 | 0xf0c500b7, | ||
| 360 | 0xbbcf01b3, | ||
| 361 | 0x1fb4f000, | ||
| 362 | 0xf410b4b0, | ||
| 363 | 0xa7f0f01b, | ||
| 364 | 0xd021f402, | ||
| 365 | /* 0x0223: mmctx_stop */ | ||
| 366 | 0xc82b0ef4, | ||
| 332 | 0xb4b600ab, | 367 | 0xb4b600ab, |
| 333 | 0x0cb9f010, | 368 | 0x0cb9f010, |
| 334 | 0xb601aec8, | 369 | 0xf112b9f0, |
| 335 | 0xbefd11e4, | 370 | 0xf0c50007, |
| 336 | 0x008bd005, | 371 | 0x0bd00103, |
| 337 | /* 0x01b4: mmctx_exec_loop */ | 372 | /* 0x023b: mmctx_stop_wait */ |
| 338 | /* 0x01b4: mmctx_wait_free */ | 373 | 0xf104bd00, |
| 339 | 0xf0008ecf, | 374 | 0xf0c500b7, |
| 340 | 0x0bf41fe4, | 375 | 0xbbcf01b3, |
| 341 | 0x00ce98fa, | 376 | 0x12bbc800, |
| 342 | 0xd005e9fd, | 377 | /* 0x024b: mmctx_done */ |
| 343 | 0xc0b6c08e, | 378 | 0xbdf31bf4, |
| 344 | 0x04cdb804, | 379 | 0x0199f094, |
| 345 | 0xc8e81bf4, | 380 | 0x170007f1, |
| 346 | 0x1bf402ab, | 381 | 0xd00203f0, |
| 347 | /* 0x01d5: mmctx_fini_wait */ | 382 | 0x04bd0009, |
| 348 | 0x008bcf18, | 383 | /* 0x025e: strand_wait */ |
| 349 | 0xb01fb4f0, | 384 | 0xa0f900f8, |
| 350 | 0x1bf410b4, | 385 | 0xf402a7f0, |
| 351 | 0x02a7f0f7, | 386 | 0xa0fcd021, |
| 352 | 0xf4c921f4, | 387 | /* 0x026a: strand_pre */ |
| 353 | /* 0x01ea: mmctx_stop */ | 388 | 0x97f000f8, |
| 354 | 0xabc81b0e, | 389 | 0xfc07f10c, |
| 355 | 0x10b4b600, | 390 | 0x0203f04a, |
| 356 | 0xf00cb9f0, | 391 | 0xbd0009d0, |
| 357 | 0x8bd012b9, | 392 | 0x5e21f504, |
| 358 | /* 0x01f9: mmctx_stop_wait */ | 393 | /* 0x027f: strand_post */ |
| 359 | 0x008bcf00, | 394 | 0xf000f802, |
| 360 | 0xf412bbc8, | 395 | 0x07f10d97, |
| 361 | /* 0x0202: mmctx_done */ | 396 | 0x03f04afc, |
| 362 | 0x94bdfa1b, | ||
| 363 | 0xf10199f0, | ||
| 364 | 0xf0170007, | ||
| 365 | 0x09d00203, | ||
| 366 | 0xf804bd00, | ||
| 367 | /* 0x0215: strand_wait */ | ||
| 368 | 0xf0a0f900, | ||
| 369 | 0x21f402a7, | ||
| 370 | 0xf8a0fcc9, | ||
| 371 | /* 0x0221: strand_pre */ | ||
| 372 | 0xfc87f100, | ||
| 373 | 0x0283f04a, | ||
| 374 | 0xd00c97f0, | ||
| 375 | 0x21f50089, | ||
| 376 | 0x00f80215, | ||
| 377 | /* 0x0234: strand_post */ | ||
| 378 | 0x4afc87f1, | ||
| 379 | 0xf00283f0, | ||
| 380 | 0x89d00d97, | ||
| 381 | 0x1521f500, | ||
| 382 | /* 0x0247: strand_set */ | ||
| 383 | 0xf100f802, | ||
| 384 | 0xf04ffca7, | ||
| 385 | 0xaba202a3, | ||
| 386 | 0xc7f00500, | ||
| 387 | 0x00acd00f, | ||
| 388 | 0xd00bc7f0, | ||
| 389 | 0x21f500bc, | ||
| 390 | 0xaed00215, | ||
| 391 | 0x0ac7f000, | ||
| 392 | 0xf500bcd0, | ||
| 393 | 0xf8021521, | ||
| 394 | /* 0x0271: strand_ctx_init */ | ||
| 395 | 0xf094bd00, | ||
| 396 | 0x07f10399, | ||
| 397 | 0x03f00f00, | ||
| 398 | 0x0009d002, | 397 | 0x0009d002, |
| 399 | 0x21f504bd, | 398 | 0x21f504bd, |
| 400 | 0xe7f00221, | 399 | 0x00f8025e, |
| 401 | 0x4721f503, | 400 | /* 0x0294: strand_set */ |
| 402 | 0xfca7f102, | 401 | 0xf10fc7f0, |
| 403 | 0x02a3f046, | 402 | 0xf04ffc07, |
| 404 | 0x0400aba0, | 403 | 0x0cd00203, |
| 405 | 0xf040a0d0, | 404 | 0xf004bd00, |
| 406 | 0xbcd001c7, | 405 | 0x07f10bc7, |
| 407 | 0x1521f500, | 406 | 0x03f04afc, |
| 408 | 0x010c9202, | 407 | 0x000cd002, |
| 409 | 0xf000acd0, | 408 | 0x07f104bd, |
| 410 | 0xbcd002c7, | 409 | 0x03f04ffc, |
| 411 | 0x1521f500, | 410 | 0x000ed002, |
| 412 | 0x3421f502, | 411 | 0xc7f004bd, |
| 413 | 0x8087f102, | 412 | 0xfc07f10a, |
| 414 | 0x0684b608, | 413 | 0x0203f04a, |
| 415 | 0xb70089cf, | 414 | 0xbd000cd0, |
| 416 | 0x95220080, | 415 | 0x5e21f504, |
| 417 | /* 0x02ca: ctx_init_strand_loop */ | 416 | /* 0x02d3: strand_ctx_init */ |
| 417 | 0xbd00f802, | ||
| 418 | 0x0399f094, | ||
| 419 | 0x0f0007f1, | ||
| 420 | 0xd00203f0, | ||
| 421 | 0x04bd0009, | ||
| 422 | 0x026a21f5, | ||
| 423 | 0xf503e7f0, | ||
| 424 | 0xbd029421, | ||
| 425 | 0xfc07f1c4, | ||
| 426 | 0x0203f047, | ||
| 427 | 0xbd000cd0, | ||
| 428 | 0x01c7f004, | ||
| 429 | 0x4afc07f1, | ||
| 430 | 0xd00203f0, | ||
| 431 | 0x04bd000c, | ||
| 432 | 0x025e21f5, | ||
| 433 | 0xf1010c92, | ||
| 434 | 0xf046fc07, | ||
| 435 | 0x0cd00203, | ||
| 436 | 0xf004bd00, | ||
| 437 | 0x07f102c7, | ||
| 438 | 0x03f04afc, | ||
| 439 | 0x000cd002, | ||
| 440 | 0x21f504bd, | ||
| 441 | 0x21f5025e, | ||
| 442 | 0x87f1027f, | ||
| 443 | 0x83f04200, | ||
| 444 | 0x0097f102, | ||
| 445 | 0x0293f020, | ||
| 446 | 0x950099cf, | ||
| 447 | /* 0x034a: ctx_init_strand_loop */ | ||
| 418 | 0x8ed008fe, | 448 | 0x8ed008fe, |
| 419 | 0x408ed000, | 449 | 0x408ed000, |
| 420 | 0xb6808acf, | 450 | 0xb6808acf, |
| @@ -428,7 +458,7 @@ uint32_t nvd7_grhub_code[] = { | |||
| 428 | 0x170007f1, | 458 | 0x170007f1, |
| 429 | 0xd00203f0, | 459 | 0xd00203f0, |
| 430 | 0x04bd0009, | 460 | 0x04bd0009, |
| 431 | /* 0x02fe: error */ | 461 | /* 0x037e: error */ |
| 432 | 0x07f100f8, | 462 | 0x07f100f8, |
| 433 | 0x03f00500, | 463 | 0x03f00500, |
| 434 | 0x000fd002, | 464 | 0x000fd002, |
| @@ -436,82 +466,117 @@ uint32_t nvd7_grhub_code[] = { | |||
| 436 | 0x0007f101, | 466 | 0x0007f101, |
| 437 | 0x0303f007, | 467 | 0x0303f007, |
| 438 | 0xbd000fd0, | 468 | 0xbd000fd0, |
| 439 | /* 0x031b: init */ | 469 | /* 0x039b: init */ |
| 440 | 0xbd00f804, | 470 | 0xbd00f804, |
| 441 | 0x0004fe04, | 471 | 0x0007fe04, |
| 442 | 0xf10007fe, | 472 | 0x420017f1, |
| 443 | 0xf0120017, | 473 | 0xcf0013f0, |
| 444 | 0x12d00227, | 474 | 0x11e70011, |
| 445 | 0xb117f100, | 475 | 0x14b60109, |
| 446 | 0x0010fe05, | 476 | 0x0014fe08, |
| 447 | 0x040017f1, | 477 | 0xf10227f0, |
| 448 | 0xf1c010d0, | 478 | 0xf0120007, |
| 449 | 0xb6040437, | 479 | 0x02d00003, |
| 450 | 0x27f10634, | 480 | 0xf104bd00, |
| 451 | 0x32d02003, | 481 | 0xfe06c817, |
| 452 | 0x0427f100, | 482 | 0x24bd0010, |
| 453 | 0x0132d020, | 483 | 0x070007f1, |
| 484 | 0xd00003f0, | ||
| 485 | 0x04bd0002, | ||
| 486 | 0x200327f1, | ||
| 487 | 0x010007f1, | ||
| 488 | 0xd00103f0, | ||
| 489 | 0x04bd0002, | ||
| 490 | 0x200427f1, | ||
| 491 | 0x010407f1, | ||
| 492 | 0xd00103f0, | ||
| 493 | 0x04bd0002, | ||
| 454 | 0x200b27f1, | 494 | 0x200b27f1, |
| 455 | 0xf10232d0, | 495 | 0x010807f1, |
| 456 | 0xd0200c27, | 496 | 0xd00103f0, |
| 457 | 0x27f10732, | 497 | 0x04bd0002, |
| 458 | 0x24b60c24, | 498 | 0x200c27f1, |
| 459 | 0x0003b906, | 499 | 0x011c07f1, |
| 460 | 0xf10023d0, | 500 | 0xd00103f0, |
| 501 | 0x04bd0002, | ||
| 502 | 0xf1010392, | ||
| 503 | 0xf0090007, | ||
| 504 | 0x03d00303, | ||
| 505 | 0xf104bd00, | ||
| 461 | 0xf0870427, | 506 | 0xf0870427, |
| 462 | 0x12d00023, | 507 | 0x07f10023, |
| 463 | 0x0012b700, | 508 | 0x03f00400, |
| 464 | 0x0427f001, | 509 | 0x0002d000, |
| 465 | 0xf40012d0, | 510 | 0x27f004bd, |
| 466 | 0xe7f11031, | 511 | 0x0007f104, |
| 467 | 0xe3f09604, | 512 | 0x0003f003, |
| 468 | 0x6821f440, | 513 | 0xbd0002d0, |
| 469 | 0x8090f1c7, | 514 | 0x1031f404, |
| 470 | 0xf4f00301, | 515 | 0x9604e7f1, |
| 471 | 0x020f801f, | 516 | 0xf440e3f0, |
| 472 | 0xbb0117f0, | 517 | 0xfeb96821, |
| 473 | 0x12b6041f, | 518 | 0x90f1c702, |
| 474 | 0x0c27f101, | 519 | 0xf0030180, |
| 475 | 0x0624b604, | 520 | 0x0f801ff4, |
| 476 | 0xd00021d0, | 521 | 0x0117f002, |
| 477 | 0x17f14021, | 522 | 0xb6041fbb, |
| 478 | 0x0e980100, | 523 | 0x07f10112, |
| 479 | 0x010f9800, | 524 | 0x03f00300, |
| 480 | 0x014721f5, | 525 | 0x0001d001, |
| 481 | 0x070037f1, | 526 | 0x07f104bd, |
| 482 | 0x950634b6, | 527 | 0x03f00400, |
| 483 | 0x34d00814, | 528 | 0x0001d001, |
| 484 | 0x4034d000, | 529 | 0x17f104bd, |
| 485 | 0x130030b7, | 530 | 0xf7f00100, |
| 486 | 0xb6001fbb, | 531 | 0xb521f502, |
| 487 | 0x3fd002f5, | 532 | 0xc721f507, |
| 488 | 0x0815b600, | 533 | 0x10f7f007, |
| 489 | 0xb60110b6, | 534 | 0x081421f5, |
| 490 | 0x1fb90814, | 535 | 0x98000e98, |
| 491 | 0x7121f502, | 536 | 0x21f5010f, |
| 492 | 0x001fbb02, | 537 | 0x14950150, |
| 493 | 0xf1020398, | 538 | 0x0007f108, |
| 494 | 0xf0200047, | 539 | 0x0103f0c0, |
| 495 | /* 0x03f6: init_gpc */ | 540 | 0xbd0004d0, |
| 496 | 0x4ea05043, | 541 | 0x0007f104, |
| 497 | 0x1fb90804, | 542 | 0x0103f0c1, |
| 498 | 0x8d21f402, | 543 | 0xbd0004d0, |
| 499 | 0x010c4ea0, | 544 | 0x0030b704, |
| 500 | 0x21f4f4bd, | 545 | 0x001fbb13, |
| 501 | 0x044ea08d, | 546 | 0xf102f5b6, |
| 502 | 0x8d21f401, | 547 | 0xf0d30007, |
| 503 | 0x01004ea0, | 548 | 0x0fd00103, |
| 504 | 0xf402f7f0, | 549 | 0xb604bd00, |
| 505 | 0x4ea08d21, | 550 | 0x10b60815, |
| 506 | /* 0x041e: init_gpc_wait */ | 551 | 0x0814b601, |
| 507 | 0x21f40800, | 552 | 0xf5021fb9, |
| 508 | 0x1fffc868, | 553 | 0xbb02d321, |
| 509 | 0xa0fa0bf4, | 554 | 0x0398001f, |
| 510 | 0xf408044e, | 555 | 0x0047f102, |
| 511 | 0x1fbb6821, | 556 | 0x5043f020, |
| 512 | 0x0040b700, | 557 | /* 0x04f4: init_gpc */ |
| 513 | 0x0132b680, | 558 | 0x08044ea0, |
| 514 | 0xf1be1bf4, | 559 | 0xf4021fb9, |
| 560 | 0x4ea09d21, | ||
| 561 | 0xf4bd010c, | ||
| 562 | 0xa09d21f4, | ||
| 563 | 0xf401044e, | ||
| 564 | 0x4ea09d21, | ||
| 565 | 0xf7f00100, | ||
| 566 | 0x9d21f402, | ||
| 567 | 0x08004ea0, | ||
| 568 | /* 0x051c: init_gpc_wait */ | ||
| 569 | 0xc86821f4, | ||
| 570 | 0x0bf41fff, | ||
| 571 | 0x044ea0fa, | ||
| 572 | 0x6821f408, | ||
| 573 | 0xb7001fbb, | ||
| 574 | 0xb6800040, | ||
| 575 | 0x1bf40132, | ||
| 576 | 0x00f7f0be, | ||
| 577 | 0x081421f5, | ||
| 578 | 0xf500f7f0, | ||
| 579 | 0xf107b521, | ||
| 515 | 0xf0010007, | 580 | 0xf0010007, |
| 516 | 0x01d00203, | 581 | 0x01d00203, |
| 517 | 0xbd04bd00, | 582 | 0xbd04bd00, |
| @@ -519,402 +584,399 @@ uint32_t nvd7_grhub_code[] = { | |||
| 519 | 0x080007f1, | 584 | 0x080007f1, |
| 520 | 0xd00203f0, | 585 | 0xd00203f0, |
| 521 | 0x04bd0001, | 586 | 0x04bd0001, |
| 522 | /* 0x0458: main */ | 587 | /* 0x0564: main */ |
| 523 | 0xf40031f4, | 588 | 0xf40031f4, |
| 524 | 0xd7f00028, | 589 | 0xd7f00028, |
| 525 | 0x3921f410, | 590 | 0x3921f410, |
| 526 | 0xb1f401f4, | 591 | 0xb1f401f4, |
| 527 | 0xf54001e4, | 592 | 0xf54001e4, |
| 528 | 0xbd00de1b, | 593 | 0xbd00e91b, |
| 529 | 0x0499f094, | 594 | 0x0499f094, |
| 530 | 0x0f0007f1, | 595 | 0x0f0007f1, |
| 531 | 0xd00203f0, | 596 | 0xd00203f0, |
| 532 | 0x04bd0009, | 597 | 0x04bd0009, |
| 533 | 0x0b0017f1, | 598 | 0xc00017f1, |
| 534 | 0xcf0614b6, | 599 | 0xcf0213f0, |
| 535 | 0x11cf4012, | 600 | 0x27f10011, |
| 536 | 0x1f13c800, | 601 | 0x23f0c100, |
| 537 | 0x00870bf5, | 602 | 0x0022cf02, |
| 538 | 0xf41f23c8, | 603 | 0xf51f13c8, |
| 539 | 0x20f9620b, | 604 | 0xc800890b, |
| 540 | 0xbd0212b9, | 605 | 0x0bf41f23, |
| 541 | 0x0799f094, | 606 | 0xb920f962, |
| 542 | 0x0f0007f1, | 607 | 0x94bd0212, |
| 543 | 0xd00203f0, | ||
| 544 | 0x04bd0009, | ||
| 545 | 0xf40132f4, | ||
| 546 | 0x21f50231, | ||
| 547 | 0x94bd082f, | ||
| 548 | 0xf10799f0, | 608 | 0xf10799f0, |
| 549 | 0xf0170007, | 609 | 0xf00f0007, |
| 550 | 0x09d00203, | 610 | 0x09d00203, |
| 551 | 0xfc04bd00, | 611 | 0xf404bd00, |
| 552 | 0xf094bd20, | 612 | 0x31f40132, |
| 553 | 0x07f10699, | 613 | 0xe821f502, |
| 554 | 0x03f00f00, | 614 | 0xf094bd09, |
| 555 | 0x0009d002, | 615 | 0x07f10799, |
| 556 | 0x31f404bd, | ||
| 557 | 0x2f21f501, | ||
| 558 | 0xf094bd08, | ||
| 559 | 0x07f10699, | ||
| 560 | 0x03f01700, | 616 | 0x03f01700, |
| 561 | 0x0009d002, | 617 | 0x0009d002, |
| 562 | 0x0ef404bd, | 618 | 0x20fc04bd, |
| 563 | /* 0x04f9: chsw_prev_no_next */ | ||
| 564 | 0xb920f931, | ||
| 565 | 0x32f40212, | ||
| 566 | 0x0232f401, | ||
| 567 | 0x082f21f5, | ||
| 568 | 0x17f120fc, | ||
| 569 | 0x14b60b00, | ||
| 570 | 0x0012d006, | ||
| 571 | /* 0x0517: chsw_no_prev */ | ||
| 572 | 0xc8130ef4, | ||
| 573 | 0x0bf41f23, | ||
| 574 | 0x0131f40d, | ||
| 575 | 0xf50232f4, | ||
| 576 | /* 0x0527: chsw_done */ | ||
| 577 | 0xf1082f21, | ||
| 578 | 0xb60b0c17, | ||
| 579 | 0x27f00614, | ||
| 580 | 0x0012d001, | ||
| 581 | 0x99f094bd, | 619 | 0x99f094bd, |
| 582 | 0x0007f104, | 620 | 0x0007f106, |
| 621 | 0x0203f00f, | ||
| 622 | 0xbd0009d0, | ||
| 623 | 0x0131f404, | ||
| 624 | 0x09e821f5, | ||
| 625 | 0x99f094bd, | ||
| 626 | 0x0007f106, | ||
| 583 | 0x0203f017, | 627 | 0x0203f017, |
| 584 | 0xbd0009d0, | 628 | 0xbd0009d0, |
| 585 | 0x130ef504, | 629 | 0x330ef404, |
| 586 | /* 0x0549: main_not_ctx_switch */ | 630 | /* 0x060c: chsw_prev_no_next */ |
| 587 | 0x01e4b0ff, | 631 | 0x12b920f9, |
| 588 | 0xb90d1bf4, | 632 | 0x0132f402, |
| 589 | 0x21f502f2, | 633 | 0xf50232f4, |
| 590 | 0x0ef407bb, | 634 | 0xfc09e821, |
| 591 | /* 0x0559: main_not_ctx_chan */ | 635 | 0x0007f120, |
| 592 | 0x02e4b046, | 636 | 0x0203f0c0, |
| 593 | 0xbd321bf4, | 637 | 0xbd0002d0, |
| 594 | 0x0799f094, | 638 | 0x130ef404, |
| 595 | 0x0f0007f1, | 639 | /* 0x062c: chsw_no_prev */ |
| 640 | 0xf41f23c8, | ||
| 641 | 0x31f40d0b, | ||
| 642 | 0x0232f401, | ||
| 643 | 0x09e821f5, | ||
| 644 | /* 0x063c: chsw_done */ | ||
| 645 | 0xf10127f0, | ||
| 646 | 0xf0c30007, | ||
| 647 | 0x02d00203, | ||
| 648 | 0xbd04bd00, | ||
| 649 | 0x0499f094, | ||
| 650 | 0x170007f1, | ||
| 596 | 0xd00203f0, | 651 | 0xd00203f0, |
| 597 | 0x04bd0009, | 652 | 0x04bd0009, |
| 598 | 0xf40132f4, | 653 | 0xff080ef5, |
| 599 | 0x21f50232, | 654 | /* 0x0660: main_not_ctx_switch */ |
| 600 | 0x94bd082f, | 655 | 0xf401e4b0, |
| 656 | 0xf2b90d1b, | ||
| 657 | 0x7821f502, | ||
| 658 | 0x460ef409, | ||
| 659 | /* 0x0670: main_not_ctx_chan */ | ||
| 660 | 0xf402e4b0, | ||
| 661 | 0x94bd321b, | ||
| 601 | 0xf10799f0, | 662 | 0xf10799f0, |
| 602 | 0xf0170007, | 663 | 0xf00f0007, |
| 603 | 0x09d00203, | 664 | 0x09d00203, |
| 604 | 0xf404bd00, | 665 | 0xf404bd00, |
| 605 | /* 0x058e: main_not_ctx_save */ | 666 | 0x32f40132, |
| 606 | 0xef94110e, | 667 | 0xe821f502, |
| 607 | 0x01f5f010, | 668 | 0xf094bd09, |
| 608 | 0x02fe21f5, | 669 | 0x07f10799, |
| 609 | 0xfec00ef5, | 670 | 0x03f01700, |
| 610 | /* 0x059c: main_done */ | 671 | 0x0009d002, |
| 611 | 0x29f024bd, | 672 | 0x0ef404bd, |
| 612 | 0x0007f11f, | 673 | /* 0x06a5: main_not_ctx_save */ |
| 613 | 0x0203f008, | 674 | 0x10ef9411, |
| 614 | 0xbd0002d0, | 675 | 0xf501f5f0, |
| 615 | 0xab0ef504, | 676 | 0xf5037e21, |
| 616 | /* 0x05b1: ih */ | 677 | /* 0x06b3: main_done */ |
| 617 | 0xfe80f9fe, | 678 | 0xbdfeb50e, |
| 618 | 0x80f90188, | 679 | 0x1f29f024, |
| 619 | 0xa0f990f9, | 680 | 0x080007f1, |
| 620 | 0xd0f9b0f9, | 681 | 0xd00203f0, |
| 621 | 0xf0f9e0f9, | 682 | 0x04bd0002, |
| 622 | 0x0acf04bd, | 683 | 0xfea00ef5, |
| 623 | 0x04abc480, | 684 | /* 0x06c8: ih */ |
| 624 | 0xf11d0bf4, | 685 | 0x88fe80f9, |
| 625 | 0xf01900b7, | 686 | 0xf980f901, |
| 626 | 0xbecf10d7, | 687 | 0xf9a0f990, |
| 627 | 0x00bfcf40, | 688 | 0xf9d0f9b0, |
| 689 | 0xbdf0f9e0, | ||
| 690 | 0x00a7f104, | ||
| 691 | 0x00a3f002, | ||
| 692 | 0xc400aacf, | ||
| 693 | 0x0bf404ab, | ||
| 694 | 0x10d7f030, | ||
| 695 | 0x1a00e7f1, | ||
| 696 | 0xcf00e3f0, | ||
| 697 | 0xf7f100ee, | ||
| 698 | 0xf3f01900, | ||
| 699 | 0x00ffcf00, | ||
| 628 | 0xb70421f4, | 700 | 0xb70421f4, |
| 629 | 0xf00400b0, | 701 | 0xf00400b0, |
| 630 | 0xbed001e7, | 702 | 0x07f101e7, |
| 631 | /* 0x05e9: ih_no_fifo */ | 703 | 0x03f01d00, |
| 632 | 0x00abe400, | 704 | 0x000ed000, |
| 633 | 0x0d0bf401, | 705 | /* 0x071a: ih_no_fifo */ |
| 634 | 0xf110d7f0, | 706 | 0xabe404bd, |
| 635 | 0xf44001e7, | 707 | 0x0bf40100, |
| 636 | /* 0x05fa: ih_no_ctxsw */ | 708 | 0x10d7f00d, |
| 637 | 0xb7f10421, | 709 | 0x4001e7f1, |
| 638 | 0xb0bd0104, | 710 | /* 0x072b: ih_no_ctxsw */ |
| 639 | 0xf4b4abff, | 711 | 0xe40421f4, |
| 640 | 0xa7f10d0b, | 712 | 0xf40400ab, |
| 641 | 0xa4b60c1c, | 713 | 0xb7f1140b, |
| 642 | 0x00abd006, | 714 | 0xbfb90100, |
| 643 | /* 0x0610: ih_no_other */ | 715 | 0x44e7f102, |
| 644 | 0xfc400ad0, | 716 | 0x40e3f001, |
| 717 | /* 0x0743: ih_no_fwmthd */ | ||
| 718 | 0xf19d21f4, | ||
| 719 | 0xbd0104b7, | ||
| 720 | 0xb4abffb0, | ||
| 721 | 0xf10f0bf4, | ||
| 722 | 0xf0070007, | ||
| 723 | 0x0bd00303, | ||
| 724 | /* 0x075b: ih_no_other */ | ||
| 725 | 0xf104bd00, | ||
| 726 | 0xf0010007, | ||
| 727 | 0x0ad00003, | ||
| 728 | 0xfc04bd00, | ||
| 645 | 0xfce0fcf0, | 729 | 0xfce0fcf0, |
| 646 | 0xfcb0fcd0, | 730 | 0xfcb0fcd0, |
| 647 | 0xfc90fca0, | 731 | 0xfc90fca0, |
| 648 | 0x0088fe80, | 732 | 0x0088fe80, |
| 649 | 0x32f480fc, | 733 | 0x32f480fc, |
| 650 | /* 0x062b: ctx_4160s */ | 734 | /* 0x077f: ctx_4160s */ |
| 651 | 0xf101f800, | 735 | 0xf001f800, |
| 652 | 0xf04160e7, | 736 | 0xffb901f7, |
| 653 | 0xf7f040e3, | 737 | 0x60e7f102, |
| 654 | 0x8d21f401, | 738 | 0x40e3f041, |
| 655 | /* 0x0638: ctx_4160s_wait */ | 739 | /* 0x078f: ctx_4160s_wait */ |
| 656 | 0xc86821f4, | 740 | 0xf19d21f4, |
| 657 | 0x0bf404ff, | ||
| 658 | /* 0x0643: ctx_4160c */ | ||
| 659 | 0xf100f8fa, | ||
| 660 | 0xf04160e7, | 741 | 0xf04160e7, |
| 661 | 0xf4bd40e3, | 742 | 0x21f440e3, |
| 662 | 0xf88d21f4, | 743 | 0x02ffb968, |
| 663 | /* 0x0651: ctx_4170s */ | 744 | 0xf404ffc8, |
| 664 | 0x70e7f100, | 745 | 0x00f8f00b, |
| 746 | /* 0x07a4: ctx_4160c */ | ||
| 747 | 0xffb9f4bd, | ||
| 748 | 0x60e7f102, | ||
| 665 | 0x40e3f041, | 749 | 0x40e3f041, |
| 666 | 0xf410f5f0, | 750 | 0xf89d21f4, |
| 667 | 0x00f88d21, | 751 | /* 0x07b5: ctx_4170s */ |
| 668 | /* 0x0660: ctx_4170w */ | 752 | 0x10f5f000, |
| 669 | 0x4170e7f1, | 753 | 0xf102ffb9, |
| 670 | 0xf440e3f0, | 754 | 0xf04170e7, |
| 671 | 0xf4f06821, | 755 | 0x21f440e3, |
| 672 | 0xf31bf410, | 756 | /* 0x07c7: ctx_4170w */ |
| 673 | /* 0x0672: ctx_redswitch */ | 757 | 0xf100f89d, |
| 674 | 0xe7f100f8, | 758 | 0xf04170e7, |
| 675 | 0xe4b60614, | 759 | 0x21f440e3, |
| 676 | 0x70f7f106, | 760 | 0x02ffb968, |
| 677 | 0x00efd002, | 761 | 0xf410f4f0, |
| 678 | /* 0x0683: ctx_redswitch_delay */ | 762 | 0x00f8f01b, |
| 679 | 0xb608f7f0, | 763 | /* 0x07dc: ctx_redswitch */ |
| 680 | 0x1bf401f2, | 764 | 0x0200e7f1, |
| 681 | 0x70f7f1fd, | 765 | 0xf040e5f0, |
| 682 | 0x00efd007, | 766 | 0xe5f020e5, |
| 683 | /* 0x0692: ctx_86c */ | 767 | 0x0007f110, |
| 684 | 0xe7f100f8, | 768 | 0x0103f085, |
| 685 | 0xe4b6086c, | 769 | 0xbd000ed0, |
| 686 | 0x00efd006, | 770 | 0x08f7f004, |
| 687 | 0x8a14e7f1, | 771 | /* 0x07f8: ctx_redswitch_delay */ |
| 688 | 0xf440e3f0, | 772 | 0xf401f2b6, |
| 689 | 0xe7f18d21, | 773 | 0xe5f1fd1b, |
| 690 | 0xe3f0a86c, | 774 | 0xe5f10400, |
| 691 | 0x8d21f441, | 775 | 0x07f10100, |
| 692 | /* 0x06b2: ctx_load */ | 776 | 0x03f08500, |
| 777 | 0x000ed001, | ||
| 778 | 0x00f804bd, | ||
| 779 | /* 0x0814: ctx_86c */ | ||
| 780 | 0x1b0007f1, | ||
| 781 | 0xd00203f0, | ||
| 782 | 0x04bd000f, | ||
| 783 | 0xf102ffb9, | ||
| 784 | 0xf08a14e7, | ||
| 785 | 0x21f440e3, | ||
| 786 | 0x02ffb99d, | ||
| 787 | 0xa86ce7f1, | ||
| 788 | 0xf441e3f0, | ||
| 789 | 0x00f89d21, | ||
| 790 | /* 0x083c: ctx_mem */ | ||
| 791 | 0x840007f1, | ||
| 792 | 0xd00203f0, | ||
| 793 | 0x04bd000f, | ||
| 794 | /* 0x0848: ctx_mem_wait */ | ||
| 795 | 0x8400f7f1, | ||
| 796 | 0xcf02f3f0, | ||
| 797 | 0xfffd00ff, | ||
| 798 | 0xf31bf405, | ||
| 799 | /* 0x085a: ctx_load */ | ||
| 693 | 0x94bd00f8, | 800 | 0x94bd00f8, |
| 694 | 0xf10599f0, | 801 | 0xf10599f0, |
| 695 | 0xf00f0007, | 802 | 0xf00f0007, |
| 696 | 0x09d00203, | 803 | 0x09d00203, |
| 697 | 0xf004bd00, | 804 | 0xf004bd00, |
| 698 | 0x21f40ca7, | 805 | 0x21f40ca7, |
| 699 | 0x2417f1c9, | 806 | 0xf1f4bdd0, |
| 700 | 0x0614b60a, | 807 | 0xf0890007, |
| 701 | 0xf10010d0, | 808 | 0x0fd00203, |
| 702 | 0xb60b0037, | 809 | 0xf104bd00, |
| 703 | 0x32d00634, | 810 | 0xf0c10007, |
| 704 | 0x0c17f140, | 811 | 0x02d00203, |
| 705 | 0x0614b60a, | 812 | 0xf104bd00, |
| 706 | 0xd00747f0, | 813 | 0xf0830007, |
| 707 | 0x14d00012, | 814 | 0x02d00203, |
| 708 | /* 0x06ed: ctx_chan_wait_0 */ | 815 | 0xf004bd00, |
| 709 | 0x4014cf40, | 816 | 0x21f507f7, |
| 710 | 0xf41f44f0, | 817 | 0x07f1083c, |
| 711 | 0x32d0fa1b, | 818 | 0x03f0c000, |
| 712 | 0x000bfe00, | 819 | 0x0002d002, |
| 713 | 0xb61f2af0, | 820 | 0x0bfe04bd, |
| 714 | 0x20b60424, | 821 | 0x1f2af000, |
| 715 | 0xf094bd02, | 822 | 0xb60424b6, |
| 823 | 0x94bd0220, | ||
| 824 | 0xf10899f0, | ||
| 825 | 0xf00f0007, | ||
| 826 | 0x09d00203, | ||
| 827 | 0xf104bd00, | ||
| 828 | 0xf0810007, | ||
| 829 | 0x02d00203, | ||
| 830 | 0xf104bd00, | ||
| 831 | 0xf1000027, | ||
| 832 | 0xf0800023, | ||
| 833 | 0x07f10225, | ||
| 834 | 0x03f08800, | ||
| 835 | 0x0002d002, | ||
| 836 | 0x17f004bd, | ||
| 837 | 0x0027f110, | ||
| 838 | 0x0223f002, | ||
| 839 | 0xf80512fa, | ||
| 840 | 0xf094bd03, | ||
| 716 | 0x07f10899, | 841 | 0x07f10899, |
| 717 | 0x03f00f00, | 842 | 0x03f01700, |
| 718 | 0x0009d002, | 843 | 0x0009d002, |
| 719 | 0x17f104bd, | 844 | 0x019804bd, |
| 720 | 0x14b60a04, | 845 | 0x1814b681, |
| 721 | 0x0012d006, | 846 | 0xb6800298, |
| 722 | 0x0a2017f1, | 847 | 0x12fd0825, |
| 723 | 0xf00614b6, | 848 | 0x16018005, |
| 724 | 0x23f10227, | ||
| 725 | 0x12d08000, | ||
| 726 | 0x1017f000, | ||
| 727 | 0x020027f1, | ||
| 728 | 0xfa0223f0, | ||
| 729 | 0x03f80512, | ||
| 730 | 0x99f094bd, | 849 | 0x99f094bd, |
| 731 | 0x0007f108, | 850 | 0x0007f109, |
| 732 | 0x0203f017, | 851 | 0x0203f00f, |
| 733 | 0xbd0009d0, | 852 | 0xbd0009d0, |
| 734 | 0x81019804, | 853 | 0x0007f104, |
| 735 | 0x981814b6, | 854 | 0x0203f081, |
| 736 | 0x25b68002, | 855 | 0xbd0001d0, |
| 737 | 0x0512fd08, | 856 | 0x0127f004, |
| 738 | 0xbd160180, | 857 | 0x880007f1, |
| 739 | 0x0999f094, | ||
| 740 | 0x0f0007f1, | ||
| 741 | 0xd00203f0, | ||
| 742 | 0x04bd0009, | ||
| 743 | 0x0a0427f1, | ||
| 744 | 0xd00624b6, | ||
| 745 | 0x27f00021, | ||
| 746 | 0x2017f101, | ||
| 747 | 0x0614b60a, | ||
| 748 | 0xf10012d0, | ||
| 749 | 0xf0010017, | ||
| 750 | 0x01fa0613, | ||
| 751 | 0xbd03f805, | ||
| 752 | 0x0999f094, | ||
| 753 | 0x170007f1, | ||
| 754 | 0xd00203f0, | 858 | 0xd00203f0, |
| 755 | 0x04bd0009, | 859 | 0x04bd0002, |
| 860 | 0x010017f1, | ||
| 861 | 0xfa0613f0, | ||
| 862 | 0x03f80501, | ||
| 756 | 0x99f094bd, | 863 | 0x99f094bd, |
| 757 | 0x0007f105, | 864 | 0x0007f109, |
| 758 | 0x0203f017, | 865 | 0x0203f017, |
| 759 | 0xbd0009d0, | 866 | 0xbd0009d0, |
| 760 | /* 0x07bb: ctx_chan */ | 867 | 0xf094bd04, |
| 761 | 0xf500f804, | 868 | 0x07f10599, |
| 762 | 0xf5062b21, | 869 | 0x03f01700, |
| 763 | 0xf006b221, | 870 | 0x0009d002, |
| 764 | 0x21f40ca7, | 871 | 0x00f804bd, |
| 765 | 0x1017f1c9, | 872 | /* 0x0978: ctx_chan */ |
| 766 | 0x0614b60a, | 873 | 0x077f21f5, |
| 767 | 0xd00527f0, | 874 | 0x085a21f5, |
| 768 | /* 0x07d6: ctx_chan_wait */ | 875 | 0xf40ca7f0, |
| 769 | 0x12cf0012, | 876 | 0xf7f0d021, |
| 770 | 0x0522fd00, | 877 | 0x3c21f505, |
| 771 | 0xf5fa1bf4, | 878 | 0xa421f508, |
| 772 | 0xf8064321, | 879 | /* 0x0993: ctx_mmio_exec */ |
| 773 | /* 0x07e5: ctx_mmio_exec */ | 880 | 0x9800f807, |
| 774 | 0x41039800, | 881 | 0x07f14103, |
| 775 | 0x0a0427f1, | 882 | 0x03f08100, |
| 776 | 0xd00624b6, | 883 | 0x0003d002, |
| 777 | 0x34bd0023, | 884 | 0x34bd04bd, |
| 778 | /* 0x07f4: ctx_mmio_loop */ | 885 | /* 0x09a4: ctx_mmio_loop */ |
| 779 | 0xf4ff34c4, | 886 | 0xf4ff34c4, |
| 780 | 0x57f10f1b, | 887 | 0x57f10f1b, |
| 781 | 0x53f00200, | 888 | 0x53f00200, |
| 782 | 0x0535fa06, | 889 | 0x0535fa06, |
| 783 | /* 0x0806: ctx_mmio_pull */ | 890 | /* 0x09b6: ctx_mmio_pull */ |
| 784 | 0x4e9803f8, | 891 | 0x4e9803f8, |
| 785 | 0x814f9880, | 892 | 0x814f9880, |
| 786 | 0xb68d21f4, | 893 | 0xb69d21f4, |
| 787 | 0x12b60830, | 894 | 0x12b60830, |
| 788 | 0xdf1bf401, | 895 | 0xdf1bf401, |
| 789 | /* 0x0818: ctx_mmio_done */ | 896 | /* 0x09c8: ctx_mmio_done */ |
| 790 | 0xd0160398, | 897 | 0xf1160398, |
| 791 | 0x00800023, | 898 | 0xf0810007, |
| 792 | 0x0017f140, | 899 | 0x03d00203, |
| 793 | 0x0613f001, | 900 | 0x8004bd00, |
| 794 | 0xf80601fa, | 901 | 0x17f14000, |
| 795 | /* 0x082f: ctx_xfer */ | 902 | 0x13f00100, |
| 796 | 0xf100f803, | 903 | 0x0601fa06, |
| 797 | 0xb60c00f7, | 904 | 0x00f803f8, |
| 798 | 0xe7f006f4, | 905 | /* 0x09e8: ctx_xfer */ |
| 799 | 0x80fed004, | 906 | 0xf104e7f0, |
| 800 | /* 0x083c: ctx_xfer_idle */ | 907 | 0xf0020007, |
| 801 | 0xf100fecf, | 908 | 0x0ed00303, |
| 802 | 0xf42000e4, | 909 | /* 0x09f7: ctx_xfer_idle */ |
| 803 | 0x11f4f91b, | 910 | 0xf104bd00, |
| 804 | 0x1102f406, | 911 | 0xf00000e7, |
| 805 | /* 0x084c: ctx_xfer_pre */ | 912 | 0xeecf03e3, |
| 806 | 0xf510f7f0, | 913 | 0x00e4f100, |
| 807 | 0xf5069221, | 914 | 0xf21bf420, |
| 808 | 0xf4062b21, | 915 | 0xf40611f4, |
| 809 | /* 0x085a: ctx_xfer_pre_load */ | 916 | /* 0x0a0e: ctx_xfer_pre */ |
| 810 | 0xf7f01c11, | 917 | 0xf7f01102, |
| 811 | 0x5121f502, | 918 | 0x1421f510, |
| 812 | 0x6021f506, | 919 | 0x7f21f508, |
| 813 | 0x7221f506, | 920 | 0x1c11f407, |
| 814 | 0xf5f4bd06, | 921 | /* 0x0a1c: ctx_xfer_pre_load */ |
| 815 | 0xf5065121, | 922 | 0xf502f7f0, |
| 816 | /* 0x0873: ctx_xfer_exec */ | 923 | 0xf507b521, |
| 817 | 0x9806b221, | 924 | 0xf507c721, |
| 818 | 0x27f11601, | 925 | 0xbd07dc21, |
| 819 | 0x24b60414, | 926 | 0xb521f5f4, |
| 820 | 0x0020d006, | 927 | 0x5a21f507, |
| 821 | 0xa500e7f1, | 928 | /* 0x0a35: ctx_xfer_exec */ |
| 822 | 0xb941e3f0, | 929 | 0x16019808, |
| 823 | 0x21f4021f, | 930 | 0x07f124bd, |
| 824 | 0x04e0b68d, | 931 | 0x03f00500, |
| 825 | 0xf001fcf0, | 932 | 0x0002d001, |
| 826 | 0x24b6022c, | 933 | 0x1fb904bd, |
| 827 | 0x05f2fd01, | 934 | 0x00e7f102, |
| 828 | 0xf18d21f4, | 935 | 0x41e3f0a5, |
| 829 | 0xf04afc17, | 936 | 0xf09d21f4, |
| 830 | 0x27f00213, | 937 | 0x2cf001fc, |
| 831 | 0x0012d00c, | 938 | 0x0124b602, |
| 832 | 0x021521f5, | 939 | 0xb905f2fd, |
| 833 | 0x47fc27f1, | 940 | 0xe7f102ff, |
| 834 | 0xd00223f0, | 941 | 0xe3f0a504, |
| 835 | 0x2cf00020, | 942 | 0x9d21f441, |
| 943 | 0x026a21f5, | ||
| 944 | 0x07f124bd, | ||
| 945 | 0x03f047fc, | ||
| 946 | 0x0002d002, | ||
| 947 | 0x2cf004bd, | ||
| 836 | 0x0320b601, | 948 | 0x0320b601, |
| 837 | 0xf00012d0, | 949 | 0x4afc07f1, |
| 838 | 0xa5f001ac, | 950 | 0xd00203f0, |
| 839 | 0x00b7f006, | 951 | 0x04bd0002, |
| 840 | 0x98000c98, | 952 | 0xf001acf0, |
| 841 | 0xe7f0010d, | 953 | 0xb7f006a5, |
| 842 | 0x6621f500, | 954 | 0x000c9800, |
| 843 | 0x08a7f001, | 955 | 0xf0010d98, |
| 844 | 0x010921f5, | 956 | 0x21f500e7, |
| 845 | 0x021521f5, | 957 | 0xa7f0016f, |
| 846 | 0xf02201f4, | 958 | 0x1021f508, |
| 847 | 0x21f40ca7, | 959 | 0x5e21f501, |
| 848 | 0x1017f1c9, | 960 | 0x1301f402, |
| 849 | 0x0614b60a, | 961 | 0xf40ca7f0, |
| 850 | 0xd00527f0, | 962 | 0xf7f0d021, |
| 851 | /* 0x08fa: ctx_xfer_post_save_wait */ | 963 | 0x3c21f505, |
| 852 | 0x12cf0012, | 964 | 0x3202f408, |
| 853 | 0x0522fd00, | 965 | /* 0x0ac4: ctx_xfer_post */ |
| 854 | 0xf4fa1bf4, | 966 | 0xf502f7f0, |
| 855 | /* 0x0906: ctx_xfer_post */ | 967 | 0xbd07b521, |
| 856 | 0xf7f03202, | 968 | 0x1421f5f4, |
| 857 | 0x5121f502, | 969 | 0x7f21f508, |
| 858 | 0xf5f4bd06, | 970 | 0xc721f502, |
| 859 | 0xf5069221, | 971 | 0xf5f4bd07, |
| 860 | 0xf5023421, | 972 | 0xf407b521, |
| 861 | 0xbd066021, | 973 | 0x01981011, |
| 862 | 0x5121f5f4, | 974 | 0x0511fd40, |
| 863 | 0x1011f406, | 975 | 0xf5070bf4, |
| 864 | 0xfd400198, | 976 | /* 0x0aef: ctx_xfer_no_post_mmio */ |
| 865 | 0x0bf40511, | 977 | 0xf5099321, |
| 866 | 0xe521f507, | 978 | /* 0x0af3: ctx_xfer_done */ |
| 867 | /* 0x0931: ctx_xfer_no_post_mmio */ | 979 | 0xf807a421, |
| 868 | 0x4321f507, | ||
| 869 | /* 0x0935: ctx_xfer_done */ | ||
| 870 | 0x0000f806, | ||
| 871 | 0x00000000, | ||
| 872 | 0x00000000, | ||
| 873 | 0x00000000, | ||
| 874 | 0x00000000, | ||
| 875 | 0x00000000, | ||
| 876 | 0x00000000, | ||
| 877 | 0x00000000, | ||
| 878 | 0x00000000, | ||
| 879 | 0x00000000, | ||
| 880 | 0x00000000, | ||
| 881 | 0x00000000, | ||
| 882 | 0x00000000, | ||
| 883 | 0x00000000, | ||
| 884 | 0x00000000, | ||
| 885 | 0x00000000, | ||
| 886 | 0x00000000, | ||
| 887 | 0x00000000, | ||
| 888 | 0x00000000, | ||
| 889 | 0x00000000, | ||
| 890 | 0x00000000, | ||
| 891 | 0x00000000, | ||
| 892 | 0x00000000, | ||
| 893 | 0x00000000, | ||
| 894 | 0x00000000, | ||
| 895 | 0x00000000, | ||
| 896 | 0x00000000, | ||
| 897 | 0x00000000, | ||
| 898 | 0x00000000, | ||
| 899 | 0x00000000, | ||
| 900 | 0x00000000, | ||
| 901 | 0x00000000, | ||
| 902 | 0x00000000, | ||
| 903 | 0x00000000, | ||
| 904 | 0x00000000, | ||
| 905 | 0x00000000, | ||
| 906 | 0x00000000, | ||
| 907 | 0x00000000, | ||
| 908 | 0x00000000, | ||
| 909 | 0x00000000, | ||
| 910 | 0x00000000, | ||
| 911 | 0x00000000, | ||
| 912 | 0x00000000, | ||
| 913 | 0x00000000, | ||
| 914 | 0x00000000, | ||
| 915 | 0x00000000, | ||
| 916 | 0x00000000, | ||
| 917 | 0x00000000, | ||
| 918 | 0x00000000, | 980 | 0x00000000, |
| 919 | 0x00000000, | 981 | 0x00000000, |
| 920 | 0x00000000, | 982 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h index eb7bc0e9576e..1c179bdd48cc 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h | |||
| @@ -206,14 +206,14 @@ uint32_t nve0_grhub_data[] = { | |||
| 206 | }; | 206 | }; |
| 207 | 207 | ||
| 208 | uint32_t nve0_grhub_code[] = { | 208 | uint32_t nve0_grhub_code[] = { |
| 209 | 0x031b0ef5, | 209 | 0x039b0ef5, |
| 210 | /* 0x0004: queue_put */ | 210 | /* 0x0004: queue_put */ |
| 211 | 0x9800d898, | 211 | 0x9800d898, |
| 212 | 0x86f001d9, | 212 | 0x86f001d9, |
| 213 | 0x0489b808, | 213 | 0x0489b808, |
| 214 | 0xf00c1bf4, | 214 | 0xf00c1bf4, |
| 215 | 0x21f502f7, | 215 | 0x21f502f7, |
| 216 | 0x00f802fe, | 216 | 0x00f8037e, |
| 217 | /* 0x001c: queue_put_next */ | 217 | /* 0x001c: queue_put_next */ |
| 218 | 0xb60798c4, | 218 | 0xb60798c4, |
| 219 | 0x8dbb0384, | 219 | 0x8dbb0384, |
| @@ -237,184 +237,214 @@ uint32_t nve0_grhub_code[] = { | |||
| 237 | /* 0x0066: queue_get_done */ | 237 | /* 0x0066: queue_get_done */ |
| 238 | 0x00f80132, | 238 | 0x00f80132, |
| 239 | /* 0x0068: nv_rd32 */ | 239 | /* 0x0068: nv_rd32 */ |
| 240 | 0x0728b7f1, | 240 | 0xf002ecb9, |
| 241 | 0xb906b4b6, | 241 | 0x07f11fc9, |
| 242 | 0xc9f002ec, | 242 | 0x03f0ca00, |
| 243 | 0x00bcd01f, | 243 | 0x000cd001, |
| 244 | /* 0x0078: nv_rd32_wait */ | 244 | /* 0x007a: nv_rd32_wait */ |
| 245 | 0xc800bccf, | 245 | 0xc7f104bd, |
| 246 | 0x1bf41fcc, | 246 | 0xc3f0ca00, |
| 247 | 0x06a7f0fa, | 247 | 0x00cccf01, |
| 248 | 0x010921f5, | 248 | 0xf41fccc8, |
| 249 | 0xf840bfcf, | 249 | 0xa7f0f31b, |
| 250 | /* 0x008d: nv_wr32 */ | 250 | 0x1021f506, |
| 251 | 0x28b7f100, | 251 | 0x00f7f101, |
| 252 | 0x06b4b607, | 252 | 0x01f3f0cb, |
| 253 | 0xb980bfd0, | 253 | 0xf800ffcf, |
| 254 | 0xc9f002ec, | 254 | /* 0x009d: nv_wr32 */ |
| 255 | 0x1ec9f01f, | 255 | 0x0007f100, |
| 256 | /* 0x00a3: nv_wr32_wait */ | 256 | 0x0103f0cc, |
| 257 | 0xcf00bcd0, | 257 | 0xbd000fd0, |
| 258 | 0xccc800bc, | 258 | 0x02ecb904, |
| 259 | 0xfa1bf41f, | 259 | 0xf01fc9f0, |
| 260 | /* 0x00ae: watchdog_reset */ | 260 | 0x07f11ec9, |
| 261 | 0x87f100f8, | 261 | 0x03f0ca00, |
| 262 | 0x84b60430, | 262 | 0x000cd001, |
| 263 | 0x1ff9f006, | 263 | /* 0x00be: nv_wr32_wait */ |
| 264 | 0xf8008fd0, | 264 | 0xc7f104bd, |
| 265 | /* 0x00bd: watchdog_clear */ | 265 | 0xc3f0ca00, |
| 266 | 0x3087f100, | 266 | 0x00cccf01, |
| 267 | 0x0684b604, | 267 | 0xf41fccc8, |
| 268 | 0xf80080d0, | 268 | 0x00f8f31b, |
| 269 | /* 0x00c9: wait_donez */ | 269 | /* 0x00d0: wait_donez */ |
| 270 | 0xf094bd00, | 270 | 0x99f094bd, |
| 271 | 0x07f10099, | 271 | 0x0007f100, |
| 272 | 0x03f00f00, | 272 | 0x0203f00f, |
| 273 | 0x0009d002, | 273 | 0xbd0009d0, |
| 274 | 0x07f104bd, | 274 | 0x0007f104, |
| 275 | 0x03f00600, | 275 | 0x0203f006, |
| 276 | 0x000ad002, | 276 | 0xbd000ad0, |
| 277 | /* 0x00e6: wait_donez_ne */ | 277 | /* 0x00ed: wait_donez_ne */ |
| 278 | 0x87f104bd, | 278 | 0x0087f104, |
| 279 | 0x83f00000, | 279 | 0x0183f000, |
| 280 | 0x0088cf01, | 280 | 0xff0088cf, |
| 281 | 0xf4888aff, | 281 | 0x1bf4888a, |
| 282 | 0x94bdf31b, | 282 | 0xf094bdf3, |
| 283 | 0xf10099f0, | ||
| 284 | 0xf0170007, | ||
| 285 | 0x09d00203, | ||
| 286 | 0xf804bd00, | ||
| 287 | /* 0x0109: wait_doneo */ | ||
| 288 | 0xf094bd00, | ||
| 289 | 0x07f10099, | 283 | 0x07f10099, |
| 290 | 0x03f00f00, | 284 | 0x03f01700, |
| 291 | 0x0009d002, | 285 | 0x0009d002, |
| 292 | 0x87f104bd, | 286 | 0x00f804bd, |
| 293 | 0x84b60818, | 287 | /* 0x0110: wait_doneo */ |
| 294 | 0x008ad006, | ||
| 295 | /* 0x0124: wait_doneo_e */ | ||
| 296 | 0x040087f1, | ||
| 297 | 0xcf0684b6, | ||
| 298 | 0x8aff0088, | ||
| 299 | 0xf30bf488, | ||
| 300 | 0x99f094bd, | 288 | 0x99f094bd, |
| 301 | 0x0007f100, | 289 | 0x0007f100, |
| 302 | 0x0203f017, | 290 | 0x0203f00f, |
| 303 | 0xbd0009d0, | 291 | 0xbd0009d0, |
| 304 | /* 0x0147: mmctx_size */ | 292 | 0x0007f104, |
| 305 | 0xbd00f804, | 293 | 0x0203f006, |
| 306 | /* 0x0149: nv_mmctx_size_loop */ | 294 | 0xbd000ad0, |
| 307 | 0x00e89894, | 295 | /* 0x012d: wait_doneo_e */ |
| 308 | 0xb61a85b6, | 296 | 0x0087f104, |
| 309 | 0x84b60180, | 297 | 0x0183f000, |
| 310 | 0x0098bb02, | 298 | 0xff0088cf, |
| 311 | 0xb804e0b6, | 299 | 0x0bf4888a, |
| 312 | 0x1bf404ef, | 300 | 0xf094bdf3, |
| 313 | 0x029fb9eb, | 301 | 0x07f10099, |
| 314 | /* 0x0166: mmctx_xfer */ | 302 | 0x03f01700, |
| 315 | 0x94bd00f8, | 303 | 0x0009d002, |
| 316 | 0xf10199f0, | 304 | 0x00f804bd, |
| 317 | 0xf00f0007, | 305 | /* 0x0150: mmctx_size */ |
| 318 | 0x09d00203, | 306 | /* 0x0152: nv_mmctx_size_loop */ |
| 319 | 0xf104bd00, | 307 | 0xe89894bd, |
| 320 | 0xb6071087, | 308 | 0x1a85b600, |
| 321 | 0x94bd0684, | 309 | 0xb60180b6, |
| 322 | 0xf405bbfd, | 310 | 0x98bb0284, |
| 323 | 0x8bd0090b, | 311 | 0x04e0b600, |
| 324 | 0x0099f000, | 312 | 0xf404efb8, |
| 325 | /* 0x018c: mmctx_base_disabled */ | 313 | 0x9fb9eb1b, |
| 326 | 0xf405eefd, | 314 | /* 0x016f: mmctx_xfer */ |
| 327 | 0x8ed00c0b, | 315 | 0xbd00f802, |
| 328 | 0xc08fd080, | 316 | 0x0199f094, |
| 329 | /* 0x019b: mmctx_multi_disabled */ | 317 | 0x0f0007f1, |
| 330 | 0xb70199f0, | 318 | 0xd00203f0, |
| 331 | 0xc8010080, | 319 | 0x04bd0009, |
| 320 | 0xbbfd94bd, | ||
| 321 | 0x120bf405, | ||
| 322 | 0xc40007f1, | ||
| 323 | 0xd00103f0, | ||
| 324 | 0x04bd000b, | ||
| 325 | /* 0x0197: mmctx_base_disabled */ | ||
| 326 | 0xfd0099f0, | ||
| 327 | 0x0bf405ee, | ||
| 328 | 0x0007f11e, | ||
| 329 | 0x0103f0c6, | ||
| 330 | 0xbd000ed0, | ||
| 331 | 0x0007f104, | ||
| 332 | 0x0103f0c7, | ||
| 333 | 0xbd000fd0, | ||
| 334 | 0x0199f004, | ||
| 335 | /* 0x01b8: mmctx_multi_disabled */ | ||
| 336 | 0xb600abc8, | ||
| 337 | 0xb9f010b4, | ||
| 338 | 0x01aec80c, | ||
| 339 | 0xfd11e4b6, | ||
| 340 | 0x07f105be, | ||
| 341 | 0x03f0c500, | ||
| 342 | 0x000bd001, | ||
| 343 | /* 0x01d6: mmctx_exec_loop */ | ||
| 344 | /* 0x01d6: mmctx_wait_free */ | ||
| 345 | 0xe7f104bd, | ||
| 346 | 0xe3f0c500, | ||
| 347 | 0x00eecf01, | ||
| 348 | 0xf41fe4f0, | ||
| 349 | 0xce98f30b, | ||
| 350 | 0x05e9fd00, | ||
| 351 | 0xc80007f1, | ||
| 352 | 0xd00103f0, | ||
| 353 | 0x04bd000e, | ||
| 354 | 0xb804c0b6, | ||
| 355 | 0x1bf404cd, | ||
| 356 | 0x02abc8d8, | ||
| 357 | /* 0x0207: mmctx_fini_wait */ | ||
| 358 | 0xf11f1bf4, | ||
| 359 | 0xf0c500b7, | ||
| 360 | 0xbbcf01b3, | ||
| 361 | 0x1fb4f000, | ||
| 362 | 0xf410b4b0, | ||
| 363 | 0xa7f0f01b, | ||
| 364 | 0xd021f402, | ||
| 365 | /* 0x0223: mmctx_stop */ | ||
| 366 | 0xc82b0ef4, | ||
| 332 | 0xb4b600ab, | 367 | 0xb4b600ab, |
| 333 | 0x0cb9f010, | 368 | 0x0cb9f010, |
| 334 | 0xb601aec8, | 369 | 0xf112b9f0, |
| 335 | 0xbefd11e4, | 370 | 0xf0c50007, |
| 336 | 0x008bd005, | 371 | 0x0bd00103, |
| 337 | /* 0x01b4: mmctx_exec_loop */ | 372 | /* 0x023b: mmctx_stop_wait */ |
| 338 | /* 0x01b4: mmctx_wait_free */ | 373 | 0xf104bd00, |
| 339 | 0xf0008ecf, | 374 | 0xf0c500b7, |
| 340 | 0x0bf41fe4, | 375 | 0xbbcf01b3, |
| 341 | 0x00ce98fa, | 376 | 0x12bbc800, |
| 342 | 0xd005e9fd, | 377 | /* 0x024b: mmctx_done */ |
| 343 | 0xc0b6c08e, | 378 | 0xbdf31bf4, |
| 344 | 0x04cdb804, | 379 | 0x0199f094, |
| 345 | 0xc8e81bf4, | 380 | 0x170007f1, |
| 346 | 0x1bf402ab, | 381 | 0xd00203f0, |
| 347 | /* 0x01d5: mmctx_fini_wait */ | 382 | 0x04bd0009, |
| 348 | 0x008bcf18, | 383 | /* 0x025e: strand_wait */ |
| 349 | 0xb01fb4f0, | 384 | 0xa0f900f8, |
| 350 | 0x1bf410b4, | 385 | 0xf402a7f0, |
| 351 | 0x02a7f0f7, | 386 | 0xa0fcd021, |
| 352 | 0xf4c921f4, | 387 | /* 0x026a: strand_pre */ |
| 353 | /* 0x01ea: mmctx_stop */ | 388 | 0x97f000f8, |
| 354 | 0xabc81b0e, | 389 | 0xfc07f10c, |
| 355 | 0x10b4b600, | 390 | 0x0203f04a, |
| 356 | 0xf00cb9f0, | 391 | 0xbd0009d0, |
| 357 | 0x8bd012b9, | 392 | 0x5e21f504, |
| 358 | /* 0x01f9: mmctx_stop_wait */ | 393 | /* 0x027f: strand_post */ |
| 359 | 0x008bcf00, | 394 | 0xf000f802, |
| 360 | 0xf412bbc8, | 395 | 0x07f10d97, |
| 361 | /* 0x0202: mmctx_done */ | 396 | 0x03f04afc, |
| 362 | 0x94bdfa1b, | ||
| 363 | 0xf10199f0, | ||
| 364 | 0xf0170007, | ||
| 365 | 0x09d00203, | ||
| 366 | 0xf804bd00, | ||
| 367 | /* 0x0215: strand_wait */ | ||
| 368 | 0xf0a0f900, | ||
| 369 | 0x21f402a7, | ||
| 370 | 0xf8a0fcc9, | ||
| 371 | /* 0x0221: strand_pre */ | ||
| 372 | 0xfc87f100, | ||
| 373 | 0x0283f04a, | ||
| 374 | 0xd00c97f0, | ||
| 375 | 0x21f50089, | ||
| 376 | 0x00f80215, | ||
| 377 | /* 0x0234: strand_post */ | ||
| 378 | 0x4afc87f1, | ||
| 379 | 0xf00283f0, | ||
| 380 | 0x89d00d97, | ||
| 381 | 0x1521f500, | ||
| 382 | /* 0x0247: strand_set */ | ||
| 383 | 0xf100f802, | ||
| 384 | 0xf04ffca7, | ||
| 385 | 0xaba202a3, | ||
| 386 | 0xc7f00500, | ||
| 387 | 0x00acd00f, | ||
| 388 | 0xd00bc7f0, | ||
| 389 | 0x21f500bc, | ||
| 390 | 0xaed00215, | ||
| 391 | 0x0ac7f000, | ||
| 392 | 0xf500bcd0, | ||
| 393 | 0xf8021521, | ||
| 394 | /* 0x0271: strand_ctx_init */ | ||
| 395 | 0xf094bd00, | ||
| 396 | 0x07f10399, | ||
| 397 | 0x03f00f00, | ||
| 398 | 0x0009d002, | 397 | 0x0009d002, |
| 399 | 0x21f504bd, | 398 | 0x21f504bd, |
| 400 | 0xe7f00221, | 399 | 0x00f8025e, |
| 401 | 0x4721f503, | 400 | /* 0x0294: strand_set */ |
| 402 | 0xfca7f102, | 401 | 0xf10fc7f0, |
| 403 | 0x02a3f046, | 402 | 0xf04ffc07, |
| 404 | 0x0400aba0, | 403 | 0x0cd00203, |
| 405 | 0xf040a0d0, | 404 | 0xf004bd00, |
| 406 | 0xbcd001c7, | 405 | 0x07f10bc7, |
| 407 | 0x1521f500, | 406 | 0x03f04afc, |
| 408 | 0x010c9202, | 407 | 0x000cd002, |
| 409 | 0xf000acd0, | 408 | 0x07f104bd, |
| 410 | 0xbcd002c7, | 409 | 0x03f04ffc, |
| 411 | 0x1521f500, | 410 | 0x000ed002, |
| 412 | 0x3421f502, | 411 | 0xc7f004bd, |
| 413 | 0x8087f102, | 412 | 0xfc07f10a, |
| 414 | 0x0684b608, | 413 | 0x0203f04a, |
| 415 | 0xb70089cf, | 414 | 0xbd000cd0, |
| 416 | 0x95220080, | 415 | 0x5e21f504, |
| 417 | /* 0x02ca: ctx_init_strand_loop */ | 416 | /* 0x02d3: strand_ctx_init */ |
| 417 | 0xbd00f802, | ||
| 418 | 0x0399f094, | ||
| 419 | 0x0f0007f1, | ||
| 420 | 0xd00203f0, | ||
| 421 | 0x04bd0009, | ||
| 422 | 0x026a21f5, | ||
| 423 | 0xf503e7f0, | ||
| 424 | 0xbd029421, | ||
| 425 | 0xfc07f1c4, | ||
| 426 | 0x0203f047, | ||
| 427 | 0xbd000cd0, | ||
| 428 | 0x01c7f004, | ||
| 429 | 0x4afc07f1, | ||
| 430 | 0xd00203f0, | ||
| 431 | 0x04bd000c, | ||
| 432 | 0x025e21f5, | ||
| 433 | 0xf1010c92, | ||
| 434 | 0xf046fc07, | ||
| 435 | 0x0cd00203, | ||
| 436 | 0xf004bd00, | ||
| 437 | 0x07f102c7, | ||
| 438 | 0x03f04afc, | ||
| 439 | 0x000cd002, | ||
| 440 | 0x21f504bd, | ||
| 441 | 0x21f5025e, | ||
| 442 | 0x87f1027f, | ||
| 443 | 0x83f04200, | ||
| 444 | 0x0097f102, | ||
| 445 | 0x0293f020, | ||
| 446 | 0x950099cf, | ||
| 447 | /* 0x034a: ctx_init_strand_loop */ | ||
| 418 | 0x8ed008fe, | 448 | 0x8ed008fe, |
| 419 | 0x408ed000, | 449 | 0x408ed000, |
| 420 | 0xb6808acf, | 450 | 0xb6808acf, |
| @@ -428,7 +458,7 @@ uint32_t nve0_grhub_code[] = { | |||
| 428 | 0x170007f1, | 458 | 0x170007f1, |
| 429 | 0xd00203f0, | 459 | 0xd00203f0, |
| 430 | 0x04bd0009, | 460 | 0x04bd0009, |
| 431 | /* 0x02fe: error */ | 461 | /* 0x037e: error */ |
| 432 | 0x07f100f8, | 462 | 0x07f100f8, |
| 433 | 0x03f00500, | 463 | 0x03f00500, |
| 434 | 0x000fd002, | 464 | 0x000fd002, |
| @@ -436,82 +466,117 @@ uint32_t nve0_grhub_code[] = { | |||
| 436 | 0x0007f101, | 466 | 0x0007f101, |
| 437 | 0x0303f007, | 467 | 0x0303f007, |
| 438 | 0xbd000fd0, | 468 | 0xbd000fd0, |
| 439 | /* 0x031b: init */ | 469 | /* 0x039b: init */ |
| 440 | 0xbd00f804, | 470 | 0xbd00f804, |
| 441 | 0x0004fe04, | 471 | 0x0007fe04, |
| 442 | 0xf10007fe, | 472 | 0x420017f1, |
| 443 | 0xf0120017, | 473 | 0xcf0013f0, |
| 444 | 0x12d00227, | 474 | 0x11e70011, |
| 445 | 0xb117f100, | 475 | 0x14b60109, |
| 446 | 0x0010fe05, | 476 | 0x0014fe08, |
| 447 | 0x040017f1, | 477 | 0xf10227f0, |
| 448 | 0xf1c010d0, | 478 | 0xf0120007, |
| 449 | 0xb6040437, | 479 | 0x02d00003, |
| 450 | 0x27f10634, | 480 | 0xf104bd00, |
| 451 | 0x32d02003, | 481 | 0xfe06c817, |
| 452 | 0x0427f100, | 482 | 0x24bd0010, |
| 453 | 0x0132d020, | 483 | 0x070007f1, |
| 484 | 0xd00003f0, | ||
| 485 | 0x04bd0002, | ||
| 486 | 0x200327f1, | ||
| 487 | 0x010007f1, | ||
| 488 | 0xd00103f0, | ||
| 489 | 0x04bd0002, | ||
| 490 | 0x200427f1, | ||
| 491 | 0x010407f1, | ||
| 492 | 0xd00103f0, | ||
| 493 | 0x04bd0002, | ||
| 454 | 0x200b27f1, | 494 | 0x200b27f1, |
| 455 | 0xf10232d0, | 495 | 0x010807f1, |
| 456 | 0xd0200c27, | 496 | 0xd00103f0, |
| 457 | 0x27f10732, | 497 | 0x04bd0002, |
| 458 | 0x24b60c24, | 498 | 0x200c27f1, |
| 459 | 0x0003b906, | 499 | 0x011c07f1, |
| 460 | 0xf10023d0, | 500 | 0xd00103f0, |
| 501 | 0x04bd0002, | ||
| 502 | 0xf1010392, | ||
| 503 | 0xf0090007, | ||
| 504 | 0x03d00303, | ||
| 505 | 0xf104bd00, | ||
| 461 | 0xf0870427, | 506 | 0xf0870427, |
| 462 | 0x12d00023, | 507 | 0x07f10023, |
| 463 | 0x0012b700, | 508 | 0x03f00400, |
| 464 | 0x0427f001, | 509 | 0x0002d000, |
| 465 | 0xf40012d0, | 510 | 0x27f004bd, |
| 466 | 0xe7f11031, | 511 | 0x0007f104, |
| 467 | 0xe3f09604, | 512 | 0x0003f003, |
| 468 | 0x6821f440, | 513 | 0xbd0002d0, |
| 469 | 0x8090f1c7, | 514 | 0x1031f404, |
| 470 | 0xf4f00301, | 515 | 0x9604e7f1, |
| 471 | 0x020f801f, | 516 | 0xf440e3f0, |
| 472 | 0xbb0117f0, | 517 | 0xfeb96821, |
| 473 | 0x12b6041f, | 518 | 0x90f1c702, |
| 474 | 0x0c27f101, | 519 | 0xf0030180, |
| 475 | 0x0624b604, | 520 | 0x0f801ff4, |
| 476 | 0xd00021d0, | 521 | 0x0117f002, |
| 477 | 0x17f14021, | 522 | 0xb6041fbb, |
| 478 | 0x0e980100, | 523 | 0x07f10112, |
| 479 | 0x010f9800, | 524 | 0x03f00300, |
| 480 | 0x014721f5, | 525 | 0x0001d001, |
| 481 | 0x070037f1, | 526 | 0x07f104bd, |
| 482 | 0x950634b6, | 527 | 0x03f00400, |
| 483 | 0x34d00814, | 528 | 0x0001d001, |
| 484 | 0x4034d000, | 529 | 0x17f104bd, |
| 485 | 0x130030b7, | 530 | 0xf7f00100, |
| 486 | 0xb6001fbb, | 531 | 0x7f21f502, |
| 487 | 0x3fd002f5, | 532 | 0x9121f507, |
| 488 | 0x0815b600, | 533 | 0x10f7f007, |
| 489 | 0xb60110b6, | 534 | 0x07de21f5, |
| 490 | 0x1fb90814, | 535 | 0x98000e98, |
| 491 | 0x7121f502, | 536 | 0x21f5010f, |
| 492 | 0x001fbb02, | 537 | 0x14950150, |
| 493 | 0xf1020398, | 538 | 0x0007f108, |
| 494 | 0xf0200047, | 539 | 0x0103f0c0, |
| 495 | /* 0x03f6: init_gpc */ | 540 | 0xbd0004d0, |
| 496 | 0x4ea05043, | 541 | 0x0007f104, |
| 497 | 0x1fb90804, | 542 | 0x0103f0c1, |
| 498 | 0x8d21f402, | 543 | 0xbd0004d0, |
| 499 | 0x010c4ea0, | 544 | 0x0030b704, |
| 500 | 0x21f4f4bd, | 545 | 0x001fbb13, |
| 501 | 0x044ea08d, | 546 | 0xf102f5b6, |
| 502 | 0x8d21f401, | 547 | 0xf0d30007, |
| 503 | 0x01004ea0, | 548 | 0x0fd00103, |
| 504 | 0xf402f7f0, | 549 | 0xb604bd00, |
| 505 | 0x4ea08d21, | 550 | 0x10b60815, |
| 506 | /* 0x041e: init_gpc_wait */ | 551 | 0x0814b601, |
| 507 | 0x21f40800, | 552 | 0xf5021fb9, |
| 508 | 0x1fffc868, | 553 | 0xbb02d321, |
| 509 | 0xa0fa0bf4, | 554 | 0x0398001f, |
| 510 | 0xf408044e, | 555 | 0x0047f102, |
| 511 | 0x1fbb6821, | 556 | 0x5043f020, |
| 512 | 0x0040b700, | 557 | /* 0x04f4: init_gpc */ |
| 513 | 0x0132b680, | 558 | 0x08044ea0, |
| 514 | 0xf1be1bf4, | 559 | 0xf4021fb9, |
| 560 | 0x4ea09d21, | ||
| 561 | 0xf4bd010c, | ||
| 562 | 0xa09d21f4, | ||
| 563 | 0xf401044e, | ||
| 564 | 0x4ea09d21, | ||
| 565 | 0xf7f00100, | ||
| 566 | 0x9d21f402, | ||
| 567 | 0x08004ea0, | ||
| 568 | /* 0x051c: init_gpc_wait */ | ||
| 569 | 0xc86821f4, | ||
| 570 | 0x0bf41fff, | ||
| 571 | 0x044ea0fa, | ||
| 572 | 0x6821f408, | ||
| 573 | 0xb7001fbb, | ||
| 574 | 0xb6800040, | ||
| 575 | 0x1bf40132, | ||
| 576 | 0x00f7f0be, | ||
| 577 | 0x07de21f5, | ||
| 578 | 0xf500f7f0, | ||
| 579 | 0xf1077f21, | ||
| 515 | 0xf0010007, | 580 | 0xf0010007, |
| 516 | 0x01d00203, | 581 | 0x01d00203, |
| 517 | 0xbd04bd00, | 582 | 0xbd04bd00, |
| @@ -519,382 +584,379 @@ uint32_t nve0_grhub_code[] = { | |||
| 519 | 0x080007f1, | 584 | 0x080007f1, |
| 520 | 0xd00203f0, | 585 | 0xd00203f0, |
| 521 | 0x04bd0001, | 586 | 0x04bd0001, |
| 522 | /* 0x0458: main */ | 587 | /* 0x0564: main */ |
| 523 | 0xf40031f4, | 588 | 0xf40031f4, |
| 524 | 0xd7f00028, | 589 | 0xd7f00028, |
| 525 | 0x3921f410, | 590 | 0x3921f410, |
| 526 | 0xb1f401f4, | 591 | 0xb1f401f4, |
| 527 | 0xf54001e4, | 592 | 0xf54001e4, |
| 528 | 0xbd00de1b, | 593 | 0xbd00e91b, |
| 529 | 0x0499f094, | 594 | 0x0499f094, |
| 530 | 0x0f0007f1, | 595 | 0x0f0007f1, |
| 531 | 0xd00203f0, | 596 | 0xd00203f0, |
| 532 | 0x04bd0009, | 597 | 0x04bd0009, |
| 533 | 0x0b0017f1, | 598 | 0xc00017f1, |
| 534 | 0xcf0614b6, | 599 | 0xcf0213f0, |
| 535 | 0x11cf4012, | 600 | 0x27f10011, |
| 536 | 0x1f13c800, | 601 | 0x23f0c100, |
| 537 | 0x00870bf5, | 602 | 0x0022cf02, |
| 538 | 0xf41f23c8, | 603 | 0xf51f13c8, |
| 539 | 0x20f9620b, | 604 | 0xc800890b, |
| 540 | 0xbd0212b9, | 605 | 0x0bf41f23, |
| 541 | 0x0799f094, | 606 | 0xb920f962, |
| 542 | 0x0f0007f1, | 607 | 0x94bd0212, |
| 543 | 0xd00203f0, | ||
| 544 | 0x04bd0009, | ||
| 545 | 0xf40132f4, | ||
| 546 | 0x21f50231, | ||
| 547 | 0x94bd0801, | ||
| 548 | 0xf10799f0, | 608 | 0xf10799f0, |
| 549 | 0xf0170007, | 609 | 0xf00f0007, |
| 550 | 0x09d00203, | 610 | 0x09d00203, |
| 551 | 0xfc04bd00, | 611 | 0xf404bd00, |
| 552 | 0xf094bd20, | 612 | 0x31f40132, |
| 553 | 0x07f10699, | 613 | 0xaa21f502, |
| 554 | 0x03f00f00, | 614 | 0xf094bd09, |
| 555 | 0x0009d002, | 615 | 0x07f10799, |
| 556 | 0x31f404bd, | ||
| 557 | 0x0121f501, | ||
| 558 | 0xf094bd08, | ||
| 559 | 0x07f10699, | ||
| 560 | 0x03f01700, | 616 | 0x03f01700, |
| 561 | 0x0009d002, | 617 | 0x0009d002, |
| 562 | 0x0ef404bd, | 618 | 0x20fc04bd, |
| 563 | /* 0x04f9: chsw_prev_no_next */ | ||
| 564 | 0xb920f931, | ||
| 565 | 0x32f40212, | ||
| 566 | 0x0232f401, | ||
| 567 | 0x080121f5, | ||
| 568 | 0x17f120fc, | ||
| 569 | 0x14b60b00, | ||
| 570 | 0x0012d006, | ||
| 571 | /* 0x0517: chsw_no_prev */ | ||
| 572 | 0xc8130ef4, | ||
| 573 | 0x0bf41f23, | ||
| 574 | 0x0131f40d, | ||
| 575 | 0xf50232f4, | ||
| 576 | /* 0x0527: chsw_done */ | ||
| 577 | 0xf1080121, | ||
| 578 | 0xb60b0c17, | ||
| 579 | 0x27f00614, | ||
| 580 | 0x0012d001, | ||
| 581 | 0x99f094bd, | 619 | 0x99f094bd, |
| 582 | 0x0007f104, | 620 | 0x0007f106, |
| 621 | 0x0203f00f, | ||
| 622 | 0xbd0009d0, | ||
| 623 | 0x0131f404, | ||
| 624 | 0x09aa21f5, | ||
| 625 | 0x99f094bd, | ||
| 626 | 0x0007f106, | ||
| 583 | 0x0203f017, | 627 | 0x0203f017, |
| 584 | 0xbd0009d0, | 628 | 0xbd0009d0, |
| 585 | 0x130ef504, | 629 | 0x330ef404, |
| 586 | /* 0x0549: main_not_ctx_switch */ | 630 | /* 0x060c: chsw_prev_no_next */ |
| 587 | 0x01e4b0ff, | 631 | 0x12b920f9, |
| 588 | 0xb90d1bf4, | 632 | 0x0132f402, |
| 589 | 0x21f502f2, | 633 | 0xf50232f4, |
| 590 | 0x0ef40795, | 634 | 0xfc09aa21, |
| 591 | /* 0x0559: main_not_ctx_chan */ | 635 | 0x0007f120, |
| 592 | 0x02e4b046, | 636 | 0x0203f0c0, |
| 593 | 0xbd321bf4, | 637 | 0xbd0002d0, |
| 594 | 0x0799f094, | 638 | 0x130ef404, |
| 595 | 0x0f0007f1, | 639 | /* 0x062c: chsw_no_prev */ |
| 640 | 0xf41f23c8, | ||
| 641 | 0x31f40d0b, | ||
| 642 | 0x0232f401, | ||
| 643 | 0x09aa21f5, | ||
| 644 | /* 0x063c: chsw_done */ | ||
| 645 | 0xf10127f0, | ||
| 646 | 0xf0c30007, | ||
| 647 | 0x02d00203, | ||
| 648 | 0xbd04bd00, | ||
| 649 | 0x0499f094, | ||
| 650 | 0x170007f1, | ||
| 596 | 0xd00203f0, | 651 | 0xd00203f0, |
| 597 | 0x04bd0009, | 652 | 0x04bd0009, |
| 598 | 0xf40132f4, | 653 | 0xff080ef5, |
| 599 | 0x21f50232, | 654 | /* 0x0660: main_not_ctx_switch */ |
| 600 | 0x94bd0801, | 655 | 0xf401e4b0, |
| 656 | 0xf2b90d1b, | ||
| 657 | 0x4221f502, | ||
| 658 | 0x460ef409, | ||
| 659 | /* 0x0670: main_not_ctx_chan */ | ||
| 660 | 0xf402e4b0, | ||
| 661 | 0x94bd321b, | ||
| 601 | 0xf10799f0, | 662 | 0xf10799f0, |
| 602 | 0xf0170007, | 663 | 0xf00f0007, |
| 603 | 0x09d00203, | 664 | 0x09d00203, |
| 604 | 0xf404bd00, | 665 | 0xf404bd00, |
| 605 | /* 0x058e: main_not_ctx_save */ | 666 | 0x32f40132, |
| 606 | 0xef94110e, | 667 | 0xaa21f502, |
| 607 | 0x01f5f010, | 668 | 0xf094bd09, |
| 608 | 0x02fe21f5, | 669 | 0x07f10799, |
| 609 | 0xfec00ef5, | 670 | 0x03f01700, |
| 610 | /* 0x059c: main_done */ | 671 | 0x0009d002, |
| 611 | 0x29f024bd, | 672 | 0x0ef404bd, |
| 612 | 0x0007f11f, | 673 | /* 0x06a5: main_not_ctx_save */ |
| 613 | 0x0203f008, | 674 | 0x10ef9411, |
| 614 | 0xbd0002d0, | 675 | 0xf501f5f0, |
| 615 | 0xab0ef504, | 676 | 0xf5037e21, |
| 616 | /* 0x05b1: ih */ | 677 | /* 0x06b3: main_done */ |
| 617 | 0xfe80f9fe, | 678 | 0xbdfeb50e, |
| 618 | 0x80f90188, | 679 | 0x1f29f024, |
| 619 | 0xa0f990f9, | 680 | 0x080007f1, |
| 620 | 0xd0f9b0f9, | 681 | 0xd00203f0, |
| 621 | 0xf0f9e0f9, | 682 | 0x04bd0002, |
| 622 | 0x0acf04bd, | 683 | 0xfea00ef5, |
| 623 | 0x04abc480, | 684 | /* 0x06c8: ih */ |
| 624 | 0xf11d0bf4, | 685 | 0x88fe80f9, |
| 625 | 0xf01900b7, | 686 | 0xf980f901, |
| 626 | 0xbecf10d7, | 687 | 0xf9a0f990, |
| 627 | 0x00bfcf40, | 688 | 0xf9d0f9b0, |
| 689 | 0xbdf0f9e0, | ||
| 690 | 0x00a7f104, | ||
| 691 | 0x00a3f002, | ||
| 692 | 0xc400aacf, | ||
| 693 | 0x0bf404ab, | ||
| 694 | 0x10d7f030, | ||
| 695 | 0x1a00e7f1, | ||
| 696 | 0xcf00e3f0, | ||
| 697 | 0xf7f100ee, | ||
| 698 | 0xf3f01900, | ||
| 699 | 0x00ffcf00, | ||
| 628 | 0xb70421f4, | 700 | 0xb70421f4, |
| 629 | 0xf00400b0, | 701 | 0xf00400b0, |
| 630 | 0xbed001e7, | 702 | 0x07f101e7, |
| 631 | /* 0x05e9: ih_no_fifo */ | 703 | 0x03f01d00, |
| 632 | 0x00abe400, | 704 | 0x000ed000, |
| 633 | 0x0d0bf401, | 705 | /* 0x071a: ih_no_fifo */ |
| 634 | 0xf110d7f0, | 706 | 0xabe404bd, |
| 635 | 0xf44001e7, | 707 | 0x0bf40100, |
| 636 | /* 0x05fa: ih_no_ctxsw */ | 708 | 0x10d7f00d, |
| 637 | 0xb7f10421, | 709 | 0x4001e7f1, |
| 638 | 0xb0bd0104, | 710 | /* 0x072b: ih_no_ctxsw */ |
| 639 | 0xf4b4abff, | 711 | 0xe40421f4, |
| 640 | 0xa7f10d0b, | 712 | 0xf40400ab, |
| 641 | 0xa4b60c1c, | 713 | 0xb7f1140b, |
| 642 | 0x00abd006, | 714 | 0xbfb90100, |
| 643 | /* 0x0610: ih_no_other */ | 715 | 0x44e7f102, |
| 644 | 0xfc400ad0, | 716 | 0x40e3f001, |
| 717 | /* 0x0743: ih_no_fwmthd */ | ||
| 718 | 0xf19d21f4, | ||
| 719 | 0xbd0104b7, | ||
| 720 | 0xb4abffb0, | ||
| 721 | 0xf10f0bf4, | ||
| 722 | 0xf0070007, | ||
| 723 | 0x0bd00303, | ||
| 724 | /* 0x075b: ih_no_other */ | ||
| 725 | 0xf104bd00, | ||
| 726 | 0xf0010007, | ||
| 727 | 0x0ad00003, | ||
| 728 | 0xfc04bd00, | ||
| 645 | 0xfce0fcf0, | 729 | 0xfce0fcf0, |
| 646 | 0xfcb0fcd0, | 730 | 0xfcb0fcd0, |
| 647 | 0xfc90fca0, | 731 | 0xfc90fca0, |
| 648 | 0x0088fe80, | 732 | 0x0088fe80, |
| 649 | 0x32f480fc, | 733 | 0x32f480fc, |
| 650 | /* 0x062b: ctx_4170s */ | 734 | /* 0x077f: ctx_4170s */ |
| 651 | 0xf101f800, | 735 | 0xf001f800, |
| 652 | 0xf04170e7, | 736 | 0xffb910f5, |
| 653 | 0xf5f040e3, | 737 | 0x70e7f102, |
| 654 | 0x8d21f410, | 738 | 0x40e3f041, |
| 655 | /* 0x063a: ctx_4170w */ | 739 | 0xf89d21f4, |
| 740 | /* 0x0791: ctx_4170w */ | ||
| 741 | 0x70e7f100, | ||
| 742 | 0x40e3f041, | ||
| 743 | 0xb96821f4, | ||
| 744 | 0xf4f002ff, | ||
| 745 | 0xf01bf410, | ||
| 746 | /* 0x07a6: ctx_redswitch */ | ||
| 656 | 0xe7f100f8, | 747 | 0xe7f100f8, |
| 657 | 0xe3f04170, | 748 | 0xe5f00200, |
| 658 | 0x6821f440, | 749 | 0x20e5f040, |
| 659 | 0xf410f4f0, | 750 | 0xf110e5f0, |
| 751 | 0xf0850007, | ||
| 752 | 0x0ed00103, | ||
| 753 | 0xf004bd00, | ||
| 754 | /* 0x07c2: ctx_redswitch_delay */ | ||
| 755 | 0xf2b608f7, | ||
| 756 | 0xfd1bf401, | ||
| 757 | 0x0400e5f1, | ||
| 758 | 0x0100e5f1, | ||
| 759 | 0x850007f1, | ||
| 760 | 0xd00103f0, | ||
| 761 | 0x04bd000e, | ||
| 762 | /* 0x07de: ctx_86c */ | ||
| 763 | 0x07f100f8, | ||
| 764 | 0x03f01b00, | ||
| 765 | 0x000fd002, | ||
| 766 | 0xffb904bd, | ||
| 767 | 0x14e7f102, | ||
| 768 | 0x40e3f08a, | ||
| 769 | 0xb99d21f4, | ||
| 770 | 0xe7f102ff, | ||
| 771 | 0xe3f0a86c, | ||
| 772 | 0x9d21f441, | ||
| 773 | /* 0x0806: ctx_mem */ | ||
| 774 | 0x07f100f8, | ||
| 775 | 0x03f08400, | ||
| 776 | 0x000fd002, | ||
| 777 | /* 0x0812: ctx_mem_wait */ | ||
| 778 | 0xf7f104bd, | ||
| 779 | 0xf3f08400, | ||
| 780 | 0x00ffcf02, | ||
| 781 | 0xf405fffd, | ||
| 660 | 0x00f8f31b, | 782 | 0x00f8f31b, |
| 661 | /* 0x064c: ctx_redswitch */ | 783 | /* 0x0824: ctx_load */ |
| 662 | 0x0614e7f1, | ||
| 663 | 0xf106e4b6, | ||
| 664 | 0xd00270f7, | ||
| 665 | 0xf7f000ef, | ||
| 666 | /* 0x065d: ctx_redswitch_delay */ | ||
| 667 | 0x01f2b608, | ||
| 668 | 0xf1fd1bf4, | ||
| 669 | 0xd00770f7, | ||
| 670 | 0x00f800ef, | ||
| 671 | /* 0x066c: ctx_86c */ | ||
| 672 | 0x086ce7f1, | ||
| 673 | 0xd006e4b6, | ||
| 674 | 0xe7f100ef, | ||
| 675 | 0xe3f08a14, | ||
| 676 | 0x8d21f440, | ||
| 677 | 0xa86ce7f1, | ||
| 678 | 0xf441e3f0, | ||
| 679 | 0x00f88d21, | ||
| 680 | /* 0x068c: ctx_load */ | ||
| 681 | 0x99f094bd, | 784 | 0x99f094bd, |
| 682 | 0x0007f105, | 785 | 0x0007f105, |
| 683 | 0x0203f00f, | 786 | 0x0203f00f, |
| 684 | 0xbd0009d0, | 787 | 0xbd0009d0, |
| 685 | 0x0ca7f004, | 788 | 0x0ca7f004, |
| 686 | 0xf1c921f4, | 789 | 0xbdd021f4, |
| 687 | 0xb60a2417, | 790 | 0x0007f1f4, |
| 688 | 0x10d00614, | 791 | 0x0203f089, |
| 689 | 0x0037f100, | 792 | 0xbd000fd0, |
| 690 | 0x0634b60b, | 793 | 0x0007f104, |
| 691 | 0xf14032d0, | 794 | 0x0203f0c1, |
| 692 | 0xb60a0c17, | 795 | 0xbd0002d0, |
| 693 | 0x47f00614, | 796 | 0x0007f104, |
| 694 | 0x0012d007, | 797 | 0x0203f083, |
| 695 | /* 0x06c7: ctx_chan_wait_0 */ | 798 | 0xbd0002d0, |
| 696 | 0xcf4014d0, | 799 | 0x07f7f004, |
| 697 | 0x44f04014, | 800 | 0x080621f5, |
| 698 | 0xfa1bf41f, | 801 | 0xc00007f1, |
| 699 | 0xfe0032d0, | 802 | 0xd00203f0, |
| 700 | 0x2af0000b, | 803 | 0x04bd0002, |
| 701 | 0x0424b61f, | 804 | 0xf0000bfe, |
| 702 | 0xbd0220b6, | 805 | 0x24b61f2a, |
| 806 | 0x0220b604, | ||
| 807 | 0x99f094bd, | ||
| 808 | 0x0007f108, | ||
| 809 | 0x0203f00f, | ||
| 810 | 0xbd0009d0, | ||
| 811 | 0x0007f104, | ||
| 812 | 0x0203f081, | ||
| 813 | 0xbd0002d0, | ||
| 814 | 0x0027f104, | ||
| 815 | 0x0023f100, | ||
| 816 | 0x0225f080, | ||
| 817 | 0x880007f1, | ||
| 818 | 0xd00203f0, | ||
| 819 | 0x04bd0002, | ||
| 820 | 0xf11017f0, | ||
| 821 | 0xf0020027, | ||
| 822 | 0x12fa0223, | ||
| 823 | 0xbd03f805, | ||
| 703 | 0x0899f094, | 824 | 0x0899f094, |
| 704 | 0x0f0007f1, | 825 | 0x170007f1, |
| 705 | 0xd00203f0, | 826 | 0xd00203f0, |
| 706 | 0x04bd0009, | 827 | 0x04bd0009, |
| 707 | 0x0a0417f1, | 828 | 0xb6810198, |
| 708 | 0xd00614b6, | 829 | 0x02981814, |
| 709 | 0x17f10012, | 830 | 0x0825b680, |
| 710 | 0x14b60a20, | 831 | 0x800512fd, |
| 711 | 0x0227f006, | 832 | 0x94bd1601, |
| 712 | 0x800023f1, | 833 | 0xf10999f0, |
| 713 | 0xf00012d0, | 834 | 0xf00f0007, |
| 714 | 0x27f11017, | ||
| 715 | 0x23f00200, | ||
| 716 | 0x0512fa02, | ||
| 717 | 0x94bd03f8, | ||
| 718 | 0xf10899f0, | ||
| 719 | 0xf0170007, | ||
| 720 | 0x09d00203, | 835 | 0x09d00203, |
| 721 | 0x9804bd00, | 836 | 0xf104bd00, |
| 722 | 0x14b68101, | 837 | 0xf0810007, |
| 723 | 0x80029818, | 838 | 0x01d00203, |
| 724 | 0xfd0825b6, | 839 | 0xf004bd00, |
| 725 | 0x01800512, | 840 | 0x07f10127, |
| 726 | 0xf094bd16, | 841 | 0x03f08800, |
| 727 | 0x07f10999, | 842 | 0x0002d002, |
| 728 | 0x03f00f00, | 843 | 0x17f104bd, |
| 729 | 0x0009d002, | 844 | 0x13f00100, |
| 730 | 0x27f104bd, | 845 | 0x0501fa06, |
| 731 | 0x24b60a04, | 846 | 0x94bd03f8, |
| 732 | 0x0021d006, | 847 | 0xf10999f0, |
| 733 | 0xf10127f0, | ||
| 734 | 0xb60a2017, | ||
| 735 | 0x12d00614, | ||
| 736 | 0x0017f100, | ||
| 737 | 0x0613f001, | ||
| 738 | 0xf80501fa, | ||
| 739 | 0xf094bd03, | ||
| 740 | 0x07f10999, | ||
| 741 | 0x03f01700, | ||
| 742 | 0x0009d002, | ||
| 743 | 0x94bd04bd, | ||
| 744 | 0xf10599f0, | ||
| 745 | 0xf0170007, | 848 | 0xf0170007, |
| 746 | 0x09d00203, | 849 | 0x09d00203, |
| 747 | 0xf804bd00, | 850 | 0xbd04bd00, |
| 748 | /* 0x0795: ctx_chan */ | 851 | 0x0599f094, |
| 749 | 0x8c21f500, | 852 | 0x170007f1, |
| 750 | 0x0ca7f006, | 853 | 0xd00203f0, |
| 751 | 0xf1c921f4, | 854 | 0x04bd0009, |
| 752 | 0xb60a1017, | 855 | /* 0x0942: ctx_chan */ |
| 753 | 0x27f00614, | 856 | 0x21f500f8, |
| 754 | 0x0012d005, | 857 | 0xa7f00824, |
| 755 | /* 0x07ac: ctx_chan_wait */ | 858 | 0xd021f40c, |
| 756 | 0xfd0012cf, | 859 | 0xf505f7f0, |
| 757 | 0x1bf40522, | 860 | 0xf8080621, |
| 758 | /* 0x07b7: ctx_mmio_exec */ | 861 | /* 0x0955: ctx_mmio_exec */ |
| 759 | 0x9800f8fa, | 862 | 0x41039800, |
| 760 | 0x27f14103, | 863 | 0x810007f1, |
| 761 | 0x24b60a04, | 864 | 0xd00203f0, |
| 762 | 0x0023d006, | 865 | 0x04bd0003, |
| 763 | /* 0x07c6: ctx_mmio_loop */ | 866 | /* 0x0966: ctx_mmio_loop */ |
| 764 | 0x34c434bd, | 867 | 0x34c434bd, |
| 765 | 0x0f1bf4ff, | 868 | 0x0f1bf4ff, |
| 766 | 0x020057f1, | 869 | 0x020057f1, |
| 767 | 0xfa0653f0, | 870 | 0xfa0653f0, |
| 768 | 0x03f80535, | 871 | 0x03f80535, |
| 769 | /* 0x07d8: ctx_mmio_pull */ | 872 | /* 0x0978: ctx_mmio_pull */ |
| 770 | 0x98804e98, | 873 | 0x98804e98, |
| 771 | 0x21f4814f, | 874 | 0x21f4814f, |
| 772 | 0x0830b68d, | 875 | 0x0830b69d, |
| 773 | 0xf40112b6, | 876 | 0xf40112b6, |
| 774 | /* 0x07ea: ctx_mmio_done */ | 877 | /* 0x098a: ctx_mmio_done */ |
| 775 | 0x0398df1b, | 878 | 0x0398df1b, |
| 776 | 0x0023d016, | 879 | 0x0007f116, |
| 777 | 0xf1400080, | 880 | 0x0203f081, |
| 778 | 0xf0010017, | 881 | 0xbd0003d0, |
| 779 | 0x01fa0613, | 882 | 0x40008004, |
| 780 | 0xf803f806, | 883 | 0x010017f1, |
| 781 | /* 0x0801: ctx_xfer */ | 884 | 0xfa0613f0, |
| 782 | 0x00f7f100, | 885 | 0x03f80601, |
| 783 | 0x06f4b60c, | 886 | /* 0x09aa: ctx_xfer */ |
| 784 | 0xd004e7f0, | 887 | 0xe7f000f8, |
| 785 | /* 0x080e: ctx_xfer_idle */ | 888 | 0x0007f104, |
| 786 | 0xfecf80fe, | 889 | 0x0303f002, |
| 787 | 0x00e4f100, | 890 | 0xbd000ed0, |
| 788 | 0xf91bf420, | 891 | /* 0x09b9: ctx_xfer_idle */ |
| 789 | 0xf40611f4, | 892 | 0x00e7f104, |
| 790 | /* 0x081e: ctx_xfer_pre */ | 893 | 0x03e3f000, |
| 791 | 0xf7f00d02, | 894 | 0xf100eecf, |
| 792 | 0x6c21f510, | 895 | 0xf42000e4, |
| 793 | 0x1c11f406, | 896 | 0x11f4f21b, |
| 794 | /* 0x0828: ctx_xfer_pre_load */ | 897 | 0x0d02f406, |
| 795 | 0xf502f7f0, | 898 | /* 0x09d0: ctx_xfer_pre */ |
| 796 | 0xf5062b21, | 899 | 0xf510f7f0, |
| 797 | 0xf5063a21, | 900 | 0xf407de21, |
| 798 | 0xbd064c21, | 901 | /* 0x09da: ctx_xfer_pre_load */ |
| 799 | 0x2b21f5f4, | 902 | 0xf7f01c11, |
| 800 | 0x8c21f506, | 903 | 0x7f21f502, |
| 801 | /* 0x0841: ctx_xfer_exec */ | 904 | 0x9121f507, |
| 802 | 0x16019806, | 905 | 0xa621f507, |
| 803 | 0x041427f1, | 906 | 0xf5f4bd07, |
| 804 | 0xd00624b6, | 907 | 0xf5077f21, |
| 805 | 0xe7f10020, | 908 | /* 0x09f3: ctx_xfer_exec */ |
| 806 | 0xe3f0a500, | 909 | 0x98082421, |
| 807 | 0x021fb941, | 910 | 0x24bd1601, |
| 808 | 0xb68d21f4, | 911 | 0x050007f1, |
| 809 | 0xfcf004e0, | 912 | 0xd00103f0, |
| 810 | 0x022cf001, | 913 | 0x04bd0002, |
| 811 | 0xfd0124b6, | 914 | 0xf1021fb9, |
| 812 | 0x21f405f2, | 915 | 0xf0a500e7, |
| 813 | 0xfc17f18d, | 916 | 0x21f441e3, |
| 814 | 0x0213f04a, | 917 | 0x01fcf09d, |
| 815 | 0xd00c27f0, | 918 | 0xb6022cf0, |
| 816 | 0x21f50012, | 919 | 0xf2fd0124, |
| 817 | 0x27f10215, | 920 | 0x02ffb905, |
| 818 | 0x23f047fc, | 921 | 0xa504e7f1, |
| 819 | 0x0020d002, | 922 | 0xf441e3f0, |
| 923 | 0x21f59d21, | ||
| 924 | 0x24bd026a, | ||
| 925 | 0x47fc07f1, | ||
| 926 | 0xd00203f0, | ||
| 927 | 0x04bd0002, | ||
| 820 | 0xb6012cf0, | 928 | 0xb6012cf0, |
| 821 | 0x12d00320, | 929 | 0x07f10320, |
| 822 | 0x01acf000, | 930 | 0x03f04afc, |
| 823 | 0xf006a5f0, | 931 | 0x0002d002, |
| 824 | 0x0c9800b7, | 932 | 0xacf004bd, |
| 825 | 0x010d9800, | 933 | 0x06a5f001, |
| 826 | 0xf500e7f0, | 934 | 0x9800b7f0, |
| 827 | 0xf0016621, | 935 | 0x0d98000c, |
| 828 | 0x21f508a7, | 936 | 0x00e7f001, |
| 829 | 0x21f50109, | 937 | 0x016f21f5, |
| 830 | 0x01f40215, | 938 | 0xf508a7f0, |
| 831 | 0x0ca7f022, | 939 | 0xf5011021, |
| 832 | 0xf1c921f4, | 940 | 0xf4025e21, |
| 833 | 0xb60a1017, | 941 | 0xa7f01301, |
| 834 | 0x27f00614, | 942 | 0xd021f40c, |
| 835 | 0x0012d005, | 943 | 0xf505f7f0, |
| 836 | /* 0x08c8: ctx_xfer_post_save_wait */ | 944 | 0xf4080621, |
| 837 | 0xfd0012cf, | 945 | /* 0x0a82: ctx_xfer_post */ |
| 838 | 0x1bf40522, | 946 | 0xf7f02e02, |
| 839 | 0x2e02f4fa, | 947 | 0x7f21f502, |
| 840 | /* 0x08d4: ctx_xfer_post */ | 948 | 0xf5f4bd07, |
| 841 | 0xf502f7f0, | 949 | 0xf507de21, |
| 842 | 0xbd062b21, | 950 | 0xf5027f21, |
| 843 | 0x6c21f5f4, | 951 | 0xbd079121, |
| 844 | 0x3421f506, | 952 | 0x7f21f5f4, |
| 845 | 0x3a21f502, | 953 | 0x1011f407, |
| 846 | 0xf5f4bd06, | 954 | 0xfd400198, |
| 847 | 0xf4062b21, | 955 | 0x0bf40511, |
| 848 | 0x01981011, | 956 | 0x5521f507, |
| 849 | 0x0511fd40, | 957 | /* 0x0aad: ctx_xfer_no_post_mmio */ |
| 850 | 0xf5070bf4, | 958 | /* 0x0aad: ctx_xfer_done */ |
| 851 | /* 0x08ff: ctx_xfer_no_post_mmio */ | 959 | 0x0000f809, |
| 852 | /* 0x08ff: ctx_xfer_done */ | ||
| 853 | 0xf807b721, | ||
| 854 | 0x00000000, | ||
| 855 | 0x00000000, | ||
| 856 | 0x00000000, | ||
| 857 | 0x00000000, | ||
| 858 | 0x00000000, | ||
| 859 | 0x00000000, | ||
| 860 | 0x00000000, | ||
| 861 | 0x00000000, | ||
| 862 | 0x00000000, | ||
| 863 | 0x00000000, | ||
| 864 | 0x00000000, | ||
| 865 | 0x00000000, | ||
| 866 | 0x00000000, | ||
| 867 | 0x00000000, | ||
| 868 | 0x00000000, | ||
| 869 | 0x00000000, | ||
| 870 | 0x00000000, | ||
| 871 | 0x00000000, | ||
| 872 | 0x00000000, | ||
| 873 | 0x00000000, | ||
| 874 | 0x00000000, | ||
| 875 | 0x00000000, | ||
| 876 | 0x00000000, | ||
| 877 | 0x00000000, | ||
| 878 | 0x00000000, | ||
| 879 | 0x00000000, | ||
| 880 | 0x00000000, | ||
| 881 | 0x00000000, | ||
| 882 | 0x00000000, | ||
| 883 | 0x00000000, | ||
| 884 | 0x00000000, | ||
| 885 | 0x00000000, | ||
| 886 | 0x00000000, | ||
| 887 | 0x00000000, | ||
| 888 | 0x00000000, | ||
| 889 | 0x00000000, | ||
| 890 | 0x00000000, | ||
| 891 | 0x00000000, | ||
| 892 | 0x00000000, | ||
| 893 | 0x00000000, | ||
| 894 | 0x00000000, | ||
| 895 | 0x00000000, | ||
| 896 | 0x00000000, | ||
| 897 | 0x00000000, | ||
| 898 | 0x00000000, | 960 | 0x00000000, |
| 899 | 0x00000000, | 961 | 0x00000000, |
| 900 | 0x00000000, | 962 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h index 438506d14749..229c0ae37228 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h | |||
| @@ -206,14 +206,14 @@ uint32_t nvf0_grhub_data[] = { | |||
| 206 | }; | 206 | }; |
| 207 | 207 | ||
| 208 | uint32_t nvf0_grhub_code[] = { | 208 | uint32_t nvf0_grhub_code[] = { |
| 209 | 0x031b0ef5, | 209 | 0x039b0ef5, |
| 210 | /* 0x0004: queue_put */ | 210 | /* 0x0004: queue_put */ |
| 211 | 0x9800d898, | 211 | 0x9800d898, |
| 212 | 0x86f001d9, | 212 | 0x86f001d9, |
| 213 | 0x0489b808, | 213 | 0x0489b808, |
| 214 | 0xf00c1bf4, | 214 | 0xf00c1bf4, |
| 215 | 0x21f502f7, | 215 | 0x21f502f7, |
| 216 | 0x00f802fe, | 216 | 0x00f8037e, |
| 217 | /* 0x001c: queue_put_next */ | 217 | /* 0x001c: queue_put_next */ |
| 218 | 0xb60798c4, | 218 | 0xb60798c4, |
| 219 | 0x8dbb0384, | 219 | 0x8dbb0384, |
| @@ -237,184 +237,214 @@ uint32_t nvf0_grhub_code[] = { | |||
| 237 | /* 0x0066: queue_get_done */ | 237 | /* 0x0066: queue_get_done */ |
| 238 | 0x00f80132, | 238 | 0x00f80132, |
| 239 | /* 0x0068: nv_rd32 */ | 239 | /* 0x0068: nv_rd32 */ |
| 240 | 0x0728b7f1, | 240 | 0xf002ecb9, |
| 241 | 0xb906b4b6, | 241 | 0x07f11fc9, |
| 242 | 0xc9f002ec, | 242 | 0x03f0ca00, |
| 243 | 0x00bcd01f, | 243 | 0x000cd001, |
| 244 | /* 0x0078: nv_rd32_wait */ | 244 | /* 0x007a: nv_rd32_wait */ |
| 245 | 0xc800bccf, | 245 | 0xc7f104bd, |
| 246 | 0x1bf41fcc, | 246 | 0xc3f0ca00, |
| 247 | 0x06a7f0fa, | 247 | 0x00cccf01, |
| 248 | 0x010921f5, | 248 | 0xf41fccc8, |
| 249 | 0xf840bfcf, | 249 | 0xa7f0f31b, |
| 250 | /* 0x008d: nv_wr32 */ | 250 | 0x1021f506, |
| 251 | 0x28b7f100, | 251 | 0x00f7f101, |
| 252 | 0x06b4b607, | 252 | 0x01f3f0cb, |
| 253 | 0xb980bfd0, | 253 | 0xf800ffcf, |
| 254 | 0xc9f002ec, | 254 | /* 0x009d: nv_wr32 */ |
| 255 | 0x1ec9f01f, | 255 | 0x0007f100, |
| 256 | /* 0x00a3: nv_wr32_wait */ | 256 | 0x0103f0cc, |
| 257 | 0xcf00bcd0, | 257 | 0xbd000fd0, |
| 258 | 0xccc800bc, | 258 | 0x02ecb904, |
| 259 | 0xfa1bf41f, | 259 | 0xf01fc9f0, |
| 260 | /* 0x00ae: watchdog_reset */ | 260 | 0x07f11ec9, |
| 261 | 0x87f100f8, | 261 | 0x03f0ca00, |
| 262 | 0x84b60430, | 262 | 0x000cd001, |
| 263 | 0x1ff9f006, | 263 | /* 0x00be: nv_wr32_wait */ |
| 264 | 0xf8008fd0, | 264 | 0xc7f104bd, |
| 265 | /* 0x00bd: watchdog_clear */ | 265 | 0xc3f0ca00, |
| 266 | 0x3087f100, | 266 | 0x00cccf01, |
| 267 | 0x0684b604, | 267 | 0xf41fccc8, |
| 268 | 0xf80080d0, | 268 | 0x00f8f31b, |
| 269 | /* 0x00c9: wait_donez */ | 269 | /* 0x00d0: wait_donez */ |
| 270 | 0xf094bd00, | 270 | 0x99f094bd, |
| 271 | 0x07f10099, | 271 | 0x0007f100, |
| 272 | 0x03f03700, | 272 | 0x0203f037, |
| 273 | 0x0009d002, | 273 | 0xbd0009d0, |
| 274 | 0x07f104bd, | 274 | 0x0007f104, |
| 275 | 0x03f00600, | 275 | 0x0203f006, |
| 276 | 0x000ad002, | 276 | 0xbd000ad0, |
| 277 | /* 0x00e6: wait_donez_ne */ | 277 | /* 0x00ed: wait_donez_ne */ |
| 278 | 0x87f104bd, | 278 | 0x0087f104, |
| 279 | 0x83f00000, | 279 | 0x0183f000, |
| 280 | 0x0088cf01, | 280 | 0xff0088cf, |
| 281 | 0xf4888aff, | 281 | 0x1bf4888a, |
| 282 | 0x94bdf31b, | 282 | 0xf094bdf3, |
| 283 | 0xf10099f0, | ||
| 284 | 0xf0170007, | ||
| 285 | 0x09d00203, | ||
| 286 | 0xf804bd00, | ||
| 287 | /* 0x0109: wait_doneo */ | ||
| 288 | 0xf094bd00, | ||
| 289 | 0x07f10099, | 283 | 0x07f10099, |
| 290 | 0x03f03700, | 284 | 0x03f01700, |
| 291 | 0x0009d002, | 285 | 0x0009d002, |
| 292 | 0x87f104bd, | 286 | 0x00f804bd, |
| 293 | 0x84b60818, | 287 | /* 0x0110: wait_doneo */ |
| 294 | 0x008ad006, | ||
| 295 | /* 0x0124: wait_doneo_e */ | ||
| 296 | 0x040087f1, | ||
| 297 | 0xcf0684b6, | ||
| 298 | 0x8aff0088, | ||
| 299 | 0xf30bf488, | ||
| 300 | 0x99f094bd, | 288 | 0x99f094bd, |
| 301 | 0x0007f100, | 289 | 0x0007f100, |
| 302 | 0x0203f017, | 290 | 0x0203f037, |
| 303 | 0xbd0009d0, | 291 | 0xbd0009d0, |
| 304 | /* 0x0147: mmctx_size */ | 292 | 0x0007f104, |
| 305 | 0xbd00f804, | 293 | 0x0203f006, |
| 306 | /* 0x0149: nv_mmctx_size_loop */ | 294 | 0xbd000ad0, |
| 307 | 0x00e89894, | 295 | /* 0x012d: wait_doneo_e */ |
| 308 | 0xb61a85b6, | 296 | 0x0087f104, |
| 309 | 0x84b60180, | 297 | 0x0183f000, |
| 310 | 0x0098bb02, | 298 | 0xff0088cf, |
| 311 | 0xb804e0b6, | 299 | 0x0bf4888a, |
| 312 | 0x1bf404ef, | 300 | 0xf094bdf3, |
| 313 | 0x029fb9eb, | 301 | 0x07f10099, |
| 314 | /* 0x0166: mmctx_xfer */ | 302 | 0x03f01700, |
| 315 | 0x94bd00f8, | 303 | 0x0009d002, |
| 316 | 0xf10199f0, | 304 | 0x00f804bd, |
| 317 | 0xf0370007, | 305 | /* 0x0150: mmctx_size */ |
| 318 | 0x09d00203, | 306 | /* 0x0152: nv_mmctx_size_loop */ |
| 319 | 0xf104bd00, | 307 | 0xe89894bd, |
| 320 | 0xb6071087, | 308 | 0x1a85b600, |
| 321 | 0x94bd0684, | 309 | 0xb60180b6, |
| 322 | 0xf405bbfd, | 310 | 0x98bb0284, |
| 323 | 0x8bd0090b, | 311 | 0x04e0b600, |
| 324 | 0x0099f000, | 312 | 0xf404efb8, |
| 325 | /* 0x018c: mmctx_base_disabled */ | 313 | 0x9fb9eb1b, |
| 326 | 0xf405eefd, | 314 | /* 0x016f: mmctx_xfer */ |
| 327 | 0x8ed00c0b, | 315 | 0xbd00f802, |
| 328 | 0xc08fd080, | 316 | 0x0199f094, |
| 329 | /* 0x019b: mmctx_multi_disabled */ | 317 | 0x370007f1, |
| 330 | 0xb70199f0, | 318 | 0xd00203f0, |
| 331 | 0xc8010080, | 319 | 0x04bd0009, |
| 320 | 0xbbfd94bd, | ||
| 321 | 0x120bf405, | ||
| 322 | 0xc40007f1, | ||
| 323 | 0xd00103f0, | ||
| 324 | 0x04bd000b, | ||
| 325 | /* 0x0197: mmctx_base_disabled */ | ||
| 326 | 0xfd0099f0, | ||
| 327 | 0x0bf405ee, | ||
| 328 | 0x0007f11e, | ||
| 329 | 0x0103f0c6, | ||
| 330 | 0xbd000ed0, | ||
| 331 | 0x0007f104, | ||
| 332 | 0x0103f0c7, | ||
| 333 | 0xbd000fd0, | ||
| 334 | 0x0199f004, | ||
| 335 | /* 0x01b8: mmctx_multi_disabled */ | ||
| 336 | 0xb600abc8, | ||
| 337 | 0xb9f010b4, | ||
| 338 | 0x01aec80c, | ||
| 339 | 0xfd11e4b6, | ||
| 340 | 0x07f105be, | ||
| 341 | 0x03f0c500, | ||
| 342 | 0x000bd001, | ||
| 343 | /* 0x01d6: mmctx_exec_loop */ | ||
| 344 | /* 0x01d6: mmctx_wait_free */ | ||
| 345 | 0xe7f104bd, | ||
| 346 | 0xe3f0c500, | ||
| 347 | 0x00eecf01, | ||
| 348 | 0xf41fe4f0, | ||
| 349 | 0xce98f30b, | ||
| 350 | 0x05e9fd00, | ||
| 351 | 0xc80007f1, | ||
| 352 | 0xd00103f0, | ||
| 353 | 0x04bd000e, | ||
| 354 | 0xb804c0b6, | ||
| 355 | 0x1bf404cd, | ||
| 356 | 0x02abc8d8, | ||
| 357 | /* 0x0207: mmctx_fini_wait */ | ||
| 358 | 0xf11f1bf4, | ||
| 359 | 0xf0c500b7, | ||
| 360 | 0xbbcf01b3, | ||
| 361 | 0x1fb4f000, | ||
| 362 | 0xf410b4b0, | ||
| 363 | 0xa7f0f01b, | ||
| 364 | 0xd021f402, | ||
| 365 | /* 0x0223: mmctx_stop */ | ||
| 366 | 0xc82b0ef4, | ||
| 332 | 0xb4b600ab, | 367 | 0xb4b600ab, |
| 333 | 0x0cb9f010, | 368 | 0x0cb9f010, |
| 334 | 0xb601aec8, | 369 | 0xf112b9f0, |
| 335 | 0xbefd11e4, | 370 | 0xf0c50007, |
| 336 | 0x008bd005, | 371 | 0x0bd00103, |
| 337 | /* 0x01b4: mmctx_exec_loop */ | 372 | /* 0x023b: mmctx_stop_wait */ |
| 338 | /* 0x01b4: mmctx_wait_free */ | 373 | 0xf104bd00, |
| 339 | 0xf0008ecf, | 374 | 0xf0c500b7, |
| 340 | 0x0bf41fe4, | 375 | 0xbbcf01b3, |
| 341 | 0x00ce98fa, | 376 | 0x12bbc800, |
| 342 | 0xd005e9fd, | 377 | /* 0x024b: mmctx_done */ |
| 343 | 0xc0b6c08e, | 378 | 0xbdf31bf4, |
| 344 | 0x04cdb804, | 379 | 0x0199f094, |
| 345 | 0xc8e81bf4, | 380 | 0x170007f1, |
| 346 | 0x1bf402ab, | 381 | 0xd00203f0, |
| 347 | /* 0x01d5: mmctx_fini_wait */ | 382 | 0x04bd0009, |
| 348 | 0x008bcf18, | 383 | /* 0x025e: strand_wait */ |
| 349 | 0xb01fb4f0, | 384 | 0xa0f900f8, |
| 350 | 0x1bf410b4, | 385 | 0xf402a7f0, |
| 351 | 0x02a7f0f7, | 386 | 0xa0fcd021, |
| 352 | 0xf4c921f4, | 387 | /* 0x026a: strand_pre */ |
| 353 | /* 0x01ea: mmctx_stop */ | 388 | 0x97f000f8, |
| 354 | 0xabc81b0e, | 389 | 0xfc07f10c, |
| 355 | 0x10b4b600, | 390 | 0x0203f04a, |
| 356 | 0xf00cb9f0, | 391 | 0xbd0009d0, |
| 357 | 0x8bd012b9, | 392 | 0x5e21f504, |
| 358 | /* 0x01f9: mmctx_stop_wait */ | 393 | /* 0x027f: strand_post */ |
| 359 | 0x008bcf00, | 394 | 0xf000f802, |
| 360 | 0xf412bbc8, | 395 | 0x07f10d97, |
| 361 | /* 0x0202: mmctx_done */ | 396 | 0x03f04afc, |
| 362 | 0x94bdfa1b, | ||
| 363 | 0xf10199f0, | ||
| 364 | 0xf0170007, | ||
| 365 | 0x09d00203, | ||
| 366 | 0xf804bd00, | ||
| 367 | /* 0x0215: strand_wait */ | ||
| 368 | 0xf0a0f900, | ||
| 369 | 0x21f402a7, | ||
| 370 | 0xf8a0fcc9, | ||
| 371 | /* 0x0221: strand_pre */ | ||
| 372 | 0xfc87f100, | ||
| 373 | 0x0283f04a, | ||
| 374 | 0xd00c97f0, | ||
| 375 | 0x21f50089, | ||
| 376 | 0x00f80215, | ||
| 377 | /* 0x0234: strand_post */ | ||
| 378 | 0x4afc87f1, | ||
| 379 | 0xf00283f0, | ||
| 380 | 0x89d00d97, | ||
| 381 | 0x1521f500, | ||
| 382 | /* 0x0247: strand_set */ | ||
| 383 | 0xf100f802, | ||
| 384 | 0xf04ffca7, | ||
| 385 | 0xaba202a3, | ||
| 386 | 0xc7f00500, | ||
| 387 | 0x00acd00f, | ||
| 388 | 0xd00bc7f0, | ||
| 389 | 0x21f500bc, | ||
| 390 | 0xaed00215, | ||
| 391 | 0x0ac7f000, | ||
| 392 | 0xf500bcd0, | ||
| 393 | 0xf8021521, | ||
| 394 | /* 0x0271: strand_ctx_init */ | ||
| 395 | 0xf094bd00, | ||
| 396 | 0x07f10399, | ||
| 397 | 0x03f03700, | ||
| 398 | 0x0009d002, | 397 | 0x0009d002, |
| 399 | 0x21f504bd, | 398 | 0x21f504bd, |
| 400 | 0xe7f00221, | 399 | 0x00f8025e, |
| 401 | 0x4721f503, | 400 | /* 0x0294: strand_set */ |
| 402 | 0xfca7f102, | 401 | 0xf10fc7f0, |
| 403 | 0x02a3f046, | 402 | 0xf04ffc07, |
| 404 | 0x0400aba0, | 403 | 0x0cd00203, |
| 405 | 0xf040a0d0, | 404 | 0xf004bd00, |
| 406 | 0xbcd001c7, | 405 | 0x07f10bc7, |
| 407 | 0x1521f500, | 406 | 0x03f04afc, |
| 408 | 0x010c9202, | 407 | 0x000cd002, |
| 409 | 0xf000acd0, | 408 | 0x07f104bd, |
| 410 | 0xbcd002c7, | 409 | 0x03f04ffc, |
| 411 | 0x1521f500, | 410 | 0x000ed002, |
| 412 | 0x3421f502, | 411 | 0xc7f004bd, |
| 413 | 0x8087f102, | 412 | 0xfc07f10a, |
| 414 | 0x0684b608, | 413 | 0x0203f04a, |
| 415 | 0xb70089cf, | 414 | 0xbd000cd0, |
| 416 | 0x95220080, | 415 | 0x5e21f504, |
| 417 | /* 0x02ca: ctx_init_strand_loop */ | 416 | /* 0x02d3: strand_ctx_init */ |
| 417 | 0xbd00f802, | ||
| 418 | 0x0399f094, | ||
| 419 | 0x370007f1, | ||
| 420 | 0xd00203f0, | ||
| 421 | 0x04bd0009, | ||
| 422 | 0x026a21f5, | ||
| 423 | 0xf503e7f0, | ||
| 424 | 0xbd029421, | ||
| 425 | 0xfc07f1c4, | ||
| 426 | 0x0203f047, | ||
| 427 | 0xbd000cd0, | ||
| 428 | 0x01c7f004, | ||
| 429 | 0x4afc07f1, | ||
| 430 | 0xd00203f0, | ||
| 431 | 0x04bd000c, | ||
| 432 | 0x025e21f5, | ||
| 433 | 0xf1010c92, | ||
| 434 | 0xf046fc07, | ||
| 435 | 0x0cd00203, | ||
| 436 | 0xf004bd00, | ||
| 437 | 0x07f102c7, | ||
| 438 | 0x03f04afc, | ||
| 439 | 0x000cd002, | ||
| 440 | 0x21f504bd, | ||
| 441 | 0x21f5025e, | ||
| 442 | 0x87f1027f, | ||
| 443 | 0x83f04200, | ||
| 444 | 0x0097f102, | ||
| 445 | 0x0293f020, | ||
| 446 | 0x950099cf, | ||
| 447 | /* 0x034a: ctx_init_strand_loop */ | ||
| 418 | 0x8ed008fe, | 448 | 0x8ed008fe, |
| 419 | 0x408ed000, | 449 | 0x408ed000, |
| 420 | 0xb6808acf, | 450 | 0xb6808acf, |
| @@ -428,7 +458,7 @@ uint32_t nvf0_grhub_code[] = { | |||
| 428 | 0x170007f1, | 458 | 0x170007f1, |
| 429 | 0xd00203f0, | 459 | 0xd00203f0, |
| 430 | 0x04bd0009, | 460 | 0x04bd0009, |
| 431 | /* 0x02fe: error */ | 461 | /* 0x037e: error */ |
| 432 | 0x07f100f8, | 462 | 0x07f100f8, |
| 433 | 0x03f00500, | 463 | 0x03f00500, |
| 434 | 0x000fd002, | 464 | 0x000fd002, |
| @@ -436,82 +466,117 @@ uint32_t nvf0_grhub_code[] = { | |||
| 436 | 0x0007f101, | 466 | 0x0007f101, |
| 437 | 0x0303f007, | 467 | 0x0303f007, |
| 438 | 0xbd000fd0, | 468 | 0xbd000fd0, |
| 439 | /* 0x031b: init */ | 469 | /* 0x039b: init */ |
| 440 | 0xbd00f804, | 470 | 0xbd00f804, |
| 441 | 0x0004fe04, | 471 | 0x0007fe04, |
| 442 | 0xf10007fe, | 472 | 0x420017f1, |
| 443 | 0xf0120017, | 473 | 0xcf0013f0, |
| 444 | 0x12d00227, | 474 | 0x11e70011, |
| 445 | 0xb117f100, | 475 | 0x14b60109, |
| 446 | 0x0010fe05, | 476 | 0x0014fe08, |
| 447 | 0x040017f1, | 477 | 0xf10227f0, |
| 448 | 0xf1c010d0, | 478 | 0xf0120007, |
| 449 | 0xb6040437, | 479 | 0x02d00003, |
| 450 | 0x27f10634, | 480 | 0xf104bd00, |
| 451 | 0x32d02003, | 481 | 0xfe06c817, |
| 452 | 0x0427f100, | 482 | 0x24bd0010, |
| 453 | 0x0132d020, | 483 | 0x070007f1, |
| 484 | 0xd00003f0, | ||
| 485 | 0x04bd0002, | ||
| 486 | 0x200327f1, | ||
| 487 | 0x010007f1, | ||
| 488 | 0xd00103f0, | ||
| 489 | 0x04bd0002, | ||
| 490 | 0x200427f1, | ||
| 491 | 0x010407f1, | ||
| 492 | 0xd00103f0, | ||
| 493 | 0x04bd0002, | ||
| 454 | 0x200b27f1, | 494 | 0x200b27f1, |
| 455 | 0xf10232d0, | 495 | 0x010807f1, |
| 456 | 0xd0200c27, | 496 | 0xd00103f0, |
| 457 | 0x27f10732, | 497 | 0x04bd0002, |
| 458 | 0x24b60c24, | 498 | 0x200c27f1, |
| 459 | 0x0003b906, | 499 | 0x011c07f1, |
| 460 | 0xf10023d0, | 500 | 0xd00103f0, |
| 501 | 0x04bd0002, | ||
| 502 | 0xf1010392, | ||
| 503 | 0xf0090007, | ||
| 504 | 0x03d00303, | ||
| 505 | 0xf104bd00, | ||
| 461 | 0xf0870427, | 506 | 0xf0870427, |
| 462 | 0x12d00023, | 507 | 0x07f10023, |
| 463 | 0x0012b700, | 508 | 0x03f00400, |
| 464 | 0x0427f001, | 509 | 0x0002d000, |
| 465 | 0xf40012d0, | 510 | 0x27f004bd, |
| 466 | 0xe7f11031, | 511 | 0x0007f104, |
| 467 | 0xe3f09604, | 512 | 0x0003f003, |
| 468 | 0x6821f440, | 513 | 0xbd0002d0, |
| 469 | 0x8090f1c7, | 514 | 0x1031f404, |
| 470 | 0xf4f00301, | 515 | 0x9604e7f1, |
| 471 | 0x020f801f, | 516 | 0xf440e3f0, |
| 472 | 0xbb0117f0, | 517 | 0xfeb96821, |
| 473 | 0x12b6041f, | 518 | 0x90f1c702, |
| 474 | 0x0c27f101, | 519 | 0xf0030180, |
| 475 | 0x0624b604, | 520 | 0x0f801ff4, |
| 476 | 0xd00021d0, | 521 | 0x0117f002, |
| 477 | 0x17f14021, | 522 | 0xb6041fbb, |
| 478 | 0x0e980100, | 523 | 0x07f10112, |
| 479 | 0x010f9800, | 524 | 0x03f00300, |
| 480 | 0x014721f5, | 525 | 0x0001d001, |
| 481 | 0x070037f1, | 526 | 0x07f104bd, |
| 482 | 0x950634b6, | 527 | 0x03f00400, |
| 483 | 0x34d00814, | 528 | 0x0001d001, |
| 484 | 0x4034d000, | 529 | 0x17f104bd, |
| 485 | 0x130030b7, | 530 | 0xf7f00100, |
| 486 | 0xb6001fbb, | 531 | 0x7f21f502, |
| 487 | 0x3fd002f5, | 532 | 0x9121f507, |
| 488 | 0x0815b600, | 533 | 0x10f7f007, |
| 489 | 0xb60110b6, | 534 | 0x07de21f5, |
| 490 | 0x1fb90814, | 535 | 0x98000e98, |
| 491 | 0x7121f502, | 536 | 0x21f5010f, |
| 492 | 0x001fbb02, | 537 | 0x14950150, |
| 493 | 0xf1020398, | 538 | 0x0007f108, |
| 494 | 0xf0200047, | 539 | 0x0103f0c0, |
| 495 | /* 0x03f6: init_gpc */ | 540 | 0xbd0004d0, |
| 496 | 0x4ea05043, | 541 | 0x0007f104, |
| 497 | 0x1fb90804, | 542 | 0x0103f0c1, |
| 498 | 0x8d21f402, | 543 | 0xbd0004d0, |
| 499 | 0x010c4ea0, | 544 | 0x0030b704, |
| 500 | 0x21f4f4bd, | 545 | 0x001fbb13, |
| 501 | 0x044ea08d, | 546 | 0xf102f5b6, |
| 502 | 0x8d21f401, | 547 | 0xf0d30007, |
| 503 | 0x01004ea0, | 548 | 0x0fd00103, |
| 504 | 0xf402f7f0, | 549 | 0xb604bd00, |
| 505 | 0x4ea08d21, | 550 | 0x10b60815, |
| 506 | /* 0x041e: init_gpc_wait */ | 551 | 0x0814b601, |
| 507 | 0x21f40800, | 552 | 0xf5021fb9, |
| 508 | 0x1fffc868, | 553 | 0xbb02d321, |
| 509 | 0xa0fa0bf4, | 554 | 0x0398001f, |
| 510 | 0xf408044e, | 555 | 0x0047f102, |
| 511 | 0x1fbb6821, | 556 | 0x5043f020, |
| 512 | 0x0040b700, | 557 | /* 0x04f4: init_gpc */ |
| 513 | 0x0132b680, | 558 | 0x08044ea0, |
| 514 | 0xf1be1bf4, | 559 | 0xf4021fb9, |
| 560 | 0x4ea09d21, | ||
| 561 | 0xf4bd010c, | ||
| 562 | 0xa09d21f4, | ||
| 563 | 0xf401044e, | ||
| 564 | 0x4ea09d21, | ||
| 565 | 0xf7f00100, | ||
| 566 | 0x9d21f402, | ||
| 567 | 0x08004ea0, | ||
| 568 | /* 0x051c: init_gpc_wait */ | ||
| 569 | 0xc86821f4, | ||
| 570 | 0x0bf41fff, | ||
| 571 | 0x044ea0fa, | ||
| 572 | 0x6821f408, | ||
| 573 | 0xb7001fbb, | ||
| 574 | 0xb6800040, | ||
| 575 | 0x1bf40132, | ||
| 576 | 0x00f7f0be, | ||
| 577 | 0x07de21f5, | ||
| 578 | 0xf500f7f0, | ||
| 579 | 0xf1077f21, | ||
| 515 | 0xf0010007, | 580 | 0xf0010007, |
| 516 | 0x01d00203, | 581 | 0x01d00203, |
| 517 | 0xbd04bd00, | 582 | 0xbd04bd00, |
| @@ -519,382 +584,379 @@ uint32_t nvf0_grhub_code[] = { | |||
| 519 | 0x300007f1, | 584 | 0x300007f1, |
| 520 | 0xd00203f0, | 585 | 0xd00203f0, |
| 521 | 0x04bd0001, | 586 | 0x04bd0001, |
| 522 | /* 0x0458: main */ | 587 | /* 0x0564: main */ |
| 523 | 0xf40031f4, | 588 | 0xf40031f4, |
| 524 | 0xd7f00028, | 589 | 0xd7f00028, |
| 525 | 0x3921f410, | 590 | 0x3921f410, |
| 526 | 0xb1f401f4, | 591 | 0xb1f401f4, |
| 527 | 0xf54001e4, | 592 | 0xf54001e4, |
| 528 | 0xbd00de1b, | 593 | 0xbd00e91b, |
| 529 | 0x0499f094, | 594 | 0x0499f094, |
| 530 | 0x370007f1, | 595 | 0x370007f1, |
| 531 | 0xd00203f0, | 596 | 0xd00203f0, |
| 532 | 0x04bd0009, | 597 | 0x04bd0009, |
| 533 | 0x0b0017f1, | 598 | 0xc00017f1, |
| 534 | 0xcf0614b6, | 599 | 0xcf0213f0, |
| 535 | 0x11cf4012, | 600 | 0x27f10011, |
| 536 | 0x1f13c800, | 601 | 0x23f0c100, |
| 537 | 0x00870bf5, | 602 | 0x0022cf02, |
| 538 | 0xf41f23c8, | 603 | 0xf51f13c8, |
| 539 | 0x20f9620b, | 604 | 0xc800890b, |
| 540 | 0xbd0212b9, | 605 | 0x0bf41f23, |
| 541 | 0x0799f094, | 606 | 0xb920f962, |
| 542 | 0x370007f1, | 607 | 0x94bd0212, |
| 543 | 0xd00203f0, | ||
| 544 | 0x04bd0009, | ||
| 545 | 0xf40132f4, | ||
| 546 | 0x21f50231, | ||
| 547 | 0x94bd0801, | ||
| 548 | 0xf10799f0, | 608 | 0xf10799f0, |
| 549 | 0xf0170007, | 609 | 0xf0370007, |
| 550 | 0x09d00203, | 610 | 0x09d00203, |
| 551 | 0xfc04bd00, | 611 | 0xf404bd00, |
| 552 | 0xf094bd20, | 612 | 0x31f40132, |
| 553 | 0x07f10699, | 613 | 0xaa21f502, |
| 554 | 0x03f03700, | 614 | 0xf094bd09, |
| 555 | 0x0009d002, | 615 | 0x07f10799, |
| 556 | 0x31f404bd, | ||
| 557 | 0x0121f501, | ||
| 558 | 0xf094bd08, | ||
| 559 | 0x07f10699, | ||
| 560 | 0x03f01700, | 616 | 0x03f01700, |
| 561 | 0x0009d002, | 617 | 0x0009d002, |
| 562 | 0x0ef404bd, | 618 | 0x20fc04bd, |
| 563 | /* 0x04f9: chsw_prev_no_next */ | ||
| 564 | 0xb920f931, | ||
| 565 | 0x32f40212, | ||
| 566 | 0x0232f401, | ||
| 567 | 0x080121f5, | ||
| 568 | 0x17f120fc, | ||
| 569 | 0x14b60b00, | ||
| 570 | 0x0012d006, | ||
| 571 | /* 0x0517: chsw_no_prev */ | ||
| 572 | 0xc8130ef4, | ||
| 573 | 0x0bf41f23, | ||
| 574 | 0x0131f40d, | ||
| 575 | 0xf50232f4, | ||
| 576 | /* 0x0527: chsw_done */ | ||
| 577 | 0xf1080121, | ||
| 578 | 0xb60b0c17, | ||
| 579 | 0x27f00614, | ||
| 580 | 0x0012d001, | ||
| 581 | 0x99f094bd, | 619 | 0x99f094bd, |
| 582 | 0x0007f104, | 620 | 0x0007f106, |
| 621 | 0x0203f037, | ||
| 622 | 0xbd0009d0, | ||
| 623 | 0x0131f404, | ||
| 624 | 0x09aa21f5, | ||
| 625 | 0x99f094bd, | ||
| 626 | 0x0007f106, | ||
| 583 | 0x0203f017, | 627 | 0x0203f017, |
| 584 | 0xbd0009d0, | 628 | 0xbd0009d0, |
| 585 | 0x130ef504, | 629 | 0x330ef404, |
| 586 | /* 0x0549: main_not_ctx_switch */ | 630 | /* 0x060c: chsw_prev_no_next */ |
| 587 | 0x01e4b0ff, | 631 | 0x12b920f9, |
| 588 | 0xb90d1bf4, | 632 | 0x0132f402, |
| 589 | 0x21f502f2, | 633 | 0xf50232f4, |
| 590 | 0x0ef40795, | 634 | 0xfc09aa21, |
| 591 | /* 0x0559: main_not_ctx_chan */ | 635 | 0x0007f120, |
| 592 | 0x02e4b046, | 636 | 0x0203f0c0, |
| 593 | 0xbd321bf4, | 637 | 0xbd0002d0, |
| 594 | 0x0799f094, | 638 | 0x130ef404, |
| 595 | 0x370007f1, | 639 | /* 0x062c: chsw_no_prev */ |
| 640 | 0xf41f23c8, | ||
| 641 | 0x31f40d0b, | ||
| 642 | 0x0232f401, | ||
| 643 | 0x09aa21f5, | ||
| 644 | /* 0x063c: chsw_done */ | ||
| 645 | 0xf10127f0, | ||
| 646 | 0xf0c30007, | ||
| 647 | 0x02d00203, | ||
| 648 | 0xbd04bd00, | ||
| 649 | 0x0499f094, | ||
| 650 | 0x170007f1, | ||
| 596 | 0xd00203f0, | 651 | 0xd00203f0, |
| 597 | 0x04bd0009, | 652 | 0x04bd0009, |
| 598 | 0xf40132f4, | 653 | 0xff080ef5, |
| 599 | 0x21f50232, | 654 | /* 0x0660: main_not_ctx_switch */ |
| 600 | 0x94bd0801, | 655 | 0xf401e4b0, |
| 656 | 0xf2b90d1b, | ||
| 657 | 0x4221f502, | ||
| 658 | 0x460ef409, | ||
| 659 | /* 0x0670: main_not_ctx_chan */ | ||
| 660 | 0xf402e4b0, | ||
| 661 | 0x94bd321b, | ||
| 601 | 0xf10799f0, | 662 | 0xf10799f0, |
| 602 | 0xf0170007, | 663 | 0xf0370007, |
| 603 | 0x09d00203, | 664 | 0x09d00203, |
| 604 | 0xf404bd00, | 665 | 0xf404bd00, |
| 605 | /* 0x058e: main_not_ctx_save */ | 666 | 0x32f40132, |
| 606 | 0xef94110e, | 667 | 0xaa21f502, |
| 607 | 0x01f5f010, | 668 | 0xf094bd09, |
| 608 | 0x02fe21f5, | 669 | 0x07f10799, |
| 609 | 0xfec00ef5, | 670 | 0x03f01700, |
| 610 | /* 0x059c: main_done */ | 671 | 0x0009d002, |
| 611 | 0x29f024bd, | 672 | 0x0ef404bd, |
| 612 | 0x0007f11f, | 673 | /* 0x06a5: main_not_ctx_save */ |
| 613 | 0x0203f030, | 674 | 0x10ef9411, |
| 614 | 0xbd0002d0, | 675 | 0xf501f5f0, |
| 615 | 0xab0ef504, | 676 | 0xf5037e21, |
| 616 | /* 0x05b1: ih */ | 677 | /* 0x06b3: main_done */ |
| 617 | 0xfe80f9fe, | 678 | 0xbdfeb50e, |
| 618 | 0x80f90188, | 679 | 0x1f29f024, |
| 619 | 0xa0f990f9, | 680 | 0x300007f1, |
| 620 | 0xd0f9b0f9, | 681 | 0xd00203f0, |
| 621 | 0xf0f9e0f9, | 682 | 0x04bd0002, |
| 622 | 0x0acf04bd, | 683 | 0xfea00ef5, |
| 623 | 0x04abc480, | 684 | /* 0x06c8: ih */ |
| 624 | 0xf11d0bf4, | 685 | 0x88fe80f9, |
| 625 | 0xf01900b7, | 686 | 0xf980f901, |
| 626 | 0xbecf10d7, | 687 | 0xf9a0f990, |
| 627 | 0x00bfcf40, | 688 | 0xf9d0f9b0, |
| 689 | 0xbdf0f9e0, | ||
| 690 | 0x00a7f104, | ||
| 691 | 0x00a3f002, | ||
| 692 | 0xc400aacf, | ||
| 693 | 0x0bf404ab, | ||
| 694 | 0x10d7f030, | ||
| 695 | 0x1a00e7f1, | ||
| 696 | 0xcf00e3f0, | ||
| 697 | 0xf7f100ee, | ||
| 698 | 0xf3f01900, | ||
| 699 | 0x00ffcf00, | ||
| 628 | 0xb70421f4, | 700 | 0xb70421f4, |
| 629 | 0xf00400b0, | 701 | 0xf00400b0, |
| 630 | 0xbed001e7, | 702 | 0x07f101e7, |
| 631 | /* 0x05e9: ih_no_fifo */ | 703 | 0x03f01d00, |
| 632 | 0x00abe400, | 704 | 0x000ed000, |
| 633 | 0x0d0bf401, | 705 | /* 0x071a: ih_no_fifo */ |
| 634 | 0xf110d7f0, | 706 | 0xabe404bd, |
| 635 | 0xf44001e7, | 707 | 0x0bf40100, |
| 636 | /* 0x05fa: ih_no_ctxsw */ | 708 | 0x10d7f00d, |
| 637 | 0xb7f10421, | 709 | 0x4001e7f1, |
| 638 | 0xb0bd0104, | 710 | /* 0x072b: ih_no_ctxsw */ |
| 639 | 0xf4b4abff, | 711 | 0xe40421f4, |
| 640 | 0xa7f10d0b, | 712 | 0xf40400ab, |
| 641 | 0xa4b60c1c, | 713 | 0xb7f1140b, |
| 642 | 0x00abd006, | 714 | 0xbfb90100, |
| 643 | /* 0x0610: ih_no_other */ | 715 | 0x44e7f102, |
| 644 | 0xfc400ad0, | 716 | 0x40e3f001, |
| 717 | /* 0x0743: ih_no_fwmthd */ | ||
| 718 | 0xf19d21f4, | ||
| 719 | 0xbd0104b7, | ||
| 720 | 0xb4abffb0, | ||
| 721 | 0xf10f0bf4, | ||
| 722 | 0xf0070007, | ||
| 723 | 0x0bd00303, | ||
| 724 | /* 0x075b: ih_no_other */ | ||
| 725 | 0xf104bd00, | ||
| 726 | 0xf0010007, | ||
| 727 | 0x0ad00003, | ||
| 728 | 0xfc04bd00, | ||
| 645 | 0xfce0fcf0, | 729 | 0xfce0fcf0, |
| 646 | 0xfcb0fcd0, | 730 | 0xfcb0fcd0, |
| 647 | 0xfc90fca0, | 731 | 0xfc90fca0, |
| 648 | 0x0088fe80, | 732 | 0x0088fe80, |
| 649 | 0x32f480fc, | 733 | 0x32f480fc, |
| 650 | /* 0x062b: ctx_4170s */ | 734 | /* 0x077f: ctx_4170s */ |
| 651 | 0xf101f800, | 735 | 0xf001f800, |
| 652 | 0xf04170e7, | 736 | 0xffb910f5, |
| 653 | 0xf5f040e3, | 737 | 0x70e7f102, |
| 654 | 0x8d21f410, | 738 | 0x40e3f041, |
| 655 | /* 0x063a: ctx_4170w */ | 739 | 0xf89d21f4, |
| 740 | /* 0x0791: ctx_4170w */ | ||
| 741 | 0x70e7f100, | ||
| 742 | 0x40e3f041, | ||
| 743 | 0xb96821f4, | ||
| 744 | 0xf4f002ff, | ||
| 745 | 0xf01bf410, | ||
| 746 | /* 0x07a6: ctx_redswitch */ | ||
| 656 | 0xe7f100f8, | 747 | 0xe7f100f8, |
| 657 | 0xe3f04170, | 748 | 0xe5f00200, |
| 658 | 0x6821f440, | 749 | 0x20e5f040, |
| 659 | 0xf410f4f0, | 750 | 0xf110e5f0, |
| 751 | 0xf0850007, | ||
| 752 | 0x0ed00103, | ||
| 753 | 0xf004bd00, | ||
| 754 | /* 0x07c2: ctx_redswitch_delay */ | ||
| 755 | 0xf2b608f7, | ||
| 756 | 0xfd1bf401, | ||
| 757 | 0x0400e5f1, | ||
| 758 | 0x0100e5f1, | ||
| 759 | 0x850007f1, | ||
| 760 | 0xd00103f0, | ||
| 761 | 0x04bd000e, | ||
| 762 | /* 0x07de: ctx_86c */ | ||
| 763 | 0x07f100f8, | ||
| 764 | 0x03f02300, | ||
| 765 | 0x000fd002, | ||
| 766 | 0xffb904bd, | ||
| 767 | 0x14e7f102, | ||
| 768 | 0x40e3f08a, | ||
| 769 | 0xb99d21f4, | ||
| 770 | 0xe7f102ff, | ||
| 771 | 0xe3f0a88c, | ||
| 772 | 0x9d21f441, | ||
| 773 | /* 0x0806: ctx_mem */ | ||
| 774 | 0x07f100f8, | ||
| 775 | 0x03f08400, | ||
| 776 | 0x000fd002, | ||
| 777 | /* 0x0812: ctx_mem_wait */ | ||
| 778 | 0xf7f104bd, | ||
| 779 | 0xf3f08400, | ||
| 780 | 0x00ffcf02, | ||
| 781 | 0xf405fffd, | ||
| 660 | 0x00f8f31b, | 782 | 0x00f8f31b, |
| 661 | /* 0x064c: ctx_redswitch */ | 783 | /* 0x0824: ctx_load */ |
| 662 | 0x0614e7f1, | ||
| 663 | 0xf106e4b6, | ||
| 664 | 0xd00270f7, | ||
| 665 | 0xf7f000ef, | ||
| 666 | /* 0x065d: ctx_redswitch_delay */ | ||
| 667 | 0x01f2b608, | ||
| 668 | 0xf1fd1bf4, | ||
| 669 | 0xd00770f7, | ||
| 670 | 0x00f800ef, | ||
| 671 | /* 0x066c: ctx_86c */ | ||
| 672 | 0x086ce7f1, | ||
| 673 | 0xd006e4b6, | ||
| 674 | 0xe7f100ef, | ||
| 675 | 0xe3f08a14, | ||
| 676 | 0x8d21f440, | ||
| 677 | 0xa86ce7f1, | ||
| 678 | 0xf441e3f0, | ||
| 679 | 0x00f88d21, | ||
| 680 | /* 0x068c: ctx_load */ | ||
| 681 | 0x99f094bd, | 784 | 0x99f094bd, |
| 682 | 0x0007f105, | 785 | 0x0007f105, |
| 683 | 0x0203f037, | 786 | 0x0203f037, |
| 684 | 0xbd0009d0, | 787 | 0xbd0009d0, |
| 685 | 0x0ca7f004, | 788 | 0x0ca7f004, |
| 686 | 0xf1c921f4, | 789 | 0xbdd021f4, |
| 687 | 0xb60a2417, | 790 | 0x0007f1f4, |
| 688 | 0x10d00614, | 791 | 0x0203f089, |
| 689 | 0x0037f100, | 792 | 0xbd000fd0, |
| 690 | 0x0634b60b, | 793 | 0x0007f104, |
| 691 | 0xf14032d0, | 794 | 0x0203f0c1, |
| 692 | 0xb60a0c17, | 795 | 0xbd0002d0, |
| 693 | 0x47f00614, | 796 | 0x0007f104, |
| 694 | 0x0012d007, | 797 | 0x0203f083, |
| 695 | /* 0x06c7: ctx_chan_wait_0 */ | 798 | 0xbd0002d0, |
| 696 | 0xcf4014d0, | 799 | 0x07f7f004, |
| 697 | 0x44f04014, | 800 | 0x080621f5, |
| 698 | 0xfa1bf41f, | 801 | 0xc00007f1, |
| 699 | 0xfe0032d0, | 802 | 0xd00203f0, |
| 700 | 0x2af0000b, | 803 | 0x04bd0002, |
| 701 | 0x0424b61f, | 804 | 0xf0000bfe, |
| 702 | 0xbd0220b6, | 805 | 0x24b61f2a, |
| 806 | 0x0220b604, | ||
| 807 | 0x99f094bd, | ||
| 808 | 0x0007f108, | ||
| 809 | 0x0203f037, | ||
| 810 | 0xbd0009d0, | ||
| 811 | 0x0007f104, | ||
| 812 | 0x0203f081, | ||
| 813 | 0xbd0002d0, | ||
| 814 | 0x0027f104, | ||
| 815 | 0x0023f100, | ||
| 816 | 0x0225f080, | ||
| 817 | 0x880007f1, | ||
| 818 | 0xd00203f0, | ||
| 819 | 0x04bd0002, | ||
| 820 | 0xf11017f0, | ||
| 821 | 0xf0020027, | ||
| 822 | 0x12fa0223, | ||
| 823 | 0xbd03f805, | ||
| 703 | 0x0899f094, | 824 | 0x0899f094, |
| 704 | 0x370007f1, | 825 | 0x170007f1, |
| 705 | 0xd00203f0, | 826 | 0xd00203f0, |
| 706 | 0x04bd0009, | 827 | 0x04bd0009, |
| 707 | 0x0a0417f1, | 828 | 0xb6810198, |
| 708 | 0xd00614b6, | 829 | 0x02981814, |
| 709 | 0x17f10012, | 830 | 0x0825b680, |
| 710 | 0x14b60a20, | 831 | 0x800512fd, |
| 711 | 0x0227f006, | 832 | 0x94bd1601, |
| 712 | 0x800023f1, | 833 | 0xf10999f0, |
| 713 | 0xf00012d0, | 834 | 0xf0370007, |
| 714 | 0x27f11017, | ||
| 715 | 0x23f00200, | ||
| 716 | 0x0512fa02, | ||
| 717 | 0x94bd03f8, | ||
| 718 | 0xf10899f0, | ||
| 719 | 0xf0170007, | ||
| 720 | 0x09d00203, | 835 | 0x09d00203, |
| 721 | 0x9804bd00, | 836 | 0xf104bd00, |
| 722 | 0x14b68101, | 837 | 0xf0810007, |
| 723 | 0x80029818, | 838 | 0x01d00203, |
| 724 | 0xfd0825b6, | 839 | 0xf004bd00, |
| 725 | 0x01800512, | 840 | 0x07f10127, |
| 726 | 0xf094bd16, | 841 | 0x03f08800, |
| 727 | 0x07f10999, | 842 | 0x0002d002, |
| 728 | 0x03f03700, | 843 | 0x17f104bd, |
| 729 | 0x0009d002, | 844 | 0x13f00100, |
| 730 | 0x27f104bd, | 845 | 0x0501fa06, |
| 731 | 0x24b60a04, | 846 | 0x94bd03f8, |
| 732 | 0x0021d006, | 847 | 0xf10999f0, |
| 733 | 0xf10127f0, | ||
| 734 | 0xb60a2017, | ||
| 735 | 0x12d00614, | ||
| 736 | 0x0017f100, | ||
| 737 | 0x0613f001, | ||
| 738 | 0xf80501fa, | ||
| 739 | 0xf094bd03, | ||
| 740 | 0x07f10999, | ||
| 741 | 0x03f01700, | ||
| 742 | 0x0009d002, | ||
| 743 | 0x94bd04bd, | ||
| 744 | 0xf10599f0, | ||
| 745 | 0xf0170007, | 848 | 0xf0170007, |
| 746 | 0x09d00203, | 849 | 0x09d00203, |
| 747 | 0xf804bd00, | 850 | 0xbd04bd00, |
| 748 | /* 0x0795: ctx_chan */ | 851 | 0x0599f094, |
| 749 | 0x8c21f500, | 852 | 0x170007f1, |
| 750 | 0x0ca7f006, | 853 | 0xd00203f0, |
| 751 | 0xf1c921f4, | 854 | 0x04bd0009, |
| 752 | 0xb60a1017, | 855 | /* 0x0942: ctx_chan */ |
| 753 | 0x27f00614, | 856 | 0x21f500f8, |
| 754 | 0x0012d005, | 857 | 0xa7f00824, |
| 755 | /* 0x07ac: ctx_chan_wait */ | 858 | 0xd021f40c, |
| 756 | 0xfd0012cf, | 859 | 0xf505f7f0, |
| 757 | 0x1bf40522, | 860 | 0xf8080621, |
| 758 | /* 0x07b7: ctx_mmio_exec */ | 861 | /* 0x0955: ctx_mmio_exec */ |
| 759 | 0x9800f8fa, | 862 | 0x41039800, |
| 760 | 0x27f14103, | 863 | 0x810007f1, |
| 761 | 0x24b60a04, | 864 | 0xd00203f0, |
| 762 | 0x0023d006, | 865 | 0x04bd0003, |
| 763 | /* 0x07c6: ctx_mmio_loop */ | 866 | /* 0x0966: ctx_mmio_loop */ |
| 764 | 0x34c434bd, | 867 | 0x34c434bd, |
| 765 | 0x0f1bf4ff, | 868 | 0x0f1bf4ff, |
| 766 | 0x020057f1, | 869 | 0x020057f1, |
| 767 | 0xfa0653f0, | 870 | 0xfa0653f0, |
| 768 | 0x03f80535, | 871 | 0x03f80535, |
| 769 | /* 0x07d8: ctx_mmio_pull */ | 872 | /* 0x0978: ctx_mmio_pull */ |
| 770 | 0x98804e98, | 873 | 0x98804e98, |
| 771 | 0x21f4814f, | 874 | 0x21f4814f, |
| 772 | 0x0830b68d, | 875 | 0x0830b69d, |
| 773 | 0xf40112b6, | 876 | 0xf40112b6, |
| 774 | /* 0x07ea: ctx_mmio_done */ | 877 | /* 0x098a: ctx_mmio_done */ |
| 775 | 0x0398df1b, | 878 | 0x0398df1b, |
| 776 | 0x0023d016, | 879 | 0x0007f116, |
| 777 | 0xf1400080, | 880 | 0x0203f081, |
| 778 | 0xf0010017, | 881 | 0xbd0003d0, |
| 779 | 0x01fa0613, | 882 | 0x40008004, |
| 780 | 0xf803f806, | 883 | 0x010017f1, |
| 781 | /* 0x0801: ctx_xfer */ | 884 | 0xfa0613f0, |
| 782 | 0x00f7f100, | 885 | 0x03f80601, |
| 783 | 0x06f4b60c, | 886 | /* 0x09aa: ctx_xfer */ |
| 784 | 0xd004e7f0, | 887 | 0xe7f000f8, |
| 785 | /* 0x080e: ctx_xfer_idle */ | 888 | 0x0007f104, |
| 786 | 0xfecf80fe, | 889 | 0x0303f002, |
| 787 | 0x00e4f100, | 890 | 0xbd000ed0, |
| 788 | 0xf91bf420, | 891 | /* 0x09b9: ctx_xfer_idle */ |
| 789 | 0xf40611f4, | 892 | 0x00e7f104, |
| 790 | /* 0x081e: ctx_xfer_pre */ | 893 | 0x03e3f000, |
| 791 | 0xf7f00d02, | 894 | 0xf100eecf, |
| 792 | 0x6c21f510, | 895 | 0xf42000e4, |
| 793 | 0x1c11f406, | 896 | 0x11f4f21b, |
| 794 | /* 0x0828: ctx_xfer_pre_load */ | 897 | 0x0d02f406, |
| 795 | 0xf502f7f0, | 898 | /* 0x09d0: ctx_xfer_pre */ |
| 796 | 0xf5062b21, | 899 | 0xf510f7f0, |
| 797 | 0xf5063a21, | 900 | 0xf407de21, |
| 798 | 0xbd064c21, | 901 | /* 0x09da: ctx_xfer_pre_load */ |
| 799 | 0x2b21f5f4, | 902 | 0xf7f01c11, |
| 800 | 0x8c21f506, | 903 | 0x7f21f502, |
| 801 | /* 0x0841: ctx_xfer_exec */ | 904 | 0x9121f507, |
| 802 | 0x16019806, | 905 | 0xa621f507, |
| 803 | 0x041427f1, | 906 | 0xf5f4bd07, |
| 804 | 0xd00624b6, | 907 | 0xf5077f21, |
| 805 | 0xe7f10020, | 908 | /* 0x09f3: ctx_xfer_exec */ |
| 806 | 0xe3f0a500, | 909 | 0x98082421, |
| 807 | 0x021fb941, | 910 | 0x24bd1601, |
| 808 | 0xb68d21f4, | 911 | 0x050007f1, |
| 809 | 0xfcf004e0, | 912 | 0xd00103f0, |
| 810 | 0x022cf001, | 913 | 0x04bd0002, |
| 811 | 0xfd0124b6, | 914 | 0xf1021fb9, |
| 812 | 0x21f405f2, | 915 | 0xf0a500e7, |
| 813 | 0xfc17f18d, | 916 | 0x21f441e3, |
| 814 | 0x0213f04a, | 917 | 0x01fcf09d, |
| 815 | 0xd00c27f0, | 918 | 0xb6022cf0, |
| 816 | 0x21f50012, | 919 | 0xf2fd0124, |
| 817 | 0x27f10215, | 920 | 0x02ffb905, |
| 818 | 0x23f047fc, | 921 | 0xa504e7f1, |
| 819 | 0x0020d002, | 922 | 0xf441e3f0, |
| 923 | 0x21f59d21, | ||
| 924 | 0x24bd026a, | ||
| 925 | 0x47fc07f1, | ||
| 926 | 0xd00203f0, | ||
| 927 | 0x04bd0002, | ||
| 820 | 0xb6012cf0, | 928 | 0xb6012cf0, |
| 821 | 0x12d00320, | 929 | 0x07f10320, |
| 822 | 0x01acf000, | 930 | 0x03f04afc, |
| 823 | 0xf006a5f0, | 931 | 0x0002d002, |
| 824 | 0x0c9800b7, | 932 | 0xacf004bd, |
| 825 | 0x010d9800, | 933 | 0x06a5f001, |
| 826 | 0xf500e7f0, | 934 | 0x9800b7f0, |
| 827 | 0xf0016621, | 935 | 0x0d98000c, |
| 828 | 0x21f508a7, | 936 | 0x00e7f001, |
| 829 | 0x21f50109, | 937 | 0x016f21f5, |
| 830 | 0x01f40215, | 938 | 0xf508a7f0, |
| 831 | 0x0ca7f022, | 939 | 0xf5011021, |
| 832 | 0xf1c921f4, | 940 | 0xf4025e21, |
| 833 | 0xb60a1017, | 941 | 0xa7f01301, |
| 834 | 0x27f00614, | 942 | 0xd021f40c, |
| 835 | 0x0012d005, | 943 | 0xf505f7f0, |
| 836 | /* 0x08c8: ctx_xfer_post_save_wait */ | 944 | 0xf4080621, |
| 837 | 0xfd0012cf, | 945 | /* 0x0a82: ctx_xfer_post */ |
| 838 | 0x1bf40522, | 946 | 0xf7f02e02, |
| 839 | 0x2e02f4fa, | 947 | 0x7f21f502, |
| 840 | /* 0x08d4: ctx_xfer_post */ | 948 | 0xf5f4bd07, |
| 841 | 0xf502f7f0, | 949 | 0xf507de21, |
| 842 | 0xbd062b21, | 950 | 0xf5027f21, |
| 843 | 0x6c21f5f4, | 951 | 0xbd079121, |
| 844 | 0x3421f506, | 952 | 0x7f21f5f4, |
| 845 | 0x3a21f502, | 953 | 0x1011f407, |
| 846 | 0xf5f4bd06, | 954 | 0xfd400198, |
| 847 | 0xf4062b21, | 955 | 0x0bf40511, |
| 848 | 0x01981011, | 956 | 0x5521f507, |
| 849 | 0x0511fd40, | 957 | /* 0x0aad: ctx_xfer_no_post_mmio */ |
| 850 | 0xf5070bf4, | 958 | /* 0x0aad: ctx_xfer_done */ |
| 851 | /* 0x08ff: ctx_xfer_no_post_mmio */ | 959 | 0x0000f809, |
| 852 | /* 0x08ff: ctx_xfer_done */ | ||
| 853 | 0xf807b721, | ||
| 854 | 0x00000000, | ||
| 855 | 0x00000000, | ||
| 856 | 0x00000000, | ||
| 857 | 0x00000000, | ||
| 858 | 0x00000000, | ||
| 859 | 0x00000000, | ||
| 860 | 0x00000000, | ||
| 861 | 0x00000000, | ||
| 862 | 0x00000000, | ||
| 863 | 0x00000000, | ||
| 864 | 0x00000000, | ||
| 865 | 0x00000000, | ||
| 866 | 0x00000000, | ||
| 867 | 0x00000000, | ||
| 868 | 0x00000000, | ||
| 869 | 0x00000000, | ||
| 870 | 0x00000000, | ||
| 871 | 0x00000000, | ||
| 872 | 0x00000000, | ||
| 873 | 0x00000000, | ||
| 874 | 0x00000000, | ||
| 875 | 0x00000000, | ||
| 876 | 0x00000000, | ||
| 877 | 0x00000000, | ||
| 878 | 0x00000000, | ||
| 879 | 0x00000000, | ||
| 880 | 0x00000000, | ||
| 881 | 0x00000000, | ||
| 882 | 0x00000000, | ||
| 883 | 0x00000000, | ||
| 884 | 0x00000000, | ||
| 885 | 0x00000000, | ||
| 886 | 0x00000000, | ||
| 887 | 0x00000000, | ||
| 888 | 0x00000000, | ||
| 889 | 0x00000000, | ||
| 890 | 0x00000000, | ||
| 891 | 0x00000000, | ||
| 892 | 0x00000000, | ||
| 893 | 0x00000000, | ||
| 894 | 0x00000000, | ||
| 895 | 0x00000000, | ||
| 896 | 0x00000000, | ||
| 897 | 0x00000000, | ||
| 898 | 0x00000000, | 960 | 0x00000000, |
| 899 | 0x00000000, | 961 | 0x00000000, |
| 900 | 0x00000000, | 962 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc index 33a5a82eccbd..6ffe28307dbd 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc +++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc | |||
| @@ -28,28 +28,135 @@ | |||
| 28 | #define GF117 0xd7 | 28 | #define GF117 0xd7 |
| 29 | #define GK100 0xe0 | 29 | #define GK100 0xe0 |
| 30 | #define GK110 0xf0 | 30 | #define GK110 0xf0 |
| 31 | #define GK208 0x108 | ||
| 31 | 32 | ||
| 33 | #define NV_PGRAPH_FECS_INTR_ACK 0x409004 | ||
| 34 | #define NV_PGRAPH_FECS_INTR 0x409008 | ||
| 35 | #define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400 | ||
| 36 | #define NV_PGRAPH_FECS_INTR_CHSW 0x00000100 | ||
| 37 | #define NV_PGRAPH_FECS_INTR_FIFO 0x00000004 | ||
| 38 | #define NV_PGRAPH_FECS_INTR_MODE 0x40900c | ||
| 39 | #define NV_PGRAPH_FECS_INTR_MODE_FIFO 0x00000004 | ||
| 40 | #define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 0x00000004 | ||
| 41 | #define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE 0x00000000 | ||
| 42 | #define NV_PGRAPH_FECS_INTR_EN_SET 0x409010 | ||
| 43 | #define NV_PGRAPH_FECS_INTR_EN_SET_FIFO 0x00000004 | ||
| 44 | #define NV_PGRAPH_FECS_INTR_ROUTE 0x40901c | ||
| 45 | #define NV_PGRAPH_FECS_ACCESS 0x409048 | ||
| 46 | #define NV_PGRAPH_FECS_ACCESS_FIFO 0x00000002 | ||
| 47 | #define NV_PGRAPH_FECS_FIFO_DATA 0x409064 | ||
| 48 | #define NV_PGRAPH_FECS_FIFO_CMD 0x409068 | ||
| 49 | #define NV_PGRAPH_FECS_FIFO_ACK 0x409074 | ||
| 50 | #define NV_PGRAPH_FECS_CAPS 0x409108 | ||
| 32 | #define NV_PGRAPH_FECS_SIGNAL 0x409400 | 51 | #define NV_PGRAPH_FECS_SIGNAL 0x409400 |
| 52 | #define NV_PGRAPH_FECS_IROUTE 0x409404 | ||
| 53 | #define NV_PGRAPH_FECS_BAR_MASK0 0x40940c | ||
| 54 | #define NV_PGRAPH_FECS_BAR_MASK1 0x409410 | ||
| 55 | #define NV_PGRAPH_FECS_BAR 0x409414 | ||
| 56 | #define NV_PGRAPH_FECS_BAR_SET 0x409418 | ||
| 57 | #define NV_PGRAPH_FECS_RED_SWITCH 0x409614 | ||
| 58 | #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 0x00000400 | ||
| 59 | #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 0x00000200 | ||
| 60 | #define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 0x00000100 | ||
| 61 | #define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 0x00000040 | ||
| 62 | #define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 0x00000020 | ||
| 63 | #define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 0x00000010 | ||
| 64 | #define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC 0x00000002 | ||
| 65 | #define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN 0x00000001 | ||
| 66 | #define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 | ||
| 67 | #define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 | ||
| 68 | #define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c | ||
| 69 | #define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 | ||
| 70 | #define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 | ||
| 71 | #define NV_PGRAPH_FECS_MMCTX_BASE 0x409710 | ||
| 72 | #define NV_PGRAPH_FECS_MMCTX_CTRL 0x409714 | ||
| 73 | #define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718 | ||
| 74 | #define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c | ||
| 75 | #define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720 | ||
| 76 | #define NV_PGRAPH_FECS_MMIO_CTRL 0x409728 | ||
| 77 | #define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c | ||
| 78 | #define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730 | ||
| 79 | #define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c | ||
| 33 | #if CHIPSET < GK110 | 80 | #if CHIPSET < GK110 |
| 34 | #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) | 81 | #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) |
| 35 | #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820) | 82 | #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820) |
| 36 | #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) | 83 | #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) |
| 84 | #define NV_PGRAPH_FECS_UNK86C 0x40986c | ||
| 37 | #else | 85 | #else |
| 38 | #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) | 86 | #define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) |
| 39 | #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) | 87 | #define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) |
| 88 | #define NV_PGRAPH_FECS_UNK86C 0x40988c | ||
| 40 | #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0) | 89 | #define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0) |
| 41 | #endif | 90 | #endif |
| 91 | #define NV_PGRAPH_FECS_STRANDS_CNT 0x409880 | ||
| 92 | #define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE 0x409908 | ||
| 93 | #define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE 0x40990c | ||
| 94 | #define NV_PGRAPH_FECS_STRAND_WORDS 0x409910 | ||
| 95 | #define NV_PGRAPH_FECS_STRAND_DATA 0x409918 | ||
| 96 | #define NV_PGRAPH_FECS_STRAND_SELECT 0x40991c | ||
| 97 | #define NV_PGRAPH_FECS_STRAND_CMD 0x409928 | ||
| 98 | #define NV_PGRAPH_FECS_STRAND_CMD_SEEK 0x00000001 | ||
| 99 | #define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO 0x00000002 | ||
| 100 | #define NV_PGRAPH_FECS_STRAND_CMD_SAVE 0x00000003 | ||
| 101 | #define NV_PGRAPH_FECS_STRAND_CMD_LOAD 0x00000004 | ||
| 102 | #define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER 0x0000000a | ||
| 103 | #define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER 0x0000000b | ||
| 104 | #define NV_PGRAPH_FECS_STRAND_CMD_ENABLE 0x0000000c | ||
| 105 | #define NV_PGRAPH_FECS_STRAND_CMD_DISABLE 0x0000000d | ||
| 106 | #define NV_PGRAPH_FECS_STRAND_FILTER 0x40993c | ||
| 107 | #define NV_PGRAPH_FECS_MEM_BASE 0x409a04 | ||
| 108 | #define NV_PGRAPH_FECS_MEM_CHAN 0x409a0c | ||
| 109 | #define NV_PGRAPH_FECS_MEM_CMD 0x409a10 | ||
| 110 | #define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 0x00000007 | ||
| 111 | #define NV_PGRAPH_FECS_MEM_TARGET 0x409a20 | ||
| 112 | #define NV_PGRAPH_FECS_MEM_TARGET_UNK31 0x80000000 | ||
| 113 | #define NV_PGRAPH_FECS_MEM_TARGET_AS 0x0000001f | ||
| 114 | #define NV_PGRAPH_FECS_MEM_TARGET_AS_VM 0x00000001 | ||
| 115 | #define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 0x00000002 | ||
| 116 | #define NV_PGRAPH_FECS_CHAN_ADDR 0x409b00 | ||
| 117 | #define NV_PGRAPH_FECS_CHAN_NEXT 0x409b04 | ||
| 118 | #define NV_PGRAPH_FECS_CHSW 0x409b0c | ||
| 119 | #define NV_PGRAPH_FECS_CHSW_ACK 0x00000001 | ||
| 42 | #define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c | 120 | #define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c |
| 121 | #define NV_PGRAPH_FECS_INTR_UP_EN 0x409c24 | ||
| 43 | 122 | ||
| 123 | #define NV_PGRAPH_GPCX_GPCCS_INTR_ACK 0x41a004 | ||
| 124 | #define NV_PGRAPH_GPCX_GPCCS_INTR 0x41a008 | ||
| 125 | #define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO 0x00000004 | ||
| 126 | #define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET 0x41a010 | ||
| 127 | #define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO 0x00000004 | ||
| 128 | #define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE 0x41a01c | ||
| 129 | #define NV_PGRAPH_GPCX_GPCCS_ACCESS 0x41a048 | ||
| 130 | #define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO 0x00000002 | ||
| 131 | #define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA 0x41a064 | ||
| 132 | #define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD 0x41a068 | ||
| 133 | #define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK 0x41a074 | ||
| 134 | #define NV_PGRAPH_GPCX_GPCCS_UNITS 0x41a608 | ||
| 135 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH 0x41a614 | ||
| 136 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 0x00000800 | ||
| 137 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE 0x00000200 | ||
| 138 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER 0x00000020 | ||
| 139 | #define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE 0x00000002 | ||
| 140 | #define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618 | ||
| 141 | #define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700 | ||
| 142 | #define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704 | ||
| 143 | #define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c | ||
| 44 | #if CHIPSET < GK110 | 144 | #if CHIPSET < GK110 |
| 45 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) | 145 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) |
| 46 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820) | 146 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820) |
| 47 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) | 147 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) |
| 148 | #define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a86c | ||
| 48 | #else | 149 | #else |
| 49 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) | 150 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) |
| 50 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) | 151 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) |
| 152 | #define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a88c | ||
| 51 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0) | 153 | #define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0) |
| 52 | #endif | 154 | #endif |
| 155 | #define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT 0x41a91c | ||
| 156 | #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD 0x41a928 | ||
| 157 | #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003 | ||
| 158 | #define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004 | ||
| 159 | #define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04 | ||
| 53 | 160 | ||
| 54 | #define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) | 161 | #define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) |
| 55 | #define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) | 162 | #define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) |
| @@ -65,24 +172,50 @@ | |||
| 65 | #define T_LCHAN 8 | 172 | #define T_LCHAN 8 |
| 66 | #define T_LCTXH 9 | 173 | #define T_LCTXH 9 |
| 67 | 174 | ||
| 68 | #define nv_mkmm(rv,r) /* | 175 | #if CHIPSET < GK208 |
| 69 | */ movw rv ((r) & 0x0000fffc) /* | 176 | #define imm32(reg,val) /* |
| 70 | */ sethi rv ((r) & 0x00ff0000) | 177 | */ movw reg ((val) & 0x0000ffff) /* |
| 178 | */ sethi reg ((val) & 0xffff0000) | ||
| 179 | #else | ||
| 180 | #define imm32(reg,val) /* | ||
| 181 | */ mov reg (val) | ||
| 182 | #endif | ||
| 183 | |||
| 71 | #define nv_mkio(rv,r,i) /* | 184 | #define nv_mkio(rv,r,i) /* |
| 72 | */ nv_mkmm(rv, (((r) & 0xffc) << 6) | ((i) << 2)) | 185 | */ imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2)) |
| 186 | |||
| 187 | #define hash # | ||
| 188 | #define fn(a) a | ||
| 189 | #if CHIPSET < GK208 | ||
| 190 | #define call(a) call fn(hash)a | ||
| 191 | #else | ||
| 192 | #define call(a) lcall fn(hash)a | ||
| 193 | #endif | ||
| 73 | 194 | ||
| 74 | #define nv_iord(rv,r,i) /* | 195 | #define nv_iord(rv,r,i) /* |
| 75 | */ nv_mkio(rv,r,i) /* | 196 | */ nv_mkio(rv,r,i) /* |
| 76 | */ iord rv I[rv] | 197 | */ iord rv I[rv] |
| 198 | |||
| 77 | #define nv_iowr(r,i,rv) /* | 199 | #define nv_iowr(r,i,rv) /* |
| 78 | */ nv_mkio($r0,r,i) /* | 200 | */ nv_mkio($r0,r,i) /* |
| 79 | */ iowr I[$r0] rv /* | 201 | */ iowr I[$r0] rv /* |
| 80 | */ clear b32 $r0 | 202 | */ clear b32 $r0 |
| 81 | 203 | ||
| 204 | #define nv_rd32(reg,addr) /* | ||
| 205 | */ imm32($r14, addr) /* | ||
| 206 | */ call(nv_rd32) /* | ||
| 207 | */ mov b32 reg $r15 | ||
| 208 | |||
| 209 | #define nv_wr32(addr,reg) /* | ||
| 210 | */ mov b32 $r15 reg /* | ||
| 211 | */ imm32($r14, addr) /* | ||
| 212 | */ call(nv_wr32) | ||
| 213 | |||
| 82 | #define trace_set(bit) /* | 214 | #define trace_set(bit) /* |
| 83 | */ clear b32 $r9 /* | 215 | */ clear b32 $r9 /* |
| 84 | */ bset $r9 bit /* | 216 | */ bset $r9 bit /* |
| 85 | */ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9) | 217 | */ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9) |
| 218 | |||
| 86 | #define trace_clr(bit) /* | 219 | #define trace_clr(bit) /* |
| 87 | */ clear b32 $r9 /* | 220 | */ clear b32 $r9 /* |
| 88 | */ bset $r9 bit /* | 221 | */ bset $r9 bit /* |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c new file mode 100644 index 000000000000..e1af65ead379 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c | |||
| @@ -0,0 +1,236 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include "nvc0.h" | ||
| 26 | |||
| 27 | /******************************************************************************* | ||
| 28 | * Graphics object classes | ||
| 29 | ******************************************************************************/ | ||
| 30 | |||
| 31 | static struct nouveau_oclass | ||
| 32 | nv108_graph_sclass[] = { | ||
| 33 | { 0x902d, &nouveau_object_ofuncs }, | ||
| 34 | { 0xa140, &nouveau_object_ofuncs }, | ||
| 35 | { 0xa197, &nouveau_object_ofuncs }, | ||
| 36 | { 0xa1c0, &nouveau_object_ofuncs }, | ||
| 37 | {} | ||
| 38 | }; | ||
| 39 | |||
| 40 | /******************************************************************************* | ||
| 41 | * PGRAPH engine/subdev functions | ||
| 42 | ******************************************************************************/ | ||
| 43 | |||
| 44 | static struct nvc0_graph_init | ||
| 45 | nv108_graph_init_regs[] = { | ||
| 46 | { 0x400080, 1, 0x04, 0x003083c2 }, | ||
| 47 | { 0x400088, 1, 0x04, 0x0001bfe7 }, | ||
| 48 | { 0x40008c, 1, 0x04, 0x00000000 }, | ||
| 49 | { 0x400090, 1, 0x04, 0x00000030 }, | ||
| 50 | { 0x40013c, 1, 0x04, 0x003901f7 }, | ||
| 51 | { 0x400140, 1, 0x04, 0x00000100 }, | ||
| 52 | { 0x400144, 1, 0x04, 0x00000000 }, | ||
| 53 | { 0x400148, 1, 0x04, 0x00000110 }, | ||
| 54 | { 0x400138, 1, 0x04, 0x00000000 }, | ||
| 55 | { 0x400130, 2, 0x04, 0x00000000 }, | ||
| 56 | { 0x400124, 1, 0x04, 0x00000002 }, | ||
| 57 | {} | ||
| 58 | }; | ||
| 59 | |||
| 60 | struct nvc0_graph_init | ||
| 61 | nv108_graph_init_unk58xx[] = { | ||
| 62 | { 0x405844, 1, 0x04, 0x00ffffff }, | ||
| 63 | { 0x405850, 1, 0x04, 0x00000000 }, | ||
| 64 | { 0x405900, 1, 0x04, 0x00000000 }, | ||
| 65 | { 0x405908, 1, 0x04, 0x00000000 }, | ||
| 66 | { 0x405928, 1, 0x04, 0x00000000 }, | ||
| 67 | { 0x40592c, 1, 0x04, 0x00000000 }, | ||
| 68 | {} | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct nvc0_graph_init | ||
| 72 | nv108_graph_init_gpc[] = { | ||
| 73 | { 0x418408, 1, 0x04, 0x00000000 }, | ||
| 74 | { 0x4184a0, 3, 0x04, 0x00000000 }, | ||
| 75 | { 0x418604, 1, 0x04, 0x00000000 }, | ||
| 76 | { 0x418680, 1, 0x04, 0x00000000 }, | ||
| 77 | { 0x418714, 1, 0x04, 0x00000000 }, | ||
| 78 | { 0x418384, 2, 0x04, 0x00000000 }, | ||
| 79 | { 0x418814, 3, 0x04, 0x00000000 }, | ||
| 80 | { 0x418b04, 1, 0x04, 0x00000000 }, | ||
| 81 | { 0x4188c8, 2, 0x04, 0x00000000 }, | ||
| 82 | { 0x4188d0, 1, 0x04, 0x00010000 }, | ||
| 83 | { 0x4188d4, 1, 0x04, 0x00000201 }, | ||
| 84 | { 0x418910, 1, 0x04, 0x00010001 }, | ||
| 85 | { 0x418914, 1, 0x04, 0x00000301 }, | ||
| 86 | { 0x418918, 1, 0x04, 0x00800000 }, | ||
| 87 | { 0x418980, 1, 0x04, 0x77777770 }, | ||
| 88 | { 0x418984, 3, 0x04, 0x77777777 }, | ||
| 89 | { 0x418c04, 1, 0x04, 0x00000000 }, | ||
| 90 | { 0x418c64, 2, 0x04, 0x00000000 }, | ||
| 91 | { 0x418c88, 1, 0x04, 0x00000000 }, | ||
| 92 | { 0x418cb4, 2, 0x04, 0x00000000 }, | ||
| 93 | { 0x418d00, 1, 0x04, 0x00000000 }, | ||
| 94 | { 0x418d28, 2, 0x04, 0x00000000 }, | ||
| 95 | { 0x418f00, 1, 0x04, 0x00000400 }, | ||
| 96 | { 0x418f08, 1, 0x04, 0x00000000 }, | ||
| 97 | { 0x418f20, 2, 0x04, 0x00000000 }, | ||
| 98 | { 0x418e00, 1, 0x04, 0x00000000 }, | ||
| 99 | { 0x418e08, 1, 0x04, 0x00000000 }, | ||
| 100 | { 0x418e1c, 2, 0x04, 0x00000000 }, | ||
| 101 | { 0x41900c, 1, 0x04, 0x00000000 }, | ||
| 102 | { 0x419018, 1, 0x04, 0x00000000 }, | ||
| 103 | {} | ||
| 104 | }; | ||
| 105 | |||
| 106 | static struct nvc0_graph_init | ||
| 107 | nv108_graph_init_tpc[] = { | ||
| 108 | { 0x419d0c, 1, 0x04, 0x00000000 }, | ||
| 109 | { 0x419d10, 1, 0x04, 0x00000014 }, | ||
| 110 | { 0x419ab0, 1, 0x04, 0x00000000 }, | ||
| 111 | { 0x419ac8, 1, 0x04, 0x00000000 }, | ||
| 112 | { 0x419ab8, 1, 0x04, 0x000000e7 }, | ||
| 113 | { 0x419abc, 2, 0x04, 0x00000000 }, | ||
| 114 | { 0x419ab4, 1, 0x04, 0x00000000 }, | ||
| 115 | { 0x419aa8, 2, 0x04, 0x00000000 }, | ||
| 116 | { 0x41980c, 1, 0x04, 0x00000010 }, | ||
| 117 | { 0x419844, 1, 0x04, 0x00000000 }, | ||
| 118 | { 0x419850, 1, 0x04, 0x00000004 }, | ||
| 119 | { 0x419854, 2, 0x04, 0x00000000 }, | ||
| 120 | { 0x419c98, 1, 0x04, 0x00000000 }, | ||
| 121 | { 0x419ca8, 1, 0x04, 0x00000000 }, | ||
| 122 | { 0x419cb0, 1, 0x04, 0x01000000 }, | ||
| 123 | { 0x419cb4, 1, 0x04, 0x00000000 }, | ||
| 124 | { 0x419cb8, 1, 0x04, 0x00b08bea }, | ||
| 125 | { 0x419c84, 1, 0x04, 0x00010384 }, | ||
| 126 | { 0x419cbc, 1, 0x04, 0x281b3646 }, | ||
| 127 | { 0x419cc0, 2, 0x04, 0x00000000 }, | ||
| 128 | { 0x419c80, 1, 0x04, 0x00000230 }, | ||
| 129 | { 0x419ccc, 2, 0x04, 0x00000000 }, | ||
| 130 | { 0x419c0c, 1, 0x04, 0x00000000 }, | ||
| 131 | { 0x419e00, 1, 0x04, 0x00000080 }, | ||
| 132 | { 0x419ea0, 1, 0x04, 0x00000000 }, | ||
| 133 | { 0x419ee4, 1, 0x04, 0x00000000 }, | ||
| 134 | { 0x419ea4, 1, 0x04, 0x00000100 }, | ||
| 135 | { 0x419ea8, 1, 0x04, 0x00000000 }, | ||
| 136 | { 0x419eb4, 1, 0x04, 0x00000000 }, | ||
| 137 | { 0x419ebc, 2, 0x04, 0x00000000 }, | ||
| 138 | { 0x419edc, 1, 0x04, 0x00000000 }, | ||
| 139 | { 0x419f00, 1, 0x04, 0x00000000 }, | ||
| 140 | { 0x419ed0, 1, 0x04, 0x00003234 }, | ||
| 141 | { 0x419f74, 1, 0x04, 0x00015555 }, | ||
| 142 | { 0x419f80, 4, 0x04, 0x00000000 }, | ||
| 143 | {} | ||
| 144 | }; | ||
| 145 | |||
| 146 | static int | ||
| 147 | nv108_graph_fini(struct nouveau_object *object, bool suspend) | ||
| 148 | { | ||
| 149 | struct nvc0_graph_priv *priv = (void *)object; | ||
| 150 | static const struct { | ||
| 151 | u32 addr; | ||
| 152 | u32 data; | ||
| 153 | } magic[] = { | ||
| 154 | { 0x020520, 0xfffffffc }, | ||
| 155 | { 0x020524, 0xfffffffe }, | ||
| 156 | { 0x020524, 0xfffffffc }, | ||
| 157 | { 0x020524, 0xfffffff8 }, | ||
| 158 | { 0x020524, 0xffffffe0 }, | ||
| 159 | { 0x020530, 0xfffffffe }, | ||
| 160 | { 0x02052c, 0xfffffffa }, | ||
| 161 | { 0x02052c, 0xfffffff0 }, | ||
| 162 | { 0x02052c, 0xffffffc0 }, | ||
| 163 | { 0x02052c, 0xffffff00 }, | ||
| 164 | { 0x02052c, 0xfffffc00 }, | ||
| 165 | { 0x02052c, 0xfffcfc00 }, | ||
| 166 | { 0x02052c, 0xfff0fc00 }, | ||
| 167 | { 0x02052c, 0xff80fc00 }, | ||
| 168 | { 0x020528, 0xfffffffe }, | ||
| 169 | { 0x020528, 0xfffffffc }, | ||
| 170 | }; | ||
| 171 | int i; | ||
| 172 | |||
| 173 | nv_mask(priv, 0x000200, 0x08001000, 0x00000000); | ||
| 174 | nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); | ||
| 175 | for (i = 0; i < ARRAY_SIZE(magic); i++) { | ||
| 176 | nv_wr32(priv, magic[i].addr, magic[i].data); | ||
| 177 | nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); | ||
| 178 | } | ||
| 179 | |||
| 180 | return nouveau_graph_fini(&priv->base, suspend); | ||
| 181 | } | ||
| 182 | |||
| 183 | static struct nvc0_graph_init * | ||
| 184 | nv108_graph_init_mmio[] = { | ||
| 185 | nv108_graph_init_regs, | ||
| 186 | nvf0_graph_init_unk40xx, | ||
| 187 | nvc0_graph_init_unk44xx, | ||
| 188 | nvc0_graph_init_unk78xx, | ||
| 189 | nvc0_graph_init_unk60xx, | ||
| 190 | nvd9_graph_init_unk64xx, | ||
| 191 | nv108_graph_init_unk58xx, | ||
| 192 | nvc0_graph_init_unk80xx, | ||
| 193 | nvf0_graph_init_unk70xx, | ||
| 194 | nvf0_graph_init_unk5bxx, | ||
| 195 | nv108_graph_init_gpc, | ||
| 196 | nv108_graph_init_tpc, | ||
| 197 | nve4_graph_init_unk, | ||
| 198 | nve4_graph_init_unk88xx, | ||
| 199 | NULL | ||
| 200 | }; | ||
| 201 | |||
| 202 | #include "fuc/hubnv108.fuc5.h" | ||
| 203 | |||
| 204 | static struct nvc0_graph_ucode | ||
| 205 | nv108_graph_fecs_ucode = { | ||
| 206 | .code.data = nv108_grhub_code, | ||
| 207 | .code.size = sizeof(nv108_grhub_code), | ||
| 208 | .data.data = nv108_grhub_data, | ||
| 209 | .data.size = sizeof(nv108_grhub_data), | ||
| 210 | }; | ||
| 211 | |||
| 212 | #include "fuc/gpcnv108.fuc5.h" | ||
| 213 | |||
| 214 | static struct nvc0_graph_ucode | ||
| 215 | nv108_graph_gpccs_ucode = { | ||
| 216 | .code.data = nv108_grgpc_code, | ||
| 217 | .code.size = sizeof(nv108_grgpc_code), | ||
| 218 | .data.data = nv108_grgpc_data, | ||
| 219 | .data.size = sizeof(nv108_grgpc_data), | ||
| 220 | }; | ||
| 221 | |||
| 222 | struct nouveau_oclass * | ||
| 223 | nv108_graph_oclass = &(struct nvc0_graph_oclass) { | ||
| 224 | .base.handle = NV_ENGINE(GR, 0x08), | ||
| 225 | .base.ofuncs = &(struct nouveau_ofuncs) { | ||
| 226 | .ctor = nvc0_graph_ctor, | ||
| 227 | .dtor = nvc0_graph_dtor, | ||
| 228 | .init = nve4_graph_init, | ||
| 229 | .fini = nv108_graph_fini, | ||
| 230 | }, | ||
| 231 | .cclass = &nv108_grctx_oclass, | ||
| 232 | .sclass = nv108_graph_sclass, | ||
| 233 | .mmio = nv108_graph_init_mmio, | ||
| 234 | .fecs.ucode = &nv108_graph_fecs_ucode, | ||
| 235 | .gpccs.ucode = &nv108_graph_gpccs_ucode, | ||
| 236 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c index 03de5175dd9f..30ed19c52e05 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c | |||
| @@ -304,12 +304,28 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine) | |||
| 304 | return timeout ? -EBUSY : 0; | 304 | return timeout ? -EBUSY : 0; |
| 305 | } | 305 | } |
| 306 | 306 | ||
| 307 | static const struct nouveau_enum nv50_mp_exec_error_names[] = { | 307 | static const struct nouveau_bitfield nv50_mp_exec_errors[] = { |
| 308 | { 3, "STACK_UNDERFLOW", NULL }, | 308 | { 0x01, "STACK_UNDERFLOW" }, |
| 309 | { 4, "QUADON_ACTIVE", NULL }, | 309 | { 0x02, "STACK_MISMATCH" }, |
| 310 | { 8, "TIMEOUT", NULL }, | 310 | { 0x04, "QUADON_ACTIVE" }, |
| 311 | { 0x10, "INVALID_OPCODE", NULL }, | 311 | { 0x08, "TIMEOUT" }, |
| 312 | { 0x40, "BREAKPOINT", NULL }, | 312 | { 0x10, "INVALID_OPCODE" }, |
| 313 | { 0x20, "PM_OVERFLOW" }, | ||
| 314 | { 0x40, "BREAKPOINT" }, | ||
| 315 | {} | ||
| 316 | }; | ||
| 317 | |||
| 318 | static const struct nouveau_bitfield nv50_mpc_traps[] = { | ||
| 319 | { 0x0000001, "LOCAL_LIMIT_READ" }, | ||
| 320 | { 0x0000010, "LOCAL_LIMIT_WRITE" }, | ||
| 321 | { 0x0000040, "STACK_LIMIT" }, | ||
| 322 | { 0x0000100, "GLOBAL_LIMIT_READ" }, | ||
| 323 | { 0x0001000, "GLOBAL_LIMIT_WRITE" }, | ||
| 324 | { 0x0010000, "MP0" }, | ||
| 325 | { 0x0020000, "MP1" }, | ||
| 326 | { 0x0040000, "GLOBAL_LIMIT_RED" }, | ||
| 327 | { 0x0400000, "GLOBAL_LIMIT_ATOM" }, | ||
| 328 | { 0x4000000, "MP2" }, | ||
| 313 | {} | 329 | {} |
| 314 | }; | 330 | }; |
| 315 | 331 | ||
| @@ -396,6 +412,60 @@ static const struct nouveau_bitfield nv50_graph_intr_name[] = { | |||
| 396 | {} | 412 | {} |
| 397 | }; | 413 | }; |
| 398 | 414 | ||
| 415 | static const struct nouveau_bitfield nv50_graph_trap_prop[] = { | ||
| 416 | { 0x00000004, "SURF_WIDTH_OVERRUN" }, | ||
| 417 | { 0x00000008, "SURF_HEIGHT_OVERRUN" }, | ||
| 418 | { 0x00000010, "DST2D_FAULT" }, | ||
| 419 | { 0x00000020, "ZETA_FAULT" }, | ||
| 420 | { 0x00000040, "RT_FAULT" }, | ||
| 421 | { 0x00000080, "CUDA_FAULT" }, | ||
| 422 | { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" }, | ||
| 423 | { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" }, | ||
| 424 | { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" }, | ||
| 425 | { 0x00000800, "DST2D_LINEAR_MISMATCH" }, | ||
| 426 | { 0x00001000, "RT_LINEAR_MISMATCH" }, | ||
| 427 | {} | ||
| 428 | }; | ||
| 429 | |||
| 430 | static void | ||
| 431 | nv50_priv_prop_trap(struct nv50_graph_priv *priv, | ||
| 432 | u32 ustatus_addr, u32 ustatus, u32 tp) | ||
| 433 | { | ||
| 434 | u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); | ||
| 435 | u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); | ||
| 436 | u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c); | ||
| 437 | u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); | ||
| 438 | u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); | ||
| 439 | u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); | ||
| 440 | u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); | ||
| 441 | |||
| 442 | /* CUDA memory: l[], g[] or stack. */ | ||
| 443 | if (ustatus & 0x00000080) { | ||
| 444 | if (e18 & 0x80000000) { | ||
| 445 | /* g[] read fault? */ | ||
| 446 | nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", | ||
| 447 | tp, e14, e10 | ((e18 >> 24) & 0x1f)); | ||
| 448 | e18 &= ~0x1f000000; | ||
| 449 | } else if (e18 & 0xc) { | ||
| 450 | /* g[] write fault? */ | ||
| 451 | nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", | ||
| 452 | tp, e14, e10 | ((e18 >> 7) & 0x1f)); | ||
| 453 | e18 &= ~0x00000f80; | ||
| 454 | } else { | ||
| 455 | nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", | ||
| 456 | tp, e14, e10); | ||
| 457 | } | ||
| 458 | ustatus &= ~0x00000080; | ||
| 459 | } | ||
| 460 | if (ustatus) { | ||
| 461 | nv_error(priv, "TRAP_PROP - TP %d -", tp); | ||
| 462 | nouveau_bitfield_print(nv50_graph_trap_prop, ustatus); | ||
| 463 | pr_cont(" - Address %02x%08x\n", e14, e10); | ||
| 464 | } | ||
| 465 | nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | ||
| 466 | tp, e0c, e18, e1c, e20, e24); | ||
| 467 | } | ||
| 468 | |||
| 399 | static void | 469 | static void |
| 400 | nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) | 470 | nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) |
| 401 | { | 471 | { |
| @@ -420,8 +490,8 @@ nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) | |||
| 420 | oplow = nv_rd32(priv, addr + 0x70); | 490 | oplow = nv_rd32(priv, addr + 0x70); |
| 421 | ophigh = nv_rd32(priv, addr + 0x74); | 491 | ophigh = nv_rd32(priv, addr + 0x74); |
| 422 | nv_error(priv, "TRAP_MP_EXEC - " | 492 | nv_error(priv, "TRAP_MP_EXEC - " |
| 423 | "TP %d MP %d: ", tpid, i); | 493 | "TP %d MP %d:", tpid, i); |
| 424 | nouveau_enum_print(nv50_mp_exec_error_names, status); | 494 | nouveau_bitfield_print(nv50_mp_exec_errors, status); |
| 425 | pr_cont(" at %06x warp %d, opcode %08x %08x\n", | 495 | pr_cont(" at %06x warp %d, opcode %08x %08x\n", |
| 426 | pc&0xffffff, pc >> 24, | 496 | pc&0xffffff, pc >> 24, |
| 427 | oplow, ophigh); | 497 | oplow, ophigh); |
| @@ -468,60 +538,19 @@ nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, | |||
| 468 | nv50_priv_mp_trap(priv, i, display); | 538 | nv50_priv_mp_trap(priv, i, display); |
| 469 | ustatus &= ~0x04030000; | 539 | ustatus &= ~0x04030000; |
| 470 | } | 540 | } |
| 471 | break; | 541 | if (ustatus && display) { |
| 472 | case 8: /* TPDMA error */ | 542 | nv_error("%s - TP%d:", name, i); |
| 473 | { | 543 | nouveau_bitfield_print(nv50_mpc_traps, ustatus); |
| 474 | u32 e0c = nv_rd32(priv, ustatus_addr + 4); | 544 | pr_cont("\n"); |
| 475 | u32 e10 = nv_rd32(priv, ustatus_addr + 8); | 545 | ustatus = 0; |
| 476 | u32 e14 = nv_rd32(priv, ustatus_addr + 0xc); | ||
| 477 | u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); | ||
| 478 | u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); | ||
| 479 | u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); | ||
| 480 | u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); | ||
| 481 | /* 2d engine destination */ | ||
| 482 | if (ustatus & 0x00000010) { | ||
| 483 | if (display) { | ||
| 484 | nv_error(priv, "TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n", | ||
| 485 | i, e14, e10); | ||
| 486 | nv_error(priv, "TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | ||
| 487 | i, e0c, e18, e1c, e20, e24); | ||
| 488 | } | ||
| 489 | ustatus &= ~0x00000010; | ||
| 490 | } | ||
| 491 | /* Render target */ | ||
| 492 | if (ustatus & 0x00000040) { | ||
| 493 | if (display) { | ||
| 494 | nv_error(priv, "TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n", | ||
| 495 | i, e14, e10); | ||
| 496 | nv_error(priv, "TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | ||
| 497 | i, e0c, e18, e1c, e20, e24); | ||
| 498 | } | ||
| 499 | ustatus &= ~0x00000040; | ||
| 500 | } | ||
| 501 | /* CUDA memory: l[], g[] or stack. */ | ||
| 502 | if (ustatus & 0x00000080) { | ||
| 503 | if (display) { | ||
| 504 | if (e18 & 0x80000000) { | ||
| 505 | /* g[] read fault? */ | ||
| 506 | nv_error(priv, "TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n", | ||
| 507 | i, e14, e10 | ((e18 >> 24) & 0x1f)); | ||
| 508 | e18 &= ~0x1f000000; | ||
| 509 | } else if (e18 & 0xc) { | ||
| 510 | /* g[] write fault? */ | ||
| 511 | nv_error(priv, "TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n", | ||
| 512 | i, e14, e10 | ((e18 >> 7) & 0x1f)); | ||
| 513 | e18 &= ~0x00000f80; | ||
| 514 | } else { | ||
| 515 | nv_error(priv, "TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n", | ||
| 516 | i, e14, e10); | ||
| 517 | } | ||
| 518 | nv_error(priv, "TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", | ||
| 519 | i, e0c, e18, e1c, e20, e24); | ||
| 520 | } | ||
| 521 | ustatus &= ~0x00000080; | ||
| 522 | } | ||
| 523 | } | 546 | } |
| 524 | break; | 547 | break; |
| 548 | case 8: /* PROP error */ | ||
| 549 | if (display) | ||
| 550 | nv50_priv_prop_trap( | ||
| 551 | priv, ustatus_addr, ustatus, i); | ||
| 552 | ustatus = 0; | ||
| 553 | break; | ||
| 525 | } | 554 | } |
| 526 | if (ustatus) { | 555 | if (ustatus) { |
| 527 | if (display) | 556 | if (display) |
| @@ -727,11 +756,11 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, | |||
| 727 | status &= ~0x080; | 756 | status &= ~0x080; |
| 728 | } | 757 | } |
| 729 | 758 | ||
| 730 | /* TPDMA: Handles TP-initiated uncached memory accesses: | 759 | /* PROP: Handles TP-initiated uncached memory accesses: |
| 731 | * l[], g[], stack, 2d surfaces, render targets. */ | 760 | * l[], g[], stack, 2d surfaces, render targets. */ |
| 732 | if (status & 0x100) { | 761 | if (status & 0x100) { |
| 733 | nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, | 762 | nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, |
| 734 | "TRAP_TPDMA"); | 763 | "TRAP_PROP"); |
| 735 | nv_wr32(priv, 0x400108, 0x100); | 764 | nv_wr32(priv, 0x400108, 0x100); |
| 736 | status &= ~0x100; | 765 | status &= ~0x100; |
| 737 | } | 766 | } |
| @@ -760,7 +789,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev) | |||
| 760 | u32 mthd = (addr & 0x00001ffc); | 789 | u32 mthd = (addr & 0x00001ffc); |
| 761 | u32 data = nv_rd32(priv, 0x400708); | 790 | u32 data = nv_rd32(priv, 0x400708); |
| 762 | u32 class = nv_rd32(priv, 0x400814); | 791 | u32 class = nv_rd32(priv, 0x400814); |
| 763 | u32 show = stat; | 792 | u32 show = stat, show_bitfield = stat; |
| 764 | int chid; | 793 | int chid; |
| 765 | 794 | ||
| 766 | engctx = nouveau_engctx_get(engine, inst); | 795 | engctx = nouveau_engctx_get(engine, inst); |
| @@ -778,21 +807,26 @@ nv50_graph_intr(struct nouveau_subdev *subdev) | |||
| 778 | nv_error(priv, "DATA_ERROR "); | 807 | nv_error(priv, "DATA_ERROR "); |
| 779 | nouveau_enum_print(nv50_data_error_names, ecode); | 808 | nouveau_enum_print(nv50_data_error_names, ecode); |
| 780 | pr_cont("\n"); | 809 | pr_cont("\n"); |
| 810 | show_bitfield &= ~0x00100000; | ||
| 781 | } | 811 | } |
| 782 | 812 | ||
| 783 | if (stat & 0x00200000) { | 813 | if (stat & 0x00200000) { |
| 784 | if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, | 814 | if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, |
| 785 | engctx)) | 815 | engctx)) |
| 786 | show &= ~0x00200000; | 816 | show &= ~0x00200000; |
| 817 | show_bitfield &= ~0x00200000; | ||
| 787 | } | 818 | } |
| 788 | 819 | ||
| 789 | nv_wr32(priv, 0x400100, stat); | 820 | nv_wr32(priv, 0x400100, stat); |
| 790 | nv_wr32(priv, 0x400500, 0x00010001); | 821 | nv_wr32(priv, 0x400500, 0x00010001); |
| 791 | 822 | ||
| 792 | if (show) { | 823 | if (show) { |
| 793 | nv_error(priv, "%s", ""); | 824 | show &= show_bitfield; |
| 794 | nouveau_bitfield_print(nv50_graph_intr_name, show); | 825 | if (show) { |
| 795 | pr_cont("\n"); | 826 | nv_error(priv, "%s", ""); |
| 827 | nouveau_bitfield_print(nv50_graph_intr_name, show); | ||
| 828 | pr_cont("\n"); | ||
| 829 | } | ||
| 796 | nv_error(priv, | 830 | nv_error(priv, |
| 797 | "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", | 831 | "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", |
| 798 | chid, (u64)inst << 12, nouveau_client_name(engctx), | 832 | chid, (u64)inst << 12, nouveau_client_name(engctx), |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c index 5c8a63dc506a..a73ab209ea88 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | |||
| @@ -901,6 +901,9 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) | |||
| 901 | } | 901 | } |
| 902 | 902 | ||
| 903 | return 0; | 903 | return 0; |
| 904 | } else | ||
| 905 | if (!oclass->fecs.ucode) { | ||
| 906 | return -ENOSYS; | ||
| 904 | } | 907 | } |
| 905 | 908 | ||
| 906 | /* load HUB microcode */ | 909 | /* load HUB microcode */ |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h index ea17a80ad7fc..b0ab6de270b2 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h | |||
| @@ -205,6 +205,11 @@ extern struct nvc0_graph_init nve4_graph_init_regs[]; | |||
| 205 | extern struct nvc0_graph_init nve4_graph_init_unk[]; | 205 | extern struct nvc0_graph_init nve4_graph_init_unk[]; |
| 206 | extern struct nvc0_graph_init nve4_graph_init_unk88xx[]; | 206 | extern struct nvc0_graph_init nve4_graph_init_unk88xx[]; |
| 207 | 207 | ||
| 208 | extern struct nvc0_graph_init nvf0_graph_init_unk40xx[]; | ||
| 209 | extern struct nvc0_graph_init nvf0_graph_init_unk70xx[]; | ||
| 210 | extern struct nvc0_graph_init nvf0_graph_init_unk5bxx[]; | ||
| 211 | extern struct nvc0_graph_init nvf0_graph_init_tpc[]; | ||
| 212 | |||
| 208 | int nvc0_grctx_generate(struct nvc0_graph_priv *); | 213 | int nvc0_grctx_generate(struct nvc0_graph_priv *); |
| 209 | void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); | 214 | void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); |
| 210 | void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *); | 215 | void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *); |
| @@ -266,6 +271,11 @@ extern struct nvc0_graph_init nve4_grctx_init_unk80xx[]; | |||
| 266 | extern struct nvc0_graph_init nve4_grctx_init_unk90xx[]; | 271 | extern struct nvc0_graph_init nve4_grctx_init_unk90xx[]; |
| 267 | 272 | ||
| 268 | extern struct nouveau_oclass *nvf0_grctx_oclass; | 273 | extern struct nouveau_oclass *nvf0_grctx_oclass; |
| 274 | extern struct nvc0_graph_init nvf0_grctx_init_unk44xx[]; | ||
| 275 | extern struct nvc0_graph_init nvf0_grctx_init_unk5bxx[]; | ||
| 276 | extern struct nvc0_graph_init nvf0_grctx_init_unk60xx[]; | ||
| 277 | |||
| 278 | extern struct nouveau_oclass *nv108_grctx_oclass; | ||
| 269 | 279 | ||
| 270 | #define mmio_data(s,a,p) do { \ | 280 | #define mmio_data(s,a,p) do { \ |
| 271 | info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \ | 281 | info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \ |
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c index 2f0ac7832234..b1acb9939d95 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c | |||
| @@ -41,7 +41,7 @@ nvf0_graph_sclass[] = { | |||
| 41 | * PGRAPH engine/subdev functions | 41 | * PGRAPH engine/subdev functions |
| 42 | ******************************************************************************/ | 42 | ******************************************************************************/ |
| 43 | 43 | ||
| 44 | static struct nvc0_graph_init | 44 | struct nvc0_graph_init |
| 45 | nvf0_graph_init_unk40xx[] = { | 45 | nvf0_graph_init_unk40xx[] = { |
| 46 | { 0x40415c, 1, 0x04, 0x00000000 }, | 46 | { 0x40415c, 1, 0x04, 0x00000000 }, |
| 47 | { 0x404170, 1, 0x04, 0x00000000 }, | 47 | { 0x404170, 1, 0x04, 0x00000000 }, |
| @@ -60,7 +60,7 @@ nvf0_graph_init_unk58xx[] = { | |||
| 60 | {} | 60 | {} |
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | static struct nvc0_graph_init | 63 | struct nvc0_graph_init |
| 64 | nvf0_graph_init_unk70xx[] = { | 64 | nvf0_graph_init_unk70xx[] = { |
| 65 | { 0x407010, 1, 0x04, 0x00000000 }, | 65 | { 0x407010, 1, 0x04, 0x00000000 }, |
| 66 | { 0x407040, 1, 0x04, 0x80440424 }, | 66 | { 0x407040, 1, 0x04, 0x80440424 }, |
| @@ -68,7 +68,7 @@ nvf0_graph_init_unk70xx[] = { | |||
| 68 | {} | 68 | {} |
| 69 | }; | 69 | }; |
| 70 | 70 | ||
| 71 | static struct nvc0_graph_init | 71 | struct nvc0_graph_init |
| 72 | nvf0_graph_init_unk5bxx[] = { | 72 | nvf0_graph_init_unk5bxx[] = { |
| 73 | { 0x405b44, 1, 0x04, 0x00000000 }, | 73 | { 0x405b44, 1, 0x04, 0x00000000 }, |
| 74 | { 0x405b50, 1, 0x04, 0x00000000 }, | 74 | { 0x405b50, 1, 0x04, 0x00000000 }, |
| @@ -114,7 +114,7 @@ nvf0_graph_init_gpc[] = { | |||
| 114 | {} | 114 | {} |
| 115 | }; | 115 | }; |
| 116 | 116 | ||
| 117 | static struct nvc0_graph_init | 117 | struct nvc0_graph_init |
| 118 | nvf0_graph_init_tpc[] = { | 118 | nvf0_graph_init_tpc[] = { |
| 119 | { 0x419d0c, 1, 0x04, 0x00000000 }, | 119 | { 0x419d0c, 1, 0x04, 0x00000000 }, |
| 120 | { 0x419d10, 1, 0x04, 0x00000014 }, | 120 | { 0x419d10, 1, 0x04, 0x00000014 }, |
| @@ -243,6 +243,6 @@ nvf0_graph_oclass = &(struct nvc0_graph_oclass) { | |||
| 243 | .cclass = &nvf0_grctx_oclass, | 243 | .cclass = &nvf0_grctx_oclass, |
| 244 | .sclass = nvf0_graph_sclass, | 244 | .sclass = nvf0_graph_sclass, |
| 245 | .mmio = nvf0_graph_init_mmio, | 245 | .mmio = nvf0_graph_init_mmio, |
| 246 | .fecs.ucode = 0 ? &nvf0_graph_fecs_ucode : NULL, | 246 | .fecs.ucode = &nvf0_graph_fecs_ucode, |
| 247 | .gpccs.ucode = &nvf0_graph_gpccs_ucode, | 247 | .gpccs.ucode = &nvf0_graph_gpccs_ucode, |
| 248 | }.base; | 248 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h index ac2881d1776a..7b8ea221b00d 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/device.h +++ b/drivers/gpu/drm/nouveau/core/include/core/device.h | |||
| @@ -38,7 +38,8 @@ enum nv_subdev_type { | |||
| 38 | NVDEV_SUBDEV_THERM, | 38 | NVDEV_SUBDEV_THERM, |
| 39 | NVDEV_SUBDEV_CLOCK, | 39 | NVDEV_SUBDEV_CLOCK, |
| 40 | 40 | ||
| 41 | NVDEV_ENGINE_DMAOBJ, | 41 | NVDEV_ENGINE_FIRST, |
| 42 | NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, | ||
| 42 | NVDEV_ENGINE_FIFO, | 43 | NVDEV_ENGINE_FIFO, |
| 43 | NVDEV_ENGINE_SW, | 44 | NVDEV_ENGINE_SW, |
| 44 | NVDEV_ENGINE_GR, | 45 | NVDEV_ENGINE_GR, |
| @@ -70,6 +71,7 @@ struct nouveau_device { | |||
| 70 | const char *dbgopt; | 71 | const char *dbgopt; |
| 71 | const char *name; | 72 | const char *name; |
| 72 | const char *cname; | 73 | const char *cname; |
| 74 | u64 disable_mask; | ||
| 73 | 75 | ||
| 74 | enum { | 76 | enum { |
| 75 | NV_04 = 0x04, | 77 | NV_04 = 0x04, |
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h index 8c32cf4d83c7..26b6b2bb1112 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h | |||
| @@ -109,6 +109,7 @@ extern struct nouveau_oclass *nv50_fifo_oclass; | |||
| 109 | extern struct nouveau_oclass *nv84_fifo_oclass; | 109 | extern struct nouveau_oclass *nv84_fifo_oclass; |
| 110 | extern struct nouveau_oclass *nvc0_fifo_oclass; | 110 | extern struct nouveau_oclass *nvc0_fifo_oclass; |
| 111 | extern struct nouveau_oclass *nve0_fifo_oclass; | 111 | extern struct nouveau_oclass *nve0_fifo_oclass; |
| 112 | extern struct nouveau_oclass *nv108_fifo_oclass; | ||
| 112 | 113 | ||
| 113 | void nv04_fifo_intr(struct nouveau_subdev *); | 114 | void nv04_fifo_intr(struct nouveau_subdev *); |
| 114 | int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); | 115 | int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); |
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h index 8e1b52312ddc..97705618de97 100644 --- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h +++ b/drivers/gpu/drm/nouveau/core/include/engine/graph.h | |||
| @@ -69,6 +69,7 @@ extern struct nouveau_oclass *nvd7_graph_oclass; | |||
| 69 | extern struct nouveau_oclass *nvd9_graph_oclass; | 69 | extern struct nouveau_oclass *nvd9_graph_oclass; |
| 70 | extern struct nouveau_oclass *nve4_graph_oclass; | 70 | extern struct nouveau_oclass *nve4_graph_oclass; |
| 71 | extern struct nouveau_oclass *nvf0_graph_oclass; | 71 | extern struct nouveau_oclass *nvf0_graph_oclass; |
| 72 | extern struct nouveau_oclass *nv108_graph_oclass; | ||
| 72 | 73 | ||
| 73 | extern const struct nouveau_bitfield nv04_graph_nsource[]; | 74 | extern const struct nouveau_bitfield nv04_graph_nsource[]; |
| 74 | extern struct nouveau_ofuncs nv04_graph_ofuncs; | 75 | extern struct nouveau_ofuncs nv04_graph_ofuncs; |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h index 4f4ff4502c3d..9faa98e67ad8 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h | |||
| @@ -4,8 +4,7 @@ | |||
| 4 | #include <core/subdev.h> | 4 | #include <core/subdev.h> |
| 5 | #include <core/device.h> | 5 | #include <core/device.h> |
| 6 | 6 | ||
| 7 | #include <subdev/fb.h> | 7 | struct nouveau_mem; |
| 8 | |||
| 9 | struct nouveau_vma; | 8 | struct nouveau_vma; |
| 10 | 9 | ||
| 11 | struct nouveau_bar { | 10 | struct nouveau_bar { |
| @@ -29,27 +28,7 @@ nouveau_bar(void *obj) | |||
| 29 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BAR]; | 28 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BAR]; |
| 30 | } | 29 | } |
| 31 | 30 | ||
| 32 | #define nouveau_bar_create(p,e,o,d) \ | ||
| 33 | nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d) | ||
| 34 | #define nouveau_bar_init(p) \ | ||
| 35 | nouveau_subdev_init(&(p)->base) | ||
| 36 | #define nouveau_bar_fini(p,s) \ | ||
| 37 | nouveau_subdev_fini(&(p)->base, (s)) | ||
| 38 | |||
| 39 | int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 40 | struct nouveau_oclass *, int, void **); | ||
| 41 | void nouveau_bar_destroy(struct nouveau_bar *); | ||
| 42 | |||
| 43 | void _nouveau_bar_dtor(struct nouveau_object *); | ||
| 44 | #define _nouveau_bar_init _nouveau_subdev_init | ||
| 45 | #define _nouveau_bar_fini _nouveau_subdev_fini | ||
| 46 | |||
| 47 | extern struct nouveau_oclass nv50_bar_oclass; | 31 | extern struct nouveau_oclass nv50_bar_oclass; |
| 48 | extern struct nouveau_oclass nvc0_bar_oclass; | 32 | extern struct nouveau_oclass nvc0_bar_oclass; |
| 49 | 33 | ||
| 50 | int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *, | ||
| 51 | struct nouveau_mem *, struct nouveau_object **); | ||
| 52 | |||
| 53 | void nv84_bar_flush(struct nouveau_bar *); | ||
| 54 | |||
| 55 | #endif | 34 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h new file mode 100644 index 000000000000..c5e6d1e6ac1d --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h | |||
| @@ -0,0 +1,66 @@ | |||
| 1 | #ifndef __NVBIOS_RAMCFG_H__ | ||
| 2 | #define __NVBIOS_RAMCFG_H__ | ||
| 3 | |||
| 4 | struct nouveau_bios; | ||
| 5 | |||
| 6 | struct nvbios_ramcfg { | ||
| 7 | unsigned rammap_11_08_01:1; | ||
| 8 | unsigned rammap_11_08_0c:2; | ||
| 9 | unsigned rammap_11_08_10:1; | ||
| 10 | unsigned rammap_11_11_0c:2; | ||
| 11 | |||
| 12 | unsigned ramcfg_11_01_01:1; | ||
| 13 | unsigned ramcfg_11_01_02:1; | ||
| 14 | unsigned ramcfg_11_01_04:1; | ||
| 15 | unsigned ramcfg_11_01_08:1; | ||
| 16 | unsigned ramcfg_11_01_10:1; | ||
| 17 | unsigned ramcfg_11_01_20:1; | ||
| 18 | unsigned ramcfg_11_01_40:1; | ||
| 19 | unsigned ramcfg_11_01_80:1; | ||
| 20 | unsigned ramcfg_11_02_03:2; | ||
| 21 | unsigned ramcfg_11_02_04:1; | ||
| 22 | unsigned ramcfg_11_02_08:1; | ||
| 23 | unsigned ramcfg_11_02_10:1; | ||
| 24 | unsigned ramcfg_11_02_40:1; | ||
| 25 | unsigned ramcfg_11_02_80:1; | ||
| 26 | unsigned ramcfg_11_03_0f:4; | ||
| 27 | unsigned ramcfg_11_03_30:2; | ||
| 28 | unsigned ramcfg_11_03_c0:2; | ||
| 29 | unsigned ramcfg_11_03_f0:4; | ||
| 30 | unsigned ramcfg_11_04:8; | ||
| 31 | unsigned ramcfg_11_06:8; | ||
| 32 | unsigned ramcfg_11_07_02:1; | ||
| 33 | unsigned ramcfg_11_07_04:1; | ||
| 34 | unsigned ramcfg_11_07_08:1; | ||
| 35 | unsigned ramcfg_11_07_10:1; | ||
| 36 | unsigned ramcfg_11_07_40:1; | ||
| 37 | unsigned ramcfg_11_07_80:1; | ||
| 38 | unsigned ramcfg_11_08_01:1; | ||
| 39 | unsigned ramcfg_11_08_02:1; | ||
| 40 | unsigned ramcfg_11_08_04:1; | ||
| 41 | unsigned ramcfg_11_08_08:1; | ||
| 42 | unsigned ramcfg_11_08_10:1; | ||
| 43 | unsigned ramcfg_11_08_20:1; | ||
| 44 | unsigned ramcfg_11_09:8; | ||
| 45 | |||
| 46 | unsigned timing[11]; | ||
| 47 | unsigned timing_20_2e_03:2; | ||
| 48 | unsigned timing_20_2e_30:2; | ||
| 49 | unsigned timing_20_2e_c0:2; | ||
| 50 | unsigned timing_20_2f_03:2; | ||
| 51 | unsigned timing_20_2c_003f:6; | ||
| 52 | unsigned timing_20_2c_1fc0:7; | ||
| 53 | unsigned timing_20_30_f8:5; | ||
| 54 | unsigned timing_20_30_07:3; | ||
| 55 | unsigned timing_20_31_0007:3; | ||
| 56 | unsigned timing_20_31_0078:4; | ||
| 57 | unsigned timing_20_31_0780:4; | ||
| 58 | unsigned timing_20_31_0800:1; | ||
| 59 | unsigned timing_20_31_7000:3; | ||
| 60 | unsigned timing_20_31_8000:1; | ||
| 61 | }; | ||
| 62 | |||
| 63 | u8 nvbios_ramcfg_count(struct nouveau_bios *); | ||
| 64 | u8 nvbios_ramcfg_index(struct nouveau_bios *); | ||
| 65 | |||
| 66 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h index bc15e0320877..5bdf8e4db40a 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h | |||
| @@ -1,11 +1,25 @@ | |||
| 1 | #ifndef __NVBIOS_RAMMAP_H__ | 1 | #ifndef __NVBIOS_RAMMAP_H__ |
| 2 | #define __NVBIOS_RAMMAP_H__ | 2 | #define __NVBIOS_RAMMAP_H__ |
| 3 | 3 | ||
| 4 | u16 nvbios_rammap_table(struct nouveau_bios *, u8 *ver, u8 *hdr, | 4 | struct nvbios_ramcfg; |
| 5 | u8 *cnt, u8 *len, u8 *snr, u8 *ssz); | 5 | |
| 6 | u16 nvbios_rammap_entry(struct nouveau_bios *, int idx, | 6 | u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr, |
| 7 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | 7 | u8 *cnt, u8 *len, u8 *snr, u8 *ssz); |
| 8 | u16 nvbios_rammap_match(struct nouveau_bios *, u16 khz, | 8 | |
| 9 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | 9 | u32 nvbios_rammapEe(struct nouveau_bios *, int idx, |
| 10 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | ||
| 11 | u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz, | ||
| 12 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | ||
| 13 | u32 nvbios_rammapEp(struct nouveau_bios *, u16 mhz, | ||
| 14 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, | ||
| 15 | struct nvbios_ramcfg *); | ||
| 16 | |||
| 17 | u32 nvbios_rammapSe(struct nouveau_bios *, u32 data, | ||
| 18 | u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, | ||
| 19 | u8 *ver, u8 *hdr); | ||
| 20 | u32 nvbios_rammapSp(struct nouveau_bios *, u32 data, | ||
| 21 | u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, | ||
| 22 | u8 *ver, u8 *hdr, | ||
| 23 | struct nvbios_ramcfg *); | ||
| 10 | 24 | ||
| 11 | #endif | 25 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h index 963694b54224..76d914b67ab5 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h | |||
| @@ -1,8 +1,14 @@ | |||
| 1 | #ifndef __NVBIOS_TIMING_H__ | 1 | #ifndef __NVBIOS_TIMING_H__ |
| 2 | #define __NVBIOS_TIMING_H__ | 2 | #define __NVBIOS_TIMING_H__ |
| 3 | 3 | ||
| 4 | u16 nvbios_timing_table(struct nouveau_bios *, | 4 | struct nvbios_ramcfg; |
| 5 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | 5 | |
| 6 | u16 nvbios_timing_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); | 6 | u16 nvbios_timingTe(struct nouveau_bios *, |
| 7 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); | ||
| 8 | u16 nvbios_timingEe(struct nouveau_bios *, int idx, | ||
| 9 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | ||
| 10 | u16 nvbios_timingEp(struct nouveau_bios *, int idx, | ||
| 11 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, | ||
| 12 | struct nvbios_ramcfg *); | ||
| 7 | 13 | ||
| 8 | #endif | 14 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h index 685c9b12ee4c..ed1ac68c38b3 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h | |||
| @@ -9,7 +9,6 @@ struct nouveau_devinit { | |||
| 9 | bool post; | 9 | bool post; |
| 10 | void (*meminit)(struct nouveau_devinit *); | 10 | void (*meminit)(struct nouveau_devinit *); |
| 11 | int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq); | 11 | int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq); |
| 12 | |||
| 13 | }; | 12 | }; |
| 14 | 13 | ||
| 15 | static inline struct nouveau_devinit * | 14 | static inline struct nouveau_devinit * |
| @@ -18,32 +17,16 @@ nouveau_devinit(void *obj) | |||
| 18 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT]; | 17 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT]; |
| 19 | } | 18 | } |
| 20 | 19 | ||
| 21 | #define nouveau_devinit_create(p,e,o,d) \ | 20 | extern struct nouveau_oclass *nv04_devinit_oclass; |
| 22 | nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d) | 21 | extern struct nouveau_oclass *nv05_devinit_oclass; |
| 23 | #define nouveau_devinit_destroy(p) \ | 22 | extern struct nouveau_oclass *nv10_devinit_oclass; |
| 24 | nouveau_subdev_destroy(&(p)->base) | 23 | extern struct nouveau_oclass *nv1a_devinit_oclass; |
| 25 | #define nouveau_devinit_init(p) ({ \ | 24 | extern struct nouveau_oclass *nv20_devinit_oclass; |
| 26 | struct nouveau_devinit *d = (p); \ | 25 | extern struct nouveau_oclass *nv50_devinit_oclass; |
| 27 | _nouveau_devinit_init(nv_object(d)); \ | 26 | extern struct nouveau_oclass *nv84_devinit_oclass; |
| 28 | }) | 27 | extern struct nouveau_oclass *nv98_devinit_oclass; |
| 29 | #define nouveau_devinit_fini(p,s) ({ \ | 28 | extern struct nouveau_oclass *nva3_devinit_oclass; |
| 30 | struct nouveau_devinit *d = (p); \ | 29 | extern struct nouveau_oclass *nvaf_devinit_oclass; |
| 31 | _nouveau_devinit_fini(nv_object(d), (s)); \ | 30 | extern struct nouveau_oclass *nvc0_devinit_oclass; |
| 32 | }) | ||
| 33 | |||
| 34 | int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 35 | struct nouveau_oclass *, int, void **); | ||
| 36 | #define _nouveau_devinit_dtor _nouveau_subdev_dtor | ||
| 37 | int _nouveau_devinit_init(struct nouveau_object *); | ||
| 38 | int _nouveau_devinit_fini(struct nouveau_object *, bool suspend); | ||
| 39 | |||
| 40 | extern struct nouveau_oclass nv04_devinit_oclass; | ||
| 41 | extern struct nouveau_oclass nv05_devinit_oclass; | ||
| 42 | extern struct nouveau_oclass nv10_devinit_oclass; | ||
| 43 | extern struct nouveau_oclass nv1a_devinit_oclass; | ||
| 44 | extern struct nouveau_oclass nv20_devinit_oclass; | ||
| 45 | extern struct nouveau_oclass nv50_devinit_oclass; | ||
| 46 | extern struct nouveau_oclass nva3_devinit_oclass; | ||
| 47 | extern struct nouveau_oclass nvc0_devinit_oclass; | ||
| 48 | 31 | ||
| 49 | #endif | 32 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h index d89dbdf39b0d..d7ecafbae1ca 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h | |||
| @@ -106,6 +106,13 @@ extern struct nouveau_oclass *nvaf_fb_oclass; | |||
| 106 | extern struct nouveau_oclass *nvc0_fb_oclass; | 106 | extern struct nouveau_oclass *nvc0_fb_oclass; |
| 107 | extern struct nouveau_oclass *nve0_fb_oclass; | 107 | extern struct nouveau_oclass *nve0_fb_oclass; |
| 108 | 108 | ||
| 109 | #include <subdev/bios/ramcfg.h> | ||
| 110 | |||
| 111 | struct nouveau_ram_data { | ||
| 112 | struct nvbios_ramcfg bios; | ||
| 113 | u32 freq; | ||
| 114 | }; | ||
| 115 | |||
| 109 | struct nouveau_ram { | 116 | struct nouveau_ram { |
| 110 | struct nouveau_object base; | 117 | struct nouveau_object base; |
| 111 | enum { | 118 | enum { |
| @@ -142,6 +149,12 @@ struct nouveau_ram { | |||
| 142 | } rammap, ramcfg, timing; | 149 | } rammap, ramcfg, timing; |
| 143 | u32 freq; | 150 | u32 freq; |
| 144 | u32 mr[16]; | 151 | u32 mr[16]; |
| 152 | u32 mr1_nuts; | ||
| 153 | |||
| 154 | struct nouveau_ram_data *next; | ||
| 155 | struct nouveau_ram_data former; | ||
| 156 | struct nouveau_ram_data xition; | ||
| 157 | struct nouveau_ram_data target; | ||
| 145 | }; | 158 | }; |
| 146 | 159 | ||
| 147 | #endif | 160 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h index 4aca33887aaa..c1df26f3230c 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h | |||
| @@ -23,21 +23,6 @@ nv_memobj(void *obj) | |||
| 23 | return obj; | 23 | return obj; |
| 24 | } | 24 | } |
| 25 | 25 | ||
| 26 | #define nouveau_instobj_create(p,e,o,d) \ | ||
| 27 | nouveau_instobj_create_((p), (e), (o), sizeof(**d), (void **)d) | ||
| 28 | #define nouveau_instobj_init(p) \ | ||
| 29 | nouveau_object_init(&(p)->base) | ||
| 30 | #define nouveau_instobj_fini(p,s) \ | ||
| 31 | nouveau_object_fini(&(p)->base, (s)) | ||
| 32 | |||
| 33 | int nouveau_instobj_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 34 | struct nouveau_oclass *, int, void **); | ||
| 35 | void nouveau_instobj_destroy(struct nouveau_instobj *); | ||
| 36 | |||
| 37 | void _nouveau_instobj_dtor(struct nouveau_object *); | ||
| 38 | #define _nouveau_instobj_init nouveau_object_init | ||
| 39 | #define _nouveau_instobj_fini nouveau_object_fini | ||
| 40 | |||
| 41 | struct nouveau_instmem { | 26 | struct nouveau_instmem { |
| 42 | struct nouveau_subdev base; | 27 | struct nouveau_subdev base; |
| 43 | struct list_head list; | 28 | struct list_head list; |
| @@ -60,21 +45,8 @@ nouveau_instmem(void *obj) | |||
| 60 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_INSTMEM]; | 45 | return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_INSTMEM]; |
| 61 | } | 46 | } |
| 62 | 47 | ||
| 63 | #define nouveau_instmem_create(p,e,o,d) \ | 48 | extern struct nouveau_oclass *nv04_instmem_oclass; |
| 64 | nouveau_instmem_create_((p), (e), (o), sizeof(**d), (void **)d) | 49 | extern struct nouveau_oclass *nv40_instmem_oclass; |
| 65 | #define nouveau_instmem_destroy(p) \ | 50 | extern struct nouveau_oclass *nv50_instmem_oclass; |
| 66 | nouveau_subdev_destroy(&(p)->base) | ||
| 67 | int nouveau_instmem_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 68 | struct nouveau_oclass *, int, void **); | ||
| 69 | int nouveau_instmem_init(struct nouveau_instmem *); | ||
| 70 | int nouveau_instmem_fini(struct nouveau_instmem *, bool); | ||
| 71 | |||
| 72 | #define _nouveau_instmem_dtor _nouveau_subdev_dtor | ||
| 73 | int _nouveau_instmem_init(struct nouveau_object *); | ||
| 74 | int _nouveau_instmem_fini(struct nouveau_object *, bool); | ||
| 75 | |||
| 76 | extern struct nouveau_oclass nv04_instmem_oclass; | ||
| 77 | extern struct nouveau_oclass nv40_instmem_oclass; | ||
| 78 | extern struct nouveau_oclass nv50_instmem_oclass; | ||
| 79 | 51 | ||
| 80 | #endif | 52 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h index fcf57fa309bf..c9509039f94b 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h | |||
| @@ -131,9 +131,5 @@ void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); | |||
| 131 | void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); | 131 | void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); |
| 132 | void nouveau_vm_unmap(struct nouveau_vma *); | 132 | void nouveau_vm_unmap(struct nouveau_vma *); |
| 133 | void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length); | 133 | void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length); |
| 134 | void nouveau_vm_map_sg(struct nouveau_vma *, u64 offset, u64 length, | ||
| 135 | struct nouveau_mem *); | ||
| 136 | void nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, | ||
| 137 | struct nouveau_mem *mem); | ||
| 138 | 134 | ||
| 139 | #endif | 135 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c index d70ba342aa2e..7098ddd54678 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c | |||
| @@ -23,7 +23,11 @@ | |||
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <core/object.h> | 25 | #include <core/object.h> |
| 26 | #include <subdev/bar.h> | 26 | |
| 27 | #include <subdev/fb.h> | ||
| 28 | #include <subdev/vm.h> | ||
| 29 | |||
| 30 | #include "priv.h" | ||
| 27 | 31 | ||
| 28 | struct nouveau_barobj { | 32 | struct nouveau_barobj { |
| 29 | struct nouveau_object base; | 33 | struct nouveau_object base; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c index 160d27f3c7b4..090d594a21b3 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c | |||
| @@ -25,10 +25,11 @@ | |||
| 25 | #include <core/gpuobj.h> | 25 | #include <core/gpuobj.h> |
| 26 | 26 | ||
| 27 | #include <subdev/timer.h> | 27 | #include <subdev/timer.h> |
| 28 | #include <subdev/bar.h> | ||
| 29 | #include <subdev/fb.h> | 28 | #include <subdev/fb.h> |
| 30 | #include <subdev/vm.h> | 29 | #include <subdev/vm.h> |
| 31 | 30 | ||
| 31 | #include "priv.h" | ||
| 32 | |||
| 32 | struct nv50_bar_priv { | 33 | struct nv50_bar_priv { |
| 33 | struct nouveau_bar base; | 34 | struct nouveau_bar base; |
| 34 | spinlock_t lock; | 35 | spinlock_t lock; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c index b2ec7411eb2e..bac5e754de35 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c | |||
| @@ -25,10 +25,11 @@ | |||
| 25 | #include <core/gpuobj.h> | 25 | #include <core/gpuobj.h> |
| 26 | 26 | ||
| 27 | #include <subdev/timer.h> | 27 | #include <subdev/timer.h> |
| 28 | #include <subdev/bar.h> | ||
| 29 | #include <subdev/fb.h> | 28 | #include <subdev/fb.h> |
| 30 | #include <subdev/vm.h> | 29 | #include <subdev/vm.h> |
| 31 | 30 | ||
| 31 | #include "priv.h" | ||
| 32 | |||
| 32 | struct nvc0_bar_priv { | 33 | struct nvc0_bar_priv { |
| 33 | struct nouveau_bar base; | 34 | struct nouveau_bar base; |
| 34 | spinlock_t lock; | 35 | spinlock_t lock; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h new file mode 100644 index 000000000000..ffad8f337ead --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | #ifndef __NVKM_BAR_PRIV_H__ | ||
| 2 | #define __NVKM_BAR_PRIV_H__ | ||
| 3 | |||
| 4 | #include <subdev/bar.h> | ||
| 5 | |||
| 6 | #define nouveau_bar_create(p,e,o,d) \ | ||
| 7 | nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d) | ||
| 8 | #define nouveau_bar_init(p) \ | ||
| 9 | nouveau_subdev_init(&(p)->base) | ||
| 10 | #define nouveau_bar_fini(p,s) \ | ||
| 11 | nouveau_subdev_fini(&(p)->base, (s)) | ||
| 12 | |||
| 13 | int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 14 | struct nouveau_oclass *, int, void **); | ||
| 15 | void nouveau_bar_destroy(struct nouveau_bar *); | ||
| 16 | |||
| 17 | void _nouveau_bar_dtor(struct nouveau_object *); | ||
| 18 | #define _nouveau_bar_init _nouveau_subdev_init | ||
| 19 | #define _nouveau_bar_fini _nouveau_subdev_fini | ||
| 20 | |||
| 21 | int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *, | ||
| 22 | struct nouveau_mem *, struct nouveau_object **); | ||
| 23 | |||
| 24 | void nv84_bar_flush(struct nouveau_bar *); | ||
| 25 | |||
| 26 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c index df1b1b423093..de201baeb053 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | #include <subdev/bios/dp.h> | 9 | #include <subdev/bios/dp.h> |
| 10 | #include <subdev/bios/gpio.h> | 10 | #include <subdev/bios/gpio.h> |
| 11 | #include <subdev/bios/init.h> | 11 | #include <subdev/bios/init.h> |
| 12 | #include <subdev/bios/ramcfg.h> | ||
| 12 | #include <subdev/devinit.h> | 13 | #include <subdev/devinit.h> |
| 13 | #include <subdev/i2c.h> | 14 | #include <subdev/i2c.h> |
| 14 | #include <subdev/vga.h> | 15 | #include <subdev/vga.h> |
| @@ -391,43 +392,14 @@ init_unknown_script(struct nouveau_bios *bios) | |||
| 391 | return 0x0000; | 392 | return 0x0000; |
| 392 | } | 393 | } |
| 393 | 394 | ||
| 394 | static u16 | ||
| 395 | init_ram_restrict_table(struct nvbios_init *init) | ||
| 396 | { | ||
| 397 | struct nouveau_bios *bios = init->bios; | ||
| 398 | struct bit_entry bit_M; | ||
| 399 | u16 data = 0x0000; | ||
| 400 | |||
| 401 | if (!bit_entry(bios, 'M', &bit_M)) { | ||
| 402 | if (bit_M.version == 1 && bit_M.length >= 5) | ||
| 403 | data = nv_ro16(bios, bit_M.offset + 3); | ||
| 404 | if (bit_M.version == 2 && bit_M.length >= 3) | ||
| 405 | data = nv_ro16(bios, bit_M.offset + 1); | ||
| 406 | } | ||
| 407 | |||
| 408 | if (data == 0x0000) | ||
| 409 | warn("ram restrict table not found\n"); | ||
| 410 | return data; | ||
| 411 | } | ||
| 412 | |||
| 413 | static u8 | 395 | static u8 |
| 414 | init_ram_restrict_group_count(struct nvbios_init *init) | 396 | init_ram_restrict_group_count(struct nvbios_init *init) |
| 415 | { | 397 | { |
| 416 | struct nouveau_bios *bios = init->bios; | 398 | return nvbios_ramcfg_count(init->bios); |
| 417 | struct bit_entry bit_M; | ||
| 418 | |||
| 419 | if (!bit_entry(bios, 'M', &bit_M)) { | ||
| 420 | if (bit_M.version == 1 && bit_M.length >= 5) | ||
| 421 | return nv_ro08(bios, bit_M.offset + 2); | ||
| 422 | if (bit_M.version == 2 && bit_M.length >= 3) | ||
| 423 | return nv_ro08(bios, bit_M.offset + 0); | ||
| 424 | } | ||
| 425 | |||
| 426 | return 0x00; | ||
| 427 | } | 399 | } |
| 428 | 400 | ||
| 429 | static u8 | 401 | static u8 |
| 430 | init_ram_restrict_strap(struct nvbios_init *init) | 402 | init_ram_restrict(struct nvbios_init *init) |
| 431 | { | 403 | { |
| 432 | /* This appears to be the behaviour of the VBIOS parser, and *is* | 404 | /* This appears to be the behaviour of the VBIOS parser, and *is* |
| 433 | * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to | 405 | * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to |
| @@ -438,18 +410,8 @@ init_ram_restrict_strap(struct nvbios_init *init) | |||
| 438 | * in case *not* re-reading the strap causes similar breakage. | 410 | * in case *not* re-reading the strap causes similar breakage. |
| 439 | */ | 411 | */ |
| 440 | if (!init->ramcfg || init->bios->version.major < 0x70) | 412 | if (!init->ramcfg || init->bios->version.major < 0x70) |
| 441 | init->ramcfg = init_rd32(init, 0x101000); | 413 | init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->bios); |
| 442 | return (init->ramcfg & 0x00000003c) >> 2; | 414 | return (init->ramcfg & 0x7fffffff); |
| 443 | } | ||
| 444 | |||
| 445 | static u8 | ||
| 446 | init_ram_restrict(struct nvbios_init *init) | ||
| 447 | { | ||
| 448 | u8 strap = init_ram_restrict_strap(init); | ||
| 449 | u16 table = init_ram_restrict_table(init); | ||
| 450 | if (table) | ||
| 451 | return nv_ro08(init->bios, table + strap); | ||
| 452 | return 0x00; | ||
| 453 | } | 415 | } |
| 454 | 416 | ||
| 455 | static u8 | 417 | static u8 |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c b/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c new file mode 100644 index 000000000000..991aedda999b --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include <subdev/bios.h> | ||
| 26 | #include <subdev/bios/bit.h> | ||
| 27 | #include <subdev/bios/ramcfg.h> | ||
| 28 | |||
| 29 | static u8 | ||
| 30 | nvbios_ramcfg_strap(struct nouveau_bios *bios) | ||
| 31 | { | ||
| 32 | return (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2; | ||
| 33 | } | ||
| 34 | |||
| 35 | u8 | ||
| 36 | nvbios_ramcfg_count(struct nouveau_bios *bios) | ||
| 37 | { | ||
| 38 | struct bit_entry bit_M; | ||
| 39 | |||
| 40 | if (!bit_entry(bios, 'M', &bit_M)) { | ||
| 41 | if (bit_M.version == 1 && bit_M.length >= 5) | ||
| 42 | return nv_ro08(bios, bit_M.offset + 2); | ||
| 43 | if (bit_M.version == 2 && bit_M.length >= 3) | ||
| 44 | return nv_ro08(bios, bit_M.offset + 0); | ||
| 45 | } | ||
| 46 | |||
| 47 | return 0x00; | ||
| 48 | } | ||
| 49 | |||
| 50 | u8 | ||
| 51 | nvbios_ramcfg_index(struct nouveau_bios *bios) | ||
| 52 | { | ||
| 53 | u8 strap = nvbios_ramcfg_strap(bios); | ||
| 54 | u32 xlat = 0x00000000; | ||
| 55 | struct bit_entry bit_M; | ||
| 56 | |||
| 57 | if (!bit_entry(bios, 'M', &bit_M)) { | ||
| 58 | if (bit_M.version == 1 && bit_M.length >= 5) | ||
| 59 | xlat = nv_ro16(bios, bit_M.offset + 3); | ||
| 60 | if (bit_M.version == 2 && bit_M.length >= 3) | ||
| 61 | xlat = nv_ro16(bios, bit_M.offset + 1); | ||
| 62 | } | ||
| 63 | |||
| 64 | if (xlat) | ||
| 65 | strap = nv_ro08(bios, xlat + strap); | ||
| 66 | return strap; | ||
| 67 | } | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c index 916fa9d302b7..1811b2cb0472 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c | |||
| @@ -24,11 +24,12 @@ | |||
| 24 | 24 | ||
| 25 | #include <subdev/bios.h> | 25 | #include <subdev/bios.h> |
| 26 | #include <subdev/bios/bit.h> | 26 | #include <subdev/bios/bit.h> |
| 27 | #include <subdev/bios/ramcfg.h> | ||
| 27 | #include <subdev/bios/rammap.h> | 28 | #include <subdev/bios/rammap.h> |
| 28 | 29 | ||
| 29 | u16 | 30 | u32 |
| 30 | nvbios_rammap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, | 31 | nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, |
| 31 | u8 *cnt, u8 *len, u8 *snr, u8 *ssz) | 32 | u8 *cnt, u8 *len, u8 *snr, u8 *ssz) |
| 32 | { | 33 | { |
| 33 | struct bit_entry bit_P; | 34 | struct bit_entry bit_P; |
| 34 | u16 rammap = 0x0000; | 35 | u16 rammap = 0x0000; |
| @@ -57,12 +58,12 @@ nvbios_rammap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, | |||
| 57 | return 0x0000; | 58 | return 0x0000; |
| 58 | } | 59 | } |
| 59 | 60 | ||
| 60 | u16 | 61 | u32 |
| 61 | nvbios_rammap_entry(struct nouveau_bios *bios, int idx, | 62 | nvbios_rammapEe(struct nouveau_bios *bios, int idx, |
| 62 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) | 63 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) |
| 63 | { | 64 | { |
| 64 | u8 snr, ssz; | 65 | u8 snr, ssz; |
| 65 | u16 rammap = nvbios_rammap_table(bios, ver, hdr, cnt, len, &snr, &ssz); | 66 | u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz); |
| 66 | if (rammap && idx < *cnt) { | 67 | if (rammap && idx < *cnt) { |
| 67 | rammap = rammap + *hdr + (idx * (*len + (snr * ssz))); | 68 | rammap = rammap + *hdr + (idx * (*len + (snr * ssz))); |
| 68 | *hdr = *len; | 69 | *hdr = *len; |
| @@ -73,16 +74,100 @@ nvbios_rammap_entry(struct nouveau_bios *bios, int idx, | |||
| 73 | return 0x0000; | 74 | return 0x0000; |
| 74 | } | 75 | } |
| 75 | 76 | ||
| 76 | u16 | 77 | u32 |
| 77 | nvbios_rammap_match(struct nouveau_bios *bios, u16 khz, | 78 | nvbios_rammapEm(struct nouveau_bios *bios, u16 khz, |
| 78 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) | 79 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) |
| 79 | { | 80 | { |
| 80 | int idx = 0; | 81 | int idx = 0; |
| 81 | u32 data; | 82 | u32 data; |
| 82 | while ((data = nvbios_rammap_entry(bios, idx++, ver, hdr, cnt, len))) { | 83 | while ((data = nvbios_rammapEe(bios, idx++, ver, hdr, cnt, len))) { |
| 83 | if (khz >= nv_ro16(bios, data + 0x00) && | 84 | if (khz >= nv_ro16(bios, data + 0x00) && |
| 84 | khz <= nv_ro16(bios, data + 0x02)) | 85 | khz <= nv_ro16(bios, data + 0x02)) |
| 85 | break; | 86 | break; |
| 86 | } | 87 | } |
| 87 | return data; | 88 | return data; |
| 88 | } | 89 | } |
| 90 | |||
| 91 | u32 | ||
| 92 | nvbios_rammapEp(struct nouveau_bios *bios, u16 khz, | ||
| 93 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, | ||
| 94 | struct nvbios_ramcfg *p) | ||
| 95 | { | ||
| 96 | u32 data = nvbios_rammapEm(bios, khz, ver, hdr, cnt, len); | ||
| 97 | memset(p, 0x00, sizeof(*p)); | ||
| 98 | switch (!!data * *ver) { | ||
| 99 | case 0x11: | ||
| 100 | p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; | ||
| 101 | p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2; | ||
| 102 | p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; | ||
| 103 | p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2; | ||
| 104 | break; | ||
| 105 | default: | ||
| 106 | data = 0; | ||
| 107 | break; | ||
| 108 | } | ||
| 109 | return data; | ||
| 110 | } | ||
| 111 | |||
| 112 | u32 | ||
| 113 | nvbios_rammapSe(struct nouveau_bios *bios, u32 data, | ||
| 114 | u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, | ||
| 115 | u8 *ver, u8 *hdr) | ||
| 116 | { | ||
| 117 | if (idx < ecnt) { | ||
| 118 | data = data + ehdr + (idx * elen); | ||
| 119 | *ver = ever; | ||
| 120 | *hdr = elen; | ||
| 121 | return data; | ||
| 122 | } | ||
| 123 | return 0; | ||
| 124 | } | ||
| 125 | |||
| 126 | u32 | ||
| 127 | nvbios_rammapSp(struct nouveau_bios *bios, u32 data, | ||
| 128 | u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, | ||
| 129 | u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) | ||
| 130 | { | ||
| 131 | data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr); | ||
| 132 | switch (!!data * *ver) { | ||
| 133 | case 0x11: | ||
| 134 | p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; | ||
| 135 | p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1; | ||
| 136 | p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2; | ||
| 137 | p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3; | ||
| 138 | p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4; | ||
| 139 | p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5; | ||
| 140 | p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6; | ||
| 141 | p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7; | ||
| 142 | p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0; | ||
| 143 | p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2; | ||
| 144 | p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; | ||
| 145 | p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; | ||
| 146 | p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; | ||
| 147 | p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7; | ||
| 148 | p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; | ||
| 149 | p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4; | ||
| 150 | p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6; | ||
| 151 | p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4; | ||
| 152 | p->ramcfg_11_04 = (nv_ro08(bios, data + 0x04) & 0xff) >> 0; | ||
| 153 | p->ramcfg_11_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; | ||
| 154 | p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1; | ||
| 155 | p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2; | ||
| 156 | p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3; | ||
| 157 | p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4; | ||
| 158 | p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6; | ||
| 159 | p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7; | ||
| 160 | p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; | ||
| 161 | p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1; | ||
| 162 | p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2; | ||
| 163 | p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3; | ||
| 164 | p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; | ||
| 165 | p->ramcfg_11_08_20 = (nv_ro08(bios, data + 0x08) & 0x20) >> 5; | ||
| 166 | p->ramcfg_11_09 = (nv_ro08(bios, data + 0x09) & 0xff) >> 0; | ||
| 167 | break; | ||
| 168 | default: | ||
| 169 | data = 0; | ||
| 170 | break; | ||
| 171 | } | ||
| 172 | return data; | ||
| 173 | } | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c index 151c2d6aaee8..350d44ab2ba2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c | |||
| @@ -24,11 +24,12 @@ | |||
| 24 | 24 | ||
| 25 | #include <subdev/bios.h> | 25 | #include <subdev/bios.h> |
| 26 | #include <subdev/bios/bit.h> | 26 | #include <subdev/bios/bit.h> |
| 27 | #include <subdev/bios/ramcfg.h> | ||
| 27 | #include <subdev/bios/timing.h> | 28 | #include <subdev/bios/timing.h> |
| 28 | 29 | ||
| 29 | u16 | 30 | u16 |
| 30 | nvbios_timing_table(struct nouveau_bios *bios, | 31 | nvbios_timingTe(struct nouveau_bios *bios, |
| 31 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) | 32 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) |
| 32 | { | 33 | { |
| 33 | struct bit_entry bit_P; | 34 | struct bit_entry bit_P; |
| 34 | u16 timing = 0x0000; | 35 | u16 timing = 0x0000; |
| @@ -47,11 +48,15 @@ nvbios_timing_table(struct nouveau_bios *bios, | |||
| 47 | *hdr = nv_ro08(bios, timing + 1); | 48 | *hdr = nv_ro08(bios, timing + 1); |
| 48 | *cnt = nv_ro08(bios, timing + 2); | 49 | *cnt = nv_ro08(bios, timing + 2); |
| 49 | *len = nv_ro08(bios, timing + 3); | 50 | *len = nv_ro08(bios, timing + 3); |
| 51 | *snr = 0; | ||
| 52 | *ssz = 0; | ||
| 50 | return timing; | 53 | return timing; |
| 51 | case 0x20: | 54 | case 0x20: |
| 52 | *hdr = nv_ro08(bios, timing + 1); | 55 | *hdr = nv_ro08(bios, timing + 1); |
| 53 | *cnt = nv_ro08(bios, timing + 3); | 56 | *cnt = nv_ro08(bios, timing + 5); |
| 54 | *len = nv_ro08(bios, timing + 2); | 57 | *len = nv_ro08(bios, timing + 2); |
| 58 | *snr = nv_ro08(bios, timing + 4); | ||
| 59 | *ssz = nv_ro08(bios, timing + 3); | ||
| 55 | return timing; | 60 | return timing; |
| 56 | default: | 61 | default: |
| 57 | break; | 62 | break; |
| @@ -63,11 +68,60 @@ nvbios_timing_table(struct nouveau_bios *bios, | |||
| 63 | } | 68 | } |
| 64 | 69 | ||
| 65 | u16 | 70 | u16 |
| 66 | nvbios_timing_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) | 71 | nvbios_timingEe(struct nouveau_bios *bios, int idx, |
| 72 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) | ||
| 67 | { | 73 | { |
| 68 | u8 hdr, cnt; | 74 | u8 snr, ssz; |
| 69 | u16 timing = nvbios_timing_table(bios, ver, &hdr, &cnt, len); | 75 | u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); |
| 70 | if (timing && idx < cnt) | 76 | if (timing && idx < *cnt) { |
| 71 | return timing + hdr + (idx * *len); | 77 | timing += *hdr + idx * (*len + (snr * ssz)); |
| 78 | *hdr = *len; | ||
| 79 | *cnt = snr; | ||
| 80 | *len = ssz; | ||
| 81 | return timing; | ||
| 82 | } | ||
| 72 | return 0x0000; | 83 | return 0x0000; |
| 73 | } | 84 | } |
| 85 | |||
| 86 | u16 | ||
| 87 | nvbios_timingEp(struct nouveau_bios *bios, int idx, | ||
| 88 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, | ||
| 89 | struct nvbios_ramcfg *p) | ||
| 90 | { | ||
| 91 | u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; | ||
| 92 | switch (!!data * *ver) { | ||
| 93 | case 0x20: | ||
| 94 | p->timing[0] = nv_ro32(bios, data + 0x00); | ||
| 95 | p->timing[1] = nv_ro32(bios, data + 0x04); | ||
| 96 | p->timing[2] = nv_ro32(bios, data + 0x08); | ||
| 97 | p->timing[3] = nv_ro32(bios, data + 0x0c); | ||
| 98 | p->timing[4] = nv_ro32(bios, data + 0x10); | ||
| 99 | p->timing[5] = nv_ro32(bios, data + 0x14); | ||
| 100 | p->timing[6] = nv_ro32(bios, data + 0x18); | ||
| 101 | p->timing[7] = nv_ro32(bios, data + 0x1c); | ||
| 102 | p->timing[8] = nv_ro32(bios, data + 0x20); | ||
| 103 | p->timing[9] = nv_ro32(bios, data + 0x24); | ||
| 104 | p->timing[10] = nv_ro32(bios, data + 0x28); | ||
| 105 | p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0; | ||
| 106 | p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4; | ||
| 107 | p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6; | ||
| 108 | p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0; | ||
| 109 | temp = nv_ro16(bios, data + 0x2c); | ||
| 110 | p->timing_20_2c_003f = (temp & 0x003f) >> 0; | ||
| 111 | p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6; | ||
| 112 | p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0; | ||
| 113 | p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3; | ||
| 114 | temp = nv_ro16(bios, data + 0x31); | ||
| 115 | p->timing_20_31_0007 = (temp & 0x0007) >> 0; | ||
| 116 | p->timing_20_31_0078 = (temp & 0x0078) >> 3; | ||
| 117 | p->timing_20_31_0780 = (temp & 0x0780) >> 7; | ||
| 118 | p->timing_20_31_0800 = (temp & 0x0800) >> 11; | ||
| 119 | p->timing_20_31_7000 = (temp & 0x7000) >> 12; | ||
| 120 | p->timing_20_31_8000 = (temp & 0x8000) >> 15; | ||
| 121 | break; | ||
| 122 | default: | ||
| 123 | data = 0; | ||
| 124 | break; | ||
| 125 | } | ||
| 126 | return data; | ||
| 127 | } | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c index e2938a21b06f..dd62baead39c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c | |||
| @@ -182,9 +182,12 @@ nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei) | |||
| 182 | clk->pstate = pstatei; | 182 | clk->pstate = pstatei; |
| 183 | 183 | ||
| 184 | if (pfb->ram->calc) { | 184 | if (pfb->ram->calc) { |
| 185 | ret = pfb->ram->calc(pfb, pstate->base.domain[nv_clk_src_mem]); | 185 | int khz = pstate->base.domain[nv_clk_src_mem]; |
| 186 | if (ret == 0) | 186 | do { |
| 187 | ret = pfb->ram->prog(pfb); | 187 | ret = pfb->ram->calc(pfb, khz); |
| 188 | if (ret == 0) | ||
| 189 | ret = pfb->ram->prog(pfb); | ||
| 190 | } while (ret > 0); | ||
| 188 | pfb->ram->tidy(pfb); | 191 | pfb->ram->tidy(pfb); |
| 189 | } | 192 | } |
| 190 | 193 | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c index 30c1f3a4158e..b74db6cfc4e2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | #include <subdev/bios.h> | 25 | #include <subdev/bios.h> |
| 26 | #include <subdev/bios/pll.h> | 26 | #include <subdev/bios/pll.h> |
| 27 | #include <subdev/clock.h> | 27 | #include <subdev/clock.h> |
| 28 | #include <subdev/devinit/priv.h> | 28 | #include <subdev/devinit/nv04.h> |
| 29 | 29 | ||
| 30 | #include "pll.h" | 30 | #include "pll.h" |
| 31 | 31 | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c index 4c62e84b96f5..d3c37c96f0e7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c | |||
| @@ -457,7 +457,7 @@ nve0_domain[] = { | |||
| 457 | { nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 }, | 457 | { nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 }, |
| 458 | { nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE }, | 458 | { nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE }, |
| 459 | { nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE }, | 459 | { nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE }, |
| 460 | { nv_clk_src_mem , 0x03, 0, "memory", 1000 }, | 460 | { nv_clk_src_mem , 0x03, 0, "memory", 500 }, |
| 461 | { nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE }, | 461 | { nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE }, |
| 462 | { nv_clk_src_hubk01 , 0x05 }, | 462 | { nv_clk_src_hubk01 , 0x05 }, |
| 463 | { nv_clk_src_vdec , 0x06 }, | 463 | { nv_clk_src_vdec , 0x06 }, |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c index 79c81d3d9bac..8fa34e8152c2 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c | |||
| @@ -24,9 +24,11 @@ | |||
| 24 | 24 | ||
| 25 | #include <core/option.h> | 25 | #include <core/option.h> |
| 26 | 26 | ||
| 27 | #include <subdev/devinit.h> | ||
| 28 | #include <subdev/bios.h> | 27 | #include <subdev/bios.h> |
| 29 | #include <subdev/bios/init.h> | 28 | #include <subdev/bios/init.h> |
| 29 | #include <subdev/vga.h> | ||
| 30 | |||
| 31 | #include "priv.h" | ||
| 30 | 32 | ||
| 31 | int | 33 | int |
| 32 | _nouveau_devinit_fini(struct nouveau_object *object, bool suspend) | 34 | _nouveau_devinit_fini(struct nouveau_object *object, bool suspend) |
| @@ -37,18 +39,41 @@ _nouveau_devinit_fini(struct nouveau_object *object, bool suspend) | |||
| 37 | if (suspend) | 39 | if (suspend) |
| 38 | devinit->post = true; | 40 | devinit->post = true; |
| 39 | 41 | ||
| 42 | /* unlock the extended vga crtc regs */ | ||
| 43 | nv_lockvgac(devinit, false); | ||
| 44 | |||
| 40 | return nouveau_subdev_fini(&devinit->base, suspend); | 45 | return nouveau_subdev_fini(&devinit->base, suspend); |
| 41 | } | 46 | } |
| 42 | 47 | ||
| 43 | int | 48 | int |
| 44 | _nouveau_devinit_init(struct nouveau_object *object) | 49 | _nouveau_devinit_init(struct nouveau_object *object) |
| 45 | { | 50 | { |
| 51 | struct nouveau_devinit_impl *impl = (void *)object->oclass; | ||
| 46 | struct nouveau_devinit *devinit = (void *)object; | 52 | struct nouveau_devinit *devinit = (void *)object; |
| 47 | int ret = nouveau_subdev_init(&devinit->base); | 53 | int ret; |
| 54 | |||
| 55 | ret = nouveau_subdev_init(&devinit->base); | ||
| 56 | if (ret) | ||
| 57 | return ret; | ||
| 58 | |||
| 59 | ret = nvbios_init(&devinit->base, devinit->post); | ||
| 48 | if (ret) | 60 | if (ret) |
| 49 | return ret; | 61 | return ret; |
| 50 | 62 | ||
| 51 | return nvbios_init(&devinit->base, devinit->post); | 63 | if (impl->disable) |
| 64 | nv_device(devinit)->disable_mask |= impl->disable(devinit); | ||
| 65 | return 0; | ||
| 66 | } | ||
| 67 | |||
| 68 | void | ||
| 69 | _nouveau_devinit_dtor(struct nouveau_object *object) | ||
| 70 | { | ||
| 71 | struct nouveau_devinit *devinit = (void *)object; | ||
| 72 | |||
| 73 | /* lock crtc regs */ | ||
| 74 | nv_lockvgac(devinit, true); | ||
| 75 | |||
| 76 | nouveau_subdev_destroy(&devinit->base); | ||
| 52 | } | 77 | } |
| 53 | 78 | ||
| 54 | int | 79 | int |
| @@ -57,6 +82,7 @@ nouveau_devinit_create_(struct nouveau_object *parent, | |||
| 57 | struct nouveau_oclass *oclass, | 82 | struct nouveau_oclass *oclass, |
| 58 | int size, void **pobject) | 83 | int size, void **pobject) |
| 59 | { | 84 | { |
| 85 | struct nouveau_devinit_impl *impl = (void *)oclass; | ||
| 60 | struct nouveau_device *device = nv_device(parent); | 86 | struct nouveau_device *device = nv_device(parent); |
| 61 | struct nouveau_devinit *devinit; | 87 | struct nouveau_devinit *devinit; |
| 62 | int ret; | 88 | int ret; |
| @@ -68,5 +94,7 @@ nouveau_devinit_create_(struct nouveau_object *parent, | |||
| 68 | return ret; | 94 | return ret; |
| 69 | 95 | ||
| 70 | devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false); | 96 | devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false); |
| 97 | devinit->meminit = impl->meminit; | ||
| 98 | devinit->pll_set = impl->pll_set; | ||
| 71 | return 0; | 99 | return 0; |
| 72 | } | 100 | } |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c index 27c8235f1a85..7037eae46e44 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c | |||
| @@ -27,12 +27,7 @@ | |||
| 27 | #include <subdev/vga.h> | 27 | #include <subdev/vga.h> |
| 28 | 28 | ||
| 29 | #include "fbmem.h" | 29 | #include "fbmem.h" |
| 30 | #include "priv.h" | 30 | #include "nv04.h" |
| 31 | |||
| 32 | struct nv04_devinit_priv { | ||
| 33 | struct nouveau_devinit base; | ||
| 34 | int owner; | ||
| 35 | }; | ||
| 36 | 31 | ||
| 37 | static void | 32 | static void |
| 38 | nv04_devinit_meminit(struct nouveau_devinit *devinit) | 33 | nv04_devinit_meminit(struct nouveau_devinit *devinit) |
| @@ -393,17 +388,21 @@ int | |||
| 393 | nv04_devinit_fini(struct nouveau_object *object, bool suspend) | 388 | nv04_devinit_fini(struct nouveau_object *object, bool suspend) |
| 394 | { | 389 | { |
| 395 | struct nv04_devinit_priv *priv = (void *)object; | 390 | struct nv04_devinit_priv *priv = (void *)object; |
| 391 | int ret; | ||
| 396 | 392 | ||
| 397 | /* make i2c busses accessible */ | 393 | /* make i2c busses accessible */ |
| 398 | nv_mask(priv, 0x000200, 0x00000001, 0x00000001); | 394 | nv_mask(priv, 0x000200, 0x00000001, 0x00000001); |
| 399 | 395 | ||
| 400 | /* unlock extended vga crtc regs, and unslave crtcs */ | 396 | ret = nouveau_devinit_fini(&priv->base, suspend); |
| 401 | nv_lockvgac(priv, false); | 397 | if (ret) |
| 398 | return ret; | ||
| 399 | |||
| 400 | /* unslave crtcs */ | ||
| 402 | if (priv->owner < 0) | 401 | if (priv->owner < 0) |
| 403 | priv->owner = nv_rdvgaowner(priv); | 402 | priv->owner = nv_rdvgaowner(priv); |
| 404 | nv_wrvgaowner(priv, 0); | 403 | nv_wrvgaowner(priv, 0); |
| 405 | 404 | ||
| 406 | return nouveau_devinit_fini(&priv->base, suspend); | 405 | return 0; |
| 407 | } | 406 | } |
| 408 | 407 | ||
| 409 | int | 408 | int |
| @@ -431,14 +430,13 @@ nv04_devinit_dtor(struct nouveau_object *object) | |||
| 431 | { | 430 | { |
| 432 | struct nv04_devinit_priv *priv = (void *)object; | 431 | struct nv04_devinit_priv *priv = (void *)object; |
| 433 | 432 | ||
| 434 | /* restore vga owner saved at first init, and lock crtc regs */ | 433 | /* restore vga owner saved at first init */ |
| 435 | nv_wrvgaowner(priv, priv->owner); | 434 | nv_wrvgaowner(priv, priv->owner); |
| 436 | nv_lockvgac(priv, true); | ||
| 437 | 435 | ||
| 438 | nouveau_devinit_destroy(&priv->base); | 436 | nouveau_devinit_destroy(&priv->base); |
| 439 | } | 437 | } |
| 440 | 438 | ||
| 441 | static int | 439 | int |
| 442 | nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 440 | nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 443 | struct nouveau_oclass *oclass, void *data, u32 size, | 441 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 444 | struct nouveau_object **pobject) | 442 | struct nouveau_object **pobject) |
| @@ -451,19 +449,19 @@ nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 451 | if (ret) | 449 | if (ret) |
| 452 | return ret; | 450 | return ret; |
| 453 | 451 | ||
| 454 | priv->base.meminit = nv04_devinit_meminit; | ||
| 455 | priv->base.pll_set = nv04_devinit_pll_set; | ||
| 456 | priv->owner = -1; | 452 | priv->owner = -1; |
| 457 | return 0; | 453 | return 0; |
| 458 | } | 454 | } |
| 459 | 455 | ||
| 460 | struct nouveau_oclass | 456 | struct nouveau_oclass * |
| 461 | nv04_devinit_oclass = { | 457 | nv04_devinit_oclass = &(struct nouveau_devinit_impl) { |
| 462 | .handle = NV_SUBDEV(DEVINIT, 0x04), | 458 | .base.handle = NV_SUBDEV(DEVINIT, 0x04), |
| 463 | .ofuncs = &(struct nouveau_ofuncs) { | 459 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 464 | .ctor = nv04_devinit_ctor, | 460 | .ctor = nv04_devinit_ctor, |
| 465 | .dtor = nv04_devinit_dtor, | 461 | .dtor = nv04_devinit_dtor, |
| 466 | .init = nv04_devinit_init, | 462 | .init = nv04_devinit_init, |
| 467 | .fini = nv04_devinit_fini, | 463 | .fini = nv04_devinit_fini, |
| 468 | }, | 464 | }, |
| 469 | }; | 465 | .meminit = nv04_devinit_meminit, |
| 466 | .pll_set = nv04_devinit_pll_set, | ||
| 467 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h new file mode 100644 index 000000000000..23470a57510c --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __NVKM_DEVINIT_NV04_H__ | ||
| 2 | #define __NVKM_DEVINIT_NV04_H__ | ||
| 3 | |||
| 4 | #include "priv.h" | ||
| 5 | |||
| 6 | struct nv04_devinit_priv { | ||
| 7 | struct nouveau_devinit base; | ||
| 8 | u8 owner; | ||
| 9 | }; | ||
| 10 | |||
| 11 | int nv04_devinit_ctor(struct nouveau_object *, struct nouveau_object *, | ||
| 12 | struct nouveau_oclass *, void *, u32, | ||
| 13 | struct nouveau_object **); | ||
| 14 | void nv04_devinit_dtor(struct nouveau_object *); | ||
| 15 | int nv04_devinit_init(struct nouveau_object *); | ||
| 16 | int nv04_devinit_fini(struct nouveau_object *, bool); | ||
| 17 | int nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32); | ||
| 18 | |||
| 19 | void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); | ||
| 20 | void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); | ||
| 21 | void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); | ||
| 22 | |||
| 23 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c index b1912a8a8942..98b7e6780dc7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c | |||
| @@ -29,12 +29,7 @@ | |||
| 29 | #include <subdev/vga.h> | 29 | #include <subdev/vga.h> |
| 30 | 30 | ||
| 31 | #include "fbmem.h" | 31 | #include "fbmem.h" |
| 32 | #include "priv.h" | 32 | #include "nv04.h" |
| 33 | |||
| 34 | struct nv05_devinit_priv { | ||
| 35 | struct nouveau_devinit base; | ||
| 36 | u8 owner; | ||
| 37 | }; | ||
| 38 | 33 | ||
| 39 | static void | 34 | static void |
| 40 | nv05_devinit_meminit(struct nouveau_devinit *devinit) | 35 | nv05_devinit_meminit(struct nouveau_devinit *devinit) |
| @@ -49,7 +44,7 @@ nv05_devinit_meminit(struct nouveau_devinit *devinit) | |||
| 49 | { 0x06, 0x00 }, | 44 | { 0x06, 0x00 }, |
| 50 | { 0x00, 0x00 } | 45 | { 0x00, 0x00 } |
| 51 | }; | 46 | }; |
| 52 | struct nv05_devinit_priv *priv = (void *)devinit; | 47 | struct nv04_devinit_priv *priv = (void *)devinit; |
| 53 | struct nouveau_bios *bios = nouveau_bios(priv); | 48 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 54 | struct io_mapping *fb; | 49 | struct io_mapping *fb; |
| 55 | u32 patt = 0xdeadbeef; | 50 | u32 patt = 0xdeadbeef; |
| @@ -130,31 +125,15 @@ out: | |||
| 130 | fbmem_fini(fb); | 125 | fbmem_fini(fb); |
| 131 | } | 126 | } |
| 132 | 127 | ||
| 133 | static int | 128 | struct nouveau_oclass * |
| 134 | nv05_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 129 | nv05_devinit_oclass = &(struct nouveau_devinit_impl) { |
| 135 | struct nouveau_oclass *oclass, void *data, u32 size, | 130 | .base.handle = NV_SUBDEV(DEVINIT, 0x05), |
| 136 | struct nouveau_object **pobject) | 131 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 137 | { | 132 | .ctor = nv04_devinit_ctor, |
| 138 | struct nv05_devinit_priv *priv; | ||
| 139 | int ret; | ||
| 140 | |||
| 141 | ret = nouveau_devinit_create(parent, engine, oclass, &priv); | ||
| 142 | *pobject = nv_object(priv); | ||
| 143 | if (ret) | ||
| 144 | return ret; | ||
| 145 | |||
| 146 | priv->base.meminit = nv05_devinit_meminit; | ||
| 147 | priv->base.pll_set = nv04_devinit_pll_set; | ||
| 148 | return 0; | ||
| 149 | } | ||
| 150 | |||
| 151 | struct nouveau_oclass | ||
| 152 | nv05_devinit_oclass = { | ||
| 153 | .handle = NV_SUBDEV(DEVINIT, 0x05), | ||
| 154 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 155 | .ctor = nv05_devinit_ctor, | ||
| 156 | .dtor = nv04_devinit_dtor, | 133 | .dtor = nv04_devinit_dtor, |
| 157 | .init = nv04_devinit_init, | 134 | .init = nv04_devinit_init, |
| 158 | .fini = nv04_devinit_fini, | 135 | .fini = nv04_devinit_fini, |
| 159 | }, | 136 | }, |
| 160 | }; | 137 | .meminit = nv05_devinit_meminit, |
| 138 | .pll_set = nv04_devinit_pll_set, | ||
| 139 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c index 8d274dba1ef1..32b3d2131a7f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c | |||
| @@ -27,17 +27,12 @@ | |||
| 27 | #include <subdev/vga.h> | 27 | #include <subdev/vga.h> |
| 28 | 28 | ||
| 29 | #include "fbmem.h" | 29 | #include "fbmem.h" |
| 30 | #include "priv.h" | 30 | #include "nv04.h" |
| 31 | |||
| 32 | struct nv10_devinit_priv { | ||
| 33 | struct nouveau_devinit base; | ||
| 34 | u8 owner; | ||
| 35 | }; | ||
| 36 | 31 | ||
| 37 | static void | 32 | static void |
| 38 | nv10_devinit_meminit(struct nouveau_devinit *devinit) | 33 | nv10_devinit_meminit(struct nouveau_devinit *devinit) |
| 39 | { | 34 | { |
| 40 | struct nv10_devinit_priv *priv = (void *)devinit; | 35 | struct nv04_devinit_priv *priv = (void *)devinit; |
| 41 | static const int mem_width[] = { 0x10, 0x00, 0x20 }; | 36 | static const int mem_width[] = { 0x10, 0x00, 0x20 }; |
| 42 | int mem_width_count; | 37 | int mem_width_count; |
| 43 | uint32_t patt = 0xdeadbeef; | 38 | uint32_t patt = 0xdeadbeef; |
| @@ -101,31 +96,15 @@ amount_found: | |||
| 101 | fbmem_fini(fb); | 96 | fbmem_fini(fb); |
| 102 | } | 97 | } |
| 103 | 98 | ||
| 104 | static int | 99 | struct nouveau_oclass * |
| 105 | nv10_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 100 | nv10_devinit_oclass = &(struct nouveau_devinit_impl) { |
| 106 | struct nouveau_oclass *oclass, void *data, u32 size, | 101 | .base.handle = NV_SUBDEV(DEVINIT, 0x10), |
| 107 | struct nouveau_object **pobject) | 102 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 108 | { | 103 | .ctor = nv04_devinit_ctor, |
| 109 | struct nv10_devinit_priv *priv; | ||
| 110 | int ret; | ||
| 111 | |||
| 112 | ret = nouveau_devinit_create(parent, engine, oclass, &priv); | ||
| 113 | *pobject = nv_object(priv); | ||
| 114 | if (ret) | ||
| 115 | return ret; | ||
| 116 | |||
| 117 | priv->base.meminit = nv10_devinit_meminit; | ||
| 118 | priv->base.pll_set = nv04_devinit_pll_set; | ||
| 119 | return 0; | ||
| 120 | } | ||
| 121 | |||
| 122 | struct nouveau_oclass | ||
| 123 | nv10_devinit_oclass = { | ||
| 124 | .handle = NV_SUBDEV(DEVINIT, 0x10), | ||
| 125 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 126 | .ctor = nv10_devinit_ctor, | ||
| 127 | .dtor = nv04_devinit_dtor, | 104 | .dtor = nv04_devinit_dtor, |
| 128 | .init = nv04_devinit_init, | 105 | .init = nv04_devinit_init, |
| 129 | .fini = nv04_devinit_fini, | 106 | .fini = nv04_devinit_fini, |
| 130 | }, | 107 | }, |
| 131 | }; | 108 | .meminit = nv10_devinit_meminit, |
| 109 | .pll_set = nv04_devinit_pll_set, | ||
| 110 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c index e9743cdabe75..526d0c6faacd 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c | |||
| @@ -22,37 +22,16 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include "priv.h" | 25 | #include "nv04.h" |
| 26 | 26 | ||
| 27 | struct nv1a_devinit_priv { | 27 | struct nouveau_oclass * |
| 28 | struct nouveau_devinit base; | 28 | nv1a_devinit_oclass = &(struct nouveau_devinit_impl) { |
| 29 | u8 owner; | 29 | .base.handle = NV_SUBDEV(DEVINIT, 0x1a), |
| 30 | }; | 30 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 31 | 31 | .ctor = nv04_devinit_ctor, | |
| 32 | static int | ||
| 33 | nv1a_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | ||
| 34 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
| 35 | struct nouveau_object **pobject) | ||
| 36 | { | ||
| 37 | struct nv1a_devinit_priv *priv; | ||
| 38 | int ret; | ||
| 39 | |||
| 40 | ret = nouveau_devinit_create(parent, engine, oclass, &priv); | ||
| 41 | *pobject = nv_object(priv); | ||
| 42 | if (ret) | ||
| 43 | return ret; | ||
| 44 | |||
| 45 | priv->base.pll_set = nv04_devinit_pll_set; | ||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | |||
| 49 | struct nouveau_oclass | ||
| 50 | nv1a_devinit_oclass = { | ||
| 51 | .handle = NV_SUBDEV(DEVINIT, 0x1a), | ||
| 52 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 53 | .ctor = nv1a_devinit_ctor, | ||
| 54 | .dtor = nv04_devinit_dtor, | 32 | .dtor = nv04_devinit_dtor, |
| 55 | .init = nv04_devinit_init, | 33 | .init = nv04_devinit_init, |
| 56 | .fini = nv04_devinit_fini, | 34 | .fini = nv04_devinit_fini, |
| 57 | }, | 35 | }, |
| 58 | }; | 36 | .pll_set = nv04_devinit_pll_set, |
| 37 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c index 6cc6080d3bc0..4689ba303b0b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c | |||
| @@ -24,18 +24,13 @@ | |||
| 24 | * | 24 | * |
| 25 | */ | 25 | */ |
| 26 | 26 | ||
| 27 | #include "priv.h" | 27 | #include "nv04.h" |
| 28 | #include "fbmem.h" | 28 | #include "fbmem.h" |
| 29 | 29 | ||
| 30 | struct nv20_devinit_priv { | ||
| 31 | struct nouveau_devinit base; | ||
| 32 | u8 owner; | ||
| 33 | }; | ||
| 34 | |||
| 35 | static void | 30 | static void |
| 36 | nv20_devinit_meminit(struct nouveau_devinit *devinit) | 31 | nv20_devinit_meminit(struct nouveau_devinit *devinit) |
| 37 | { | 32 | { |
| 38 | struct nv20_devinit_priv *priv = (void *)devinit; | 33 | struct nv04_devinit_priv *priv = (void *)devinit; |
| 39 | struct nouveau_device *device = nv_device(priv); | 34 | struct nouveau_device *device = nv_device(priv); |
| 40 | uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900); | 35 | uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900); |
| 41 | uint32_t amount, off; | 36 | uint32_t amount, off; |
| @@ -65,31 +60,15 @@ nv20_devinit_meminit(struct nouveau_devinit *devinit) | |||
| 65 | fbmem_fini(fb); | 60 | fbmem_fini(fb); |
| 66 | } | 61 | } |
| 67 | 62 | ||
| 68 | static int | 63 | struct nouveau_oclass * |
| 69 | nv20_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 64 | nv20_devinit_oclass = &(struct nouveau_devinit_impl) { |
| 70 | struct nouveau_oclass *oclass, void *data, u32 size, | 65 | .base.handle = NV_SUBDEV(DEVINIT, 0x20), |
| 71 | struct nouveau_object **pobject) | 66 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 72 | { | 67 | .ctor = nv04_devinit_ctor, |
| 73 | struct nv20_devinit_priv *priv; | ||
| 74 | int ret; | ||
| 75 | |||
| 76 | ret = nouveau_devinit_create(parent, engine, oclass, &priv); | ||
| 77 | *pobject = nv_object(priv); | ||
| 78 | if (ret) | ||
| 79 | return ret; | ||
| 80 | |||
| 81 | priv->base.meminit = nv20_devinit_meminit; | ||
| 82 | priv->base.pll_set = nv04_devinit_pll_set; | ||
| 83 | return 0; | ||
| 84 | } | ||
| 85 | |||
| 86 | struct nouveau_oclass | ||
| 87 | nv20_devinit_oclass = { | ||
| 88 | .handle = NV_SUBDEV(DEVINIT, 0x20), | ||
| 89 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 90 | .ctor = nv20_devinit_ctor, | ||
| 91 | .dtor = nv04_devinit_dtor, | 68 | .dtor = nv04_devinit_dtor, |
| 92 | .init = nv04_devinit_init, | 69 | .init = nv04_devinit_init, |
| 93 | .fini = nv04_devinit_fini, | 70 | .fini = nv04_devinit_fini, |
| 94 | }, | 71 | }, |
| 95 | }; | 72 | .meminit = nv20_devinit_meminit, |
| 73 | .pll_set = nv04_devinit_pll_set, | ||
| 74 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c index 6df72247c477..b46c62a1d5d8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #include <subdev/bios/init.h> | 28 | #include <subdev/bios/init.h> |
| 29 | #include <subdev/vga.h> | 29 | #include <subdev/vga.h> |
| 30 | 30 | ||
| 31 | #include "priv.h" | 31 | #include "nv50.h" |
| 32 | 32 | ||
| 33 | static int | 33 | int |
| 34 | nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) | 34 | nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) |
| 35 | { | 35 | { |
| 36 | struct nv50_devinit_priv *priv = (void *)devinit; | 36 | struct nv50_devinit_priv *priv = (void *)devinit; |
| @@ -74,6 +74,19 @@ nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) | |||
| 74 | return 0; | 74 | return 0; |
| 75 | } | 75 | } |
| 76 | 76 | ||
| 77 | static u64 | ||
| 78 | nv50_devinit_disable(struct nouveau_devinit *devinit) | ||
| 79 | { | ||
| 80 | struct nv50_devinit_priv *priv = (void *)devinit; | ||
| 81 | u32 r001540 = nv_rd32(priv, 0x001540); | ||
| 82 | u64 disable = 0ULL; | ||
| 83 | |||
| 84 | if (!(r001540 & 0x40000000)) | ||
| 85 | disable |= (1ULL << NVDEV_ENGINE_MPEG); | ||
| 86 | |||
| 87 | return disable; | ||
| 88 | } | ||
| 89 | |||
| 77 | int | 90 | int |
| 78 | nv50_devinit_init(struct nouveau_object *object) | 91 | nv50_devinit_init(struct nouveau_object *object) |
| 79 | { | 92 | { |
| @@ -120,7 +133,7 @@ nv50_devinit_init(struct nouveau_object *object) | |||
| 120 | return 0; | 133 | return 0; |
| 121 | } | 134 | } |
| 122 | 135 | ||
| 123 | static int | 136 | int |
| 124 | nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 137 | nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 125 | struct nouveau_oclass *oclass, void *data, u32 size, | 138 | struct nouveau_oclass *oclass, void *data, u32 size, |
| 126 | struct nouveau_object **pobject) | 139 | struct nouveau_object **pobject) |
| @@ -133,17 +146,18 @@ nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 133 | if (ret) | 146 | if (ret) |
| 134 | return ret; | 147 | return ret; |
| 135 | 148 | ||
| 136 | priv->base.pll_set = nv50_devinit_pll_set; | ||
| 137 | return 0; | 149 | return 0; |
| 138 | } | 150 | } |
| 139 | 151 | ||
| 140 | struct nouveau_oclass | 152 | struct nouveau_oclass * |
| 141 | nv50_devinit_oclass = { | 153 | nv50_devinit_oclass = &(struct nouveau_devinit_impl) { |
| 142 | .handle = NV_SUBDEV(DEVINIT, 0x50), | 154 | .base.handle = NV_SUBDEV(DEVINIT, 0x50), |
| 143 | .ofuncs = &(struct nouveau_ofuncs) { | 155 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 144 | .ctor = nv50_devinit_ctor, | 156 | .ctor = nv50_devinit_ctor, |
| 145 | .dtor = _nouveau_devinit_dtor, | 157 | .dtor = _nouveau_devinit_dtor, |
| 146 | .init = nv50_devinit_init, | 158 | .init = nv50_devinit_init, |
| 147 | .fini = _nouveau_devinit_fini, | 159 | .fini = _nouveau_devinit_fini, |
| 148 | }, | 160 | }, |
| 149 | }; | 161 | .pll_set = nv50_devinit_pll_set, |
| 162 | .disable = nv50_devinit_disable, | ||
| 163 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h new file mode 100644 index 000000000000..141c27e9f182 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | #ifndef __NVKM_DEVINIT_NV50_H__ | ||
| 2 | #define __NVKM_DEVINIT_NV50_H__ | ||
| 3 | |||
| 4 | #include "priv.h" | ||
| 5 | |||
| 6 | struct nv50_devinit_priv { | ||
| 7 | struct nouveau_devinit base; | ||
| 8 | }; | ||
| 9 | |||
| 10 | int nv50_devinit_ctor(struct nouveau_object *, struct nouveau_object *, | ||
| 11 | struct nouveau_oclass *, void *, u32, | ||
| 12 | struct nouveau_object **); | ||
| 13 | int nv50_devinit_init(struct nouveau_object *); | ||
| 14 | int nv50_devinit_pll_set(struct nouveau_devinit *, u32, u32); | ||
| 15 | |||
| 16 | int nva3_devinit_pll_set(struct nouveau_devinit *, u32, u32); | ||
| 17 | |||
| 18 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c new file mode 100644 index 000000000000..787422505d87 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include "nv50.h" | ||
| 26 | |||
| 27 | static u64 | ||
| 28 | nv84_devinit_disable(struct nouveau_devinit *devinit) | ||
| 29 | { | ||
| 30 | struct nv50_devinit_priv *priv = (void *)devinit; | ||
| 31 | u32 r001540 = nv_rd32(priv, 0x001540); | ||
| 32 | u32 r00154c = nv_rd32(priv, 0x00154c); | ||
| 33 | u64 disable = 0ULL; | ||
| 34 | |||
| 35 | if (!(r001540 & 0x40000000)) { | ||
| 36 | disable |= (1ULL << NVDEV_ENGINE_MPEG); | ||
| 37 | disable |= (1ULL << NVDEV_ENGINE_VP); | ||
| 38 | disable |= (1ULL << NVDEV_ENGINE_BSP); | ||
| 39 | disable |= (1ULL << NVDEV_ENGINE_CRYPT); | ||
| 40 | } | ||
| 41 | |||
| 42 | if (!(r00154c & 0x00000004)) | ||
| 43 | disable |= (1ULL << NVDEV_ENGINE_DISP); | ||
| 44 | if (!(r00154c & 0x00000020)) | ||
| 45 | disable |= (1ULL << NVDEV_ENGINE_BSP); | ||
| 46 | if (!(r00154c & 0x00000040)) | ||
| 47 | disable |= (1ULL << NVDEV_ENGINE_CRYPT); | ||
| 48 | |||
| 49 | return disable; | ||
| 50 | } | ||
| 51 | |||
| 52 | struct nouveau_oclass * | ||
| 53 | nv84_devinit_oclass = &(struct nouveau_devinit_impl) { | ||
| 54 | .base.handle = NV_SUBDEV(DEVINIT, 0x84), | ||
| 55 | .base.ofuncs = &(struct nouveau_ofuncs) { | ||
| 56 | .ctor = nv50_devinit_ctor, | ||
| 57 | .dtor = _nouveau_devinit_dtor, | ||
| 58 | .init = nv50_devinit_init, | ||
| 59 | .fini = _nouveau_devinit_fini, | ||
| 60 | }, | ||
| 61 | .pll_set = nv50_devinit_pll_set, | ||
| 62 | .disable = nv84_devinit_disable, | ||
| 63 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c new file mode 100644 index 000000000000..2b0e963fc6f0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include "nv50.h" | ||
| 26 | |||
| 27 | static u64 | ||
| 28 | nv98_devinit_disable(struct nouveau_devinit *devinit) | ||
| 29 | { | ||
| 30 | struct nv50_devinit_priv *priv = (void *)devinit; | ||
| 31 | u32 r001540 = nv_rd32(priv, 0x001540); | ||
| 32 | u32 r00154c = nv_rd32(priv, 0x00154c); | ||
| 33 | u64 disable = 0ULL; | ||
| 34 | |||
| 35 | if (!(r001540 & 0x40000000)) { | ||
| 36 | disable |= (1ULL << NVDEV_ENGINE_VP); | ||
| 37 | disable |= (1ULL << NVDEV_ENGINE_BSP); | ||
| 38 | disable |= (1ULL << NVDEV_ENGINE_PPP); | ||
| 39 | } | ||
| 40 | |||
| 41 | if (!(r00154c & 0x00000004)) | ||
| 42 | disable |= (1ULL << NVDEV_ENGINE_DISP); | ||
| 43 | if (!(r00154c & 0x00000020)) | ||
| 44 | disable |= (1ULL << NVDEV_ENGINE_BSP); | ||
| 45 | if (!(r00154c & 0x00000040)) | ||
| 46 | disable |= (1ULL << NVDEV_ENGINE_CRYPT); | ||
| 47 | |||
| 48 | return disable; | ||
| 49 | } | ||
| 50 | |||
| 51 | struct nouveau_oclass * | ||
| 52 | nv98_devinit_oclass = &(struct nouveau_devinit_impl) { | ||
| 53 | .base.handle = NV_SUBDEV(DEVINIT, 0x98), | ||
| 54 | .base.ofuncs = &(struct nouveau_ofuncs) { | ||
| 55 | .ctor = nv50_devinit_ctor, | ||
| 56 | .dtor = _nouveau_devinit_dtor, | ||
| 57 | .init = nv50_devinit_init, | ||
| 58 | .fini = _nouveau_devinit_fini, | ||
| 59 | }, | ||
| 60 | .pll_set = nv50_devinit_pll_set, | ||
| 61 | .disable = nv98_devinit_disable, | ||
| 62 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c index 76a68b290141..6dedf1dad7f7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c | |||
| @@ -22,12 +22,12 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include "priv.h" | 25 | #include "nv50.h" |
| 26 | 26 | ||
| 27 | static int | 27 | int |
| 28 | nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) | 28 | nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) |
| 29 | { | 29 | { |
| 30 | struct nva3_devinit_priv *priv = (void *)devinit; | 30 | struct nv50_devinit_priv *priv = (void *)devinit; |
| 31 | struct nouveau_bios *bios = nouveau_bios(priv); | 31 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 32 | struct nvbios_pll info; | 32 | struct nvbios_pll info; |
| 33 | int N, fN, M, P; | 33 | int N, fN, M, P; |
| @@ -58,30 +58,38 @@ nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) | |||
| 58 | return ret; | 58 | return ret; |
| 59 | } | 59 | } |
| 60 | 60 | ||
| 61 | static int | 61 | static u64 |
| 62 | nva3_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 62 | nva3_devinit_disable(struct nouveau_devinit *devinit) |
| 63 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
| 64 | struct nouveau_object **pobject) | ||
| 65 | { | 63 | { |
| 66 | struct nv50_devinit_priv *priv; | 64 | struct nv50_devinit_priv *priv = (void *)devinit; |
| 67 | int ret; | 65 | u32 r001540 = nv_rd32(priv, 0x001540); |
| 66 | u32 r00154c = nv_rd32(priv, 0x00154c); | ||
| 67 | u64 disable = 0ULL; | ||
| 68 | 68 | ||
| 69 | ret = nouveau_devinit_create(parent, engine, oclass, &priv); | 69 | if (!(r001540 & 0x40000000)) { |
| 70 | *pobject = nv_object(priv); | 70 | disable |= (1ULL << NVDEV_ENGINE_VP); |
| 71 | if (ret) | 71 | disable |= (1ULL << NVDEV_ENGINE_PPP); |
| 72 | return ret; | 72 | } |
| 73 | |||
| 74 | if (!(r00154c & 0x00000004)) | ||
| 75 | disable |= (1ULL << NVDEV_ENGINE_DISP); | ||
| 76 | if (!(r00154c & 0x00000020)) | ||
| 77 | disable |= (1ULL << NVDEV_ENGINE_BSP); | ||
| 78 | if (!(r00154c & 0x00000200)) | ||
| 79 | disable |= (1ULL << NVDEV_ENGINE_COPY0); | ||
| 73 | 80 | ||
| 74 | priv->base.pll_set = nva3_devinit_pll_set; | 81 | return disable; |
| 75 | return 0; | ||
| 76 | } | 82 | } |
| 77 | 83 | ||
| 78 | struct nouveau_oclass | 84 | struct nouveau_oclass * |
| 79 | nva3_devinit_oclass = { | 85 | nva3_devinit_oclass = &(struct nouveau_devinit_impl) { |
| 80 | .handle = NV_SUBDEV(DEVINIT, 0xa3), | 86 | .base.handle = NV_SUBDEV(DEVINIT, 0xa3), |
| 81 | .ofuncs = &(struct nouveau_ofuncs) { | 87 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 82 | .ctor = nva3_devinit_ctor, | 88 | .ctor = nv50_devinit_ctor, |
| 83 | .dtor = _nouveau_devinit_dtor, | 89 | .dtor = _nouveau_devinit_dtor, |
| 84 | .init = nv50_devinit_init, | 90 | .init = nv50_devinit_init, |
| 85 | .fini = _nouveau_devinit_fini, | 91 | .fini = _nouveau_devinit_fini, |
| 86 | }, | 92 | }, |
| 87 | }; | 93 | .pll_set = nva3_devinit_pll_set, |
| 94 | .disable = nva3_devinit_disable, | ||
| 95 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c new file mode 100644 index 000000000000..4fc68d27eff3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include "nv50.h" | ||
| 26 | |||
| 27 | static u64 | ||
| 28 | nvaf_devinit_disable(struct nouveau_devinit *devinit) | ||
| 29 | { | ||
| 30 | struct nv50_devinit_priv *priv = (void *)devinit; | ||
| 31 | u32 r001540 = nv_rd32(priv, 0x001540); | ||
| 32 | u32 r00154c = nv_rd32(priv, 0x00154c); | ||
| 33 | u64 disable = 0; | ||
| 34 | |||
| 35 | if (!(r001540 & 0x40000000)) { | ||
| 36 | disable |= (1ULL << NVDEV_ENGINE_VP); | ||
| 37 | disable |= (1ULL << NVDEV_ENGINE_PPP); | ||
| 38 | } | ||
| 39 | |||
| 40 | if (!(r00154c & 0x00000004)) | ||
| 41 | disable |= (1ULL << NVDEV_ENGINE_DISP); | ||
| 42 | if (!(r00154c & 0x00000020)) | ||
| 43 | disable |= (1ULL << NVDEV_ENGINE_BSP); | ||
| 44 | if (!(r00154c & 0x00000040)) | ||
| 45 | disable |= (1ULL << NVDEV_ENGINE_VIC); | ||
| 46 | if (!(r00154c & 0x00000200)) | ||
| 47 | disable |= (1ULL << NVDEV_ENGINE_COPY0); | ||
| 48 | |||
| 49 | return disable; | ||
| 50 | } | ||
| 51 | |||
| 52 | struct nouveau_oclass * | ||
| 53 | nvaf_devinit_oclass = &(struct nouveau_devinit_impl) { | ||
| 54 | .base.handle = NV_SUBDEV(DEVINIT, 0xaf), | ||
| 55 | .base.ofuncs = &(struct nouveau_ofuncs) { | ||
| 56 | .ctor = nv50_devinit_ctor, | ||
| 57 | .dtor = _nouveau_devinit_dtor, | ||
| 58 | .init = nv50_devinit_init, | ||
| 59 | .fini = _nouveau_devinit_fini, | ||
| 60 | }, | ||
| 61 | .pll_set = nva3_devinit_pll_set, | ||
| 62 | .disable = nvaf_devinit_disable, | ||
| 63 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c index 19e265bf4574..fa7e63766b1b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c | |||
| @@ -22,12 +22,12 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include "priv.h" | 25 | #include "nv50.h" |
| 26 | 26 | ||
| 27 | static int | 27 | static int |
| 28 | nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) | 28 | nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) |
| 29 | { | 29 | { |
| 30 | struct nvc0_devinit_priv *priv = (void *)devinit; | 30 | struct nv50_devinit_priv *priv = (void *)devinit; |
| 31 | struct nouveau_bios *bios = nouveau_bios(priv); | 31 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 32 | struct nvbios_pll info; | 32 | struct nvbios_pll info; |
| 33 | int N, fN, M, P; | 33 | int N, fN, M, P; |
| @@ -59,6 +59,33 @@ nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) | |||
| 59 | return ret; | 59 | return ret; |
| 60 | } | 60 | } |
| 61 | 61 | ||
| 62 | static u64 | ||
| 63 | nvc0_devinit_disable(struct nouveau_devinit *devinit) | ||
| 64 | { | ||
| 65 | struct nv50_devinit_priv *priv = (void *)devinit; | ||
| 66 | u32 r022500 = nv_rd32(priv, 0x022500); | ||
| 67 | u64 disable = 0ULL; | ||
| 68 | |||
| 69 | if (r022500 & 0x00000001) | ||
| 70 | disable |= (1ULL << NVDEV_ENGINE_DISP); | ||
| 71 | |||
| 72 | if (r022500 & 0x00000002) { | ||
| 73 | disable |= (1ULL << NVDEV_ENGINE_VP); | ||
| 74 | disable |= (1ULL << NVDEV_ENGINE_PPP); | ||
| 75 | } | ||
| 76 | |||
| 77 | if (r022500 & 0x00000004) | ||
| 78 | disable |= (1ULL << NVDEV_ENGINE_BSP); | ||
| 79 | if (r022500 & 0x00000008) | ||
| 80 | disable |= (1ULL << NVDEV_ENGINE_VENC); | ||
| 81 | if (r022500 & 0x00000100) | ||
| 82 | disable |= (1ULL << NVDEV_ENGINE_COPY0); | ||
| 83 | if (r022500 & 0x00000200) | ||
| 84 | disable |= (1ULL << NVDEV_ENGINE_COPY1); | ||
| 85 | |||
| 86 | return disable; | ||
| 87 | } | ||
| 88 | |||
| 62 | static int | 89 | static int |
| 63 | nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 90 | nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 64 | struct nouveau_oclass *oclass, void *data, u32 size, | 91 | struct nouveau_oclass *oclass, void *data, u32 size, |
| @@ -72,19 +99,20 @@ nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 72 | if (ret) | 99 | if (ret) |
| 73 | return ret; | 100 | return ret; |
| 74 | 101 | ||
| 75 | priv->base.pll_set = nvc0_devinit_pll_set; | ||
| 76 | if (nv_rd32(priv, 0x022500) & 0x00000001) | 102 | if (nv_rd32(priv, 0x022500) & 0x00000001) |
| 77 | priv->base.post = true; | 103 | priv->base.post = true; |
| 78 | return 0; | 104 | return 0; |
| 79 | } | 105 | } |
| 80 | 106 | ||
| 81 | struct nouveau_oclass | 107 | struct nouveau_oclass * |
| 82 | nvc0_devinit_oclass = { | 108 | nvc0_devinit_oclass = &(struct nouveau_devinit_impl) { |
| 83 | .handle = NV_SUBDEV(DEVINIT, 0xc0), | 109 | .base.handle = NV_SUBDEV(DEVINIT, 0xc0), |
| 84 | .ofuncs = &(struct nouveau_ofuncs) { | 110 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 85 | .ctor = nvc0_devinit_ctor, | 111 | .ctor = nvc0_devinit_ctor, |
| 86 | .dtor = _nouveau_devinit_dtor, | 112 | .dtor = _nouveau_devinit_dtor, |
| 87 | .init = nv50_devinit_init, | 113 | .init = nv50_devinit_init, |
| 88 | .fini = _nouveau_devinit_fini, | 114 | .fini = _nouveau_devinit_fini, |
| 89 | }, | 115 | }, |
| 90 | }; | 116 | .pll_set = nvc0_devinit_pll_set, |
| 117 | .disable = nvc0_devinit_disable, | ||
| 118 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h index 7d622e2b0171..822a2fbf44a5 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h +++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h | |||
| @@ -6,20 +6,32 @@ | |||
| 6 | #include <subdev/clock/pll.h> | 6 | #include <subdev/clock/pll.h> |
| 7 | #include <subdev/devinit.h> | 7 | #include <subdev/devinit.h> |
| 8 | 8 | ||
| 9 | void nv04_devinit_dtor(struct nouveau_object *); | 9 | struct nouveau_devinit_impl { |
| 10 | int nv04_devinit_init(struct nouveau_object *); | 10 | struct nouveau_oclass base; |
| 11 | int nv04_devinit_fini(struct nouveau_object *, bool); | 11 | void (*meminit)(struct nouveau_devinit *); |
| 12 | int nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32); | 12 | int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq); |
| 13 | 13 | u64 (*disable)(struct nouveau_devinit *); | |
| 14 | void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); | ||
| 15 | void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); | ||
| 16 | void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); | ||
| 17 | |||
| 18 | |||
| 19 | struct nv50_devinit_priv { | ||
| 20 | struct nouveau_devinit base; | ||
| 21 | }; | 14 | }; |
| 22 | 15 | ||
| 23 | int nv50_devinit_init(struct nouveau_object *); | 16 | #define nouveau_devinit_create(p,e,o,d) \ |
| 17 | nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d) | ||
| 18 | #define nouveau_devinit_destroy(p) ({ \ | ||
| 19 | struct nouveau_devinit *d = (p); \ | ||
| 20 | _nouveau_devinit_dtor(nv_object(d)); \ | ||
| 21 | }) | ||
| 22 | #define nouveau_devinit_init(p) ({ \ | ||
| 23 | struct nouveau_devinit *d = (p); \ | ||
| 24 | _nouveau_devinit_init(nv_object(d)); \ | ||
| 25 | }) | ||
| 26 | #define nouveau_devinit_fini(p,s) ({ \ | ||
| 27 | struct nouveau_devinit *d = (p); \ | ||
| 28 | _nouveau_devinit_fini(nv_object(d), (s)); \ | ||
| 29 | }) | ||
| 30 | |||
| 31 | int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 32 | struct nouveau_oclass *, int, void **); | ||
| 33 | void _nouveau_devinit_dtor(struct nouveau_object *); | ||
| 34 | int _nouveau_devinit_init(struct nouveau_object *); | ||
| 35 | int _nouveau_devinit_fini(struct nouveau_object *, bool suspend); | ||
| 24 | 36 | ||
| 25 | #endif | 37 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c index 34f9605ffee6..66fe959b4f74 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c | |||
| @@ -25,35 +25,44 @@ | |||
| 25 | #include <subdev/bios.h> | 25 | #include <subdev/bios.h> |
| 26 | #include "priv.h" | 26 | #include "priv.h" |
| 27 | 27 | ||
| 28 | /* binary driver only executes this path if the condition (a) is true | ||
| 29 | * for any configuration (combination of rammap+ramcfg+timing) that | ||
| 30 | * can be reached on a given card. for now, we will execute the branch | ||
| 31 | * unconditionally in the hope that a "false everywhere" in the bios | ||
| 32 | * tables doesn't actually mean "don't touch this". | ||
| 33 | */ | ||
| 34 | #define NOTE00(a) 1 | ||
| 35 | |||
| 28 | int | 36 | int |
| 29 | nouveau_gddr5_calc(struct nouveau_ram *ram) | 37 | nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts) |
| 30 | { | 38 | { |
| 31 | struct nouveau_bios *bios = nouveau_bios(ram); | 39 | int pd, lf, xd, vh, vr, vo, l3; |
| 32 | int pd, lf, xd, vh, vr, vo; | 40 | int WL, CL, WR, at[2], dt, ds; |
| 33 | int WL, CL, WR, at, dt, ds; | ||
| 34 | int rq = ram->freq < 1000000; /* XXX */ | 41 | int rq = ram->freq < 1000000; /* XXX */ |
| 35 | 42 | ||
| 36 | switch (!!ram->ramcfg.data * ram->ramcfg.version) { | 43 | switch (ram->ramcfg.version) { |
| 37 | case 0x11: | 44 | case 0x11: |
| 38 | pd = (nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x80) >> 7; | 45 | pd = ram->next->bios.ramcfg_11_01_80; |
| 39 | lf = (nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x40) >> 6; | 46 | lf = ram->next->bios.ramcfg_11_01_40; |
| 40 | xd = !(nv_ro08(bios, ram->ramcfg.data + 0x01) & 0x20); | 47 | xd = !ram->next->bios.ramcfg_11_01_20; |
| 41 | vh = (nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x10) >> 4; | 48 | vh = ram->next->bios.ramcfg_11_02_10; |
| 42 | vr = (nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x04) >> 2; | 49 | vr = ram->next->bios.ramcfg_11_02_04; |
| 43 | vo = nv_ro08(bios, ram->ramcfg.data + 0x06) & 0xff; | 50 | vo = ram->next->bios.ramcfg_11_06; |
| 51 | l3 = !ram->next->bios.ramcfg_11_07_02; | ||
| 44 | break; | 52 | break; |
| 45 | default: | 53 | default: |
| 46 | return -ENOSYS; | 54 | return -ENOSYS; |
| 47 | } | 55 | } |
| 48 | 56 | ||
| 49 | switch (!!ram->timing.data * ram->timing.version) { | 57 | switch (ram->timing.version) { |
| 50 | case 0x20: | 58 | case 0x20: |
| 51 | WL = (nv_ro16(bios, ram->timing.data + 0x04) & 0x0f80) >> 7; | 59 | WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; |
| 52 | CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f; | 60 | CL = (ram->next->bios.timing[1] & 0x0000001f); |
| 53 | WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f; | 61 | WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; |
| 54 | at = (nv_ro08(bios, ram->timing.data + 0x2e) & 0xc0) >> 6; | 62 | at[0] = ram->next->bios.timing_20_2e_c0; |
| 55 | dt = nv_ro08(bios, ram->timing.data + 0x2e) & 0x03; | 63 | at[1] = ram->next->bios.timing_20_2e_30; |
| 56 | ds = nv_ro08(bios, ram->timing.data + 0x2f) & 0x03; | 64 | dt = ram->next->bios.timing_20_2e_03; |
| 65 | ds = ram->next->bios.timing_20_2f_03; | ||
| 57 | break; | 66 | break; |
| 58 | default: | 67 | default: |
| 59 | return -ENOSYS; | 68 | return -ENOSYS; |
| @@ -71,13 +80,25 @@ nouveau_gddr5_calc(struct nouveau_ram *ram) | |||
| 71 | 80 | ||
| 72 | ram->mr[1] &= ~0x0bf; | 81 | ram->mr[1] &= ~0x0bf; |
| 73 | ram->mr[1] |= (xd & 0x01) << 7; | 82 | ram->mr[1] |= (xd & 0x01) << 7; |
| 74 | ram->mr[1] |= (at & 0x03) << 4; | 83 | ram->mr[1] |= (at[0] & 0x03) << 4; |
| 75 | ram->mr[1] |= (dt & 0x03) << 2; | 84 | ram->mr[1] |= (dt & 0x03) << 2; |
| 76 | ram->mr[1] |= (ds & 0x03) << 0; | 85 | ram->mr[1] |= (ds & 0x03) << 0; |
| 77 | 86 | ||
| 87 | /* this seems wrong, alternate field used for the broadcast | ||
| 88 | * on nuts vs non-nuts configs.. meh, it matches for now. | ||
| 89 | */ | ||
| 90 | ram->mr1_nuts = ram->mr[1]; | ||
| 91 | if (nuts) { | ||
| 92 | ram->mr[1] &= ~0x030; | ||
| 93 | ram->mr[1] |= (at[1] & 0x03) << 4; | ||
| 94 | } | ||
| 95 | |||
| 78 | ram->mr[3] &= ~0x020; | 96 | ram->mr[3] &= ~0x020; |
| 79 | ram->mr[3] |= (rq & 0x01) << 5; | 97 | ram->mr[3] |= (rq & 0x01) << 5; |
| 80 | 98 | ||
| 99 | ram->mr[5] &= ~0x004; | ||
| 100 | ram->mr[5] |= (l3 << 2); | ||
| 101 | |||
| 81 | if (!vo) | 102 | if (!vo) |
| 82 | vo = (ram->mr[6] & 0xff0) >> 4; | 103 | vo = (ram->mr[6] & 0xff0) >> 4; |
| 83 | if (ram->mr[6] & 0x001) | 104 | if (ram->mr[6] & 0x001) |
| @@ -86,11 +107,16 @@ nouveau_gddr5_calc(struct nouveau_ram *ram) | |||
| 86 | ram->mr[6] |= (vo & 0xff) << 4; | 107 | ram->mr[6] |= (vo & 0xff) << 4; |
| 87 | ram->mr[6] |= (pd & 0x01) << 0; | 108 | ram->mr[6] |= (pd & 0x01) << 0; |
| 88 | 109 | ||
| 89 | if (!(ram->mr[7] & 0x100)) | 110 | if (NOTE00(vr)) { |
| 90 | vr = 0; /* binary driver does this.. bug? */ | 111 | ram->mr[7] &= ~0x300; |
| 91 | ram->mr[7] &= ~0x188; | 112 | ram->mr[7] |= (vr & 0x03) << 8; |
| 92 | ram->mr[7] |= (vr & 0x01) << 8; | 113 | } |
| 114 | ram->mr[7] &= ~0x088; | ||
| 93 | ram->mr[7] |= (vh & 0x01) << 7; | 115 | ram->mr[7] |= (vh & 0x01) << 7; |
| 94 | ram->mr[7] |= (lf & 0x01) << 3; | 116 | ram->mr[7] |= (lf & 0x01) << 3; |
| 117 | |||
| 118 | ram->mr[8] &= ~0x003; | ||
| 119 | ram->mr[8] |= (WR & 0x10) >> 3; | ||
| 120 | ram->mr[8] |= (CL & 0x10) >> 4; | ||
| 95 | return 0; | 121 | return 0; |
| 96 | } | 122 | } |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c index e5fc37c4caac..45470e1f0385 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c | |||
| @@ -33,6 +33,21 @@ nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) | |||
| 33 | return likely((nvc0_pte_storage_type_map[memtype] != 0xff)); | 33 | return likely((nvc0_pte_storage_type_map[memtype] != 0xff)); |
| 34 | } | 34 | } |
| 35 | 35 | ||
| 36 | static void | ||
| 37 | nvc0_fb_intr(struct nouveau_subdev *subdev) | ||
| 38 | { | ||
| 39 | struct nvc0_fb_priv *priv = (void *)subdev; | ||
| 40 | u32 intr = nv_rd32(priv, 0x000100); | ||
| 41 | if (intr & 0x08000000) { | ||
| 42 | nv_debug(priv, "PFFB intr\n"); | ||
| 43 | intr &= ~0x08000000; | ||
| 44 | } | ||
| 45 | if (intr & 0x00002000) { | ||
| 46 | nv_debug(priv, "PBFB intr\n"); | ||
| 47 | intr &= ~0x00002000; | ||
| 48 | } | ||
| 49 | } | ||
| 50 | |||
| 36 | int | 51 | int |
| 37 | nvc0_fb_init(struct nouveau_object *object) | 52 | nvc0_fb_init(struct nouveau_object *object) |
| 38 | { | 53 | { |
| @@ -86,6 +101,7 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 86 | return -EFAULT; | 101 | return -EFAULT; |
| 87 | } | 102 | } |
| 88 | 103 | ||
| 104 | nv_subdev(priv)->intr = nvc0_fb_intr; | ||
| 89 | return 0; | 105 | return 0; |
| 90 | } | 106 | } |
| 91 | 107 | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h index 493125214e88..edaf95dee612 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h | |||
| @@ -34,7 +34,7 @@ extern struct nouveau_oclass nvc0_ram_oclass; | |||
| 34 | extern struct nouveau_oclass nve0_ram_oclass; | 34 | extern struct nouveau_oclass nve0_ram_oclass; |
| 35 | 35 | ||
| 36 | int nouveau_sddr3_calc(struct nouveau_ram *ram); | 36 | int nouveau_sddr3_calc(struct nouveau_ram *ram); |
| 37 | int nouveau_gddr5_calc(struct nouveau_ram *ram); | 37 | int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); |
| 38 | 38 | ||
| 39 | #define nouveau_fb_create(p,e,c,d) \ | 39 | #define nouveau_fb_create(p,e,c,d) \ |
| 40 | nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d) | 40 | nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d) |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c index 76762a17d89c..c7fdb3a9e88b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c | |||
| @@ -70,13 +70,11 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 70 | struct nv50_ramseq *hwsq = &ram->hwsq; | 70 | struct nv50_ramseq *hwsq = &ram->hwsq; |
| 71 | struct nvbios_perfE perfE; | 71 | struct nvbios_perfE perfE; |
| 72 | struct nvbios_pll mpll; | 72 | struct nvbios_pll mpll; |
| 73 | struct bit_entry M; | ||
| 74 | struct { | 73 | struct { |
| 75 | u32 data; | 74 | u32 data; |
| 76 | u8 size; | 75 | u8 size; |
| 77 | } ramcfg, timing; | 76 | } ramcfg, timing; |
| 78 | u8 ver, hdr, cnt, strap; | 77 | u8 ver, hdr, cnt, len, strap; |
| 79 | u32 data; | ||
| 80 | int N1, M1, N2, M2, P; | 78 | int N1, M1, N2, M2, P; |
| 81 | int ret, i; | 79 | int ret, i; |
| 82 | 80 | ||
| @@ -93,16 +91,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 93 | } while (perfE.memory < freq); | 91 | } while (perfE.memory < freq); |
| 94 | 92 | ||
| 95 | /* locate specific data set for the attached memory */ | 93 | /* locate specific data set for the attached memory */ |
| 96 | if (bit_entry(bios, 'M', &M) || M.version != 1 || M.length < 5) { | 94 | strap = nvbios_ramcfg_index(bios); |
| 97 | nv_error(pfb, "invalid/missing memory table\n"); | ||
| 98 | return -EINVAL; | ||
| 99 | } | ||
| 100 | |||
| 101 | strap = (nv_rd32(pfb, 0x101000) & 0x0000003c) >> 2; | ||
| 102 | data = nv_ro16(bios, M.offset + 3); | ||
| 103 | if (data) | ||
| 104 | strap = nv_ro08(bios, data + strap); | ||
| 105 | |||
| 106 | if (strap >= cnt) { | 95 | if (strap >= cnt) { |
| 107 | nv_error(pfb, "invalid ramcfg strap\n"); | 96 | nv_error(pfb, "invalid ramcfg strap\n"); |
| 108 | return -EINVAL; | 97 | return -EINVAL; |
| @@ -113,7 +102,8 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 113 | /* lookup memory timings, if bios says they're present */ | 102 | /* lookup memory timings, if bios says they're present */ |
| 114 | strap = nv_ro08(bios, ramcfg.data + 0x01); | 103 | strap = nv_ro08(bios, ramcfg.data + 0x01); |
| 115 | if (strap != 0xff) { | 104 | if (strap != 0xff) { |
| 116 | timing.data = nvbios_timing_entry(bios, strap, &ver, &hdr); | 105 | timing.data = nvbios_timingEe(bios, strap, &ver, &hdr, |
| 106 | &cnt, &len); | ||
| 117 | if (!timing.data || ver != 0x10 || hdr < 0x12) { | 107 | if (!timing.data || ver != 0x10 || hdr < 0x12) { |
| 118 | nv_error(pfb, "invalid/missing timing entry " | 108 | nv_error(pfb, "invalid/missing timing entry " |
| 119 | "%02x %04x %02x %02x\n", | 109 | "%02x %04x %02x %02x\n", |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c index f6292cd9207c..f4ae8aa46a25 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c | |||
| @@ -79,8 +79,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 79 | struct nva3_ram *ram = (void *)pfb->ram; | 79 | struct nva3_ram *ram = (void *)pfb->ram; |
| 80 | struct nva3_ramfuc *fuc = &ram->fuc; | 80 | struct nva3_ramfuc *fuc = &ram->fuc; |
| 81 | struct nva3_clock_info mclk; | 81 | struct nva3_clock_info mclk; |
| 82 | struct bit_entry M; | 82 | u8 ver, cnt, len, strap; |
| 83 | u8 ver, cnt, strap; | ||
| 84 | u32 data; | 83 | u32 data; |
| 85 | struct { | 84 | struct { |
| 86 | u32 data; | 85 | u32 data; |
| @@ -91,24 +90,15 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 91 | int ret; | 90 | int ret; |
| 92 | 91 | ||
| 93 | /* lookup memory config data relevant to the target frequency */ | 92 | /* lookup memory config data relevant to the target frequency */ |
| 94 | rammap.data = nvbios_rammap_match(bios, freq / 1000, &ver, &rammap.size, | 93 | rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, |
| 95 | &cnt, &ramcfg.size); | 94 | &cnt, &ramcfg.size); |
| 96 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { | 95 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { |
| 97 | nv_error(pfb, "invalid/missing rammap entry\n"); | 96 | nv_error(pfb, "invalid/missing rammap entry\n"); |
| 98 | return -EINVAL; | 97 | return -EINVAL; |
| 99 | } | 98 | } |
| 100 | 99 | ||
| 101 | /* locate specific data set for the attached memory */ | 100 | /* locate specific data set for the attached memory */ |
| 102 | if (bit_entry(bios, 'M', &M) || M.version != 2 || M.length < 3) { | 101 | strap = nvbios_ramcfg_index(bios); |
| 103 | nv_error(pfb, "invalid/missing memory table\n"); | ||
| 104 | return -EINVAL; | ||
| 105 | } | ||
| 106 | |||
| 107 | strap = (nv_rd32(pfb, 0x101000) & 0x0000003c) >> 2; | ||
| 108 | data = nv_ro16(bios, M.offset + 1); | ||
| 109 | if (data) | ||
| 110 | strap = nv_ro08(bios, data + strap); | ||
| 111 | |||
| 112 | if (strap >= cnt) { | 102 | if (strap >= cnt) { |
| 113 | nv_error(pfb, "invalid ramcfg strap\n"); | 103 | nv_error(pfb, "invalid ramcfg strap\n"); |
| 114 | return -EINVAL; | 104 | return -EINVAL; |
| @@ -123,8 +113,8 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 123 | /* lookup memory timings, if bios says they're present */ | 113 | /* lookup memory timings, if bios says they're present */ |
| 124 | strap = nv_ro08(bios, ramcfg.data + 0x01); | 114 | strap = nv_ro08(bios, ramcfg.data + 0x01); |
| 125 | if (strap != 0xff) { | 115 | if (strap != 0xff) { |
| 126 | timing.data = nvbios_timing_entry(bios, strap, &ver, | 116 | timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, |
| 127 | &timing.size); | 117 | &cnt, &len); |
| 128 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { | 118 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { |
| 129 | nv_error(pfb, "invalid/missing timing entry\n"); | 119 | nv_error(pfb, "invalid/missing timing entry\n"); |
| 130 | return -EINVAL; | 120 | return -EINVAL; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c index f464547c6bab..0391b824ee76 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c | |||
| @@ -23,7 +23,6 @@ | |||
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <subdev/bios.h> | 25 | #include <subdev/bios.h> |
| 26 | #include <subdev/bios/bit.h> | ||
| 27 | #include <subdev/bios/pll.h> | 26 | #include <subdev/bios/pll.h> |
| 28 | #include <subdev/bios/rammap.h> | 27 | #include <subdev/bios/rammap.h> |
| 29 | #include <subdev/bios/timing.h> | 28 | #include <subdev/bios/timing.h> |
| @@ -134,9 +133,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 134 | struct nouveau_bios *bios = nouveau_bios(pfb); | 133 | struct nouveau_bios *bios = nouveau_bios(pfb); |
| 135 | struct nvc0_ram *ram = (void *)pfb->ram; | 134 | struct nvc0_ram *ram = (void *)pfb->ram; |
| 136 | struct nvc0_ramfuc *fuc = &ram->fuc; | 135 | struct nvc0_ramfuc *fuc = &ram->fuc; |
| 137 | struct bit_entry M; | 136 | u8 ver, cnt, len, strap; |
| 138 | u8 ver, cnt, strap; | ||
| 139 | u32 data; | ||
| 140 | struct { | 137 | struct { |
| 141 | u32 data; | 138 | u32 data; |
| 142 | u8 size; | 139 | u8 size; |
| @@ -147,24 +144,15 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 147 | int ret; | 144 | int ret; |
| 148 | 145 | ||
| 149 | /* lookup memory config data relevant to the target frequency */ | 146 | /* lookup memory config data relevant to the target frequency */ |
| 150 | rammap.data = nvbios_rammap_match(bios, freq / 1000, &ver, &rammap.size, | 147 | rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, |
| 151 | &cnt, &ramcfg.size); | 148 | &cnt, &ramcfg.size); |
| 152 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { | 149 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { |
| 153 | nv_error(pfb, "invalid/missing rammap entry\n"); | 150 | nv_error(pfb, "invalid/missing rammap entry\n"); |
| 154 | return -EINVAL; | 151 | return -EINVAL; |
| 155 | } | 152 | } |
| 156 | 153 | ||
| 157 | /* locate specific data set for the attached memory */ | 154 | /* locate specific data set for the attached memory */ |
| 158 | if (bit_entry(bios, 'M', &M) || M.version != 2 || M.length < 3) { | 155 | strap = nvbios_ramcfg_index(bios); |
| 159 | nv_error(pfb, "invalid/missing memory table\n"); | ||
| 160 | return -EINVAL; | ||
| 161 | } | ||
| 162 | |||
| 163 | strap = (nv_rd32(pfb, 0x101000) & 0x0000003c) >> 2; | ||
| 164 | data = nv_ro16(bios, M.offset + 1); | ||
| 165 | if (data) | ||
| 166 | strap = nv_ro08(bios, data + strap); | ||
| 167 | |||
| 168 | if (strap >= cnt) { | 156 | if (strap >= cnt) { |
| 169 | nv_error(pfb, "invalid ramcfg strap\n"); | 157 | nv_error(pfb, "invalid ramcfg strap\n"); |
| 170 | return -EINVAL; | 158 | return -EINVAL; |
| @@ -179,8 +167,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 179 | /* lookup memory timings, if bios says they're present */ | 167 | /* lookup memory timings, if bios says they're present */ |
| 180 | strap = nv_ro08(bios, ramcfg.data + 0x01); | 168 | strap = nv_ro08(bios, ramcfg.data + 0x01); |
| 181 | if (strap != 0xff) { | 169 | if (strap != 0xff) { |
| 182 | timing.data = nvbios_timing_entry(bios, strap, &ver, | 170 | timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, |
| 183 | &timing.size); | 171 | &cnt, &len); |
| 184 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { | 172 | if (!timing.data || ver != 0x10 || timing.size < 0x19) { |
| 185 | nv_error(pfb, "invalid/missing timing entry\n"); | 173 | nv_error(pfb, "invalid/missing timing entry\n"); |
| 186 | return -EINVAL; | 174 | return -EINVAL; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index bc86cfd084f6..3257c522a021 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <subdev/gpio.h> | 25 | #include <subdev/gpio.h> |
| 26 | 26 | ||
| 27 | #include <subdev/bios.h> | 27 | #include <subdev/bios.h> |
| 28 | #include <subdev/bios/bit.h> | ||
| 29 | #include <subdev/bios/pll.h> | 28 | #include <subdev/bios/pll.h> |
| 30 | #include <subdev/bios/init.h> | 29 | #include <subdev/bios/init.h> |
| 31 | #include <subdev/bios/rammap.h> | 30 | #include <subdev/bios/rammap.h> |
| @@ -42,6 +41,14 @@ | |||
| 42 | 41 | ||
| 43 | #include "ramfuc.h" | 42 | #include "ramfuc.h" |
| 44 | 43 | ||
| 44 | /* binary driver only executes this path if the condition (a) is true | ||
| 45 | * for any configuration (combination of rammap+ramcfg+timing) that | ||
| 46 | * can be reached on a given card. for now, we will execute the branch | ||
| 47 | * unconditionally in the hope that a "false everywhere" in the bios | ||
| 48 | * tables doesn't actually mean "don't touch this". | ||
| 49 | */ | ||
| 50 | #define NOTE00(a) 1 | ||
| 51 | |||
| 45 | struct nve0_ramfuc { | 52 | struct nve0_ramfuc { |
| 46 | struct ramfuc base; | 53 | struct ramfuc base; |
| 47 | 54 | ||
| @@ -104,7 +111,9 @@ struct nve0_ramfuc { | |||
| 104 | struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */ | 111 | struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */ |
| 105 | 112 | ||
| 106 | struct ramfuc_reg r_0x62c000; | 113 | struct ramfuc_reg r_0x62c000; |
| 114 | |||
| 107 | struct ramfuc_reg r_0x10f200; | 115 | struct ramfuc_reg r_0x10f200; |
| 116 | |||
| 108 | struct ramfuc_reg r_0x10f210; | 117 | struct ramfuc_reg r_0x10f210; |
| 109 | struct ramfuc_reg r_0x10f310; | 118 | struct ramfuc_reg r_0x10f310; |
| 110 | struct ramfuc_reg r_0x10f314; | 119 | struct ramfuc_reg r_0x10f314; |
| @@ -118,12 +127,17 @@ struct nve0_ramfuc { | |||
| 118 | struct ramfuc_reg r_0x10f65c; | 127 | struct ramfuc_reg r_0x10f65c; |
| 119 | struct ramfuc_reg r_0x10f6bc; | 128 | struct ramfuc_reg r_0x10f6bc; |
| 120 | struct ramfuc_reg r_0x100710; | 129 | struct ramfuc_reg r_0x100710; |
| 121 | struct ramfuc_reg r_0x10f750; | 130 | struct ramfuc_reg r_0x100750; |
| 122 | }; | 131 | }; |
| 123 | 132 | ||
| 124 | struct nve0_ram { | 133 | struct nve0_ram { |
| 125 | struct nouveau_ram base; | 134 | struct nouveau_ram base; |
| 126 | struct nve0_ramfuc fuc; | 135 | struct nve0_ramfuc fuc; |
| 136 | |||
| 137 | u32 parts; | ||
| 138 | u32 pmask; | ||
| 139 | u32 pnuts; | ||
| 140 | |||
| 127 | int from; | 141 | int from; |
| 128 | int mode; | 142 | int mode; |
| 129 | int N1, fN1, M1, P1; | 143 | int N1, fN1, M1, P1; |
| @@ -134,17 +148,17 @@ struct nve0_ram { | |||
| 134 | * GDDR5 | 148 | * GDDR5 |
| 135 | ******************************************************************************/ | 149 | ******************************************************************************/ |
| 136 | static void | 150 | static void |
| 137 | train(struct nve0_ramfuc *fuc, u32 magic) | 151 | nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) |
| 138 | { | 152 | { |
| 139 | struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); | 153 | struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); |
| 140 | struct nouveau_fb *pfb = nouveau_fb(ram); | 154 | u32 addr = 0x110974, i; |
| 141 | const int mc = nv_rd32(pfb, 0x02243c); | 155 | |
| 142 | int i; | 156 | ram_mask(fuc, 0x10f910, mask, data); |
| 143 | 157 | ram_mask(fuc, 0x10f914, mask, data); | |
| 144 | ram_mask(fuc, 0x10f910, 0xbc0e0000, magic); | 158 | |
| 145 | ram_mask(fuc, 0x10f914, 0xbc0e0000, magic); | 159 | for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { |
| 146 | for (i = 0; i < mc; i++) { | 160 | if (ram->pmask & (1 << i)) |
| 147 | const u32 addr = 0x110974 + (i * 0x1000); | 161 | continue; |
| 148 | ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); | 162 | ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); |
| 149 | } | 163 | } |
| 150 | } | 164 | } |
| @@ -199,12 +213,12 @@ r1373f4_init(struct nve0_ramfuc *fuc) | |||
| 199 | } | 213 | } |
| 200 | 214 | ||
| 201 | static void | 215 | static void |
| 202 | r1373f4_fini(struct nve0_ramfuc *fuc, u32 ramcfg) | 216 | r1373f4_fini(struct nve0_ramfuc *fuc) |
| 203 | { | 217 | { |
| 204 | struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); | 218 | struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); |
| 205 | struct nouveau_bios *bios = nouveau_bios(ram); | 219 | struct nouveau_ram_data *next = ram->base.next; |
| 206 | u8 v0 = (nv_ro08(bios, ramcfg + 0x03) & 0xc0) >> 6; | 220 | u8 v0 = next->bios.ramcfg_11_03_c0; |
| 207 | u8 v1 = (nv_ro08(bios, ramcfg + 0x03) & 0x30) >> 4; | 221 | u8 v1 = next->bios.ramcfg_11_03_30; |
| 208 | u32 tmp; | 222 | u32 tmp; |
| 209 | 223 | ||
| 210 | tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; | 224 | tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; |
| @@ -220,25 +234,46 @@ r1373f4_fini(struct nve0_ramfuc *fuc, u32 ramcfg) | |||
| 220 | ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); | 234 | ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); |
| 221 | } | 235 | } |
| 222 | 236 | ||
| 237 | static void | ||
| 238 | nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, | ||
| 239 | u32 _mask, u32 _data, u32 _copy) | ||
| 240 | { | ||
| 241 | struct nve0_fb_priv *priv = (void *)nouveau_fb(ram); | ||
| 242 | struct ramfuc *fuc = &ram->fuc.base; | ||
| 243 | u32 addr = 0x110000 + (reg->addr[0] & 0xfff); | ||
| 244 | u32 mask = _mask | _copy; | ||
| 245 | u32 data = (_data & _mask) | (reg->data & _copy); | ||
| 246 | u32 i; | ||
| 247 | |||
| 248 | for (i = 0; i < 16; i++, addr += 0x1000) { | ||
| 249 | if (ram->pnuts & (1 << i)) { | ||
| 250 | u32 prev = nv_rd32(priv, addr); | ||
| 251 | u32 next = (prev & ~mask) | data; | ||
| 252 | nouveau_memx_wr32(fuc->memx, addr, next); | ||
| 253 | } | ||
| 254 | } | ||
| 255 | } | ||
| 256 | #define ram_nuts(s,r,m,d,c) \ | ||
| 257 | nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) | ||
| 258 | |||
| 223 | static int | 259 | static int |
| 224 | nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | 260 | nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) |
| 225 | { | 261 | { |
| 226 | struct nouveau_bios *bios = nouveau_bios(pfb); | ||
| 227 | struct nve0_ram *ram = (void *)pfb->ram; | 262 | struct nve0_ram *ram = (void *)pfb->ram; |
| 228 | struct nve0_ramfuc *fuc = &ram->fuc; | 263 | struct nve0_ramfuc *fuc = &ram->fuc; |
| 229 | const u32 rammap = ram->base.rammap.data; | 264 | struct nouveau_ram_data *next = ram->base.next; |
| 230 | const u32 ramcfg = ram->base.ramcfg.data; | 265 | int vc = !(next->bios.ramcfg_11_02_08); |
| 231 | const u32 timing = ram->base.timing.data; | 266 | int mv = !(next->bios.ramcfg_11_02_04); |
| 232 | int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08); | ||
| 233 | int mv = 1; /*XXX*/ | ||
| 234 | u32 mask, data; | 267 | u32 mask, data; |
| 235 | 268 | ||
| 236 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); | 269 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); |
| 237 | ram_wr32(fuc, 0x62c000, 0x0f0f0000); | 270 | ram_wr32(fuc, 0x62c000, 0x0f0f0000); |
| 238 | 271 | ||
| 239 | /* MR1: turn termination on early, for some reason.. */ | 272 | /* MR1: turn termination on early, for some reason.. */ |
| 240 | if ((ram->base.mr[1] & 0x03c) != 0x030) | 273 | if ((ram->base.mr[1] & 0x03c) != 0x030) { |
| 241 | ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); | 274 | ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); |
| 275 | ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000); | ||
| 276 | } | ||
| 242 | 277 | ||
| 243 | if (vc == 1 && ram_have(fuc, gpio2E)) { | 278 | if (vc == 1 && ram_have(fuc, gpio2E)) { |
| 244 | u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); | 279 | u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); |
| @@ -250,8 +285,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 250 | 285 | ||
| 251 | ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); | 286 | ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); |
| 252 | 287 | ||
| 253 | ram_mask(fuc, 0x10f914, 0x01020000, 0x000c0000); | 288 | nve0_ram_train(fuc, 0x01020000, 0x000c0000); |
| 254 | ram_mask(fuc, 0x10f910, 0x01020000, 0x000c0000); | ||
| 255 | 289 | ||
| 256 | ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ | 290 | ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ |
| 257 | ram_nsec(fuc, 1000); | 291 | ram_nsec(fuc, 1000); |
| @@ -280,28 +314,28 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 280 | 314 | ||
| 281 | if (1) { | 315 | if (1) { |
| 282 | data |= 0x800807e0; | 316 | data |= 0x800807e0; |
| 283 | switch (nv_ro08(bios, ramcfg + 0x03) & 0xc0) { | 317 | switch (next->bios.ramcfg_11_03_c0) { |
| 284 | case 0xc0: data &= ~0x00000040; break; | 318 | case 3: data &= ~0x00000040; break; |
| 285 | case 0x80: data &= ~0x00000100; break; | 319 | case 2: data &= ~0x00000100; break; |
| 286 | case 0x40: data &= ~0x80000000; break; | 320 | case 1: data &= ~0x80000000; break; |
| 287 | case 0x00: data &= ~0x00000400; break; | 321 | case 0: data &= ~0x00000400; break; |
| 288 | } | 322 | } |
| 289 | 323 | ||
| 290 | switch (nv_ro08(bios, ramcfg + 0x03) & 0x30) { | 324 | switch (next->bios.ramcfg_11_03_30) { |
| 291 | case 0x30: data &= ~0x00000020; break; | 325 | case 3: data &= ~0x00000020; break; |
| 292 | case 0x20: data &= ~0x00000080; break; | 326 | case 2: data &= ~0x00000080; break; |
| 293 | case 0x10: data &= ~0x00080000; break; | 327 | case 1: data &= ~0x00080000; break; |
| 294 | case 0x00: data &= ~0x00000200; break; | 328 | case 0: data &= ~0x00000200; break; |
| 295 | } | 329 | } |
| 296 | } | 330 | } |
| 297 | 331 | ||
| 298 | if (nv_ro08(bios, ramcfg + 0x02) & 0x80) | 332 | if (next->bios.ramcfg_11_02_80) |
| 299 | mask |= 0x03000000; | 333 | mask |= 0x03000000; |
| 300 | if (nv_ro08(bios, ramcfg + 0x02) & 0x40) | 334 | if (next->bios.ramcfg_11_02_40) |
| 301 | mask |= 0x00002000; | 335 | mask |= 0x00002000; |
| 302 | if (nv_ro08(bios, ramcfg + 0x07) & 0x10) | 336 | if (next->bios.ramcfg_11_07_10) |
| 303 | mask |= 0x00004000; | 337 | mask |= 0x00004000; |
| 304 | if (nv_ro08(bios, ramcfg + 0x07) & 0x08) | 338 | if (next->bios.ramcfg_11_07_08) |
| 305 | mask |= 0x00000003; | 339 | mask |= 0x00000003; |
| 306 | else { | 340 | else { |
| 307 | mask |= 0x34000000; | 341 | mask |= 0x34000000; |
| @@ -314,18 +348,18 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 314 | 348 | ||
| 315 | if (ram->from == 2 && ram->mode != 2) { | 349 | if (ram->from == 2 && ram->mode != 2) { |
| 316 | ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); | 350 | ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); |
| 317 | ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000); | 351 | ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000); |
| 318 | ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); | 352 | ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); |
| 319 | ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); | 353 | ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); |
| 320 | ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); | 354 | ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); |
| 321 | r1373f4_init(fuc); | 355 | r1373f4_init(fuc); |
| 322 | ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); | 356 | ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); |
| 323 | r1373f4_fini(fuc, ramcfg); | 357 | r1373f4_fini(fuc); |
| 324 | ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); | 358 | ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); |
| 325 | } else | 359 | } else |
| 326 | if (ram->from != 2 && ram->mode != 2) { | 360 | if (ram->from != 2 && ram->mode != 2) { |
| 327 | r1373f4_init(fuc); | 361 | r1373f4_init(fuc); |
| 328 | r1373f4_fini(fuc, ramcfg); | 362 | r1373f4_fini(fuc); |
| 329 | } | 363 | } |
| 330 | 364 | ||
| 331 | if (ram_have(fuc, gpioMV)) { | 365 | if (ram_have(fuc, gpioMV)) { |
| @@ -336,49 +370,54 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 336 | } | 370 | } |
| 337 | } | 371 | } |
| 338 | 372 | ||
| 339 | if ( (nv_ro08(bios, ramcfg + 0x02) & 0x40) || | 373 | if ( (next->bios.ramcfg_11_02_40) || |
| 340 | (nv_ro08(bios, ramcfg + 0x07) & 0x10)) { | 374 | (next->bios.ramcfg_11_07_10)) { |
| 341 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); | 375 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); |
| 342 | ram_nsec(fuc, 20000); | 376 | ram_nsec(fuc, 20000); |
| 343 | } | 377 | } |
| 344 | 378 | ||
| 345 | if (ram->from != 2 && ram->mode == 2) { | 379 | if (ram->from != 2 && ram->mode == 2) { |
| 380 | if (0 /*XXX: Titan */) | ||
| 381 | ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000); | ||
| 346 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); | 382 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); |
| 347 | ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); | 383 | ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); |
| 348 | ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); | 384 | ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); |
| 349 | r1373f4_init(fuc); | 385 | r1373f4_init(fuc); |
| 350 | r1373f4_fini(fuc, ramcfg); | 386 | r1373f4_fini(fuc); |
| 351 | ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); | 387 | ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); |
| 352 | ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); | 388 | ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); |
| 353 | } else | 389 | } else |
| 354 | if (ram->from == 2 && ram->mode == 2) { | 390 | if (ram->from == 2 && ram->mode == 2) { |
| 355 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); | 391 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); |
| 356 | r1373f4_init(fuc); | 392 | r1373f4_init(fuc); |
| 357 | r1373f4_fini(fuc, ramcfg); | 393 | r1373f4_fini(fuc); |
| 358 | } | 394 | } |
| 359 | 395 | ||
| 360 | if (ram->mode != 2) /*XXX*/ { | 396 | if (ram->mode != 2) /*XXX*/ { |
| 361 | if (nv_ro08(bios, ramcfg + 0x07) & 0x40) | 397 | if (next->bios.ramcfg_11_07_40) |
| 362 | ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); | 398 | ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); |
| 363 | } | 399 | } |
| 364 | 400 | ||
| 365 | data = (nv_ro08(bios, rammap + 0x11) & 0x0c) >> 2; | 401 | ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); |
| 366 | ram_wr32(fuc, 0x10f65c, 0x00000011 * data); | 402 | ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); |
| 367 | ram_wr32(fuc, 0x10f6b8, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); | 403 | ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); |
| 368 | ram_wr32(fuc, 0x10f6bc, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); | ||
| 369 | 404 | ||
| 370 | data = nv_ro08(bios, ramcfg + 0x04); | 405 | if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) { |
| 371 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { | 406 | ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04); |
| 372 | ram_wr32(fuc, 0x10f698, 0x01010101 * data); | 407 | ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04); |
| 373 | ram_wr32(fuc, 0x10f69c, 0x01010101 * data); | 408 | } else |
| 409 | if (!next->bios.ramcfg_11_07_08) { | ||
| 410 | ram_wr32(fuc, 0x10f698, 0x00000000); | ||
| 411 | ram_wr32(fuc, 0x10f69c, 0x00000000); | ||
| 374 | } | 412 | } |
| 375 | 413 | ||
| 376 | if (ram->mode != 2) { | 414 | if (ram->mode != 2) { |
| 377 | u32 temp = ram_rd32(fuc, 0x10f694) & ~0xff00ff00; | 415 | u32 data = 0x01000100 * next->bios.ramcfg_11_04; |
| 378 | ram_wr32(fuc, 0x10f694, temp | (0x01000100 * data)); | 416 | ram_nuke(fuc, 0x10f694); |
| 417 | ram_mask(fuc, 0x10f694, 0xff00ff00, data); | ||
| 379 | } | 418 | } |
| 380 | 419 | ||
| 381 | if (ram->mode == 2 && (nv_ro08(bios, ramcfg + 0x08) & 0x10)) | 420 | if (ram->mode == 2 && (next->bios.ramcfg_11_08_10)) |
| 382 | data = 0x00000080; | 421 | data = 0x00000080; |
| 383 | else | 422 | else |
| 384 | data = 0x00000000; | 423 | data = 0x00000000; |
| @@ -386,19 +425,19 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 386 | 425 | ||
| 387 | mask = 0x00070000; | 426 | mask = 0x00070000; |
| 388 | data = 0x00000000; | 427 | data = 0x00000000; |
| 389 | if (!(nv_ro08(bios, ramcfg + 0x02) & 0x80)) | 428 | if (!(next->bios.ramcfg_11_02_80)) |
| 390 | data |= 0x03000000; | 429 | data |= 0x03000000; |
| 391 | if (!(nv_ro08(bios, ramcfg + 0x02) & 0x40)) | 430 | if (!(next->bios.ramcfg_11_02_40)) |
| 392 | data |= 0x00002000; | 431 | data |= 0x00002000; |
| 393 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x10)) | 432 | if (!(next->bios.ramcfg_11_07_10)) |
| 394 | data |= 0x00004000; | 433 | data |= 0x00004000; |
| 395 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) | 434 | if (!(next->bios.ramcfg_11_07_08)) |
| 396 | data |= 0x00000003; | 435 | data |= 0x00000003; |
| 397 | else | 436 | else |
| 398 | data |= 0x74000000; | 437 | data |= 0x74000000; |
| 399 | ram_mask(fuc, 0x10f824, mask, data); | 438 | ram_mask(fuc, 0x10f824, mask, data); |
| 400 | 439 | ||
| 401 | if (nv_ro08(bios, ramcfg + 0x01) & 0x08) | 440 | if (next->bios.ramcfg_11_01_08) |
| 402 | data = 0x00000000; | 441 | data = 0x00000000; |
| 403 | else | 442 | else |
| 404 | data = 0x00001000; | 443 | data = 0x00001000; |
| @@ -409,61 +448,90 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 409 | ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); | 448 | ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); |
| 410 | } | 449 | } |
| 411 | 450 | ||
| 412 | if (nv_ro08(bios, ramcfg + 0x08) & 0x01) | 451 | if (next->bios.ramcfg_11_08_01) |
| 413 | data = 0x00100000; | 452 | data = 0x00100000; |
| 414 | else | 453 | else |
| 415 | data = 0x00000000; | 454 | data = 0x00000000; |
| 416 | ram_mask(fuc, 0x10f82c, 0x00100000, data); | 455 | ram_mask(fuc, 0x10f82c, 0x00100000, data); |
| 417 | 456 | ||
| 418 | data = 0x00000000; | 457 | data = 0x00000000; |
| 419 | if (nv_ro08(bios, ramcfg + 0x08) & 0x08) | 458 | if (next->bios.ramcfg_11_08_08) |
| 420 | data |= 0x00002000; | 459 | data |= 0x00002000; |
| 421 | if (nv_ro08(bios, ramcfg + 0x08) & 0x04) | 460 | if (next->bios.ramcfg_11_08_04) |
| 422 | data |= 0x00001000; | 461 | data |= 0x00001000; |
| 423 | if (nv_ro08(bios, ramcfg + 0x08) & 0x02) | 462 | if (next->bios.ramcfg_11_08_02) |
| 424 | data |= 0x00004000; | 463 | data |= 0x00004000; |
| 425 | ram_mask(fuc, 0x10f830, 0x00007000, data); | 464 | ram_mask(fuc, 0x10f830, 0x00007000, data); |
| 426 | 465 | ||
| 427 | /* PFB timing */ | 466 | /* PFB timing */ |
| 428 | ram_mask(fuc, 0x10f248, 0xffffffff, nv_ro32(bios, timing + 0x28)); | 467 | ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); |
| 429 | ram_mask(fuc, 0x10f290, 0xffffffff, nv_ro32(bios, timing + 0x00)); | 468 | ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); |
| 430 | ram_mask(fuc, 0x10f294, 0xffffffff, nv_ro32(bios, timing + 0x04)); | 469 | ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); |
| 431 | ram_mask(fuc, 0x10f298, 0xffffffff, nv_ro32(bios, timing + 0x08)); | 470 | ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); |
| 432 | ram_mask(fuc, 0x10f29c, 0xffffffff, nv_ro32(bios, timing + 0x0c)); | 471 | ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); |
| 433 | ram_mask(fuc, 0x10f2a0, 0xffffffff, nv_ro32(bios, timing + 0x10)); | 472 | ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); |
| 434 | ram_mask(fuc, 0x10f2a4, 0xffffffff, nv_ro32(bios, timing + 0x14)); | 473 | ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); |
| 435 | ram_mask(fuc, 0x10f2a8, 0xffffffff, nv_ro32(bios, timing + 0x18)); | 474 | ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); |
| 436 | ram_mask(fuc, 0x10f2ac, 0xffffffff, nv_ro32(bios, timing + 0x1c)); | 475 | ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); |
| 437 | ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20)); | 476 | ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); |
| 438 | ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24)); | 477 | ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); |
| 439 | 478 | ||
| 440 | data = (nv_ro08(bios, ramcfg + 0x02) & 0x03) << 8; | 479 | data = mask = 0x00000000; |
| 441 | if (nv_ro08(bios, ramcfg + 0x01) & 0x10) | 480 | if (NOTE00(ramcfg_08_20)) { |
| 442 | data |= 0x70000000; | 481 | if (next->bios.ramcfg_11_08_20) |
| 443 | ram_mask(fuc, 0x10f604, 0x70000300, data); | 482 | data |= 0x01000000; |
| 444 | 483 | mask |= 0x01000000; | |
| 445 | data = (nv_ro08(bios, timing + 0x30) & 0x07) << 28; | 484 | } |
| 446 | if (nv_ro08(bios, ramcfg + 0x01) & 0x01) | 485 | ram_mask(fuc, 0x10f200, mask, data); |
| 447 | data |= 0x00000100; | 486 | |
| 448 | ram_mask(fuc, 0x10f614, 0x70000000, data); | 487 | data = mask = 0x00000000; |
| 449 | 488 | if (NOTE00(ramcfg_02_03 != 0)) { | |
| 450 | data = (nv_ro08(bios, timing + 0x30) & 0x07) << 28; | 489 | data |= (next->bios.ramcfg_11_02_03) << 8; |
| 451 | if (nv_ro08(bios, ramcfg + 0x01) & 0x02) | 490 | mask |= 0x00000300; |
| 452 | data |= 0x00000100; | 491 | } |
| 453 | ram_mask(fuc, 0x10f610, 0x70000000, data); | 492 | if (NOTE00(ramcfg_01_10)) { |
| 493 | if (next->bios.ramcfg_11_01_10) | ||
| 494 | data |= 0x70000000; | ||
| 495 | mask |= 0x70000000; | ||
| 496 | } | ||
| 497 | ram_mask(fuc, 0x10f604, mask, data); | ||
| 498 | |||
| 499 | data = mask = 0x00000000; | ||
| 500 | if (NOTE00(timing_30_07 != 0)) { | ||
| 501 | data |= (next->bios.timing_20_30_07) << 28; | ||
| 502 | mask |= 0x70000000; | ||
| 503 | } | ||
| 504 | if (NOTE00(ramcfg_01_01)) { | ||
| 505 | if (next->bios.ramcfg_11_01_01) | ||
| 506 | data |= 0x00000100; | ||
| 507 | mask |= 0x00000100; | ||
| 508 | } | ||
| 509 | ram_mask(fuc, 0x10f614, mask, data); | ||
| 510 | |||
| 511 | data = mask = 0x00000000; | ||
| 512 | if (NOTE00(timing_30_07 != 0)) { | ||
| 513 | data |= (next->bios.timing_20_30_07) << 28; | ||
| 514 | mask |= 0x70000000; | ||
| 515 | } | ||
| 516 | if (NOTE00(ramcfg_01_02)) { | ||
| 517 | if (next->bios.ramcfg_11_01_02) | ||
| 518 | data |= 0x00000100; | ||
| 519 | mask |= 0x00000100; | ||
| 520 | } | ||
| 521 | ram_mask(fuc, 0x10f610, mask, data); | ||
| 454 | 522 | ||
| 455 | mask = 0x33f00000; | 523 | mask = 0x33f00000; |
| 456 | data = 0x00000000; | 524 | data = 0x00000000; |
| 457 | if (!(nv_ro08(bios, ramcfg + 0x01) & 0x04)) | 525 | if (!(next->bios.ramcfg_11_01_04)) |
| 458 | data |= 0x20200000; | 526 | data |= 0x20200000; |
| 459 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) | 527 | if (!(next->bios.ramcfg_11_07_80)) |
| 460 | data |= 0x12800000; | 528 | data |= 0x12800000; |
| 461 | /*XXX: see note above about there probably being some condition | 529 | /*XXX: see note above about there probably being some condition |
| 462 | * for the 10f824 stuff that uses ramcfg 3... | 530 | * for the 10f824 stuff that uses ramcfg 3... |
| 463 | */ | 531 | */ |
| 464 | if ( (nv_ro08(bios, ramcfg + 0x03) & 0xf0)) { | 532 | if ( (next->bios.ramcfg_11_03_f0)) { |
| 465 | if (nv_ro08(bios, rammap + 0x08) & 0x0c) { | 533 | if (next->bios.rammap_11_08_0c) { |
| 466 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) | 534 | if (!(next->bios.ramcfg_11_07_80)) |
| 467 | mask |= 0x00000020; | 535 | mask |= 0x00000020; |
| 468 | else | 536 | else |
| 469 | data |= 0x00000020; | 537 | data |= 0x00000020; |
| @@ -476,49 +544,53 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 476 | 544 | ||
| 477 | ram_mask(fuc, 0x10f808, mask, data); | 545 | ram_mask(fuc, 0x10f808, mask, data); |
| 478 | 546 | ||
| 479 | data = nv_ro08(bios, ramcfg + 0x03) & 0x0f; | 547 | ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); |
| 480 | ram_wr32(fuc, 0x10f870, 0x11111111 * data); | ||
| 481 | 548 | ||
| 482 | data = nv_ro08(bios, ramcfg + 0x02) & 0x03; | 549 | data = mask = 0x00000000; |
| 483 | if (nv_ro08(bios, ramcfg + 0x01) & 0x10) | 550 | if (NOTE00(ramcfg_02_03 != 0)) { |
| 484 | data |= 0x00000004; | 551 | data |= next->bios.ramcfg_11_02_03; |
| 485 | if ((nv_rd32(bios, 0x100770) & 0x00000004) != (data & 0x00000004)) { | 552 | mask |= 0x00000003; |
| 486 | ram_wr32(fuc, 0x10f750, 0x04000009); | 553 | } |
| 554 | if (NOTE00(ramcfg_01_10)) { | ||
| 555 | if (next->bios.ramcfg_11_01_10) | ||
| 556 | data |= 0x00000004; | ||
| 557 | mask |= 0x00000004; | ||
| 558 | } | ||
| 559 | |||
| 560 | if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) { | ||
| 561 | ram_mask(fuc, 0x100750, 0x00000008, 0x00000008); | ||
| 487 | ram_wr32(fuc, 0x100710, 0x00000000); | 562 | ram_wr32(fuc, 0x100710, 0x00000000); |
| 488 | ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); | 563 | ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); |
| 489 | } | 564 | } |
| 490 | ram_mask(fuc, 0x100770, 0x00000007, data); | ||
| 491 | 565 | ||
| 492 | data = (nv_ro08(bios, timing + 0x30) & 0x07) << 8; | 566 | data = (next->bios.timing_20_30_07) << 8; |
| 493 | if (nv_ro08(bios, ramcfg + 0x01) & 0x01) | 567 | if (next->bios.ramcfg_11_01_01) |
| 494 | data |= 0x80000000; | 568 | data |= 0x80000000; |
| 495 | ram_mask(fuc, 0x100778, 0x00000700, data); | 569 | ram_mask(fuc, 0x100778, 0x00000700, data); |
| 496 | 570 | ||
| 497 | data = nv_ro16(bios, timing + 0x2c); | 571 | ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); |
| 498 | ram_mask(fuc, 0x10f250, 0x000003f0, (data & 0x003f) << 4); | 572 | data = (next->bios.timing[10] & 0x7f000000) >> 24; |
| 499 | ram_mask(fuc, 0x10f24c, 0x7f000000, (data & 0x1fc0) << 18); | 573 | if (data < next->bios.timing_20_2c_1fc0) |
| 500 | 574 | data = next->bios.timing_20_2c_1fc0; | |
| 501 | data = nv_ro08(bios, timing + 0x30); | 575 | ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); |
| 502 | ram_mask(fuc, 0x10f224, 0x001f0000, (data & 0xf8) << 13); | 576 | ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); |
| 503 | 577 | ||
| 504 | data = nv_ro16(bios, timing + 0x31); | 578 | ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 | |
| 505 | ram_mask(fuc, 0x10fec4, 0x041e0f07, (data & 0x0800) << 15 | | 579 | next->bios.timing_20_31_0780 << 17 | |
| 506 | (data & 0x0780) << 10 | | 580 | next->bios.timing_20_31_0078 << 8 | |
| 507 | (data & 0x0078) << 5 | | 581 | next->bios.timing_20_31_0007); |
| 508 | (data & 0x0007)); | 582 | ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 | |
| 509 | ram_mask(fuc, 0x10fec8, 0x00000027, (data & 0x8000) >> 10 | | 583 | next->bios.timing_20_31_7000); |
| 510 | (data & 0x7000) >> 12); | ||
| 511 | 584 | ||
| 512 | ram_wr32(fuc, 0x10f090, 0x4000007e); | 585 | ram_wr32(fuc, 0x10f090, 0x4000007e); |
| 513 | ram_nsec(fuc, 1000); | 586 | ram_nsec(fuc, 2000); |
| 514 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ | 587 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ |
| 515 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ | 588 | ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ |
| 516 | ram_nsec(fuc, 2000); | ||
| 517 | ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ | 589 | ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ |
| 518 | 590 | ||
| 519 | if ((nv_ro08(bios, ramcfg + 0x08) & 0x10) && (ram->mode == 2) /*XXX*/) { | 591 | if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) { |
| 520 | u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); | 592 | u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); |
| 521 | train(fuc, 0xa4010000); /*XXX*/ | 593 | nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ |
| 522 | ram_nsec(fuc, 1000); | 594 | ram_nsec(fuc, 1000); |
| 523 | ram_wr32(fuc, 0x10f294, temp); | 595 | ram_wr32(fuc, 0x10f294, temp); |
| 524 | } | 596 | } |
| @@ -528,7 +600,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 528 | ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); | 600 | ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); |
| 529 | ram_nsec(fuc, 1000); | 601 | ram_nsec(fuc, 1000); |
| 530 | ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); | 602 | ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); |
| 531 | ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5]); | 603 | ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ |
| 532 | ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); | 604 | ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); |
| 533 | ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); | 605 | ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); |
| 534 | 606 | ||
| @@ -544,12 +616,13 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 544 | ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ | 616 | ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ |
| 545 | ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); | 617 | ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); |
| 546 | ram_nsec(fuc, 1000); | 618 | ram_nsec(fuc, 1000); |
| 619 | ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800); | ||
| 547 | 620 | ||
| 548 | data = ram_rd32(fuc, 0x10f978); | 621 | data = ram_rd32(fuc, 0x10f978); |
| 549 | data &= ~0x00046144; | 622 | data &= ~0x00046144; |
| 550 | data |= 0x0000000b; | 623 | data |= 0x0000000b; |
| 551 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { | 624 | if (!(next->bios.ramcfg_11_07_08)) { |
| 552 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x04)) | 625 | if (!(next->bios.ramcfg_11_07_04)) |
| 553 | data |= 0x0000200c; | 626 | data |= 0x0000200c; |
| 554 | else | 627 | else |
| 555 | data |= 0x00000000; | 628 | data |= 0x00000000; |
| @@ -563,44 +636,43 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 563 | ram_wr32(fuc, 0x10f830, data); | 636 | ram_wr32(fuc, 0x10f830, data); |
| 564 | } | 637 | } |
| 565 | 638 | ||
| 566 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { | 639 | if (!(next->bios.ramcfg_11_07_08)) { |
| 567 | data = 0x88020000; | 640 | data = 0x88020000; |
| 568 | if ( (nv_ro08(bios, ramcfg + 0x07) & 0x04)) | 641 | if ( (next->bios.ramcfg_11_07_04)) |
| 569 | data |= 0x10000000; | 642 | data |= 0x10000000; |
| 570 | if (!(nv_ro08(bios, rammap + 0x08) & 0x10)) | 643 | if (!(next->bios.rammap_11_08_10)) |
| 571 | data |= 0x00080000; | 644 | data |= 0x00080000; |
| 572 | } else { | 645 | } else { |
| 573 | data = 0xa40e0000; | 646 | data = 0xa40e0000; |
| 574 | } | 647 | } |
| 575 | train(fuc, data); | 648 | nve0_ram_train(fuc, 0xbc0f0000, data); |
| 576 | ram_nsec(fuc, 1000); | 649 | if (1) /* XXX: not always? */ |
| 650 | ram_nsec(fuc, 1000); | ||
| 577 | 651 | ||
| 578 | if (ram->mode == 2) { /*XXX*/ | 652 | if (ram->mode == 2) { /*XXX*/ |
| 579 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004); | 653 | ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004); |
| 580 | } | 654 | } |
| 581 | 655 | ||
| 582 | /* MR5: (re)enable LP3 if necessary | 656 | /* LP3 */ |
| 583 | * XXX: need to find the switch, keeping off for now | 657 | if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5]) |
| 584 | */ | 658 | ram_nsec(fuc, 1000); |
| 585 | ram_mask(fuc, mr[5], 0x00000004, 0x00000000); | ||
| 586 | 659 | ||
| 587 | if (ram->mode != 2) { | 660 | if (ram->mode != 2) { |
| 588 | ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); | 661 | ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); |
| 589 | ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); | 662 | ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); |
| 590 | } | 663 | } |
| 591 | 664 | ||
| 592 | if (nv_ro08(bios, ramcfg + 0x07) & 0x02) { | 665 | if (next->bios.ramcfg_11_07_02) |
| 593 | ram_mask(fuc, 0x10f910, 0x80020000, 0x01000000); | 666 | nve0_ram_train(fuc, 0x80020000, 0x01000000); |
| 594 | ram_mask(fuc, 0x10f914, 0x80020000, 0x01000000); | ||
| 595 | } | ||
| 596 | 667 | ||
| 597 | ram_wr32(fuc, 0x62c000, 0x0f0f0f00); | 668 | ram_wr32(fuc, 0x62c000, 0x0f0f0f00); |
| 598 | 669 | ||
| 599 | if (nv_ro08(bios, rammap + 0x08) & 0x01) | 670 | if (next->bios.rammap_11_08_01) |
| 600 | data = 0x00000800; | 671 | data = 0x00000800; |
| 601 | else | 672 | else |
| 602 | data = 0x00000000; | 673 | data = 0x00000000; |
| 603 | ram_mask(fuc, 0x10f200, 0x00000800, data); | 674 | ram_mask(fuc, 0x10f200, 0x00000800, data); |
| 675 | ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800); | ||
| 604 | return 0; | 676 | return 0; |
| 605 | } | 677 | } |
| 606 | 678 | ||
| @@ -611,17 +683,14 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) | |||
| 611 | static int | 683 | static int |
| 612 | nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | 684 | nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) |
| 613 | { | 685 | { |
| 614 | struct nouveau_bios *bios = nouveau_bios(pfb); | ||
| 615 | struct nve0_ram *ram = (void *)pfb->ram; | 686 | struct nve0_ram *ram = (void *)pfb->ram; |
| 616 | struct nve0_ramfuc *fuc = &ram->fuc; | 687 | struct nve0_ramfuc *fuc = &ram->fuc; |
| 617 | const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); | 688 | const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); |
| 618 | const u32 runk0 = ram->fN1 << 16; | 689 | const u32 runk0 = ram->fN1 << 16; |
| 619 | const u32 runk1 = ram->fN1; | 690 | const u32 runk1 = ram->fN1; |
| 620 | const u32 rammap = ram->base.rammap.data; | 691 | struct nouveau_ram_data *next = ram->base.next; |
| 621 | const u32 ramcfg = ram->base.ramcfg.data; | 692 | int vc = !(next->bios.ramcfg_11_02_08); |
| 622 | const u32 timing = ram->base.timing.data; | 693 | int mv = !(next->bios.ramcfg_11_02_04); |
| 623 | int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08); | ||
| 624 | int mv = 1; /*XXX*/ | ||
| 625 | u32 mask, data; | 694 | u32 mask, data; |
| 626 | 695 | ||
| 627 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); | 696 | ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); |
| @@ -636,7 +705,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
| 636 | } | 705 | } |
| 637 | 706 | ||
| 638 | ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); | 707 | ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); |
| 639 | if ((nv_ro08(bios, ramcfg + 0x03) & 0xf0)) | 708 | if ((next->bios.ramcfg_11_03_f0)) |
| 640 | ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); | 709 | ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); |
| 641 | 710 | ||
| 642 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ | 711 | ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ |
| @@ -661,28 +730,28 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
| 661 | if (1) { | 730 | if (1) { |
| 662 | mask |= 0x800807e0; | 731 | mask |= 0x800807e0; |
| 663 | data |= 0x800807e0; | 732 | data |= 0x800807e0; |
| 664 | switch (nv_ro08(bios, ramcfg + 0x03) & 0xc0) { | 733 | switch (next->bios.ramcfg_11_03_c0) { |
| 665 | case 0xc0: data &= ~0x00000040; break; | 734 | case 3: data &= ~0x00000040; break; |
| 666 | case 0x80: data &= ~0x00000100; break; | 735 | case 2: data &= ~0x00000100; break; |
| 667 | case 0x40: data &= ~0x80000000; break; | 736 | case 1: data &= ~0x80000000; break; |
| 668 | case 0x00: data &= ~0x00000400; break; | 737 | case 0: data &= ~0x00000400; break; |
| 669 | } | 738 | } |
| 670 | 739 | ||
| 671 | switch (nv_ro08(bios, ramcfg + 0x03) & 0x30) { | 740 | switch (next->bios.ramcfg_11_03_30) { |
| 672 | case 0x30: data &= ~0x00000020; break; | 741 | case 3: data &= ~0x00000020; break; |
| 673 | case 0x20: data &= ~0x00000080; break; | 742 | case 2: data &= ~0x00000080; break; |
| 674 | case 0x10: data &= ~0x00080000; break; | 743 | case 1: data &= ~0x00080000; break; |
| 675 | case 0x00: data &= ~0x00000200; break; | 744 | case 0: data &= ~0x00000200; break; |
| 676 | } | 745 | } |
| 677 | } | 746 | } |
| 678 | 747 | ||
| 679 | if (nv_ro08(bios, ramcfg + 0x02) & 0x80) | 748 | if (next->bios.ramcfg_11_02_80) |
| 680 | mask |= 0x03000000; | 749 | mask |= 0x03000000; |
| 681 | if (nv_ro08(bios, ramcfg + 0x02) & 0x40) | 750 | if (next->bios.ramcfg_11_02_40) |
| 682 | mask |= 0x00002000; | 751 | mask |= 0x00002000; |
| 683 | if (nv_ro08(bios, ramcfg + 0x07) & 0x10) | 752 | if (next->bios.ramcfg_11_07_10) |
| 684 | mask |= 0x00004000; | 753 | mask |= 0x00004000; |
| 685 | if (nv_ro08(bios, ramcfg + 0x07) & 0x08) | 754 | if (next->bios.ramcfg_11_07_08) |
| 686 | mask |= 0x00000003; | 755 | mask |= 0x00000003; |
| 687 | else | 756 | else |
| 688 | mask |= 0x14000000; | 757 | mask |= 0x14000000; |
| @@ -692,7 +761,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
| 692 | 761 | ||
| 693 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); | 762 | ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); |
| 694 | data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; | 763 | data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; |
| 695 | data |= (nv_ro08(bios, ramcfg + 0x03) & 0x30) << 12; | 764 | data |= (next->bios.ramcfg_11_03_30) << 12; |
| 696 | ram_wr32(fuc, 0x1373ec, data); | 765 | ram_wr32(fuc, 0x1373ec, data); |
| 697 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); | 766 | ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); |
| 698 | ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); | 767 | ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); |
| @@ -724,68 +793,67 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
| 724 | } | 793 | } |
| 725 | } | 794 | } |
| 726 | 795 | ||
| 727 | if ( (nv_ro08(bios, ramcfg + 0x02) & 0x40) || | 796 | if ( (next->bios.ramcfg_11_02_40) || |
| 728 | (nv_ro08(bios, ramcfg + 0x07) & 0x10)) { | 797 | (next->bios.ramcfg_11_07_10)) { |
| 729 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); | 798 | ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); |
| 730 | ram_nsec(fuc, 20000); | 799 | ram_nsec(fuc, 20000); |
| 731 | } | 800 | } |
| 732 | 801 | ||
| 733 | if (ram->mode != 2) /*XXX*/ { | 802 | if (ram->mode != 2) /*XXX*/ { |
| 734 | if (nv_ro08(bios, ramcfg + 0x07) & 0x40) | 803 | if (next->bios.ramcfg_11_07_40) |
| 735 | ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); | 804 | ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); |
| 736 | } | 805 | } |
| 737 | 806 | ||
| 738 | data = (nv_ro08(bios, rammap + 0x11) & 0x0c) >> 2; | 807 | ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); |
| 739 | ram_wr32(fuc, 0x10f65c, 0x00000011 * data); | 808 | ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); |
| 740 | ram_wr32(fuc, 0x10f6b8, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); | 809 | ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); |
| 741 | ram_wr32(fuc, 0x10f6bc, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); | ||
| 742 | 810 | ||
| 743 | mask = 0x00010000; | 811 | mask = 0x00010000; |
| 744 | data = 0x00000000; | 812 | data = 0x00000000; |
| 745 | if (!(nv_ro08(bios, ramcfg + 0x02) & 0x80)) | 813 | if (!(next->bios.ramcfg_11_02_80)) |
| 746 | data |= 0x03000000; | 814 | data |= 0x03000000; |
| 747 | if (!(nv_ro08(bios, ramcfg + 0x02) & 0x40)) | 815 | if (!(next->bios.ramcfg_11_02_40)) |
| 748 | data |= 0x00002000; | 816 | data |= 0x00002000; |
| 749 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x10)) | 817 | if (!(next->bios.ramcfg_11_07_10)) |
| 750 | data |= 0x00004000; | 818 | data |= 0x00004000; |
| 751 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) | 819 | if (!(next->bios.ramcfg_11_07_08)) |
| 752 | data |= 0x00000003; | 820 | data |= 0x00000003; |
| 753 | else | 821 | else |
| 754 | data |= 0x14000000; | 822 | data |= 0x14000000; |
| 755 | ram_mask(fuc, 0x10f824, mask, data); | 823 | ram_mask(fuc, 0x10f824, mask, data); |
| 756 | ram_nsec(fuc, 1000); | 824 | ram_nsec(fuc, 1000); |
| 757 | 825 | ||
| 758 | if (nv_ro08(bios, ramcfg + 0x08) & 0x01) | 826 | if (next->bios.ramcfg_11_08_01) |
| 759 | data = 0x00100000; | 827 | data = 0x00100000; |
| 760 | else | 828 | else |
| 761 | data = 0x00000000; | 829 | data = 0x00000000; |
| 762 | ram_mask(fuc, 0x10f82c, 0x00100000, data); | 830 | ram_mask(fuc, 0x10f82c, 0x00100000, data); |
| 763 | 831 | ||
| 764 | /* PFB timing */ | 832 | /* PFB timing */ |
| 765 | ram_mask(fuc, 0x10f248, 0xffffffff, nv_ro32(bios, timing + 0x28)); | 833 | ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); |
| 766 | ram_mask(fuc, 0x10f290, 0xffffffff, nv_ro32(bios, timing + 0x00)); | 834 | ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); |
| 767 | ram_mask(fuc, 0x10f294, 0xffffffff, nv_ro32(bios, timing + 0x04)); | 835 | ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); |
| 768 | ram_mask(fuc, 0x10f298, 0xffffffff, nv_ro32(bios, timing + 0x08)); | 836 | ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); |
| 769 | ram_mask(fuc, 0x10f29c, 0xffffffff, nv_ro32(bios, timing + 0x0c)); | 837 | ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); |
| 770 | ram_mask(fuc, 0x10f2a0, 0xffffffff, nv_ro32(bios, timing + 0x10)); | 838 | ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); |
| 771 | ram_mask(fuc, 0x10f2a4, 0xffffffff, nv_ro32(bios, timing + 0x14)); | 839 | ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); |
| 772 | ram_mask(fuc, 0x10f2a8, 0xffffffff, nv_ro32(bios, timing + 0x18)); | 840 | ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); |
| 773 | ram_mask(fuc, 0x10f2ac, 0xffffffff, nv_ro32(bios, timing + 0x1c)); | 841 | ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); |
| 774 | ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20)); | 842 | ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); |
| 775 | ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24)); | 843 | ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); |
| 776 | 844 | ||
| 777 | mask = 0x33f00000; | 845 | mask = 0x33f00000; |
| 778 | data = 0x00000000; | 846 | data = 0x00000000; |
| 779 | if (!(nv_ro08(bios, ramcfg + 0x01) & 0x04)) | 847 | if (!(next->bios.ramcfg_11_01_04)) |
| 780 | data |= 0x20200000; | 848 | data |= 0x20200000; |
| 781 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) | 849 | if (!(next->bios.ramcfg_11_07_80)) |
| 782 | data |= 0x12800000; | 850 | data |= 0x12800000; |
| 783 | /*XXX: see note above about there probably being some condition | 851 | /*XXX: see note above about there probably being some condition |
| 784 | * for the 10f824 stuff that uses ramcfg 3... | 852 | * for the 10f824 stuff that uses ramcfg 3... |
| 785 | */ | 853 | */ |
| 786 | if ( (nv_ro08(bios, ramcfg + 0x03) & 0xf0)) { | 854 | if ( (next->bios.ramcfg_11_03_f0)) { |
| 787 | if (nv_ro08(bios, rammap + 0x08) & 0x0c) { | 855 | if (next->bios.rammap_11_08_0c) { |
| 788 | if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) | 856 | if (!(next->bios.ramcfg_11_07_80)) |
| 789 | mask |= 0x00000020; | 857 | mask |= 0x00000020; |
| 790 | else | 858 | else |
| 791 | data |= 0x00000020; | 859 | data |= 0x00000020; |
| @@ -799,21 +867,16 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
| 799 | 867 | ||
| 800 | ram_mask(fuc, 0x10f808, mask, data); | 868 | ram_mask(fuc, 0x10f808, mask, data); |
| 801 | 869 | ||
| 802 | data = nv_ro08(bios, ramcfg + 0x03) & 0x0f; | 870 | ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); |
| 803 | ram_wr32(fuc, 0x10f870, 0x11111111 * data); | ||
| 804 | 871 | ||
| 805 | data = nv_ro16(bios, timing + 0x2c); | 872 | ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); |
| 806 | ram_mask(fuc, 0x10f250, 0x000003f0, (data & 0x003f) << 4); | ||
| 807 | 873 | ||
| 808 | if (((nv_ro32(bios, timing + 0x2c) & 0x00001fc0) >> 6) > | 874 | data = (next->bios.timing[10] & 0x7f000000) >> 24; |
| 809 | ((nv_ro32(bios, timing + 0x28) & 0x7f000000) >> 24)) | 875 | if (data < next->bios.timing_20_2c_1fc0) |
| 810 | data = (nv_ro32(bios, timing + 0x2c) & 0x00001fc0) >> 6; | 876 | data = next->bios.timing_20_2c_1fc0; |
| 811 | else | ||
| 812 | data = (nv_ro32(bios, timing + 0x28) & 0x1f000000) >> 24; | ||
| 813 | ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); | 877 | ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); |
| 814 | 878 | ||
| 815 | data = nv_ro08(bios, timing + 0x30); | 879 | ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8); |
| 816 | ram_mask(fuc, 0x10f224, 0x001f0000, (data & 0xf8) << 13); | ||
| 817 | 880 | ||
| 818 | ram_wr32(fuc, 0x10f090, 0x4000007f); | 881 | ram_wr32(fuc, 0x10f090, 0x4000007f); |
| 819 | ram_nsec(fuc, 1000); | 882 | ram_nsec(fuc, 1000); |
| @@ -855,7 +918,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
| 855 | 918 | ||
| 856 | ram_wr32(fuc, 0x62c000, 0x0f0f0f00); | 919 | ram_wr32(fuc, 0x62c000, 0x0f0f0f00); |
| 857 | 920 | ||
| 858 | if (nv_ro08(bios, rammap + 0x08) & 0x01) | 921 | if (next->bios.rammap_11_08_01) |
| 859 | data = 0x00000800; | 922 | data = 0x00000800; |
| 860 | else | 923 | else |
| 861 | data = 0x00000000; | 924 | data = 0x00000000; |
| @@ -868,21 +931,18 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) | |||
| 868 | ******************************************************************************/ | 931 | ******************************************************************************/ |
| 869 | 932 | ||
| 870 | static int | 933 | static int |
| 871 | nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | 934 | nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq, |
| 935 | struct nouveau_ram_data *data) | ||
| 872 | { | 936 | { |
| 873 | struct nouveau_bios *bios = nouveau_bios(pfb); | 937 | struct nouveau_bios *bios = nouveau_bios(pfb); |
| 874 | struct nve0_ram *ram = (void *)pfb->ram; | 938 | struct nve0_ram *ram = (void *)pfb->ram; |
| 875 | struct nve0_ramfuc *fuc = &ram->fuc; | 939 | u8 strap, cnt, len; |
| 876 | struct bit_entry M; | ||
| 877 | int ret, refclk, strap, i; | ||
| 878 | u32 data; | ||
| 879 | u8 cnt; | ||
| 880 | 940 | ||
| 881 | /* lookup memory config data relevant to the target frequency */ | 941 | /* lookup memory config data relevant to the target frequency */ |
| 882 | ram->base.rammap.data = nvbios_rammap_match(bios, freq / 1000, | 942 | ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000, |
| 883 | &ram->base.rammap.version, | 943 | &ram->base.rammap.version, |
| 884 | &ram->base.rammap.size, &cnt, | 944 | &ram->base.rammap.size, |
| 885 | &ram->base.ramcfg.size); | 945 | &cnt, &len, &data->bios); |
| 886 | if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 || | 946 | if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 || |
| 887 | ram->base.rammap.size < 0x09) { | 947 | ram->base.rammap.size < 0x09) { |
| 888 | nv_error(pfb, "invalid/missing rammap entry\n"); | 948 | nv_error(pfb, "invalid/missing rammap entry\n"); |
| @@ -890,24 +950,13 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 890 | } | 950 | } |
| 891 | 951 | ||
| 892 | /* locate specific data set for the attached memory */ | 952 | /* locate specific data set for the attached memory */ |
| 893 | if (bit_entry(bios, 'M', &M) || M.version != 2 || M.length < 3) { | 953 | ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data, |
| 894 | nv_error(pfb, "invalid/missing memory table\n"); | 954 | ram->base.rammap.version, |
| 895 | return -EINVAL; | 955 | ram->base.rammap.size, cnt, len, |
| 896 | } | 956 | nvbios_ramcfg_index(bios), |
| 897 | 957 | &ram->base.ramcfg.version, | |
| 898 | strap = (nv_rd32(pfb, 0x101000) & 0x0000003c) >> 2; | 958 | &ram->base.ramcfg.size, |
| 899 | data = nv_ro16(bios, M.offset + 1); | 959 | &data->bios); |
| 900 | if (data) | ||
| 901 | strap = nv_ro08(bios, data + strap); | ||
| 902 | |||
| 903 | if (strap >= cnt) { | ||
| 904 | nv_error(pfb, "invalid ramcfg strap\n"); | ||
| 905 | return -EINVAL; | ||
| 906 | } | ||
| 907 | |||
| 908 | ram->base.ramcfg.version = ram->base.rammap.version; | ||
| 909 | ram->base.ramcfg.data = ram->base.rammap.data + ram->base.rammap.size + | ||
| 910 | (ram->base.ramcfg.size * strap); | ||
| 911 | if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 || | 960 | if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 || |
| 912 | ram->base.ramcfg.size < 0x08) { | 961 | ram->base.ramcfg.size < 0x08) { |
| 913 | nv_error(pfb, "invalid/missing ramcfg entry\n"); | 962 | nv_error(pfb, "invalid/missing ramcfg entry\n"); |
| @@ -918,9 +967,9 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 918 | strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); | 967 | strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); |
| 919 | if (strap != 0xff) { | 968 | if (strap != 0xff) { |
| 920 | ram->base.timing.data = | 969 | ram->base.timing.data = |
| 921 | nvbios_timing_entry(bios, strap, | 970 | nvbios_timingEp(bios, strap, &ram->base.timing.version, |
| 922 | &ram->base.timing.version, | 971 | &ram->base.timing.size, &cnt, &len, |
| 923 | &ram->base.timing.size); | 972 | &data->bios); |
| 924 | if (!ram->base.timing.data || | 973 | if (!ram->base.timing.data || |
| 925 | ram->base.timing.version != 0x20 || | 974 | ram->base.timing.version != 0x20 || |
| 926 | ram->base.timing.size < 0x33) { | 975 | ram->base.timing.size < 0x33) { |
| @@ -931,11 +980,23 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 931 | ram->base.timing.data = 0; | 980 | ram->base.timing.data = 0; |
| 932 | } | 981 | } |
| 933 | 982 | ||
| 983 | data->freq = freq; | ||
| 984 | return 0; | ||
| 985 | } | ||
| 986 | |||
| 987 | static int | ||
| 988 | nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) | ||
| 989 | { | ||
| 990 | struct nve0_ram *ram = (void *)pfb->ram; | ||
| 991 | struct nve0_ramfuc *fuc = &ram->fuc; | ||
| 992 | int refclk, i; | ||
| 993 | int ret; | ||
| 994 | |||
| 934 | ret = ram_init(fuc, pfb); | 995 | ret = ram_init(fuc, pfb); |
| 935 | if (ret) | 996 | if (ret) |
| 936 | return ret; | 997 | return ret; |
| 937 | 998 | ||
| 938 | ram->mode = (freq > fuc->refpll.vco1.max_freq) ? 2 : 1; | 999 | ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; |
| 939 | ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; | 1000 | ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; |
| 940 | 1001 | ||
| 941 | /* XXX: this is *not* what nvidia do. on fermi nvidia generally | 1002 | /* XXX: this is *not* what nvidia do. on fermi nvidia generally |
| @@ -946,7 +1007,7 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 946 | * so far, i've seen very weird values being chosen by nvidia on | 1007 | * so far, i've seen very weird values being chosen by nvidia on |
| 947 | * kepler boards, no idea how/why they're chosen. | 1008 | * kepler boards, no idea how/why they're chosen. |
| 948 | */ | 1009 | */ |
| 949 | refclk = freq; | 1010 | refclk = next->freq; |
| 950 | if (ram->mode == 2) | 1011 | if (ram->mode == 2) |
| 951 | refclk = fuc->mempll.refclk; | 1012 | refclk = fuc->mempll.refclk; |
| 952 | 1013 | ||
| @@ -968,7 +1029,7 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 968 | fuc->mempll.min_p = 1; | 1029 | fuc->mempll.min_p = 1; |
| 969 | fuc->mempll.max_p = 2; | 1030 | fuc->mempll.max_p = 2; |
| 970 | 1031 | ||
| 971 | ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, freq, | 1032 | ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, |
| 972 | &ram->N2, NULL, &ram->M2, &ram->P2); | 1033 | &ram->N2, NULL, &ram->M2, &ram->P2); |
| 973 | if (ret <= 0) { | 1034 | if (ret <= 0) { |
| 974 | nv_error(pfb, "unable to calc mempll\n"); | 1035 | nv_error(pfb, "unable to calc mempll\n"); |
| @@ -980,17 +1041,18 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 980 | if (ram_have(fuc, mr[i])) | 1041 | if (ram_have(fuc, mr[i])) |
| 981 | ram->base.mr[i] = ram_rd32(fuc, mr[i]); | 1042 | ram->base.mr[i] = ram_rd32(fuc, mr[i]); |
| 982 | } | 1043 | } |
| 1044 | ram->base.freq = next->freq; | ||
| 983 | 1045 | ||
| 984 | switch (ram->base.type) { | 1046 | switch (ram->base.type) { |
| 985 | case NV_MEM_TYPE_DDR3: | 1047 | case NV_MEM_TYPE_DDR3: |
| 986 | ret = nouveau_sddr3_calc(&ram->base); | 1048 | ret = nouveau_sddr3_calc(&ram->base); |
| 987 | if (ret == 0) | 1049 | if (ret == 0) |
| 988 | ret = nve0_ram_calc_sddr3(pfb, freq); | 1050 | ret = nve0_ram_calc_sddr3(pfb, next->freq); |
| 989 | break; | 1051 | break; |
| 990 | case NV_MEM_TYPE_GDDR5: | 1052 | case NV_MEM_TYPE_GDDR5: |
| 991 | ret = nouveau_gddr5_calc(&ram->base); | 1053 | ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0); |
| 992 | if (ret == 0) | 1054 | if (ret == 0) |
| 993 | ret = nve0_ram_calc_gddr5(pfb, freq); | 1055 | ret = nve0_ram_calc_gddr5(pfb, next->freq); |
| 994 | break; | 1056 | break; |
| 995 | default: | 1057 | default: |
| 996 | ret = -ENOSYS; | 1058 | ret = -ENOSYS; |
| @@ -1001,13 +1063,55 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
| 1001 | } | 1063 | } |
| 1002 | 1064 | ||
| 1003 | static int | 1065 | static int |
| 1066 | nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) | ||
| 1067 | { | ||
| 1068 | struct nouveau_clock *clk = nouveau_clock(pfb); | ||
| 1069 | struct nve0_ram *ram = (void *)pfb->ram; | ||
| 1070 | struct nouveau_ram_data *xits = &ram->base.xition; | ||
| 1071 | struct nouveau_ram_data *copy; | ||
| 1072 | int ret; | ||
| 1073 | |||
| 1074 | if (ram->base.next == NULL) { | ||
| 1075 | ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), | ||
| 1076 | &ram->base.former); | ||
| 1077 | if (ret) | ||
| 1078 | return ret; | ||
| 1079 | |||
| 1080 | ret = nve0_ram_calc_data(pfb, freq, &ram->base.target); | ||
| 1081 | if (ret) | ||
| 1082 | return ret; | ||
| 1083 | |||
| 1084 | if (ram->base.target.freq < ram->base.former.freq) { | ||
| 1085 | *xits = ram->base.target; | ||
| 1086 | copy = &ram->base.former; | ||
| 1087 | } else { | ||
| 1088 | *xits = ram->base.former; | ||
| 1089 | copy = &ram->base.target; | ||
| 1090 | } | ||
| 1091 | |||
| 1092 | xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04; | ||
| 1093 | xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03; | ||
| 1094 | xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07; | ||
| 1095 | |||
| 1096 | ram->base.next = &ram->base.target; | ||
| 1097 | if (memcmp(xits, &ram->base.former, sizeof(xits->bios))) | ||
| 1098 | ram->base.next = &ram->base.xition; | ||
| 1099 | } else { | ||
| 1100 | BUG_ON(ram->base.next != &ram->base.xition); | ||
| 1101 | ram->base.next = &ram->base.target; | ||
| 1102 | } | ||
| 1103 | |||
| 1104 | return nve0_ram_calc_xits(pfb, ram->base.next); | ||
| 1105 | } | ||
| 1106 | |||
| 1107 | static int | ||
| 1004 | nve0_ram_prog(struct nouveau_fb *pfb) | 1108 | nve0_ram_prog(struct nouveau_fb *pfb) |
| 1005 | { | 1109 | { |
| 1006 | struct nouveau_device *device = nv_device(pfb); | 1110 | struct nouveau_device *device = nv_device(pfb); |
| 1007 | struct nve0_ram *ram = (void *)pfb->ram; | 1111 | struct nve0_ram *ram = (void *)pfb->ram; |
| 1008 | struct nve0_ramfuc *fuc = &ram->fuc; | 1112 | struct nve0_ramfuc *fuc = &ram->fuc; |
| 1009 | ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", false)); | 1113 | ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", false)); |
| 1010 | return 0; | 1114 | return (ram->base.next == &ram->base.xition); |
| 1011 | } | 1115 | } |
| 1012 | 1116 | ||
| 1013 | static void | 1117 | static void |
| @@ -1015,6 +1119,7 @@ nve0_ram_tidy(struct nouveau_fb *pfb) | |||
| 1015 | { | 1119 | { |
| 1016 | struct nve0_ram *ram = (void *)pfb->ram; | 1120 | struct nve0_ram *ram = (void *)pfb->ram; |
| 1017 | struct nve0_ramfuc *fuc = &ram->fuc; | 1121 | struct nve0_ramfuc *fuc = &ram->fuc; |
| 1122 | ram->base.next = NULL; | ||
| 1018 | ram_exec(fuc, false); | 1123 | ram_exec(fuc, false); |
| 1019 | } | 1124 | } |
| 1020 | 1125 | ||
| @@ -1055,7 +1160,7 @@ nve0_ram_init(struct nouveau_object *object) | |||
| 1055 | * binary driver skips the one that's already been setup by | 1160 | * binary driver skips the one that's already been setup by |
| 1056 | * the init tables. | 1161 | * the init tables. |
| 1057 | */ | 1162 | */ |
| 1058 | data = nvbios_rammap_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); | 1163 | data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); |
| 1059 | if (!data || hdr < 0x15) | 1164 | if (!data || hdr < 0x15) |
| 1060 | return -EINVAL; | 1165 | return -EINVAL; |
| 1061 | 1166 | ||
| @@ -1073,6 +1178,7 @@ nve0_ram_init(struct nouveau_object *object) | |||
| 1073 | data += 4; | 1178 | data += 4; |
| 1074 | } | 1179 | } |
| 1075 | nv_wr32(pfb, 0x10f65c, save); | 1180 | nv_wr32(pfb, 0x10f65c, save); |
| 1181 | nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); | ||
| 1076 | 1182 | ||
| 1077 | switch (ram->base.type) { | 1183 | switch (ram->base.type) { |
| 1078 | case NV_MEM_TYPE_GDDR5: | 1184 | case NV_MEM_TYPE_GDDR5: |
| @@ -1117,7 +1223,8 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 1117 | struct nouveau_gpio *gpio = nouveau_gpio(pfb); | 1223 | struct nouveau_gpio *gpio = nouveau_gpio(pfb); |
| 1118 | struct dcb_gpio_func func; | 1224 | struct dcb_gpio_func func; |
| 1119 | struct nve0_ram *ram; | 1225 | struct nve0_ram *ram; |
| 1120 | int ret; | 1226 | int ret, i; |
| 1227 | u32 tmp; | ||
| 1121 | 1228 | ||
| 1122 | ret = nvc0_ram_create(parent, engine, oclass, &ram); | 1229 | ret = nvc0_ram_create(parent, engine, oclass, &ram); |
| 1123 | *pobject = nv_object(ram); | 1230 | *pobject = nv_object(ram); |
| @@ -1136,6 +1243,25 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 1136 | break; | 1243 | break; |
| 1137 | } | 1244 | } |
| 1138 | 1245 | ||
| 1246 | /* calculate a mask of differently configured memory partitions, | ||
| 1247 | * because, of course reclocking wasn't complicated enough | ||
| 1248 | * already without having to treat some of them differently to | ||
| 1249 | * the others.... | ||
| 1250 | */ | ||
| 1251 | ram->parts = nv_rd32(pfb, 0x022438); | ||
| 1252 | ram->pmask = nv_rd32(pfb, 0x022554); | ||
| 1253 | ram->pnuts = 0; | ||
| 1254 | for (i = 0, tmp = 0; i < ram->parts; i++) { | ||
| 1255 | if (!(ram->pmask & (1 << i))) { | ||
| 1256 | u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000)); | ||
| 1257 | if (tmp && tmp != cfg1) { | ||
| 1258 | ram->pnuts |= (1 << i); | ||
| 1259 | continue; | ||
| 1260 | } | ||
| 1261 | tmp = cfg1; | ||
| 1262 | } | ||
| 1263 | } | ||
| 1264 | |||
| 1139 | // parse bios data for both pll's | 1265 | // parse bios data for both pll's |
| 1140 | ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); | 1266 | ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); |
| 1141 | if (ret) { | 1267 | if (ret) { |
| @@ -1248,7 +1374,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 1248 | ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c); | 1374 | ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c); |
| 1249 | ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc); | 1375 | ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc); |
| 1250 | ram->fuc.r_0x100710 = ramfuc_reg(0x100710); | 1376 | ram->fuc.r_0x100710 = ramfuc_reg(0x100710); |
| 1251 | ram->fuc.r_0x10f750 = ramfuc_reg(0x10f750); | 1377 | ram->fuc.r_0x100750 = ramfuc_reg(0x100750); |
| 1252 | return 0; | 1378 | return 0; |
| 1253 | } | 1379 | } |
| 1254 | 1380 | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c index 6565f3dbbe04..14706d9842ca 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c | |||
| @@ -22,7 +22,24 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <subdev/instmem.h> | 25 | #include "priv.h" |
| 26 | |||
| 27 | /****************************************************************************** | ||
| 28 | * instmem object base implementation | ||
| 29 | *****************************************************************************/ | ||
| 30 | |||
| 31 | void | ||
| 32 | _nouveau_instobj_dtor(struct nouveau_object *object) | ||
| 33 | { | ||
| 34 | struct nouveau_instmem *imem = (void *)object->engine; | ||
| 35 | struct nouveau_instobj *iobj = (void *)object; | ||
| 36 | |||
| 37 | mutex_lock(&nv_subdev(imem)->mutex); | ||
| 38 | list_del(&iobj->head); | ||
| 39 | mutex_unlock(&nv_subdev(imem)->mutex); | ||
| 40 | |||
| 41 | return nouveau_object_destroy(&iobj->base); | ||
| 42 | } | ||
| 26 | 43 | ||
| 27 | int | 44 | int |
| 28 | nouveau_instobj_create_(struct nouveau_object *parent, | 45 | nouveau_instobj_create_(struct nouveau_object *parent, |
| @@ -46,73 +63,26 @@ nouveau_instobj_create_(struct nouveau_object *parent, | |||
| 46 | return 0; | 63 | return 0; |
| 47 | } | 64 | } |
| 48 | 65 | ||
| 49 | void | 66 | /****************************************************************************** |
| 50 | nouveau_instobj_destroy(struct nouveau_instobj *iobj) | 67 | * instmem subdev base implementation |
| 51 | { | 68 | *****************************************************************************/ |
| 52 | struct nouveau_subdev *subdev = nv_subdev(iobj->base.engine); | ||
| 53 | 69 | ||
| 54 | mutex_lock(&subdev->mutex); | 70 | static int |
| 55 | list_del(&iobj->head); | 71 | nouveau_instmem_alloc(struct nouveau_instmem *imem, |
| 56 | mutex_unlock(&subdev->mutex); | 72 | struct nouveau_object *parent, u32 size, u32 align, |
| 57 | 73 | struct nouveau_object **pobject) | |
| 58 | return nouveau_object_destroy(&iobj->base); | ||
| 59 | } | ||
| 60 | |||
| 61 | void | ||
| 62 | _nouveau_instobj_dtor(struct nouveau_object *object) | ||
| 63 | { | 74 | { |
| 64 | struct nouveau_instobj *iobj = (void *)object; | 75 | struct nouveau_object *engine = nv_object(imem); |
| 65 | return nouveau_instobj_destroy(iobj); | 76 | struct nouveau_instmem_impl *impl = (void *)engine->oclass; |
| 77 | struct nouveau_instobj_args args = { .size = size, .align = align }; | ||
| 78 | return nouveau_object_ctor(parent, engine, impl->instobj, &args, | ||
| 79 | sizeof(args), pobject); | ||
| 66 | } | 80 | } |
| 67 | 81 | ||
| 68 | int | 82 | int |
| 69 | nouveau_instmem_create_(struct nouveau_object *parent, | 83 | _nouveau_instmem_fini(struct nouveau_object *object, bool suspend) |
| 70 | struct nouveau_object *engine, | ||
| 71 | struct nouveau_oclass *oclass, | ||
| 72 | int length, void **pobject) | ||
| 73 | { | ||
| 74 | struct nouveau_instmem *imem; | ||
| 75 | int ret; | ||
| 76 | |||
| 77 | ret = nouveau_subdev_create_(parent, engine, oclass, 0, | ||
| 78 | "INSTMEM", "instmem", length, pobject); | ||
| 79 | imem = *pobject; | ||
| 80 | if (ret) | ||
| 81 | return ret; | ||
| 82 | |||
| 83 | INIT_LIST_HEAD(&imem->list); | ||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | |||
| 87 | int | ||
| 88 | nouveau_instmem_init(struct nouveau_instmem *imem) | ||
| 89 | { | ||
| 90 | struct nouveau_instobj *iobj; | ||
| 91 | int ret, i; | ||
| 92 | |||
| 93 | ret = nouveau_subdev_init(&imem->base); | ||
| 94 | if (ret) | ||
| 95 | return ret; | ||
| 96 | |||
| 97 | mutex_lock(&imem->base.mutex); | ||
| 98 | |||
| 99 | list_for_each_entry(iobj, &imem->list, head) { | ||
| 100 | if (iobj->suspend) { | ||
| 101 | for (i = 0; i < iobj->size; i += 4) | ||
| 102 | nv_wo32(iobj, i, iobj->suspend[i / 4]); | ||
| 103 | vfree(iobj->suspend); | ||
| 104 | iobj->suspend = NULL; | ||
| 105 | } | ||
| 106 | } | ||
| 107 | |||
| 108 | mutex_unlock(&imem->base.mutex); | ||
| 109 | |||
| 110 | return 0; | ||
| 111 | } | ||
| 112 | |||
| 113 | int | ||
| 114 | nouveau_instmem_fini(struct nouveau_instmem *imem, bool suspend) | ||
| 115 | { | 84 | { |
| 85 | struct nouveau_instmem *imem = (void *)object; | ||
| 116 | struct nouveau_instobj *iobj; | 86 | struct nouveau_instobj *iobj; |
| 117 | int i, ret = 0; | 87 | int i, ret = 0; |
| 118 | 88 | ||
| @@ -143,12 +113,45 @@ int | |||
| 143 | _nouveau_instmem_init(struct nouveau_object *object) | 113 | _nouveau_instmem_init(struct nouveau_object *object) |
| 144 | { | 114 | { |
| 145 | struct nouveau_instmem *imem = (void *)object; | 115 | struct nouveau_instmem *imem = (void *)object; |
| 146 | return nouveau_instmem_init(imem); | 116 | struct nouveau_instobj *iobj; |
| 117 | int ret, i; | ||
| 118 | |||
| 119 | ret = nouveau_subdev_init(&imem->base); | ||
| 120 | if (ret) | ||
| 121 | return ret; | ||
| 122 | |||
| 123 | mutex_lock(&imem->base.mutex); | ||
| 124 | |||
| 125 | list_for_each_entry(iobj, &imem->list, head) { | ||
| 126 | if (iobj->suspend) { | ||
| 127 | for (i = 0; i < iobj->size; i += 4) | ||
| 128 | nv_wo32(iobj, i, iobj->suspend[i / 4]); | ||
| 129 | vfree(iobj->suspend); | ||
| 130 | iobj->suspend = NULL; | ||
| 131 | } | ||
| 132 | } | ||
| 133 | |||
| 134 | mutex_unlock(&imem->base.mutex); | ||
| 135 | |||
| 136 | return 0; | ||
| 147 | } | 137 | } |
| 148 | 138 | ||
| 149 | int | 139 | int |
| 150 | _nouveau_instmem_fini(struct nouveau_object *object, bool suspend) | 140 | nouveau_instmem_create_(struct nouveau_object *parent, |
| 141 | struct nouveau_object *engine, | ||
| 142 | struct nouveau_oclass *oclass, | ||
| 143 | int length, void **pobject) | ||
| 151 | { | 144 | { |
| 152 | struct nouveau_instmem *imem = (void *)object; | 145 | struct nouveau_instmem *imem; |
| 153 | return nouveau_instmem_fini(imem, suspend); | 146 | int ret; |
| 147 | |||
| 148 | ret = nouveau_subdev_create_(parent, engine, oclass, 0, | ||
| 149 | "INSTMEM", "instmem", length, pobject); | ||
| 150 | imem = *pobject; | ||
| 151 | if (ret) | ||
| 152 | return ret; | ||
| 153 | |||
| 154 | INIT_LIST_HEAD(&imem->list); | ||
| 155 | imem->alloc = nouveau_instmem_alloc; | ||
| 156 | return 0; | ||
| 154 | } | 157 | } |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c index 795393d7b2f5..7b64befee48f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c | |||
| @@ -22,10 +22,35 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <subdev/fb.h> | ||
| 26 | |||
| 27 | #include "nv04.h" | 25 | #include "nv04.h" |
| 28 | 26 | ||
| 27 | /****************************************************************************** | ||
| 28 | * instmem object implementation | ||
| 29 | *****************************************************************************/ | ||
| 30 | |||
| 31 | static u32 | ||
| 32 | nv04_instobj_rd32(struct nouveau_object *object, u64 addr) | ||
| 33 | { | ||
| 34 | struct nv04_instobj_priv *node = (void *)object; | ||
| 35 | return nv_ro32(object->engine, node->mem->offset + addr); | ||
| 36 | } | ||
| 37 | |||
| 38 | static void | ||
| 39 | nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data) | ||
| 40 | { | ||
| 41 | struct nv04_instobj_priv *node = (void *)object; | ||
| 42 | nv_wo32(object->engine, node->mem->offset + addr, data); | ||
| 43 | } | ||
| 44 | |||
| 45 | static void | ||
| 46 | nv04_instobj_dtor(struct nouveau_object *object) | ||
| 47 | { | ||
| 48 | struct nv04_instmem_priv *priv = (void *)object->engine; | ||
| 49 | struct nv04_instobj_priv *node = (void *)object; | ||
| 50 | nouveau_mm_free(&priv->heap, &node->mem); | ||
| 51 | nouveau_instobj_destroy(&node->base); | ||
| 52 | } | ||
| 53 | |||
| 29 | static int | 54 | static int |
| 30 | nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 55 | nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 31 | struct nouveau_oclass *oclass, void *data, u32 size, | 56 | struct nouveau_oclass *oclass, void *data, u32 size, |
| @@ -33,18 +58,19 @@ nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 33 | { | 58 | { |
| 34 | struct nv04_instmem_priv *priv = (void *)engine; | 59 | struct nv04_instmem_priv *priv = (void *)engine; |
| 35 | struct nv04_instobj_priv *node; | 60 | struct nv04_instobj_priv *node; |
| 36 | int ret, align; | 61 | struct nouveau_instobj_args *args = data; |
| 62 | int ret; | ||
| 37 | 63 | ||
| 38 | align = (unsigned long)data; | 64 | if (!args->align) |
| 39 | if (!align) | 65 | args->align = 1; |
| 40 | align = 1; | ||
| 41 | 66 | ||
| 42 | ret = nouveau_instobj_create(parent, engine, oclass, &node); | 67 | ret = nouveau_instobj_create(parent, engine, oclass, &node); |
| 43 | *pobject = nv_object(node); | 68 | *pobject = nv_object(node); |
| 44 | if (ret) | 69 | if (ret) |
| 45 | return ret; | 70 | return ret; |
| 46 | 71 | ||
| 47 | ret = nouveau_mm_head(&priv->heap, 1, size, size, align, &node->mem); | 72 | ret = nouveau_mm_head(&priv->heap, 1, args->size, args->size, |
| 73 | args->align, &node->mem); | ||
| 48 | if (ret) | 74 | if (ret) |
| 49 | return ret; | 75 | return ret; |
| 50 | 76 | ||
| @@ -53,32 +79,9 @@ nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 53 | return 0; | 79 | return 0; |
| 54 | } | 80 | } |
| 55 | 81 | ||
| 56 | static void | 82 | struct nouveau_instobj_impl |
| 57 | nv04_instobj_dtor(struct nouveau_object *object) | ||
| 58 | { | ||
| 59 | struct nv04_instmem_priv *priv = (void *)object->engine; | ||
| 60 | struct nv04_instobj_priv *node = (void *)object; | ||
| 61 | nouveau_mm_free(&priv->heap, &node->mem); | ||
| 62 | nouveau_instobj_destroy(&node->base); | ||
| 63 | } | ||
| 64 | |||
| 65 | static u32 | ||
| 66 | nv04_instobj_rd32(struct nouveau_object *object, u64 addr) | ||
| 67 | { | ||
| 68 | struct nv04_instobj_priv *node = (void *)object; | ||
| 69 | return nv_ro32(object->engine, node->mem->offset + addr); | ||
| 70 | } | ||
| 71 | |||
| 72 | static void | ||
| 73 | nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data) | ||
| 74 | { | ||
| 75 | struct nv04_instobj_priv *node = (void *)object; | ||
| 76 | nv_wo32(object->engine, node->mem->offset + addr, data); | ||
| 77 | } | ||
| 78 | |||
| 79 | static struct nouveau_oclass | ||
| 80 | nv04_instobj_oclass = { | 83 | nv04_instobj_oclass = { |
| 81 | .ofuncs = &(struct nouveau_ofuncs) { | 84 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 82 | .ctor = nv04_instobj_ctor, | 85 | .ctor = nv04_instobj_ctor, |
| 83 | .dtor = nv04_instobj_dtor, | 86 | .dtor = nv04_instobj_dtor, |
| 84 | .init = _nouveau_instobj_init, | 87 | .init = _nouveau_instobj_init, |
| @@ -88,19 +91,34 @@ nv04_instobj_oclass = { | |||
| 88 | }, | 91 | }, |
| 89 | }; | 92 | }; |
| 90 | 93 | ||
| 91 | int | 94 | /****************************************************************************** |
| 92 | nv04_instmem_alloc(struct nouveau_instmem *imem, struct nouveau_object *parent, | 95 | * instmem subdev implementation |
| 93 | u32 size, u32 align, struct nouveau_object **pobject) | 96 | *****************************************************************************/ |
| 97 | |||
| 98 | static u32 | ||
| 99 | nv04_instmem_rd32(struct nouveau_object *object, u64 addr) | ||
| 94 | { | 100 | { |
| 95 | struct nouveau_object *engine = nv_object(imem); | 101 | return nv_rd32(object, 0x700000 + addr); |
| 96 | int ret; | 102 | } |
| 97 | 103 | ||
| 98 | ret = nouveau_object_ctor(parent, engine, &nv04_instobj_oclass, | 104 | static void |
| 99 | (void *)(unsigned long)align, size, pobject); | 105 | nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) |
| 100 | if (ret) | 106 | { |
| 101 | return ret; | 107 | return nv_wr32(object, 0x700000 + addr, data); |
| 108 | } | ||
| 102 | 109 | ||
| 103 | return 0; | 110 | void |
| 111 | nv04_instmem_dtor(struct nouveau_object *object) | ||
| 112 | { | ||
| 113 | struct nv04_instmem_priv *priv = (void *)object; | ||
| 114 | nouveau_gpuobj_ref(NULL, &priv->ramfc); | ||
| 115 | nouveau_gpuobj_ref(NULL, &priv->ramro); | ||
| 116 | nouveau_ramht_ref(NULL, &priv->ramht); | ||
| 117 | nouveau_gpuobj_ref(NULL, &priv->vbios); | ||
| 118 | nouveau_mm_fini(&priv->heap); | ||
| 119 | if (priv->iomem) | ||
| 120 | iounmap(priv->iomem); | ||
| 121 | nouveau_instmem_destroy(&priv->base); | ||
| 104 | } | 122 | } |
| 105 | 123 | ||
| 106 | static int | 124 | static int |
| @@ -118,7 +136,6 @@ nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 118 | 136 | ||
| 119 | /* PRAMIN aperture maps over the end of VRAM, reserve it */ | 137 | /* PRAMIN aperture maps over the end of VRAM, reserve it */ |
| 120 | priv->base.reserved = 512 * 1024; | 138 | priv->base.reserved = 512 * 1024; |
| 121 | priv->base.alloc = nv04_instmem_alloc; | ||
| 122 | 139 | ||
| 123 | ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); | 140 | ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); |
| 124 | if (ret) | 141 | if (ret) |
| @@ -150,36 +167,10 @@ nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 150 | return 0; | 167 | return 0; |
| 151 | } | 168 | } |
| 152 | 169 | ||
| 153 | void | 170 | struct nouveau_oclass * |
| 154 | nv04_instmem_dtor(struct nouveau_object *object) | 171 | nv04_instmem_oclass = &(struct nouveau_instmem_impl) { |
| 155 | { | 172 | .base.handle = NV_SUBDEV(INSTMEM, 0x04), |
| 156 | struct nv04_instmem_priv *priv = (void *)object; | 173 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 157 | nouveau_gpuobj_ref(NULL, &priv->ramfc); | ||
| 158 | nouveau_gpuobj_ref(NULL, &priv->ramro); | ||
| 159 | nouveau_ramht_ref(NULL, &priv->ramht); | ||
| 160 | nouveau_gpuobj_ref(NULL, &priv->vbios); | ||
| 161 | nouveau_mm_fini(&priv->heap); | ||
| 162 | if (priv->iomem) | ||
| 163 | iounmap(priv->iomem); | ||
| 164 | nouveau_instmem_destroy(&priv->base); | ||
| 165 | } | ||
| 166 | |||
| 167 | static u32 | ||
| 168 | nv04_instmem_rd32(struct nouveau_object *object, u64 addr) | ||
| 169 | { | ||
| 170 | return nv_rd32(object, 0x700000 + addr); | ||
| 171 | } | ||
| 172 | |||
| 173 | static void | ||
| 174 | nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) | ||
| 175 | { | ||
| 176 | return nv_wr32(object, 0x700000 + addr, data); | ||
| 177 | } | ||
| 178 | |||
| 179 | struct nouveau_oclass | ||
| 180 | nv04_instmem_oclass = { | ||
| 181 | .handle = NV_SUBDEV(INSTMEM, 0x04), | ||
| 182 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 183 | .ctor = nv04_instmem_ctor, | 174 | .ctor = nv04_instmem_ctor, |
| 184 | .dtor = nv04_instmem_dtor, | 175 | .dtor = nv04_instmem_dtor, |
| 185 | .init = _nouveau_instmem_init, | 176 | .init = _nouveau_instmem_init, |
| @@ -187,4 +178,5 @@ nv04_instmem_oclass = { | |||
| 187 | .rd32 = nv04_instmem_rd32, | 178 | .rd32 = nv04_instmem_rd32, |
| 188 | .wr32 = nv04_instmem_wr32, | 179 | .wr32 = nv04_instmem_wr32, |
| 189 | }, | 180 | }, |
| 190 | }; | 181 | .instobj = &nv04_instobj_oclass.base, |
| 182 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h index b15b61310236..095fbc6fc099 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h | |||
| @@ -5,7 +5,9 @@ | |||
| 5 | #include <core/ramht.h> | 5 | #include <core/ramht.h> |
| 6 | #include <core/mm.h> | 6 | #include <core/mm.h> |
| 7 | 7 | ||
| 8 | #include <subdev/instmem.h> | 8 | #include "priv.h" |
| 9 | |||
| 10 | extern struct nouveau_instobj_impl nv04_instobj_oclass; | ||
| 9 | 11 | ||
| 10 | struct nv04_instmem_priv { | 12 | struct nv04_instmem_priv { |
| 11 | struct nouveau_instmem base; | 13 | struct nouveau_instmem base; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c index b10a143787a7..ec0b9661d614 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c | |||
| @@ -26,6 +26,24 @@ | |||
| 26 | 26 | ||
| 27 | #include "nv04.h" | 27 | #include "nv04.h" |
| 28 | 28 | ||
| 29 | /****************************************************************************** | ||
| 30 | * instmem subdev implementation | ||
| 31 | *****************************************************************************/ | ||
| 32 | |||
| 33 | static u32 | ||
| 34 | nv40_instmem_rd32(struct nouveau_object *object, u64 addr) | ||
| 35 | { | ||
| 36 | struct nv04_instmem_priv *priv = (void *)object; | ||
| 37 | return ioread32_native(priv->iomem + addr); | ||
| 38 | } | ||
| 39 | |||
| 40 | static void | ||
| 41 | nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) | ||
| 42 | { | ||
| 43 | struct nv04_instmem_priv *priv = (void *)object; | ||
| 44 | iowrite32_native(data, priv->iomem + addr); | ||
| 45 | } | ||
| 46 | |||
| 29 | static int | 47 | static int |
| 30 | nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 48 | nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
| 31 | struct nouveau_oclass *oclass, void *data, u32 size, | 49 | struct nouveau_oclass *oclass, void *data, u32 size, |
| @@ -69,7 +87,6 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 69 | priv->base.reserved += 512 * 1024; /* object storage */ | 87 | priv->base.reserved += 512 * 1024; /* object storage */ |
| 70 | 88 | ||
| 71 | priv->base.reserved = round_up(priv->base.reserved, 4096); | 89 | priv->base.reserved = round_up(priv->base.reserved, 4096); |
| 72 | priv->base.alloc = nv04_instmem_alloc; | ||
| 73 | 90 | ||
| 74 | ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); | 91 | ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); |
| 75 | if (ret) | 92 | if (ret) |
| @@ -106,24 +123,10 @@ nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 106 | return 0; | 123 | return 0; |
| 107 | } | 124 | } |
| 108 | 125 | ||
| 109 | static u32 | 126 | struct nouveau_oclass * |
| 110 | nv40_instmem_rd32(struct nouveau_object *object, u64 addr) | 127 | nv40_instmem_oclass = &(struct nouveau_instmem_impl) { |
| 111 | { | 128 | .base.handle = NV_SUBDEV(INSTMEM, 0x40), |
| 112 | struct nv04_instmem_priv *priv = (void *)object; | 129 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 113 | return ioread32_native(priv->iomem + addr); | ||
| 114 | } | ||
| 115 | |||
| 116 | static void | ||
| 117 | nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) | ||
| 118 | { | ||
| 119 | struct nv04_instmem_priv *priv = (void *)object; | ||
| 120 | iowrite32_native(data, priv->iomem + addr); | ||
| 121 | } | ||
| 122 | |||
| 123 | struct nouveau_oclass | ||
| 124 | nv40_instmem_oclass = { | ||
| 125 | .handle = NV_SUBDEV(INSTMEM, 0x40), | ||
| 126 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 127 | .ctor = nv40_instmem_ctor, | 130 | .ctor = nv40_instmem_ctor, |
| 128 | .dtor = nv04_instmem_dtor, | 131 | .dtor = nv04_instmem_dtor, |
| 129 | .init = _nouveau_instmem_init, | 132 | .init = _nouveau_instmem_init, |
| @@ -131,4 +134,5 @@ nv40_instmem_oclass = { | |||
| 131 | .rd32 = nv40_instmem_rd32, | 134 | .rd32 = nv40_instmem_rd32, |
| 132 | .wr32 = nv40_instmem_wr32, | 135 | .wr32 = nv40_instmem_wr32, |
| 133 | }, | 136 | }, |
| 134 | }; | 137 | .instobj = &nv04_instobj_oclass.base, |
| 138 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c index 97bc5dff93e7..7cb3b098a08d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c | |||
| @@ -22,11 +22,11 @@ | |||
| 22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <subdev/instmem.h> | ||
| 26 | #include <subdev/fb.h> | 25 | #include <subdev/fb.h> |
| 27 | |||
| 28 | #include <core/mm.h> | 26 | #include <core/mm.h> |
| 29 | 27 | ||
| 28 | #include "priv.h" | ||
| 29 | |||
| 30 | struct nv50_instmem_priv { | 30 | struct nv50_instmem_priv { |
| 31 | struct nouveau_instmem base; | 31 | struct nouveau_instmem base; |
| 32 | spinlock_t lock; | 32 | spinlock_t lock; |
| @@ -38,42 +38,9 @@ struct nv50_instobj_priv { | |||
| 38 | struct nouveau_mem *mem; | 38 | struct nouveau_mem *mem; |
| 39 | }; | 39 | }; |
| 40 | 40 | ||
| 41 | static int | 41 | /****************************************************************************** |
| 42 | nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 42 | * instmem object implementation |
| 43 | struct nouveau_oclass *oclass, void *data, u32 size, | 43 | *****************************************************************************/ |
| 44 | struct nouveau_object **pobject) | ||
| 45 | { | ||
| 46 | struct nouveau_fb *pfb = nouveau_fb(parent); | ||
| 47 | struct nv50_instobj_priv *node; | ||
| 48 | u32 align = (unsigned long)data; | ||
| 49 | int ret; | ||
| 50 | |||
| 51 | size = max((size + 4095) & ~4095, (u32)4096); | ||
| 52 | align = max((align + 4095) & ~4095, (u32)4096); | ||
| 53 | |||
| 54 | ret = nouveau_instobj_create(parent, engine, oclass, &node); | ||
| 55 | *pobject = nv_object(node); | ||
| 56 | if (ret) | ||
| 57 | return ret; | ||
| 58 | |||
| 59 | ret = pfb->ram->get(pfb, size, align, 0, 0x800, &node->mem); | ||
| 60 | if (ret) | ||
| 61 | return ret; | ||
| 62 | |||
| 63 | node->base.addr = node->mem->offset; | ||
| 64 | node->base.size = node->mem->size << 12; | ||
| 65 | node->mem->page_shift = 12; | ||
| 66 | return 0; | ||
| 67 | } | ||
| 68 | |||
| 69 | static void | ||
| 70 | nv50_instobj_dtor(struct nouveau_object *object) | ||
| 71 | { | ||
| 72 | struct nv50_instobj_priv *node = (void *)object; | ||
| 73 | struct nouveau_fb *pfb = nouveau_fb(object); | ||
| 74 | pfb->ram->put(pfb, &node->mem); | ||
| 75 | nouveau_instobj_destroy(&node->base); | ||
| 76 | } | ||
| 77 | 44 | ||
| 78 | static u32 | 45 | static u32 |
| 79 | nv50_instobj_rd32(struct nouveau_object *object, u64 offset) | 46 | nv50_instobj_rd32(struct nouveau_object *object, u64 offset) |
| @@ -113,9 +80,46 @@ nv50_instobj_wr32(struct nouveau_object *object, u64 offset, u32 data) | |||
| 113 | spin_unlock_irqrestore(&priv->lock, flags); | 80 | spin_unlock_irqrestore(&priv->lock, flags); |
| 114 | } | 81 | } |
| 115 | 82 | ||
| 116 | static struct nouveau_oclass | 83 | static void |
| 84 | nv50_instobj_dtor(struct nouveau_object *object) | ||
| 85 | { | ||
| 86 | struct nv50_instobj_priv *node = (void *)object; | ||
| 87 | struct nouveau_fb *pfb = nouveau_fb(object); | ||
| 88 | pfb->ram->put(pfb, &node->mem); | ||
| 89 | nouveau_instobj_destroy(&node->base); | ||
| 90 | } | ||
| 91 | |||
| 92 | static int | ||
| 93 | nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | ||
| 94 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
| 95 | struct nouveau_object **pobject) | ||
| 96 | { | ||
| 97 | struct nouveau_fb *pfb = nouveau_fb(parent); | ||
| 98 | struct nouveau_instobj_args *args = data; | ||
| 99 | struct nv50_instobj_priv *node; | ||
| 100 | int ret; | ||
| 101 | |||
| 102 | args->size = max((args->size + 4095) & ~4095, (u32)4096); | ||
| 103 | args->align = max((args->align + 4095) & ~4095, (u32)4096); | ||
| 104 | |||
| 105 | ret = nouveau_instobj_create(parent, engine, oclass, &node); | ||
| 106 | *pobject = nv_object(node); | ||
| 107 | if (ret) | ||
| 108 | return ret; | ||
| 109 | |||
| 110 | ret = pfb->ram->get(pfb, args->size, args->align, 0, 0x800, &node->mem); | ||
| 111 | if (ret) | ||
| 112 | return ret; | ||
| 113 | |||
| 114 | node->base.addr = node->mem->offset; | ||
| 115 | node->base.size = node->mem->size << 12; | ||
| 116 | node->mem->page_shift = 12; | ||
| 117 | return 0; | ||
| 118 | } | ||
| 119 | |||
| 120 | static struct nouveau_instobj_impl | ||
| 117 | nv50_instobj_oclass = { | 121 | nv50_instobj_oclass = { |
| 118 | .ofuncs = &(struct nouveau_ofuncs) { | 122 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 119 | .ctor = nv50_instobj_ctor, | 123 | .ctor = nv50_instobj_ctor, |
| 120 | .dtor = nv50_instobj_dtor, | 124 | .dtor = nv50_instobj_dtor, |
| 121 | .init = _nouveau_instobj_init, | 125 | .init = _nouveau_instobj_init, |
| @@ -125,13 +129,16 @@ nv50_instobj_oclass = { | |||
| 125 | }, | 129 | }, |
| 126 | }; | 130 | }; |
| 127 | 131 | ||
| 132 | /****************************************************************************** | ||
| 133 | * instmem subdev implementation | ||
| 134 | *****************************************************************************/ | ||
| 135 | |||
| 128 | static int | 136 | static int |
| 129 | nv50_instmem_alloc(struct nouveau_instmem *imem, struct nouveau_object *parent, | 137 | nv50_instmem_fini(struct nouveau_object *object, bool suspend) |
| 130 | u32 size, u32 align, struct nouveau_object **pobject) | ||
| 131 | { | 138 | { |
| 132 | struct nouveau_object *engine = nv_object(imem); | 139 | struct nv50_instmem_priv *priv = (void *)object; |
| 133 | return nouveau_object_ctor(parent, engine, &nv50_instobj_oclass, | 140 | priv->addr = ~0ULL; |
| 134 | (void *)(unsigned long)align, size, pobject); | 141 | return nouveau_instmem_fini(&priv->base, suspend); |
| 135 | } | 142 | } |
| 136 | 143 | ||
| 137 | static int | 144 | static int |
| @@ -148,25 +155,17 @@ nv50_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
| 148 | return ret; | 155 | return ret; |
| 149 | 156 | ||
| 150 | spin_lock_init(&priv->lock); | 157 | spin_lock_init(&priv->lock); |
| 151 | priv->base.alloc = nv50_instmem_alloc; | ||
| 152 | return 0; | 158 | return 0; |
| 153 | } | 159 | } |
| 154 | 160 | ||
| 155 | static int | 161 | struct nouveau_oclass * |
| 156 | nv50_instmem_fini(struct nouveau_object *object, bool suspend) | 162 | nv50_instmem_oclass = &(struct nouveau_instmem_impl) { |
| 157 | { | 163 | .base.handle = NV_SUBDEV(INSTMEM, 0x50), |
| 158 | struct nv50_instmem_priv *priv = (void *)object; | 164 | .base.ofuncs = &(struct nouveau_ofuncs) { |
| 159 | priv->addr = ~0ULL; | ||
| 160 | return nouveau_instmem_fini(&priv->base, suspend); | ||
| 161 | } | ||
| 162 | |||
| 163 | struct nouveau_oclass | ||
| 164 | nv50_instmem_oclass = { | ||
| 165 | .handle = NV_SUBDEV(INSTMEM, 0x50), | ||
| 166 | .ofuncs = &(struct nouveau_ofuncs) { | ||
| 167 | .ctor = nv50_instmem_ctor, | 165 | .ctor = nv50_instmem_ctor, |
| 168 | .dtor = _nouveau_instmem_dtor, | 166 | .dtor = _nouveau_instmem_dtor, |
| 169 | .init = _nouveau_instmem_init, | 167 | .init = _nouveau_instmem_init, |
| 170 | .fini = nv50_instmem_fini, | 168 | .fini = nv50_instmem_fini, |
| 171 | }, | 169 | }, |
| 172 | }; | 170 | .instobj = &nv50_instobj_oclass.base, |
| 171 | }.base; | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h new file mode 100644 index 000000000000..8d67dedc5bb2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | #ifndef __NVKM_INSTMEM_PRIV_H__ | ||
| 2 | #define __NVKM_INSTMEM_PRIV_H__ | ||
| 3 | |||
| 4 | #include <subdev/instmem.h> | ||
| 5 | |||
| 6 | struct nouveau_instobj_impl { | ||
| 7 | struct nouveau_oclass base; | ||
| 8 | }; | ||
| 9 | |||
| 10 | struct nouveau_instobj_args { | ||
| 11 | u32 size; | ||
| 12 | u32 align; | ||
| 13 | }; | ||
| 14 | |||
| 15 | #define nouveau_instobj_create(p,e,o,d) \ | ||
| 16 | nouveau_instobj_create_((p), (e), (o), sizeof(**d), (void **)d) | ||
| 17 | #define nouveau_instobj_destroy(p) ({ \ | ||
| 18 | struct nouveau_instobj *iobj = (p); \ | ||
| 19 | _nouveau_instobj_dtor(nv_object(iobj)); \ | ||
| 20 | }) | ||
| 21 | #define nouveau_instobj_init(p) \ | ||
| 22 | nouveau_object_init(&(p)->base) | ||
| 23 | #define nouveau_instobj_fini(p,s) \ | ||
| 24 | nouveau_object_fini(&(p)->base, (s)) | ||
| 25 | |||
| 26 | int nouveau_instobj_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 27 | struct nouveau_oclass *, int, void **); | ||
| 28 | void _nouveau_instobj_dtor(struct nouveau_object *); | ||
| 29 | #define _nouveau_instobj_init nouveau_object_init | ||
| 30 | #define _nouveau_instobj_fini nouveau_object_fini | ||
| 31 | |||
| 32 | struct nouveau_instmem_impl { | ||
| 33 | struct nouveau_oclass base; | ||
| 34 | struct nouveau_oclass *instobj; | ||
| 35 | }; | ||
| 36 | |||
| 37 | #define nouveau_instmem_create(p,e,o,d) \ | ||
| 38 | nouveau_instmem_create_((p), (e), (o), sizeof(**d), (void **)d) | ||
| 39 | #define nouveau_instmem_destroy(p) \ | ||
| 40 | nouveau_subdev_destroy(&(p)->base) | ||
| 41 | #define nouveau_instmem_init(p) ({ \ | ||
| 42 | struct nouveau_instmem *imem = (p); \ | ||
| 43 | _nouveau_instmem_init(nv_object(imem)); \ | ||
| 44 | }) | ||
| 45 | #define nouveau_instmem_fini(p,s) ({ \ | ||
| 46 | struct nouveau_instmem *imem = (p); \ | ||
| 47 | _nouveau_instmem_fini(nv_object(imem), (s)); \ | ||
| 48 | }) | ||
| 49 | |||
| 50 | int nouveau_instmem_create_(struct nouveau_object *, struct nouveau_object *, | ||
| 51 | struct nouveau_oclass *, int, void **); | ||
| 52 | #define _nouveau_instmem_dtor _nouveau_subdev_dtor | ||
| 53 | int _nouveau_instmem_init(struct nouveau_object *); | ||
| 54 | int _nouveau_instmem_fini(struct nouveau_object *, bool); | ||
| 55 | |||
| 56 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c index c02b4763a2d5..34472d317097 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c | |||
| @@ -32,6 +32,7 @@ nvc0_mc_intr[] = { | |||
| 32 | { 0x00000080, NVDEV_ENGINE_COPY2 }, | 32 | { 0x00000080, NVDEV_ENGINE_COPY2 }, |
| 33 | { 0x00000100, NVDEV_ENGINE_FIFO }, | 33 | { 0x00000100, NVDEV_ENGINE_FIFO }, |
| 34 | { 0x00001000, NVDEV_ENGINE_GR }, | 34 | { 0x00001000, NVDEV_ENGINE_GR }, |
| 35 | { 0x00002000, NVDEV_SUBDEV_FB }, | ||
| 35 | { 0x00008000, NVDEV_ENGINE_BSP }, | 36 | { 0x00008000, NVDEV_ENGINE_BSP }, |
| 36 | { 0x00040000, NVDEV_SUBDEV_THERM }, | 37 | { 0x00040000, NVDEV_SUBDEV_THERM }, |
| 37 | { 0x00020000, NVDEV_ENGINE_VP }, | 38 | { 0x00020000, NVDEV_ENGINE_VP }, |
| @@ -40,6 +41,7 @@ nvc0_mc_intr[] = { | |||
| 40 | { 0x01000000, NVDEV_SUBDEV_PWR }, | 41 | { 0x01000000, NVDEV_SUBDEV_PWR }, |
| 41 | { 0x02000000, NVDEV_SUBDEV_LTCG }, | 42 | { 0x02000000, NVDEV_SUBDEV_LTCG }, |
| 42 | { 0x04000000, NVDEV_ENGINE_DISP }, | 43 | { 0x04000000, NVDEV_ENGINE_DISP }, |
| 44 | { 0x08000000, NVDEV_SUBDEV_FB }, | ||
| 43 | { 0x10000000, NVDEV_SUBDEV_BUS }, | 45 | { 0x10000000, NVDEV_SUBDEV_BUS }, |
| 44 | { 0x40000000, NVDEV_SUBDEV_IBUS }, | 46 | { 0x40000000, NVDEV_SUBDEV_IBUS }, |
| 45 | { 0x80000000, NVDEV_ENGINE_SW }, | 47 | { 0x80000000, NVDEV_ENGINE_SW }, |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc new file mode 100644 index 000000000000..757dda700024 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc | |||
| @@ -0,0 +1,393 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Red Hat Inc. | ||
| 3 | * | ||
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
| 5 | * copy of this software and associated documentation files (the "Software"), | ||
| 6 | * to deal in the Software without restriction, including without limitation | ||
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
| 9 | * Software is furnished to do so, subject to the following conditions: | ||
| 10 | * | ||
| 11 | * The above copyright notice and this permission notice shall be included in | ||
| 12 | * all copies or substantial portions of the Software. | ||
| 13 | * | ||
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
| 21 | * | ||
| 22 | * Authors: Ben Skeggs | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define T_TIMEOUT 2200000 | ||
| 26 | #define T_RISEFALL 1000 | ||
| 27 | #define T_HOLD 5000 | ||
| 28 | |||
| 29 | #ifdef INCLUDE_PROC | ||
| 30 | process(PROC_I2C_, #i2c_init, #i2c_recv) | ||
| 31 | #endif | ||
| 32 | |||
| 33 | /****************************************************************************** | ||
| 34 | * I2C_ data segment | ||
| 35 | *****************************************************************************/ | ||
| 36 | #ifdef INCLUDE_DATA | ||
| 37 | i2c_scl_map: | ||
| 38 | .b32 NV_PPWR_OUTPUT_I2C_0_SCL | ||
| 39 | .b32 NV_PPWR_OUTPUT_I2C_1_SCL | ||
| 40 | .b32 NV_PPWR_OUTPUT_I2C_2_SCL | ||
| 41 | .b32 NV_PPWR_OUTPUT_I2C_3_SCL | ||
| 42 | .b32 NV_PPWR_OUTPUT_I2C_4_SCL | ||
| 43 | .b32 NV_PPWR_OUTPUT_I2C_5_SCL | ||
| 44 | .b32 NV_PPWR_OUTPUT_I2C_6_SCL | ||
| 45 | .b32 NV_PPWR_OUTPUT_I2C_7_SCL | ||
| 46 | .b32 NV_PPWR_OUTPUT_I2C_8_SCL | ||
| 47 | .b32 NV_PPWR_OUTPUT_I2C_9_SCL | ||
| 48 | i2c_sda_map: | ||
| 49 | .b32 NV_PPWR_OUTPUT_I2C_0_SDA | ||
| 50 | .b32 NV_PPWR_OUTPUT_I2C_1_SDA | ||
| 51 | .b32 NV_PPWR_OUTPUT_I2C_2_SDA | ||
| 52 | .b32 NV_PPWR_OUTPUT_I2C_3_SDA | ||
| 53 | .b32 NV_PPWR_OUTPUT_I2C_4_SDA | ||
| 54 | .b32 NV_PPWR_OUTPUT_I2C_5_SDA | ||
| 55 | .b32 NV_PPWR_OUTPUT_I2C_6_SDA | ||
| 56 | .b32 NV_PPWR_OUTPUT_I2C_7_SDA | ||
| 57 | .b32 NV_PPWR_OUTPUT_I2C_8_SDA | ||
| 58 | .b32 NV_PPWR_OUTPUT_I2C_9_SDA | ||
| 59 | #if NVKM_PPWR_CHIPSET < GF119 | ||
| 60 | i2c_ctrl: | ||
| 61 | .b32 0x00e138 | ||
| 62 | .b32 0x00e150 | ||
| 63 | .b32 0x00e168 | ||
| 64 | .b32 0x00e180 | ||
| 65 | .b32 0x00e254 | ||
| 66 | .b32 0x00e274 | ||
| 67 | .b32 0x00e764 | ||
| 68 | .b32 0x00e780 | ||
| 69 | .b32 0x00e79c | ||
| 70 | .b32 0x00e7b8 | ||
| 71 | #endif | ||
| 72 | #endif | ||
| 73 | |||
| 74 | /****************************************************************************** | ||
| 75 | * I2C_ code segment | ||
| 76 | *****************************************************************************/ | ||
| 77 | #ifdef INCLUDE_CODE | ||
| 78 | |||
| 79 | // $r3 - value | ||
| 80 | // $r2 - sda line | ||
| 81 | // $r1 - scl line | ||
| 82 | // $r0 - zero | ||
| 83 | i2c_drive_scl: | ||
| 84 | cmp b32 $r3 0 | ||
| 85 | bra e #i2c_drive_scl_lo | ||
| 86 | nv_iowr(NV_PPWR_OUTPUT_SET, $r1) | ||
| 87 | ret | ||
| 88 | i2c_drive_scl_lo: | ||
| 89 | nv_iowr(NV_PPWR_OUTPUT_CLR, $r1) | ||
| 90 | ret | ||
| 91 | |||
| 92 | i2c_drive_sda: | ||
| 93 | cmp b32 $r3 0 | ||
| 94 | bra e #i2c_drive_sda_lo | ||
| 95 | nv_iowr(NV_PPWR_OUTPUT_SET, $r2) | ||
| 96 | ret | ||
| 97 | i2c_drive_sda_lo: | ||
| 98 | nv_iowr(NV_PPWR_OUTPUT_CLR, $r2) | ||
| 99 | ret | ||
| 100 | |||
| 101 | i2c_sense_scl: | ||
| 102 | bclr $flags $p1 | ||
| 103 | nv_iord($r3, NV_PPWR_INPUT) | ||
| 104 | and $r3 $r1 | ||
| 105 | bra z #i2c_sense_scl_done | ||
| 106 | bset $flags $p1 | ||
| 107 | i2c_sense_scl_done: | ||
| 108 | ret | ||
| 109 | |||
| 110 | i2c_sense_sda: | ||
| 111 | bclr $flags $p1 | ||
| 112 | nv_iord($r3, NV_PPWR_INPUT) | ||
| 113 | and $r3 $r2 | ||
| 114 | bra z #i2c_sense_sda_done | ||
| 115 | bset $flags $p1 | ||
| 116 | i2c_sense_sda_done: | ||
| 117 | ret | ||
| 118 | |||
| 119 | #define i2c_drive_scl(v) /* | ||
| 120 | */ mov $r3 (v) /* | ||
| 121 | */ call(i2c_drive_scl) | ||
| 122 | #define i2c_drive_sda(v) /* | ||
| 123 | */ mov $r3 (v) /* | ||
| 124 | */ call(i2c_drive_sda) | ||
| 125 | #define i2c_sense_scl() /* | ||
| 126 | */ call(i2c_sense_scl) | ||
| 127 | #define i2c_sense_sda() /* | ||
| 128 | */ call(i2c_sense_sda) | ||
| 129 | #define i2c_delay(v) /* | ||
| 130 | */ mov $r14 (v) /* | ||
| 131 | */ call(nsec) | ||
| 132 | |||
| 133 | #define i2c_trace_init() /* | ||
| 134 | */ imm32($r6, 0x10000000) /* | ||
| 135 | */ sub b32 $r7 $r6 1 /* | ||
| 136 | */ | ||
| 137 | #define i2c_trace_down() /* | ||
| 138 | */ shr b32 $r6 4 /* | ||
| 139 | */ push $r5 /* | ||
| 140 | */ shl b32 $r5 $r6 4 /* | ||
| 141 | */ sub b32 $r5 $r6 /* | ||
| 142 | */ not b32 $r5 /* | ||
| 143 | */ and $r7 $r5 /* | ||
| 144 | */ pop $r5 /* | ||
| 145 | */ | ||
| 146 | #define i2c_trace_exit() /* | ||
| 147 | */ shl b32 $r6 4 /* | ||
| 148 | */ | ||
| 149 | #define i2c_trace_next() /* | ||
| 150 | */ add b32 $r7 $r6 /* | ||
| 151 | */ | ||
| 152 | #define i2c_trace_call(func) /* | ||
| 153 | */ i2c_trace_next() /* | ||
| 154 | */ i2c_trace_down() /* | ||
| 155 | */ call(func) /* | ||
| 156 | */ i2c_trace_exit() /* | ||
| 157 | */ | ||
| 158 | |||
| 159 | i2c_raise_scl: | ||
| 160 | push $r4 | ||
| 161 | mov $r4 (T_TIMEOUT / T_RISEFALL) | ||
| 162 | i2c_drive_scl(1) | ||
| 163 | i2c_raise_scl_wait: | ||
| 164 | i2c_delay(T_RISEFALL) | ||
| 165 | i2c_sense_scl() | ||
| 166 | bra $p1 #i2c_raise_scl_done | ||
| 167 | sub b32 $r4 1 | ||
| 168 | bra nz #i2c_raise_scl_wait | ||
| 169 | i2c_raise_scl_done: | ||
| 170 | pop $r4 | ||
| 171 | ret | ||
| 172 | |||
| 173 | i2c_start: | ||
| 174 | i2c_sense_scl() | ||
| 175 | bra not $p1 #i2c_start_rep | ||
| 176 | i2c_sense_sda() | ||
| 177 | bra not $p1 #i2c_start_rep | ||
| 178 | bra #i2c_start_send | ||
| 179 | i2c_start_rep: | ||
| 180 | i2c_drive_scl(0) | ||
| 181 | i2c_drive_sda(1) | ||
| 182 | i2c_trace_call(i2c_raise_scl) | ||
| 183 | bra not $p1 #i2c_start_out | ||
| 184 | i2c_start_send: | ||
| 185 | i2c_drive_sda(0) | ||
| 186 | i2c_delay(T_HOLD) | ||
| 187 | i2c_drive_scl(0) | ||
| 188 | i2c_delay(T_HOLD) | ||
| 189 | i2c_start_out: | ||
| 190 | ret | ||
| 191 | |||
| 192 | i2c_stop: | ||
| 193 | i2c_drive_scl(0) | ||
| 194 | i2c_drive_sda(0) | ||
| 195 | i2c_delay(T_RISEFALL) | ||
| 196 | i2c_drive_scl(1) | ||
| 197 | i2c_delay(T_HOLD) | ||
| 198 | i2c_drive_sda(1) | ||
| 199 | i2c_delay(T_HOLD) | ||
| 200 | ret | ||
| 201 | |||
| 202 | // $r3 - value | ||
| 203 | // $r2 - sda line | ||
| 204 | // $r1 - scl line | ||
| 205 | // $r0 - zero | ||
| 206 | i2c_bitw: | ||
| 207 | call(i2c_drive_sda) | ||
| 208 | i2c_delay(T_RISEFALL) | ||
| 209 | i2c_trace_call(i2c_raise_scl) | ||
| 210 | bra not $p1 #i2c_bitw_out | ||
| 211 | i2c_delay(T_HOLD) | ||
| 212 | i2c_drive_scl(0) | ||
| 213 | i2c_delay(T_HOLD) | ||
| 214 | i2c_bitw_out: | ||
| 215 | ret | ||
| 216 | |||
| 217 | // $r3 - value (out) | ||
| 218 | // $r2 - sda line | ||
| 219 | // $r1 - scl line | ||
| 220 | // $r0 - zero | ||
| 221 | i2c_bitr: | ||
| 222 | i2c_drive_sda(1) | ||
| 223 | i2c_delay(T_RISEFALL) | ||
| 224 | i2c_trace_call(i2c_raise_scl) | ||
| 225 | bra not $p1 #i2c_bitr_done | ||
| 226 | i2c_sense_sda() | ||
| 227 | i2c_drive_scl(0) | ||
| 228 | i2c_delay(T_HOLD) | ||
| 229 | xbit $r3 $flags $p1 | ||
| 230 | bset $flags $p1 | ||
| 231 | i2c_bitr_done: | ||
| 232 | ret | ||
| 233 | |||
| 234 | i2c_get_byte: | ||
| 235 | mov $r5 0 | ||
| 236 | mov $r4 8 | ||
| 237 | i2c_get_byte_next: | ||
| 238 | shl b32 $r5 1 | ||
| 239 | i2c_trace_call(i2c_bitr) | ||
| 240 | bra not $p1 #i2c_get_byte_done | ||
| 241 | or $r5 $r3 | ||
| 242 | sub b32 $r4 1 | ||
| 243 | bra nz #i2c_get_byte_next | ||
| 244 | mov $r3 1 | ||
| 245 | i2c_trace_call(i2c_bitw) | ||
| 246 | i2c_get_byte_done: | ||
| 247 | ret | ||
| 248 | |||
| 249 | i2c_put_byte: | ||
| 250 | mov $r4 8 | ||
| 251 | i2c_put_byte_next: | ||
| 252 | sub b32 $r4 1 | ||
| 253 | xbit $r3 $r5 $r4 | ||
| 254 | i2c_trace_call(i2c_bitw) | ||
| 255 | bra not $p1 #i2c_put_byte_done | ||
| 256 | cmp b32 $r4 0 | ||
| 257 | bra ne #i2c_put_byte_next | ||
| 258 | i2c_trace_call(i2c_bitr) | ||
| 259 | bra not $p1 #i2c_put_byte_done | ||
| 260 | i2c_trace_next() | ||
| 261 | cmp b32 $r3 1 | ||
| 262 | bra ne #i2c_put_byte_done | ||
| 263 | bclr $flags $p1 // nack | ||
| 264 | i2c_put_byte_done: | ||
| 265 | ret | ||
| 266 | |||
| 267 | i2c_addr: | ||
| 268 | i2c_trace_call(i2c_start) | ||
| 269 | bra not $p1 #i2c_addr_done | ||
| 270 | extr $r3 $r12 I2C__MSG_DATA0_ADDR | ||
| 271 | shl b32 $r3 1 | ||
| 272 | or $r5 $r3 | ||
| 273 | i2c_trace_call(i2c_put_byte) | ||
| 274 | i2c_addr_done: | ||
| 275 | ret | ||
| 276 | |||
| 277 | i2c_acquire_addr: | ||
| 278 | extr $r14 $r12 I2C__MSG_DATA0_PORT | ||
| 279 | #if NVKM_PPWR_CHIPSET < GF119 | ||
| 280 | shl b32 $r14 2 | ||
| 281 | add b32 $r14 #i2c_ctrl | ||
| 282 | ld b32 $r14 D[$r14] | ||
| 283 | #else | ||
| 284 | shl b32 $r14 5 | ||
| 285 | add b32 $r14 0x00d014 | ||
| 286 | #endif | ||
| 287 | ret | ||
| 288 | |||
| 289 | i2c_acquire: | ||
| 290 | call(i2c_acquire_addr) | ||
| 291 | call(rd32) | ||
| 292 | bset $r13 3 | ||
| 293 | call(wr32) | ||
| 294 | ret | ||
| 295 | |||
| 296 | i2c_release: | ||
| 297 | call(i2c_acquire_addr) | ||
| 298 | call(rd32) | ||
| 299 | bclr $r13 3 | ||
| 300 | call(wr32) | ||
| 301 | ret | ||
| 302 | |||
| 303 | // description | ||
| 304 | // | ||
| 305 | // $r15 - current (i2c) | ||
| 306 | // $r14 - sender process name | ||
| 307 | // $r13 - message | ||
| 308 | // $r12 - data0 | ||
| 309 | // $r11 - data1 | ||
| 310 | // $r0 - zero | ||
| 311 | i2c_recv: | ||
| 312 | bclr $flags $p1 | ||
| 313 | extr $r1 $r12 I2C__MSG_DATA0_PORT | ||
| 314 | shl b32 $r1 2 | ||
| 315 | cmp b32 $r1 (#i2c_sda_map - #i2c_scl_map) | ||
| 316 | bra ge #i2c_recv_done | ||
| 317 | add b32 $r3 $r1 #i2c_sda_map | ||
| 318 | ld b32 $r2 D[$r3] | ||
| 319 | add b32 $r3 $r1 #i2c_scl_map | ||
| 320 | ld b32 $r1 D[$r3] | ||
| 321 | |||
| 322 | bset $flags $p2 | ||
| 323 | push $r13 | ||
| 324 | push $r14 | ||
| 325 | |||
| 326 | push $r13 | ||
| 327 | i2c_trace_init() | ||
| 328 | i2c_trace_call(i2c_acquire) | ||
| 329 | pop $r13 | ||
| 330 | |||
| 331 | cmp b32 $r13 I2C__MSG_RD08 | ||
| 332 | bra ne #i2c_recv_not_rd08 | ||
| 333 | mov $r5 0 | ||
| 334 | i2c_trace_call(i2c_addr) | ||
| 335 | bra not $p1 #i2c_recv_done | ||
| 336 | extr $r5 $r12 I2C__MSG_DATA0_RD08_REG | ||
| 337 | i2c_trace_call(i2c_put_byte) | ||
| 338 | bra not $p1 #i2c_recv_done | ||
| 339 | mov $r5 1 | ||
| 340 | i2c_trace_call(i2c_addr) | ||
| 341 | bra not $p1 #i2c_recv_done | ||
| 342 | i2c_trace_call(i2c_get_byte) | ||
| 343 | bra not $p1 #i2c_recv_done | ||
| 344 | ins $r11 $r5 I2C__MSG_DATA1_RD08_VAL | ||
| 345 | i2c_trace_call(i2c_stop) | ||
| 346 | mov b32 $r11 $r5 | ||
| 347 | clear b32 $r7 | ||
| 348 | bra #i2c_recv_done | ||
| 349 | |||
| 350 | i2c_recv_not_rd08: | ||
| 351 | cmp b32 $r13 I2C__MSG_WR08 | ||
| 352 | bra ne #i2c_recv_not_wr08 | ||
| 353 | mov $r5 0 | ||
| 354 | call(i2c_addr) | ||
| 355 | bra not $p1 #i2c_recv_done | ||
| 356 | extr $r5 $r12 I2C__MSG_DATA0_WR08_REG | ||
| 357 | call(i2c_put_byte) | ||
| 358 | bra not $p1 #i2c_recv_done | ||
| 359 | mov $r5 0 | ||
| 360 | call(i2c_addr) | ||
| 361 | bra not $p1 #i2c_recv_done | ||
| 362 | extr $r5 $r11 I2C__MSG_DATA1_WR08_VAL | ||
| 363 | call(i2c_put_byte) | ||
| 364 | bra not $p1 #i2c_recv_done | ||
| 365 | call(i2c_stop) | ||
| 366 | clear b32 $r7 | ||
| 367 | extr $r5 $r12 I2C__MSG_DATA0_WR08_SYNC | ||
| 368 | bra nz #i2c_recv_done | ||
| 369 | bclr $flags $p2 | ||
| 370 | bra #i2c_recv_done | ||
| 371 | |||
| 372 | i2c_recv_not_wr08: | ||
| 373 | |||
| 374 | i2c_recv_done: | ||
| 375 | extr $r14 $r12 I2C__MSG_DATA0_PORT | ||
| 376 | call(i2c_release) | ||
| 377 | |||
| 378 | pop $r14 | ||
| 379 | pop $r13 | ||
| 380 | bra not $p2 #i2c_recv_exit | ||
| 381 | mov b32 $r12 $r7 | ||
| 382 | call(send) | ||
| 383 | |||
| 384 | i2c_recv_exit: | ||
| 385 | ret | ||
| 386 | |||
| 387 | // description | ||
| 388 | // | ||
| 389 | // $r15 - current (i2c) | ||
| 390 | // $r0 - zero | ||
| 391 | i2c_init: | ||
| 392 | ret | ||
| 393 | #endif | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc index 0a7b05fa5c11..8f29badd785f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc | |||
| @@ -51,12 +51,12 @@ time_next: .b32 0 | |||
| 51 | // $r0 - zero | 51 | // $r0 - zero |
| 52 | rd32: | 52 | rd32: |
| 53 | nv_iowr(NV_PPWR_MMIO_ADDR, $r14) | 53 | nv_iowr(NV_PPWR_MMIO_ADDR, $r14) |
| 54 | mov $r14 NV_PPWR_MMIO_CTRL_OP_RD | 54 | mov $r13 NV_PPWR_MMIO_CTRL_OP_RD |
| 55 | sethi $r14 NV_PPWR_MMIO_CTRL_TRIGGER | 55 | sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER |
| 56 | nv_iowr(NV_PPWR_MMIO_CTRL, $r14) | 56 | nv_iowr(NV_PPWR_MMIO_CTRL, $r13) |
| 57 | rd32_wait: | 57 | rd32_wait: |
| 58 | nv_iord($r14, NV_PPWR_MMIO_CTRL) | 58 | nv_iord($r13, NV_PPWR_MMIO_CTRL) |
| 59 | and $r14 NV_PPWR_MMIO_CTRL_STATUS | 59 | and $r13 NV_PPWR_MMIO_CTRL_STATUS |
| 60 | bra nz #rd32_wait | 60 | bra nz #rd32_wait |
| 61 | nv_iord($r13, NV_PPWR_MMIO_DATA) | 61 | nv_iord($r13, NV_PPWR_MMIO_DATA) |
| 62 | ret | 62 | ret |
| @@ -70,23 +70,25 @@ rd32: | |||
| 70 | wr32: | 70 | wr32: |
| 71 | nv_iowr(NV_PPWR_MMIO_ADDR, $r14) | 71 | nv_iowr(NV_PPWR_MMIO_ADDR, $r14) |
| 72 | nv_iowr(NV_PPWR_MMIO_DATA, $r13) | 72 | nv_iowr(NV_PPWR_MMIO_DATA, $r13) |
| 73 | mov $r14 NV_PPWR_MMIO_CTRL_OP_WR | 73 | mov $r13 NV_PPWR_MMIO_CTRL_OP_WR |
| 74 | or $r14 NV_PPWR_MMIO_CTRL_MASK_B32_0 | 74 | or $r13 NV_PPWR_MMIO_CTRL_MASK_B32_0 |
| 75 | sethi $r14 NV_PPWR_MMIO_CTRL_TRIGGER | 75 | sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER |
| 76 | 76 | ||
| 77 | #ifdef NVKM_FALCON_MMIO_TRAP | 77 | #ifdef NVKM_FALCON_MMIO_TRAP |
| 78 | mov $r8 NV_PPWR_INTR_TRIGGER_USER1 | 78 | push $r13 |
| 79 | nv_iowr(NV_PPWR_INTR_TRIGGER, $r8) | 79 | mov $r13 NV_PPWR_INTR_TRIGGER_USER1 |
| 80 | nv_iowr(NV_PPWR_INTR_TRIGGER, $r13) | ||
| 80 | wr32_host: | 81 | wr32_host: |
| 81 | nv_iord($r8, NV_PPWR_INTR) | 82 | nv_iord($r13, NV_PPWR_INTR) |
| 82 | and $r8 NV_PPWR_INTR_USER1 | 83 | and $r13 NV_PPWR_INTR_USER1 |
| 83 | bra nz #wr32_host | 84 | bra nz #wr32_host |
| 85 | pop $r13 | ||
| 84 | #endif | 86 | #endif |
| 85 | 87 | ||
| 86 | nv_iowr(NV_PPWR_MMIO_CTRL, $r14) | 88 | nv_iowr(NV_PPWR_MMIO_CTRL, $r13) |
| 87 | wr32_wait: | 89 | wr32_wait: |
| 88 | nv_iord($r14, NV_PPWR_MMIO_CTRL) | 90 | nv_iord($r13, NV_PPWR_MMIO_CTRL) |
| 89 | and $r14 NV_PPWR_MMIO_CTRL_STATUS | 91 | and $r13 NV_PPWR_MMIO_CTRL_STATUS |
| 90 | bra nz #wr32_wait | 92 | bra nz #wr32_wait |
| 91 | ret | 93 | ret |
| 92 | 94 | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc index 2a74ea907604..e2a63ac5422b 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc | |||
| @@ -83,6 +83,50 @@ | |||
| 83 | #define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002 | 83 | #define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002 |
| 84 | #define NV_PPWR_OUTPUT 0x07c0 | 84 | #define NV_PPWR_OUTPUT 0x07c0 |
| 85 | #define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004 | 85 | #define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004 |
| 86 | #if NVKM_PPWR_CHIPSET < GF119 | ||
| 87 | #define NV_PPWR_OUTPUT_I2C_3_SCL 0x00000100 | ||
| 88 | #define NV_PPWR_OUTPUT_I2C_3_SDA 0x00000200 | ||
| 89 | #define NV_PPWR_OUTPUT_I2C_0_SCL 0x00001000 | ||
| 90 | #define NV_PPWR_OUTPUT_I2C_0_SDA 0x00002000 | ||
| 91 | #define NV_PPWR_OUTPUT_I2C_1_SCL 0x00004000 | ||
| 92 | #define NV_PPWR_OUTPUT_I2C_1_SDA 0x00008000 | ||
| 93 | #define NV_PPWR_OUTPUT_I2C_2_SCL 0x00010000 | ||
| 94 | #define NV_PPWR_OUTPUT_I2C_2_SDA 0x00020000 | ||
| 95 | #define NV_PPWR_OUTPUT_I2C_4_SCL 0x00040000 | ||
| 96 | #define NV_PPWR_OUTPUT_I2C_4_SDA 0x00080000 | ||
| 97 | #define NV_PPWR_OUTPUT_I2C_5_SCL 0x00100000 | ||
| 98 | #define NV_PPWR_OUTPUT_I2C_5_SDA 0x00200000 | ||
| 99 | #define NV_PPWR_OUTPUT_I2C_6_SCL 0x00400000 | ||
| 100 | #define NV_PPWR_OUTPUT_I2C_6_SDA 0x00800000 | ||
| 101 | #define NV_PPWR_OUTPUT_I2C_7_SCL 0x01000000 | ||
| 102 | #define NV_PPWR_OUTPUT_I2C_7_SDA 0x02000000 | ||
| 103 | #define NV_PPWR_OUTPUT_I2C_8_SCL 0x04000000 | ||
| 104 | #define NV_PPWR_OUTPUT_I2C_8_SDA 0x08000000 | ||
| 105 | #define NV_PPWR_OUTPUT_I2C_9_SCL 0x10000000 | ||
| 106 | #define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000 | ||
| 107 | #else | ||
| 108 | #define NV_PPWR_OUTPUT_I2C_0_SCL 0x00000400 | ||
| 109 | #define NV_PPWR_OUTPUT_I2C_1_SCL 0x00000800 | ||
| 110 | #define NV_PPWR_OUTPUT_I2C_2_SCL 0x00001000 | ||
| 111 | #define NV_PPWR_OUTPUT_I2C_3_SCL 0x00002000 | ||
| 112 | #define NV_PPWR_OUTPUT_I2C_4_SCL 0x00004000 | ||
| 113 | #define NV_PPWR_OUTPUT_I2C_5_SCL 0x00008000 | ||
| 114 | #define NV_PPWR_OUTPUT_I2C_6_SCL 0x00010000 | ||
| 115 | #define NV_PPWR_OUTPUT_I2C_7_SCL 0x00020000 | ||
| 116 | #define NV_PPWR_OUTPUT_I2C_8_SCL 0x00040000 | ||
| 117 | #define NV_PPWR_OUTPUT_I2C_9_SCL 0x00080000 | ||
| 118 | #define NV_PPWR_OUTPUT_I2C_0_SDA 0x00100000 | ||
| 119 | #define NV_PPWR_OUTPUT_I2C_1_SDA 0x00200000 | ||
| 120 | #define NV_PPWR_OUTPUT_I2C_2_SDA 0x00400000 | ||
| 121 | #define NV_PPWR_OUTPUT_I2C_3_SDA 0x00800000 | ||
| 122 | #define NV_PPWR_OUTPUT_I2C_4_SDA 0x01000000 | ||
| 123 | #define NV_PPWR_OUTPUT_I2C_5_SDA 0x02000000 | ||
| 124 | #define NV_PPWR_OUTPUT_I2C_6_SDA 0x04000000 | ||
| 125 | #define NV_PPWR_OUTPUT_I2C_7_SDA 0x08000000 | ||
| 126 | #define NV_PPWR_OUTPUT_I2C_8_SDA 0x10000000 | ||
| 127 | #define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000 | ||
| 128 | #endif | ||
| 129 | #define NV_PPWR_INPUT 0x07c4 | ||
| 86 | #define NV_PPWR_OUTPUT_SET 0x07e0 | 130 | #define NV_PPWR_OUTPUT_SET 0x07e0 |
| 87 | #define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004 | 131 | #define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004 |
| 88 | #define NV_PPWR_OUTPUT_CLR 0x07e4 | 132 | #define NV_PPWR_OUTPUT_CLR 0x07e4 |
| @@ -125,6 +169,15 @@ | |||
| 125 | */ .b32 0 /* | 169 | */ .b32 0 /* |
| 126 | */ .skip 64 | 170 | */ .skip 64 |
| 127 | 171 | ||
| 172 | #if NV_PPWR_CHIPSET < GK208 | ||
| 173 | #define imm32(reg,val) /* | ||
| 174 | */ movw reg ((val) & 0x0000ffff) /* | ||
| 175 | */ sethi reg ((val) & 0xffff0000) | ||
| 176 | #else | ||
| 177 | #define imm32(reg,val) /* | ||
| 178 | */ mov reg (val) | ||
| 179 | #endif | ||
| 180 | |||
| 128 | #ifndef NVKM_FALCON_UNSHIFTED_IO | 181 | #ifndef NVKM_FALCON_UNSHIFTED_IO |
| 129 | #define nv_iord(reg,ior) /* | 182 | #define nv_iord(reg,ior) /* |
| 130 | */ mov reg ior /* | 183 | */ mov reg ior /* |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc index 947be536daef..17a8a383d91a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | #include "host.fuc" | 37 | #include "host.fuc" |
| 38 | #include "memx.fuc" | 38 | #include "memx.fuc" |
| 39 | #include "perf.fuc" | 39 | #include "perf.fuc" |
| 40 | #include "i2c_.fuc" | ||
| 40 | #include "test.fuc" | 41 | #include "test.fuc" |
| 41 | #include "idle.fuc" | 42 | #include "idle.fuc" |
| 42 | #undef INCLUDE_PROC | 43 | #undef INCLUDE_PROC |
| @@ -46,6 +47,7 @@ | |||
| 46 | #include "host.fuc" | 47 | #include "host.fuc" |
| 47 | #include "memx.fuc" | 48 | #include "memx.fuc" |
| 48 | #include "perf.fuc" | 49 | #include "perf.fuc" |
| 50 | #include "i2c_.fuc" | ||
| 49 | #include "test.fuc" | 51 | #include "test.fuc" |
| 50 | #include "idle.fuc" | 52 | #include "idle.fuc" |
| 51 | #undef INCLUDE_DATA | 53 | #undef INCLUDE_DATA |
| @@ -57,6 +59,7 @@ | |||
| 57 | #include "host.fuc" | 59 | #include "host.fuc" |
| 58 | #include "memx.fuc" | 60 | #include "memx.fuc" |
| 59 | #include "perf.fuc" | 61 | #include "perf.fuc" |
| 62 | #include "i2c_.fuc" | ||
| 60 | #include "test.fuc" | 63 | #include "test.fuc" |
| 61 | #include "idle.fuc" | 64 | #include "idle.fuc" |
| 62 | #undef INCLUDE_CODE | 65 | #undef INCLUDE_CODE |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h index 9342e2d7d3b7..4bd43a99fdcc 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h | |||
| @@ -89,16 +89,9 @@ uint32_t nv108_pwr_data[] = { | |||
| 89 | 0x00000000, | 89 | 0x00000000, |
| 90 | 0x00000000, | 90 | 0x00000000, |
| 91 | 0x00000000, | 91 | 0x00000000, |
| 92 | 0x54534554, | 92 | 0x5f433249, |
| 93 | 0x00000494, | 93 | 0x00000877, |
| 94 | 0x00000475, | 94 | 0x0000071e, |
| 95 | 0x00000000, | ||
| 96 | 0x00000000, | ||
| 97 | 0x00000000, | ||
| 98 | 0x00000000, | ||
| 99 | 0x00000000, | ||
| 100 | 0x00000000, | ||
| 101 | 0x00000000, | ||
| 102 | 0x00000000, | 95 | 0x00000000, |
| 103 | 0x00000000, | 96 | 0x00000000, |
| 104 | 0x00000000, | 97 | 0x00000000, |
| @@ -111,16 +104,6 @@ uint32_t nv108_pwr_data[] = { | |||
| 111 | 0x00000000, | 104 | 0x00000000, |
| 112 | 0x00000000, | 105 | 0x00000000, |
| 113 | 0x00000000, | 106 | 0x00000000, |
| 114 | 0x454c4449, | ||
| 115 | 0x0000049f, | ||
| 116 | 0x0000049d, | ||
| 117 | 0x00000000, | ||
| 118 | 0x00000000, | ||
| 119 | 0x00000000, | ||
| 120 | 0x00000000, | ||
| 121 | 0x00000000, | ||
| 122 | 0x00000000, | ||
| 123 | 0x00000000, | ||
| 124 | 0x00000000, | 107 | 0x00000000, |
| 125 | 0x00000000, | 108 | 0x00000000, |
| 126 | 0x00000000, | 109 | 0x00000000, |
| @@ -128,17 +111,16 @@ uint32_t nv108_pwr_data[] = { | |||
| 128 | 0x00000000, | 111 | 0x00000000, |
| 129 | 0x00000000, | 112 | 0x00000000, |
| 130 | 0x00000000, | 113 | 0x00000000, |
| 114 | 0x54534554, | ||
| 115 | 0x00000898, | ||
| 116 | 0x00000879, | ||
| 131 | 0x00000000, | 117 | 0x00000000, |
| 132 | 0x00000000, | 118 | 0x00000000, |
| 133 | 0x00000000, | 119 | 0x00000000, |
| 134 | 0x00000000, | 120 | 0x00000000, |
| 135 | 0x00000000, | 121 | 0x00000000, |
| 136 | /* 0x0210: proc_list_tail */ | ||
| 137 | /* 0x0210: time_prev */ | ||
| 138 | 0x00000000, | 122 | 0x00000000, |
| 139 | /* 0x0214: time_next */ | ||
| 140 | 0x00000000, | 123 | 0x00000000, |
| 141 | /* 0x0218: fifo_queue */ | ||
| 142 | 0x00000000, | 124 | 0x00000000, |
| 143 | 0x00000000, | 125 | 0x00000000, |
| 144 | 0x00000000, | 126 | 0x00000000, |
| @@ -151,6 +133,9 @@ uint32_t nv108_pwr_data[] = { | |||
| 151 | 0x00000000, | 133 | 0x00000000, |
| 152 | 0x00000000, | 134 | 0x00000000, |
| 153 | 0x00000000, | 135 | 0x00000000, |
| 136 | 0x454c4449, | ||
| 137 | 0x000008a3, | ||
| 138 | 0x000008a1, | ||
| 154 | 0x00000000, | 139 | 0x00000000, |
| 155 | 0x00000000, | 140 | 0x00000000, |
| 156 | 0x00000000, | 141 | 0x00000000, |
| @@ -170,9 +155,12 @@ uint32_t nv108_pwr_data[] = { | |||
| 170 | 0x00000000, | 155 | 0x00000000, |
| 171 | 0x00000000, | 156 | 0x00000000, |
| 172 | 0x00000000, | 157 | 0x00000000, |
| 158 | /* 0x0268: proc_list_tail */ | ||
| 159 | /* 0x0268: time_prev */ | ||
| 173 | 0x00000000, | 160 | 0x00000000, |
| 174 | /* 0x0298: rfifo_queue */ | 161 | /* 0x026c: time_next */ |
| 175 | 0x00000000, | 162 | 0x00000000, |
| 163 | /* 0x0270: fifo_queue */ | ||
| 176 | 0x00000000, | 164 | 0x00000000, |
| 177 | 0x00000000, | 165 | 0x00000000, |
| 178 | 0x00000000, | 166 | 0x00000000, |
| @@ -204,31 +192,8 @@ uint32_t nv108_pwr_data[] = { | |||
| 204 | 0x00000000, | 192 | 0x00000000, |
| 205 | 0x00000000, | 193 | 0x00000000, |
| 206 | 0x00000000, | 194 | 0x00000000, |
| 207 | /* 0x0318: memx_func_head */ | ||
| 208 | 0x00010000, | ||
| 209 | 0x00000000, | ||
| 210 | 0x000003a9, | ||
| 211 | /* 0x0324: memx_func_next */ | ||
| 212 | 0x00000001, | ||
| 213 | 0x00000000, | ||
| 214 | 0x000003c7, | ||
| 215 | 0x00000002, | ||
| 216 | 0x00000002, | ||
| 217 | 0x000003df, | ||
| 218 | 0x00040003, | ||
| 219 | 0x00000000, | ||
| 220 | 0x00000407, | ||
| 221 | 0x00010004, | ||
| 222 | 0x00000000, | ||
| 223 | 0x00000421, | ||
| 224 | /* 0x0354: memx_func_tail */ | ||
| 225 | /* 0x0354: memx_data_head */ | ||
| 226 | 0x00000000, | ||
| 227 | 0x00000000, | ||
| 228 | 0x00000000, | ||
| 229 | 0x00000000, | ||
| 230 | 0x00000000, | ||
| 231 | 0x00000000, | 195 | 0x00000000, |
| 196 | /* 0x02f0: rfifo_queue */ | ||
| 232 | 0x00000000, | 197 | 0x00000000, |
| 233 | 0x00000000, | 198 | 0x00000000, |
| 234 | 0x00000000, | 199 | 0x00000000, |
| @@ -261,10 +226,25 @@ uint32_t nv108_pwr_data[] = { | |||
| 261 | 0x00000000, | 226 | 0x00000000, |
| 262 | 0x00000000, | 227 | 0x00000000, |
| 263 | 0x00000000, | 228 | 0x00000000, |
| 229 | /* 0x0370: memx_func_head */ | ||
| 230 | 0x00010000, | ||
| 264 | 0x00000000, | 231 | 0x00000000, |
| 232 | 0x000003a9, | ||
| 233 | /* 0x037c: memx_func_next */ | ||
| 234 | 0x00000001, | ||
| 265 | 0x00000000, | 235 | 0x00000000, |
| 236 | 0x000003c7, | ||
| 237 | 0x00000002, | ||
| 238 | 0x00000002, | ||
| 239 | 0x000003df, | ||
| 240 | 0x00040003, | ||
| 266 | 0x00000000, | 241 | 0x00000000, |
| 242 | 0x00000407, | ||
| 243 | 0x00010004, | ||
| 267 | 0x00000000, | 244 | 0x00000000, |
| 245 | 0x00000421, | ||
| 246 | /* 0x03ac: memx_func_tail */ | ||
| 247 | /* 0x03ac: memx_data_head */ | ||
| 268 | 0x00000000, | 248 | 0x00000000, |
| 269 | 0x00000000, | 249 | 0x00000000, |
| 270 | 0x00000000, | 250 | 0x00000000, |
| @@ -735,7 +715,6 @@ uint32_t nv108_pwr_data[] = { | |||
| 735 | 0x00000000, | 715 | 0x00000000, |
| 736 | 0x00000000, | 716 | 0x00000000, |
| 737 | 0x00000000, | 717 | 0x00000000, |
| 738 | /* 0x0b54: memx_data_tail */ | ||
| 739 | 0x00000000, | 718 | 0x00000000, |
| 740 | 0x00000000, | 719 | 0x00000000, |
| 741 | 0x00000000, | 720 | 0x00000000, |
| @@ -778,6 +757,29 @@ uint32_t nv108_pwr_data[] = { | |||
| 778 | 0x00000000, | 757 | 0x00000000, |
| 779 | 0x00000000, | 758 | 0x00000000, |
| 780 | 0x00000000, | 759 | 0x00000000, |
| 760 | /* 0x0bac: memx_data_tail */ | ||
| 761 | /* 0x0bac: i2c_scl_map */ | ||
| 762 | 0x00000400, | ||
| 763 | 0x00000800, | ||
| 764 | 0x00001000, | ||
| 765 | 0x00002000, | ||
| 766 | 0x00004000, | ||
| 767 | 0x00008000, | ||
| 768 | 0x00010000, | ||
| 769 | 0x00020000, | ||
| 770 | 0x00040000, | ||
| 771 | 0x00080000, | ||
| 772 | /* 0x0bd4: i2c_sda_map */ | ||
| 773 | 0x00100000, | ||
| 774 | 0x00200000, | ||
| 775 | 0x00400000, | ||
| 776 | 0x00800000, | ||
| 777 | 0x01000000, | ||
| 778 | 0x02000000, | ||
| 779 | 0x04000000, | ||
| 780 | 0x08000000, | ||
| 781 | 0x10000000, | ||
| 782 | 0x20000000, | ||
| 781 | 0x00000000, | 783 | 0x00000000, |
| 782 | }; | 784 | }; |
| 783 | 785 | ||
| @@ -786,13 +788,13 @@ uint32_t nv108_pwr_code[] = { | |||
| 786 | /* 0x0004: rd32 */ | 788 | /* 0x0004: rd32 */ |
| 787 | 0xf607a040, | 789 | 0xf607a040, |
| 788 | 0x04bd000e, | 790 | 0x04bd000e, |
| 789 | 0xe3f0010e, | 791 | 0xd3f0010d, |
| 790 | 0x07ac4001, | 792 | 0x07ac4001, |
| 791 | 0xbd000ef6, | 793 | 0xbd000df6, |
| 792 | /* 0x0019: rd32_wait */ | 794 | /* 0x0019: rd32_wait */ |
| 793 | 0x07ac4e04, | 795 | 0x07ac4d04, |
| 794 | 0xf100eecf, | 796 | 0xf100ddcf, |
| 795 | 0xf47000e4, | 797 | 0xf47000d4, |
| 796 | 0xa44df61b, | 798 | 0xa44df61b, |
| 797 | 0x00ddcf07, | 799 | 0x00ddcf07, |
| 798 | /* 0x002e: wr32 */ | 800 | /* 0x002e: wr32 */ |
| @@ -800,14 +802,14 @@ uint32_t nv108_pwr_code[] = { | |||
| 800 | 0x000ef607, | 802 | 0x000ef607, |
| 801 | 0xa44004bd, | 803 | 0xa44004bd, |
| 802 | 0x000df607, | 804 | 0x000df607, |
| 803 | 0x020e04bd, | 805 | 0x020d04bd, |
| 804 | 0xf0f0e5f0, | 806 | 0xf0f0d5f0, |
| 805 | 0xac4001e3, | 807 | 0xac4001d3, |
| 806 | 0x000ef607, | 808 | 0x000df607, |
| 807 | /* 0x004e: wr32_wait */ | 809 | /* 0x004e: wr32_wait */ |
| 808 | 0xac4e04bd, | 810 | 0xac4d04bd, |
| 809 | 0x00eecf07, | 811 | 0x00ddcf07, |
| 810 | 0x7000e4f1, | 812 | 0x7000d4f1, |
| 811 | 0xf8f61bf4, | 813 | 0xf8f61bf4, |
| 812 | /* 0x005d: nsec */ | 814 | /* 0x005d: nsec */ |
| 813 | 0xcf2c0800, | 815 | 0xcf2c0800, |
| @@ -832,20 +834,20 @@ uint32_t nv108_pwr_code[] = { | |||
| 832 | 0x03e99800, | 834 | 0x03e99800, |
| 833 | 0xf40096b0, | 835 | 0xf40096b0, |
| 834 | 0x0a98280b, | 836 | 0x0a98280b, |
| 835 | 0x029abb84, | 837 | 0x029abb9a, |
| 836 | 0x0d0e1cf4, | 838 | 0x0d0e1cf4, |
| 837 | 0x01de7e01, | 839 | 0x01de7e01, |
| 838 | 0xf494bd00, | 840 | 0xf494bd00, |
| 839 | /* 0x00b2: intr_watchdog_next_time */ | 841 | /* 0x00b2: intr_watchdog_next_time */ |
| 840 | 0x0a98140e, | 842 | 0x0a98140e, |
| 841 | 0x00a6b085, | 843 | 0x00a6b09b, |
| 842 | 0xa6080bf4, | 844 | 0xa6080bf4, |
| 843 | 0x061cf49a, | 845 | 0x061cf49a, |
| 844 | /* 0x00c0: intr_watchdog_next_time_set */ | 846 | /* 0x00c0: intr_watchdog_next_time_set */ |
| 845 | /* 0x00c3: intr_watchdog_next_proc */ | 847 | /* 0x00c3: intr_watchdog_next_proc */ |
| 846 | 0xb58509b5, | 848 | 0xb59b09b5, |
| 847 | 0xe0b603e9, | 849 | 0xe0b603e9, |
| 848 | 0x10e6b158, | 850 | 0x68e6b158, |
| 849 | 0xc81bf402, | 851 | 0xc81bf402, |
| 850 | /* 0x00d2: intr */ | 852 | /* 0x00d2: intr */ |
| 851 | 0x00f900f8, | 853 | 0x00f900f8, |
| @@ -862,15 +864,15 @@ uint32_t nv108_pwr_code[] = { | |||
| 862 | 0x080804bd, | 864 | 0x080804bd, |
| 863 | 0xc40088cf, | 865 | 0xc40088cf, |
| 864 | 0x0bf40289, | 866 | 0x0bf40289, |
| 865 | 0x8500b51f, | 867 | 0x9b00b51f, |
| 866 | 0x957e580e, | 868 | 0x957e580e, |
| 867 | 0x09980000, | 869 | 0x09980000, |
| 868 | 0x0096b085, | 870 | 0x0096b09b, |
| 869 | 0x000d0bf4, | 871 | 0x000d0bf4, |
| 870 | 0x0009f634, | 872 | 0x0009f634, |
| 871 | 0x09b504bd, | 873 | 0x09b504bd, |
| 872 | /* 0x0125: intr_skip_watchdog */ | 874 | /* 0x0125: intr_skip_watchdog */ |
| 873 | 0x0089e484, | 875 | 0x0089e49a, |
| 874 | 0x360bf408, | 876 | 0x360bf408, |
| 875 | 0xcf068849, | 877 | 0xcf068849, |
| 876 | 0x9ac40099, | 878 | 0x9ac40099, |
| @@ -918,7 +920,7 @@ uint32_t nv108_pwr_code[] = { | |||
| 918 | /* 0x01c6: timer_reset */ | 920 | /* 0x01c6: timer_reset */ |
| 919 | 0x3400161e, | 921 | 0x3400161e, |
| 920 | 0xbd000ef6, | 922 | 0xbd000ef6, |
| 921 | 0x840eb504, | 923 | 0x9a0eb504, |
| 922 | /* 0x01d0: timer_enable */ | 924 | /* 0x01d0: timer_enable */ |
| 923 | 0x38000108, | 925 | 0x38000108, |
| 924 | 0xbd0008f6, | 926 | 0xbd0008f6, |
| @@ -949,7 +951,7 @@ uint32_t nv108_pwr_code[] = { | |||
| 949 | 0xa6008a98, | 951 | 0xa6008a98, |
| 950 | 0x100bf4ae, | 952 | 0x100bf4ae, |
| 951 | 0xb15880b6, | 953 | 0xb15880b6, |
| 952 | 0xf4021086, | 954 | 0xf4026886, |
| 953 | 0x32f4f11b, | 955 | 0x32f4f11b, |
| 954 | /* 0x0239: find_done */ | 956 | /* 0x0239: find_done */ |
| 955 | 0xfc8eb201, | 957 | 0xfc8eb201, |
| @@ -1009,7 +1011,7 @@ uint32_t nv108_pwr_code[] = { | |||
| 1009 | 0x0bf412a6, | 1011 | 0x0bf412a6, |
| 1010 | 0x071ec42e, | 1012 | 0x071ec42e, |
| 1011 | 0xb704ee94, | 1013 | 0xb704ee94, |
| 1012 | 0x980218e0, | 1014 | 0x980270e0, |
| 1013 | 0xec9803eb, | 1015 | 0xec9803eb, |
| 1014 | 0x01ed9802, | 1016 | 0x01ed9802, |
| 1015 | 0x7e00ee98, | 1017 | 0x7e00ee98, |
| @@ -1031,7 +1033,7 @@ uint32_t nv108_pwr_code[] = { | |||
| 1031 | 0xf412a608, | 1033 | 0xf412a608, |
| 1032 | 0x23c4ef0b, | 1034 | 0x23c4ef0b, |
| 1033 | 0x0434b607, | 1035 | 0x0434b607, |
| 1034 | 0x029830b7, | 1036 | 0x02f030b7, |
| 1035 | 0xb5033bb5, | 1037 | 0xb5033bb5, |
| 1036 | 0x3db5023c, | 1038 | 0x3db5023c, |
| 1037 | 0x003eb501, | 1039 | 0x003eb501, |
| @@ -1044,11 +1046,11 @@ uint32_t nv108_pwr_code[] = { | |||
| 1044 | /* 0x0379: host_init */ | 1046 | /* 0x0379: host_init */ |
| 1045 | 0x00804100, | 1047 | 0x00804100, |
| 1046 | 0xf11014b6, | 1048 | 0xf11014b6, |
| 1047 | 0x40021815, | 1049 | 0x40027015, |
| 1048 | 0x01f604d0, | 1050 | 0x01f604d0, |
| 1049 | 0x4104bd00, | 1051 | 0x4104bd00, |
| 1050 | 0x14b60080, | 1052 | 0x14b60080, |
| 1051 | 0x9815f110, | 1053 | 0xf015f110, |
| 1052 | 0x04dc4002, | 1054 | 0x04dc4002, |
| 1053 | 0xbd0001f6, | 1055 | 0xbd0001f6, |
| 1054 | 0x40010104, | 1056 | 0x40010104, |
| @@ -1101,13 +1103,13 @@ uint32_t nv108_pwr_code[] = { | |||
| 1101 | 0x001398b2, | 1103 | 0x001398b2, |
| 1102 | 0x950410b6, | 1104 | 0x950410b6, |
| 1103 | 0x30f01034, | 1105 | 0x30f01034, |
| 1104 | 0xc835980c, | 1106 | 0xde35980c, |
| 1105 | 0x12a655f9, | 1107 | 0x12a655f9, |
| 1106 | 0xfced1ef4, | 1108 | 0xfced1ef4, |
| 1107 | 0x7ee0fcd0, | 1109 | 0x7ee0fcd0, |
| 1108 | 0xf800023f, | 1110 | 0xf800023f, |
| 1109 | /* 0x0455: memx_info */ | 1111 | /* 0x0455: memx_info */ |
| 1110 | 0x03544c00, | 1112 | 0x03ac4c00, |
| 1111 | 0x7e08004b, | 1113 | 0x7e08004b, |
| 1112 | 0xf800023f, | 1114 | 0xf800023f, |
| 1113 | /* 0x0461: memx_recv */ | 1115 | /* 0x0461: memx_recv */ |
| @@ -1119,7 +1121,301 @@ uint32_t nv108_pwr_code[] = { | |||
| 1119 | /* 0x0471: perf_recv */ | 1121 | /* 0x0471: perf_recv */ |
| 1120 | /* 0x0473: perf_init */ | 1122 | /* 0x0473: perf_init */ |
| 1121 | 0xf800f800, | 1123 | 0xf800f800, |
| 1122 | /* 0x0475: test_recv */ | 1124 | /* 0x0475: i2c_drive_scl */ |
| 1125 | 0x0036b000, | ||
| 1126 | 0x400d0bf4, | ||
| 1127 | 0x01f607e0, | ||
| 1128 | 0xf804bd00, | ||
| 1129 | /* 0x0485: i2c_drive_scl_lo */ | ||
| 1130 | 0x07e44000, | ||
| 1131 | 0xbd0001f6, | ||
| 1132 | /* 0x048f: i2c_drive_sda */ | ||
| 1133 | 0xb000f804, | ||
| 1134 | 0x0bf40036, | ||
| 1135 | 0x07e0400d, | ||
| 1136 | 0xbd0002f6, | ||
| 1137 | /* 0x049f: i2c_drive_sda_lo */ | ||
| 1138 | 0x4000f804, | ||
| 1139 | 0x02f607e4, | ||
| 1140 | 0xf804bd00, | ||
| 1141 | /* 0x04a9: i2c_sense_scl */ | ||
| 1142 | 0x0132f400, | ||
| 1143 | 0xcf07c443, | ||
| 1144 | 0x31fd0033, | ||
| 1145 | 0x060bf404, | ||
| 1146 | /* 0x04bb: i2c_sense_scl_done */ | ||
| 1147 | 0xf80131f4, | ||
| 1148 | /* 0x04bd: i2c_sense_sda */ | ||
| 1149 | 0x0132f400, | ||
| 1150 | 0xcf07c443, | ||
| 1151 | 0x32fd0033, | ||
| 1152 | 0x060bf404, | ||
| 1153 | /* 0x04cf: i2c_sense_sda_done */ | ||
| 1154 | 0xf80131f4, | ||
| 1155 | /* 0x04d1: i2c_raise_scl */ | ||
| 1156 | 0x4440f900, | ||
| 1157 | 0x01030898, | ||
| 1158 | 0x0004757e, | ||
| 1159 | /* 0x04dc: i2c_raise_scl_wait */ | ||
| 1160 | 0x7e03e84e, | ||
| 1161 | 0x7e00005d, | ||
| 1162 | 0xf40004a9, | ||
| 1163 | 0x42b60901, | ||
| 1164 | 0xef1bf401, | ||
| 1165 | /* 0x04f0: i2c_raise_scl_done */ | ||
| 1166 | 0x00f840fc, | ||
| 1167 | /* 0x04f4: i2c_start */ | ||
| 1168 | 0x0004a97e, | ||
| 1169 | 0x7e0d11f4, | ||
| 1170 | 0xf40004bd, | ||
| 1171 | 0x0ef40611, | ||
| 1172 | /* 0x0505: i2c_start_rep */ | ||
| 1173 | 0x7e00032e, | ||
| 1174 | 0x03000475, | ||
| 1175 | 0x048f7e01, | ||
| 1176 | 0x0076bb00, | ||
| 1177 | 0xf90465b6, | ||
| 1178 | 0x04659450, | ||
| 1179 | 0xbd0256bb, | ||
| 1180 | 0x0475fd50, | ||
| 1181 | 0xd17e50fc, | ||
| 1182 | 0x64b60004, | ||
| 1183 | 0x1d11f404, | ||
| 1184 | /* 0x0530: i2c_start_send */ | ||
| 1185 | 0x8f7e0003, | ||
| 1186 | 0x884e0004, | ||
| 1187 | 0x005d7e13, | ||
| 1188 | 0x7e000300, | ||
| 1189 | 0x4e000475, | ||
| 1190 | 0x5d7e1388, | ||
| 1191 | /* 0x054a: i2c_start_out */ | ||
| 1192 | 0x00f80000, | ||
| 1193 | /* 0x054c: i2c_stop */ | ||
| 1194 | 0x757e0003, | ||
| 1195 | 0x00030004, | ||
| 1196 | 0x00048f7e, | ||
| 1197 | 0x7e03e84e, | ||
| 1198 | 0x0300005d, | ||
| 1199 | 0x04757e01, | ||
| 1200 | 0x13884e00, | ||
| 1201 | 0x00005d7e, | ||
| 1202 | 0x8f7e0103, | ||
| 1203 | 0x884e0004, | ||
| 1204 | 0x005d7e13, | ||
| 1205 | /* 0x057b: i2c_bitw */ | ||
| 1206 | 0x7e00f800, | ||
| 1207 | 0x4e00048f, | ||
| 1208 | 0x5d7e03e8, | ||
| 1209 | 0x76bb0000, | ||
| 1210 | 0x0465b600, | ||
| 1211 | 0x659450f9, | ||
| 1212 | 0x0256bb04, | ||
| 1213 | 0x75fd50bd, | ||
| 1214 | 0x7e50fc04, | ||
| 1215 | 0xb60004d1, | ||
| 1216 | 0x11f40464, | ||
| 1217 | 0x13884e17, | ||
| 1218 | 0x00005d7e, | ||
| 1219 | 0x757e0003, | ||
| 1220 | 0x884e0004, | ||
| 1221 | 0x005d7e13, | ||
| 1222 | /* 0x05b9: i2c_bitw_out */ | ||
| 1223 | /* 0x05bb: i2c_bitr */ | ||
| 1224 | 0x0300f800, | ||
| 1225 | 0x048f7e01, | ||
| 1226 | 0x03e84e00, | ||
| 1227 | 0x00005d7e, | ||
| 1228 | 0xb60076bb, | ||
| 1229 | 0x50f90465, | ||
| 1230 | 0xbb046594, | ||
| 1231 | 0x50bd0256, | ||
| 1232 | 0xfc0475fd, | ||
| 1233 | 0x04d17e50, | ||
| 1234 | 0x0464b600, | ||
| 1235 | 0x7e1a11f4, | ||
| 1236 | 0x030004bd, | ||
| 1237 | 0x04757e00, | ||
| 1238 | 0x13884e00, | ||
| 1239 | 0x00005d7e, | ||
| 1240 | 0xf4013cf0, | ||
| 1241 | /* 0x05fe: i2c_bitr_done */ | ||
| 1242 | 0x00f80131, | ||
| 1243 | /* 0x0600: i2c_get_byte */ | ||
| 1244 | 0x08040005, | ||
| 1245 | /* 0x0604: i2c_get_byte_next */ | ||
| 1246 | 0xbb0154b6, | ||
| 1247 | 0x65b60076, | ||
| 1248 | 0x9450f904, | ||
| 1249 | 0x56bb0465, | ||
| 1250 | 0xfd50bd02, | ||
| 1251 | 0x50fc0475, | ||
| 1252 | 0x0005bb7e, | ||
| 1253 | 0xf40464b6, | ||
| 1254 | 0x53fd2a11, | ||
| 1255 | 0x0142b605, | ||
| 1256 | 0x03d81bf4, | ||
| 1257 | 0x0076bb01, | ||
| 1258 | 0xf90465b6, | ||
| 1259 | 0x04659450, | ||
| 1260 | 0xbd0256bb, | ||
| 1261 | 0x0475fd50, | ||
| 1262 | 0x7b7e50fc, | ||
| 1263 | 0x64b60005, | ||
| 1264 | /* 0x064d: i2c_get_byte_done */ | ||
| 1265 | /* 0x064f: i2c_put_byte */ | ||
| 1266 | 0x0400f804, | ||
| 1267 | /* 0x0651: i2c_put_byte_next */ | ||
| 1268 | 0x0142b608, | ||
| 1269 | 0xbb3854ff, | ||
| 1270 | 0x65b60076, | ||
| 1271 | 0x9450f904, | ||
| 1272 | 0x56bb0465, | ||
| 1273 | 0xfd50bd02, | ||
| 1274 | 0x50fc0475, | ||
| 1275 | 0x00057b7e, | ||
| 1276 | 0xf40464b6, | ||
| 1277 | 0x46b03411, | ||
| 1278 | 0xd81bf400, | ||
| 1279 | 0xb60076bb, | ||
| 1280 | 0x50f90465, | ||
| 1281 | 0xbb046594, | ||
| 1282 | 0x50bd0256, | ||
| 1283 | 0xfc0475fd, | ||
| 1284 | 0x05bb7e50, | ||
| 1285 | 0x0464b600, | ||
| 1286 | 0xbb0f11f4, | ||
| 1287 | 0x36b00076, | ||
| 1288 | 0x061bf401, | ||
| 1289 | /* 0x06a7: i2c_put_byte_done */ | ||
| 1290 | 0xf80132f4, | ||
| 1291 | /* 0x06a9: i2c_addr */ | ||
| 1292 | 0x0076bb00, | ||
| 1293 | 0xf90465b6, | ||
| 1294 | 0x04659450, | ||
| 1295 | 0xbd0256bb, | ||
| 1296 | 0x0475fd50, | ||
| 1297 | 0xf47e50fc, | ||
| 1298 | 0x64b60004, | ||
| 1299 | 0x2911f404, | ||
| 1300 | 0x012ec3e7, | ||
| 1301 | 0xfd0134b6, | ||
| 1302 | 0x76bb0553, | ||
| 1303 | 0x0465b600, | ||
| 1304 | 0x659450f9, | ||
| 1305 | 0x0256bb04, | ||
| 1306 | 0x75fd50bd, | ||
| 1307 | 0x7e50fc04, | ||
| 1308 | 0xb600064f, | ||
| 1309 | /* 0x06ee: i2c_addr_done */ | ||
| 1310 | 0x00f80464, | ||
| 1311 | /* 0x06f0: i2c_acquire_addr */ | ||
| 1312 | 0xb6f8cec7, | ||
| 1313 | 0xe0b705e4, | ||
| 1314 | 0x00f8d014, | ||
| 1315 | /* 0x06fc: i2c_acquire */ | ||
| 1316 | 0x0006f07e, | ||
| 1317 | 0x0000047e, | ||
| 1318 | 0x7e03d9f0, | ||
| 1319 | 0xf800002e, | ||
| 1320 | /* 0x070d: i2c_release */ | ||
| 1321 | 0x06f07e00, | ||
| 1322 | 0x00047e00, | ||
| 1323 | 0x03daf000, | ||
| 1324 | 0x00002e7e, | ||
| 1325 | /* 0x071e: i2c_recv */ | ||
| 1326 | 0x32f400f8, | ||
| 1327 | 0xf8c1c701, | ||
| 1328 | 0xb00214b6, | ||
| 1329 | 0x1ff52816, | ||
| 1330 | 0x13b80137, | ||
| 1331 | 0x98000bd4, | ||
| 1332 | 0x13b80032, | ||
| 1333 | 0x98000bac, | ||
| 1334 | 0x31f40031, | ||
| 1335 | 0xf9d0f902, | ||
| 1336 | 0xf1d0f9e0, | ||
| 1337 | 0xf1000067, | ||
| 1338 | 0x92100063, | ||
| 1339 | 0x76bb0167, | ||
| 1340 | 0x0465b600, | ||
| 1341 | 0x659450f9, | ||
| 1342 | 0x0256bb04, | ||
| 1343 | 0x75fd50bd, | ||
| 1344 | 0x7e50fc04, | ||
| 1345 | 0xb60006fc, | ||
| 1346 | 0xd0fc0464, | ||
| 1347 | 0xf500d6b0, | ||
| 1348 | 0x0500b01b, | ||
| 1349 | 0x0076bb00, | ||
| 1350 | 0xf90465b6, | ||
| 1351 | 0x04659450, | ||
| 1352 | 0xbd0256bb, | ||
| 1353 | 0x0475fd50, | ||
| 1354 | 0xa97e50fc, | ||
| 1355 | 0x64b60006, | ||
| 1356 | 0xcc11f504, | ||
| 1357 | 0xe0c5c700, | ||
| 1358 | 0xb60076bb, | ||
| 1359 | 0x50f90465, | ||
| 1360 | 0xbb046594, | ||
| 1361 | 0x50bd0256, | ||
| 1362 | 0xfc0475fd, | ||
| 1363 | 0x064f7e50, | ||
| 1364 | 0x0464b600, | ||
| 1365 | 0x00a911f5, | ||
| 1366 | 0x76bb0105, | ||
| 1367 | 0x0465b600, | ||
| 1368 | 0x659450f9, | ||
| 1369 | 0x0256bb04, | ||
| 1370 | 0x75fd50bd, | ||
| 1371 | 0x7e50fc04, | ||
| 1372 | 0xb60006a9, | ||
| 1373 | 0x11f50464, | ||
| 1374 | 0x76bb0087, | ||
| 1375 | 0x0465b600, | ||
| 1376 | 0x659450f9, | ||
| 1377 | 0x0256bb04, | ||
| 1378 | 0x75fd50bd, | ||
| 1379 | 0x7e50fc04, | ||
| 1380 | 0xb6000600, | ||
| 1381 | 0x11f40464, | ||
| 1382 | 0xe05bcb67, | ||
| 1383 | 0xb60076bb, | ||
| 1384 | 0x50f90465, | ||
| 1385 | 0xbb046594, | ||
| 1386 | 0x50bd0256, | ||
| 1387 | 0xfc0475fd, | ||
| 1388 | 0x054c7e50, | ||
| 1389 | 0x0464b600, | ||
| 1390 | 0x74bd5bb2, | ||
| 1391 | /* 0x0823: i2c_recv_not_rd08 */ | ||
| 1392 | 0xb0410ef4, | ||
| 1393 | 0x1bf401d6, | ||
| 1394 | 0x7e00053b, | ||
| 1395 | 0xf40006a9, | ||
| 1396 | 0xc5c73211, | ||
| 1397 | 0x064f7ee0, | ||
| 1398 | 0x2811f400, | ||
| 1399 | 0xa97e0005, | ||
| 1400 | 0x11f40006, | ||
| 1401 | 0xe0b5c71f, | ||
| 1402 | 0x00064f7e, | ||
| 1403 | 0x7e1511f4, | ||
| 1404 | 0xbd00054c, | ||
| 1405 | 0x08c5c774, | ||
| 1406 | 0xf4091bf4, | ||
| 1407 | 0x0ef40232, | ||
| 1408 | /* 0x0861: i2c_recv_not_wr08 */ | ||
| 1409 | /* 0x0861: i2c_recv_done */ | ||
| 1410 | 0xf8cec703, | ||
| 1411 | 0x00070d7e, | ||
| 1412 | 0xd0fce0fc, | ||
| 1413 | 0xb20912f4, | ||
| 1414 | 0x023f7e7c, | ||
| 1415 | /* 0x0875: i2c_recv_exit */ | ||
| 1416 | /* 0x0877: i2c_init */ | ||
| 1417 | 0xf800f800, | ||
| 1418 | /* 0x0879: test_recv */ | ||
| 1123 | 0x04584100, | 1419 | 0x04584100, |
| 1124 | 0xb60011cf, | 1420 | 0xb60011cf, |
| 1125 | 0x58400110, | 1421 | 0x58400110, |
| @@ -1128,26 +1424,26 @@ uint32_t nv108_pwr_code[] = { | |||
| 1128 | 0xe3f1d900, | 1424 | 0xe3f1d900, |
| 1129 | 0x967e134f, | 1425 | 0x967e134f, |
| 1130 | 0x00f80001, | 1426 | 0x00f80001, |
| 1131 | /* 0x0494: test_init */ | 1427 | /* 0x0898: test_init */ |
| 1132 | 0x7e08004e, | 1428 | 0x7e08004e, |
| 1133 | 0xf8000196, | 1429 | 0xf8000196, |
| 1134 | /* 0x049d: idle_recv */ | 1430 | /* 0x08a1: idle_recv */ |
| 1135 | /* 0x049f: idle */ | 1431 | /* 0x08a3: idle */ |
| 1136 | 0xf400f800, | 1432 | 0xf400f800, |
| 1137 | 0x54410031, | 1433 | 0x54410031, |
| 1138 | 0x0011cf04, | 1434 | 0x0011cf04, |
| 1139 | 0x400110b6, | 1435 | 0x400110b6, |
| 1140 | 0x01f60454, | 1436 | 0x01f60454, |
| 1141 | /* 0x04b3: idle_loop */ | 1437 | /* 0x08b7: idle_loop */ |
| 1142 | 0x0104bd00, | 1438 | 0x0104bd00, |
| 1143 | 0x0232f458, | 1439 | 0x0232f458, |
| 1144 | /* 0x04b8: idle_proc */ | 1440 | /* 0x08bc: idle_proc */ |
| 1145 | /* 0x04b8: idle_proc_exec */ | 1441 | /* 0x08bc: idle_proc_exec */ |
| 1146 | 0x1eb210f9, | 1442 | 0x1eb210f9, |
| 1147 | 0x0002487e, | 1443 | 0x0002487e, |
| 1148 | 0x11f410fc, | 1444 | 0x11f410fc, |
| 1149 | 0x0231f409, | 1445 | 0x0231f409, |
| 1150 | /* 0x04cb: idle_proc_next */ | 1446 | /* 0x08cf: idle_proc_next */ |
| 1151 | 0xb6f00ef4, | 1447 | 0xb6f00ef4, |
| 1152 | 0x1fa65810, | 1448 | 0x1fa65810, |
| 1153 | 0xf4e81bf4, | 1449 | 0xf4e81bf4, |
| @@ -1161,5 +1457,4 @@ uint32_t nv108_pwr_code[] = { | |||
| 1161 | 0x00000000, | 1457 | 0x00000000, |
| 1162 | 0x00000000, | 1458 | 0x00000000, |
| 1163 | 0x00000000, | 1459 | 0x00000000, |
| 1164 | 0x00000000, | ||
| 1165 | }; | 1460 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc index 6fde0b89e5aa..6744fcc06151 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | #include "host.fuc" | 37 | #include "host.fuc" |
| 38 | #include "memx.fuc" | 38 | #include "memx.fuc" |
| 39 | #include "perf.fuc" | 39 | #include "perf.fuc" |
| 40 | #include "i2c_.fuc" | ||
| 40 | #include "test.fuc" | 41 | #include "test.fuc" |
| 41 | #include "idle.fuc" | 42 | #include "idle.fuc" |
| 42 | #undef INCLUDE_PROC | 43 | #undef INCLUDE_PROC |
| @@ -46,6 +47,7 @@ | |||
| 46 | #include "host.fuc" | 47 | #include "host.fuc" |
| 47 | #include "memx.fuc" | 48 | #include "memx.fuc" |
| 48 | #include "perf.fuc" | 49 | #include "perf.fuc" |
| 50 | #include "i2c_.fuc" | ||
| 49 | #include "test.fuc" | 51 | #include "test.fuc" |
| 50 | #include "idle.fuc" | 52 | #include "idle.fuc" |
| 51 | #undef INCLUDE_DATA | 53 | #undef INCLUDE_DATA |
| @@ -57,6 +59,7 @@ | |||
| 57 | #include "host.fuc" | 59 | #include "host.fuc" |
| 58 | #include "memx.fuc" | 60 | #include "memx.fuc" |
| 59 | #include "perf.fuc" | 61 | #include "perf.fuc" |
| 62 | #include "i2c_.fuc" | ||
| 60 | #include "test.fuc" | 63 | #include "test.fuc" |
| 61 | #include "idle.fuc" | 64 | #include "idle.fuc" |
| 62 | #undef INCLUDE_CODE | 65 | #undef INCLUDE_CODE |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h index 0fa4d7dcd407..5a73fa620978 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h | |||
| @@ -89,9 +89,31 @@ uint32_t nva3_pwr_data[] = { | |||
| 89 | 0x00000000, | 89 | 0x00000000, |
| 90 | 0x00000000, | 90 | 0x00000000, |
| 91 | 0x00000000, | 91 | 0x00000000, |
| 92 | 0x5f433249, | ||
| 93 | 0x00000982, | ||
| 94 | 0x00000825, | ||
| 95 | 0x00000000, | ||
| 96 | 0x00000000, | ||
| 97 | 0x00000000, | ||
| 98 | 0x00000000, | ||
| 99 | 0x00000000, | ||
| 100 | 0x00000000, | ||
| 101 | 0x00000000, | ||
| 102 | 0x00000000, | ||
| 103 | 0x00000000, | ||
| 104 | 0x00000000, | ||
| 105 | 0x00000000, | ||
| 106 | 0x00000000, | ||
| 107 | 0x00000000, | ||
| 108 | 0x00000000, | ||
| 109 | 0x00000000, | ||
| 110 | 0x00000000, | ||
| 111 | 0x00000000, | ||
| 112 | 0x00000000, | ||
| 113 | 0x00000000, | ||
| 92 | 0x54534554, | 114 | 0x54534554, |
| 93 | 0x0000057b, | 115 | 0x000009ab, |
| 94 | 0x00000554, | 116 | 0x00000984, |
| 95 | 0x00000000, | 117 | 0x00000000, |
| 96 | 0x00000000, | 118 | 0x00000000, |
| 97 | 0x00000000, | 119 | 0x00000000, |
| @@ -112,8 +134,8 @@ uint32_t nva3_pwr_data[] = { | |||
| 112 | 0x00000000, | 134 | 0x00000000, |
| 113 | 0x00000000, | 135 | 0x00000000, |
| 114 | 0x454c4449, | 136 | 0x454c4449, |
| 115 | 0x00000587, | 137 | 0x000009b7, |
| 116 | 0x00000585, | 138 | 0x000009b5, |
| 117 | 0x00000000, | 139 | 0x00000000, |
| 118 | 0x00000000, | 140 | 0x00000000, |
| 119 | 0x00000000, | 141 | 0x00000000, |
| @@ -133,12 +155,12 @@ uint32_t nva3_pwr_data[] = { | |||
| 133 | 0x00000000, | 155 | 0x00000000, |
| 134 | 0x00000000, | 156 | 0x00000000, |
| 135 | 0x00000000, | 157 | 0x00000000, |
| 136 | /* 0x0210: proc_list_tail */ | 158 | /* 0x0268: proc_list_tail */ |
| 137 | /* 0x0210: time_prev */ | 159 | /* 0x0268: time_prev */ |
| 138 | 0x00000000, | 160 | 0x00000000, |
| 139 | /* 0x0214: time_next */ | 161 | /* 0x026c: time_next */ |
| 140 | 0x00000000, | 162 | 0x00000000, |
| 141 | /* 0x0218: fifo_queue */ | 163 | /* 0x0270: fifo_queue */ |
| 142 | 0x00000000, | 164 | 0x00000000, |
| 143 | 0x00000000, | 165 | 0x00000000, |
| 144 | 0x00000000, | 166 | 0x00000000, |
| @@ -171,7 +193,7 @@ uint32_t nva3_pwr_data[] = { | |||
| 171 | 0x00000000, | 193 | 0x00000000, |
| 172 | 0x00000000, | 194 | 0x00000000, |
| 173 | 0x00000000, | 195 | 0x00000000, |
| 174 | /* 0x0298: rfifo_queue */ | 196 | /* 0x02f0: rfifo_queue */ |
| 175 | 0x00000000, | 197 | 0x00000000, |
| 176 | 0x00000000, | 198 | 0x00000000, |
| 177 | 0x00000000, | 199 | 0x00000000, |
| @@ -204,11 +226,11 @@ uint32_t nva3_pwr_data[] = { | |||
| 204 | 0x00000000, | 226 | 0x00000000, |
| 205 | 0x00000000, | 227 | 0x00000000, |
| 206 | 0x00000000, | 228 | 0x00000000, |
| 207 | /* 0x0318: memx_func_head */ | 229 | /* 0x0370: memx_func_head */ |
| 208 | 0x00010000, | 230 | 0x00010000, |
| 209 | 0x00000000, | 231 | 0x00000000, |
| 210 | 0x0000046f, | 232 | 0x0000046f, |
| 211 | /* 0x0324: memx_func_next */ | 233 | /* 0x037c: memx_func_next */ |
| 212 | 0x00000001, | 234 | 0x00000001, |
| 213 | 0x00000000, | 235 | 0x00000000, |
| 214 | 0x00000496, | 236 | 0x00000496, |
| @@ -221,8 +243,18 @@ uint32_t nva3_pwr_data[] = { | |||
| 221 | 0x00010004, | 243 | 0x00010004, |
| 222 | 0x00000000, | 244 | 0x00000000, |
| 223 | 0x000004fc, | 245 | 0x000004fc, |
| 224 | /* 0x0354: memx_func_tail */ | 246 | /* 0x03ac: memx_func_tail */ |
| 225 | /* 0x0354: memx_data_head */ | 247 | /* 0x03ac: memx_data_head */ |
| 248 | 0x00000000, | ||
| 249 | 0x00000000, | ||
| 250 | 0x00000000, | ||
| 251 | 0x00000000, | ||
| 252 | 0x00000000, | ||
| 253 | 0x00000000, | ||
| 254 | 0x00000000, | ||
| 255 | 0x00000000, | ||
| 256 | 0x00000000, | ||
| 257 | 0x00000000, | ||
| 226 | 0x00000000, | 258 | 0x00000000, |
| 227 | 0x00000000, | 259 | 0x00000000, |
| 228 | 0x00000000, | 260 | 0x00000000, |
| @@ -725,6 +757,42 @@ uint32_t nva3_pwr_data[] = { | |||
| 725 | 0x00000000, | 757 | 0x00000000, |
| 726 | 0x00000000, | 758 | 0x00000000, |
| 727 | 0x00000000, | 759 | 0x00000000, |
| 760 | /* 0x0bac: memx_data_tail */ | ||
| 761 | /* 0x0bac: i2c_scl_map */ | ||
| 762 | 0x00001000, | ||
| 763 | 0x00004000, | ||
| 764 | 0x00010000, | ||
| 765 | 0x00000100, | ||
| 766 | 0x00040000, | ||
| 767 | 0x00100000, | ||
| 768 | 0x00400000, | ||
| 769 | 0x01000000, | ||
| 770 | 0x04000000, | ||
| 771 | 0x10000000, | ||
| 772 | /* 0x0bd4: i2c_sda_map */ | ||
| 773 | 0x00002000, | ||
| 774 | 0x00008000, | ||
| 775 | 0x00020000, | ||
| 776 | 0x00000200, | ||
| 777 | 0x00080000, | ||
| 778 | 0x00200000, | ||
| 779 | 0x00800000, | ||
| 780 | 0x02000000, | ||
| 781 | 0x08000000, | ||
| 782 | 0x20000000, | ||
| 783 | /* 0x0bfc: i2c_ctrl */ | ||
| 784 | 0x0000e138, | ||
| 785 | 0x0000e150, | ||
| 786 | 0x0000e168, | ||
| 787 | 0x0000e180, | ||
| 788 | 0x0000e254, | ||
| 789 | 0x0000e274, | ||
| 790 | 0x0000e764, | ||
| 791 | 0x0000e780, | ||
| 792 | 0x0000e79c, | ||
| 793 | 0x0000e7b8, | ||
| 794 | 0x00000000, | ||
| 795 | 0x00000000, | ||
| 728 | 0x00000000, | 796 | 0x00000000, |
| 729 | 0x00000000, | 797 | 0x00000000, |
| 730 | 0x00000000, | 798 | 0x00000000, |
| @@ -735,7 +803,6 @@ uint32_t nva3_pwr_data[] = { | |||
| 735 | 0x00000000, | 803 | 0x00000000, |
| 736 | 0x00000000, | 804 | 0x00000000, |
| 737 | 0x00000000, | 805 | 0x00000000, |
| 738 | /* 0x0b54: memx_data_tail */ | ||
| 739 | 0x00000000, | 806 | 0x00000000, |
| 740 | 0x00000000, | 807 | 0x00000000, |
| 741 | 0x00000000, | 808 | 0x00000000, |
| @@ -787,15 +854,15 @@ uint32_t nva3_pwr_code[] = { | |||
| 787 | 0x07a007f1, | 854 | 0x07a007f1, |
| 788 | 0xd00604b6, | 855 | 0xd00604b6, |
| 789 | 0x04bd000e, | 856 | 0x04bd000e, |
| 790 | 0xf001e7f0, | 857 | 0xf001d7f0, |
| 791 | 0x07f101e3, | 858 | 0x07f101d3, |
| 792 | 0x04b607ac, | 859 | 0x04b607ac, |
| 793 | 0x000ed006, | 860 | 0x000dd006, |
| 794 | /* 0x0022: rd32_wait */ | 861 | /* 0x0022: rd32_wait */ |
| 795 | 0xe7f104bd, | 862 | 0xd7f104bd, |
| 796 | 0xe4b607ac, | 863 | 0xd4b607ac, |
| 797 | 0x00eecf06, | 864 | 0x00ddcf06, |
| 798 | 0x7000e4f1, | 865 | 0x7000d4f1, |
| 799 | 0xf1f21bf4, | 866 | 0xf1f21bf4, |
| 800 | 0xb607a4d7, | 867 | 0xb607a4d7, |
| 801 | 0xddcf06d4, | 868 | 0xddcf06d4, |
| @@ -807,15 +874,15 @@ uint32_t nva3_pwr_code[] = { | |||
| 807 | 0xb607a407, | 874 | 0xb607a407, |
| 808 | 0x0dd00604, | 875 | 0x0dd00604, |
| 809 | 0xf004bd00, | 876 | 0xf004bd00, |
| 810 | 0xe5f002e7, | 877 | 0xd5f002d7, |
| 811 | 0x01e3f0f0, | 878 | 0x01d3f0f0, |
| 812 | 0x07ac07f1, | 879 | 0x07ac07f1, |
| 813 | 0xd00604b6, | 880 | 0xd00604b6, |
| 814 | 0x04bd000e, | 881 | 0x04bd000d, |
| 815 | /* 0x006c: wr32_wait */ | 882 | /* 0x006c: wr32_wait */ |
| 816 | 0x07ace7f1, | 883 | 0x07acd7f1, |
| 817 | 0xcf06e4b6, | 884 | 0xcf06d4b6, |
| 818 | 0xe4f100ee, | 885 | 0xd4f100dd, |
| 819 | 0x1bf47000, | 886 | 0x1bf47000, |
| 820 | /* 0x007f: nsec */ | 887 | /* 0x007f: nsec */ |
| 821 | 0xf000f8f2, | 888 | 0xf000f8f2, |
| @@ -845,21 +912,21 @@ uint32_t nva3_pwr_code[] = { | |||
| 845 | 0x9800f8df, | 912 | 0x9800f8df, |
| 846 | 0x96b003e9, | 913 | 0x96b003e9, |
| 847 | 0x2a0bf400, | 914 | 0x2a0bf400, |
| 848 | 0xbb840a98, | 915 | 0xbb9a0a98, |
| 849 | 0x1cf4029a, | 916 | 0x1cf4029a, |
| 850 | 0x01d7f00f, | 917 | 0x01d7f00f, |
| 851 | 0x025421f5, | 918 | 0x025421f5, |
| 852 | 0x0ef494bd, | 919 | 0x0ef494bd, |
| 853 | /* 0x00e9: intr_watchdog_next_time */ | 920 | /* 0x00e9: intr_watchdog_next_time */ |
| 854 | 0x850a9815, | 921 | 0x9b0a9815, |
| 855 | 0xf400a6b0, | 922 | 0xf400a6b0, |
| 856 | 0x9ab8090b, | 923 | 0x9ab8090b, |
| 857 | 0x061cf406, | 924 | 0x061cf406, |
| 858 | /* 0x00f8: intr_watchdog_next_time_set */ | 925 | /* 0x00f8: intr_watchdog_next_time_set */ |
| 859 | /* 0x00fb: intr_watchdog_next_proc */ | 926 | /* 0x00fb: intr_watchdog_next_proc */ |
| 860 | 0x80850980, | 927 | 0x809b0980, |
| 861 | 0xe0b603e9, | 928 | 0xe0b603e9, |
| 862 | 0x10e6b158, | 929 | 0x68e6b158, |
| 863 | 0xc61bf402, | 930 | 0xc61bf402, |
| 864 | /* 0x010a: intr */ | 931 | /* 0x010a: intr */ |
| 865 | 0x00f900f8, | 932 | 0x00f900f8, |
| @@ -880,15 +947,15 @@ uint32_t nva3_pwr_code[] = { | |||
| 880 | 0x0088cf06, | 947 | 0x0088cf06, |
| 881 | 0xf40289c4, | 948 | 0xf40289c4, |
| 882 | 0x0080230b, | 949 | 0x0080230b, |
| 883 | 0x58e7f085, | 950 | 0x58e7f09b, |
| 884 | 0x98cb21f4, | 951 | 0x98cb21f4, |
| 885 | 0x96b08509, | 952 | 0x96b09b09, |
| 886 | 0x110bf400, | 953 | 0x110bf400, |
| 887 | 0xb63407f0, | 954 | 0xb63407f0, |
| 888 | 0x09d00604, | 955 | 0x09d00604, |
| 889 | 0x8004bd00, | 956 | 0x8004bd00, |
| 890 | /* 0x016e: intr_skip_watchdog */ | 957 | /* 0x016e: intr_skip_watchdog */ |
| 891 | 0x89e48409, | 958 | 0x89e49a09, |
| 892 | 0x0bf40800, | 959 | 0x0bf40800, |
| 893 | 0x8897f148, | 960 | 0x8897f148, |
| 894 | 0x0694b606, | 961 | 0x0694b606, |
| @@ -948,7 +1015,7 @@ uint32_t nva3_pwr_code[] = { | |||
| 948 | 0x000ed006, | 1015 | 0x000ed006, |
| 949 | 0x0e8004bd, | 1016 | 0x0e8004bd, |
| 950 | /* 0x0241: timer_enable */ | 1017 | /* 0x0241: timer_enable */ |
| 951 | 0x0187f084, | 1018 | 0x0187f09a, |
| 952 | 0xb63807f0, | 1019 | 0xb63807f0, |
| 953 | 0x08d00604, | 1020 | 0x08d00604, |
| 954 | /* 0x024f: timer_done */ | 1021 | /* 0x024f: timer_done */ |
| @@ -979,7 +1046,7 @@ uint32_t nva3_pwr_code[] = { | |||
| 979 | 0xb8008a98, | 1046 | 0xb8008a98, |
| 980 | 0x0bf406ae, | 1047 | 0x0bf406ae, |
| 981 | 0x5880b610, | 1048 | 0x5880b610, |
| 982 | 0x021086b1, | 1049 | 0x026886b1, |
| 983 | 0xf4f01bf4, | 1050 | 0xf4f01bf4, |
| 984 | /* 0x02b2: find_done */ | 1051 | /* 0x02b2: find_done */ |
| 985 | 0x8eb90132, | 1052 | 0x8eb90132, |
| @@ -1049,7 +1116,7 @@ uint32_t nva3_pwr_code[] = { | |||
| 1049 | 0x320bf406, | 1116 | 0x320bf406, |
| 1050 | 0x94071ec4, | 1117 | 0x94071ec4, |
| 1051 | 0xe0b704ee, | 1118 | 0xe0b704ee, |
| 1052 | 0xeb980218, | 1119 | 0xeb980270, |
| 1053 | 0x02ec9803, | 1120 | 0x02ec9803, |
| 1054 | 0x9801ed98, | 1121 | 0x9801ed98, |
| 1055 | 0x21f500ee, | 1122 | 0x21f500ee, |
| @@ -1075,7 +1142,7 @@ uint32_t nva3_pwr_code[] = { | |||
| 1075 | 0xe60bf406, | 1142 | 0xe60bf406, |
| 1076 | 0xb60723c4, | 1143 | 0xb60723c4, |
| 1077 | 0x30b70434, | 1144 | 0x30b70434, |
| 1078 | 0x3b800298, | 1145 | 0x3b8002f0, |
| 1079 | 0x023c8003, | 1146 | 0x023c8003, |
| 1080 | 0x80013d80, | 1147 | 0x80013d80, |
| 1081 | 0x20b6003e, | 1148 | 0x20b6003e, |
| @@ -1090,13 +1157,13 @@ uint32_t nva3_pwr_code[] = { | |||
| 1090 | /* 0x0430: host_init */ | 1157 | /* 0x0430: host_init */ |
| 1091 | 0x008017f1, | 1158 | 0x008017f1, |
| 1092 | 0xf11014b6, | 1159 | 0xf11014b6, |
| 1093 | 0xf1021815, | 1160 | 0xf1027015, |
| 1094 | 0xb604d007, | 1161 | 0xb604d007, |
| 1095 | 0x01d00604, | 1162 | 0x01d00604, |
| 1096 | 0xf104bd00, | 1163 | 0xf104bd00, |
| 1097 | 0xb6008017, | 1164 | 0xb6008017, |
| 1098 | 0x15f11014, | 1165 | 0x15f11014, |
| 1099 | 0x07f10298, | 1166 | 0x07f102f0, |
| 1100 | 0x04b604dc, | 1167 | 0x04b604dc, |
| 1101 | 0x0001d006, | 1168 | 0x0001d006, |
| 1102 | 0x17f004bd, | 1169 | 0x17f004bd, |
| @@ -1156,14 +1223,14 @@ uint32_t nva3_pwr_code[] = { | |||
| 1156 | 0x00139802, | 1223 | 0x00139802, |
| 1157 | 0x950410b6, | 1224 | 0x950410b6, |
| 1158 | 0x30f01034, | 1225 | 0x30f01034, |
| 1159 | 0xc835980c, | 1226 | 0xde35980c, |
| 1160 | 0x12b855f9, | 1227 | 0x12b855f9, |
| 1161 | 0xec1ef406, | 1228 | 0xec1ef406, |
| 1162 | 0xe0fcd0fc, | 1229 | 0xe0fcd0fc, |
| 1163 | 0x02b921f5, | 1230 | 0x02b921f5, |
| 1164 | /* 0x0532: memx_info */ | 1231 | /* 0x0532: memx_info */ |
| 1165 | 0xc7f100f8, | 1232 | 0xc7f100f8, |
| 1166 | 0xb7f10354, | 1233 | 0xb7f103ac, |
| 1167 | 0x21f50800, | 1234 | 0x21f50800, |
| 1168 | 0x00f802b9, | 1235 | 0x00f802b9, |
| 1169 | /* 0x0540: memx_recv */ | 1236 | /* 0x0540: memx_recv */ |
| @@ -1175,7 +1242,312 @@ uint32_t nva3_pwr_code[] = { | |||
| 1175 | /* 0x0550: perf_recv */ | 1242 | /* 0x0550: perf_recv */ |
| 1176 | /* 0x0552: perf_init */ | 1243 | /* 0x0552: perf_init */ |
| 1177 | 0x00f800f8, | 1244 | 0x00f800f8, |
| 1178 | /* 0x0554: test_recv */ | 1245 | /* 0x0554: i2c_drive_scl */ |
| 1246 | 0xf40036b0, | ||
| 1247 | 0x07f1110b, | ||
| 1248 | 0x04b607e0, | ||
| 1249 | 0x0001d006, | ||
| 1250 | 0x00f804bd, | ||
| 1251 | /* 0x0568: i2c_drive_scl_lo */ | ||
| 1252 | 0x07e407f1, | ||
| 1253 | 0xd00604b6, | ||
| 1254 | 0x04bd0001, | ||
| 1255 | /* 0x0576: i2c_drive_sda */ | ||
| 1256 | 0x36b000f8, | ||
| 1257 | 0x110bf400, | ||
| 1258 | 0x07e007f1, | ||
| 1259 | 0xd00604b6, | ||
| 1260 | 0x04bd0002, | ||
| 1261 | /* 0x058a: i2c_drive_sda_lo */ | ||
| 1262 | 0x07f100f8, | ||
| 1263 | 0x04b607e4, | ||
| 1264 | 0x0002d006, | ||
| 1265 | 0x00f804bd, | ||
| 1266 | /* 0x0598: i2c_sense_scl */ | ||
| 1267 | 0xf10132f4, | ||
| 1268 | 0xb607c437, | ||
| 1269 | 0x33cf0634, | ||
| 1270 | 0x0431fd00, | ||
| 1271 | 0xf4060bf4, | ||
| 1272 | /* 0x05ae: i2c_sense_scl_done */ | ||
| 1273 | 0x00f80131, | ||
| 1274 | /* 0x05b0: i2c_sense_sda */ | ||
| 1275 | 0xf10132f4, | ||
| 1276 | 0xb607c437, | ||
| 1277 | 0x33cf0634, | ||
| 1278 | 0x0432fd00, | ||
| 1279 | 0xf4060bf4, | ||
| 1280 | /* 0x05c6: i2c_sense_sda_done */ | ||
| 1281 | 0x00f80131, | ||
| 1282 | /* 0x05c8: i2c_raise_scl */ | ||
| 1283 | 0x47f140f9, | ||
| 1284 | 0x37f00898, | ||
| 1285 | 0x5421f501, | ||
| 1286 | /* 0x05d5: i2c_raise_scl_wait */ | ||
| 1287 | 0xe8e7f105, | ||
| 1288 | 0x7f21f403, | ||
| 1289 | 0x059821f5, | ||
| 1290 | 0xb60901f4, | ||
| 1291 | 0x1bf40142, | ||
| 1292 | /* 0x05e9: i2c_raise_scl_done */ | ||
| 1293 | 0xf840fcef, | ||
| 1294 | /* 0x05ed: i2c_start */ | ||
| 1295 | 0x9821f500, | ||
| 1296 | 0x0d11f405, | ||
| 1297 | 0x05b021f5, | ||
| 1298 | 0xf40611f4, | ||
| 1299 | /* 0x05fe: i2c_start_rep */ | ||
| 1300 | 0x37f0300e, | ||
| 1301 | 0x5421f500, | ||
| 1302 | 0x0137f005, | ||
| 1303 | 0x057621f5, | ||
| 1304 | 0xb60076bb, | ||
| 1305 | 0x50f90465, | ||
| 1306 | 0xbb046594, | ||
| 1307 | 0x50bd0256, | ||
| 1308 | 0xfc0475fd, | ||
| 1309 | 0xc821f550, | ||
| 1310 | 0x0464b605, | ||
| 1311 | /* 0x062b: i2c_start_send */ | ||
| 1312 | 0xf01f11f4, | ||
| 1313 | 0x21f50037, | ||
| 1314 | 0xe7f10576, | ||
| 1315 | 0x21f41388, | ||
| 1316 | 0x0037f07f, | ||
| 1317 | 0x055421f5, | ||
| 1318 | 0x1388e7f1, | ||
| 1319 | /* 0x0647: i2c_start_out */ | ||
| 1320 | 0xf87f21f4, | ||
| 1321 | /* 0x0649: i2c_stop */ | ||
| 1322 | 0x0037f000, | ||
| 1323 | 0x055421f5, | ||
| 1324 | 0xf50037f0, | ||
| 1325 | 0xf1057621, | ||
| 1326 | 0xf403e8e7, | ||
| 1327 | 0x37f07f21, | ||
| 1328 | 0x5421f501, | ||
| 1329 | 0x88e7f105, | ||
| 1330 | 0x7f21f413, | ||
| 1331 | 0xf50137f0, | ||
| 1332 | 0xf1057621, | ||
| 1333 | 0xf41388e7, | ||
| 1334 | 0x00f87f21, | ||
| 1335 | /* 0x067c: i2c_bitw */ | ||
| 1336 | 0x057621f5, | ||
| 1337 | 0x03e8e7f1, | ||
| 1338 | 0xbb7f21f4, | ||
| 1339 | 0x65b60076, | ||
| 1340 | 0x9450f904, | ||
| 1341 | 0x56bb0465, | ||
| 1342 | 0xfd50bd02, | ||
| 1343 | 0x50fc0475, | ||
| 1344 | 0x05c821f5, | ||
| 1345 | 0xf40464b6, | ||
| 1346 | 0xe7f11811, | ||
| 1347 | 0x21f41388, | ||
| 1348 | 0x0037f07f, | ||
| 1349 | 0x055421f5, | ||
| 1350 | 0x1388e7f1, | ||
| 1351 | /* 0x06bb: i2c_bitw_out */ | ||
| 1352 | 0xf87f21f4, | ||
| 1353 | /* 0x06bd: i2c_bitr */ | ||
| 1354 | 0x0137f000, | ||
| 1355 | 0x057621f5, | ||
| 1356 | 0x03e8e7f1, | ||
| 1357 | 0xbb7f21f4, | ||
| 1358 | 0x65b60076, | ||
| 1359 | 0x9450f904, | ||
| 1360 | 0x56bb0465, | ||
| 1361 | 0xfd50bd02, | ||
| 1362 | 0x50fc0475, | ||
| 1363 | 0x05c821f5, | ||
| 1364 | 0xf40464b6, | ||
| 1365 | 0x21f51b11, | ||
| 1366 | 0x37f005b0, | ||
| 1367 | 0x5421f500, | ||
| 1368 | 0x88e7f105, | ||
| 1369 | 0x7f21f413, | ||
| 1370 | 0xf4013cf0, | ||
| 1371 | /* 0x0702: i2c_bitr_done */ | ||
| 1372 | 0x00f80131, | ||
| 1373 | /* 0x0704: i2c_get_byte */ | ||
| 1374 | 0xf00057f0, | ||
| 1375 | /* 0x070a: i2c_get_byte_next */ | ||
| 1376 | 0x54b60847, | ||
| 1377 | 0x0076bb01, | ||
| 1378 | 0xf90465b6, | ||
| 1379 | 0x04659450, | ||
| 1380 | 0xbd0256bb, | ||
| 1381 | 0x0475fd50, | ||
| 1382 | 0x21f550fc, | ||
| 1383 | 0x64b606bd, | ||
| 1384 | 0x2b11f404, | ||
| 1385 | 0xb60553fd, | ||
| 1386 | 0x1bf40142, | ||
| 1387 | 0x0137f0d8, | ||
| 1388 | 0xb60076bb, | ||
| 1389 | 0x50f90465, | ||
| 1390 | 0xbb046594, | ||
| 1391 | 0x50bd0256, | ||
| 1392 | 0xfc0475fd, | ||
| 1393 | 0x7c21f550, | ||
| 1394 | 0x0464b606, | ||
| 1395 | /* 0x0754: i2c_get_byte_done */ | ||
| 1396 | /* 0x0756: i2c_put_byte */ | ||
| 1397 | 0x47f000f8, | ||
| 1398 | /* 0x0759: i2c_put_byte_next */ | ||
| 1399 | 0x0142b608, | ||
| 1400 | 0xbb3854ff, | ||
| 1401 | 0x65b60076, | ||
| 1402 | 0x9450f904, | ||
| 1403 | 0x56bb0465, | ||
| 1404 | 0xfd50bd02, | ||
| 1405 | 0x50fc0475, | ||
| 1406 | 0x067c21f5, | ||
| 1407 | 0xf40464b6, | ||
| 1408 | 0x46b03411, | ||
| 1409 | 0xd81bf400, | ||
| 1410 | 0xb60076bb, | ||
| 1411 | 0x50f90465, | ||
| 1412 | 0xbb046594, | ||
| 1413 | 0x50bd0256, | ||
| 1414 | 0xfc0475fd, | ||
| 1415 | 0xbd21f550, | ||
| 1416 | 0x0464b606, | ||
| 1417 | 0xbb0f11f4, | ||
| 1418 | 0x36b00076, | ||
| 1419 | 0x061bf401, | ||
| 1420 | /* 0x07af: i2c_put_byte_done */ | ||
| 1421 | 0xf80132f4, | ||
| 1422 | /* 0x07b1: i2c_addr */ | ||
| 1423 | 0x0076bb00, | ||
| 1424 | 0xf90465b6, | ||
| 1425 | 0x04659450, | ||
| 1426 | 0xbd0256bb, | ||
| 1427 | 0x0475fd50, | ||
| 1428 | 0x21f550fc, | ||
| 1429 | 0x64b605ed, | ||
| 1430 | 0x2911f404, | ||
| 1431 | 0x012ec3e7, | ||
| 1432 | 0xfd0134b6, | ||
| 1433 | 0x76bb0553, | ||
| 1434 | 0x0465b600, | ||
| 1435 | 0x659450f9, | ||
| 1436 | 0x0256bb04, | ||
| 1437 | 0x75fd50bd, | ||
| 1438 | 0xf550fc04, | ||
| 1439 | 0xb6075621, | ||
| 1440 | /* 0x07f6: i2c_addr_done */ | ||
| 1441 | 0x00f80464, | ||
| 1442 | /* 0x07f8: i2c_acquire_addr */ | ||
| 1443 | 0xb6f8cec7, | ||
| 1444 | 0xe0b702e4, | ||
| 1445 | 0xee980bfc, | ||
| 1446 | /* 0x0807: i2c_acquire */ | ||
| 1447 | 0xf500f800, | ||
| 1448 | 0xf407f821, | ||
| 1449 | 0xd9f00421, | ||
| 1450 | 0x3f21f403, | ||
| 1451 | /* 0x0816: i2c_release */ | ||
| 1452 | 0x21f500f8, | ||
| 1453 | 0x21f407f8, | ||
| 1454 | 0x03daf004, | ||
| 1455 | 0xf83f21f4, | ||
| 1456 | /* 0x0825: i2c_recv */ | ||
| 1457 | 0x0132f400, | ||
| 1458 | 0xb6f8c1c7, | ||
| 1459 | 0x16b00214, | ||
| 1460 | 0x3a1ff528, | ||
| 1461 | 0xd413a001, | ||
| 1462 | 0x0032980b, | ||
| 1463 | 0x0bac13a0, | ||
| 1464 | 0xf4003198, | ||
| 1465 | 0xd0f90231, | ||
| 1466 | 0xd0f9e0f9, | ||
| 1467 | 0x000067f1, | ||
| 1468 | 0x100063f1, | ||
| 1469 | 0xbb016792, | ||
| 1470 | 0x65b60076, | ||
| 1471 | 0x9450f904, | ||
| 1472 | 0x56bb0465, | ||
| 1473 | 0xfd50bd02, | ||
| 1474 | 0x50fc0475, | ||
| 1475 | 0x080721f5, | ||
| 1476 | 0xfc0464b6, | ||
| 1477 | 0x00d6b0d0, | ||
| 1478 | 0x00b31bf5, | ||
| 1479 | 0xbb0057f0, | ||
| 1480 | 0x65b60076, | ||
| 1481 | 0x9450f904, | ||
| 1482 | 0x56bb0465, | ||
| 1483 | 0xfd50bd02, | ||
| 1484 | 0x50fc0475, | ||
| 1485 | 0x07b121f5, | ||
| 1486 | 0xf50464b6, | ||
| 1487 | 0xc700d011, | ||
| 1488 | 0x76bbe0c5, | ||
| 1489 | 0x0465b600, | ||
| 1490 | 0x659450f9, | ||
| 1491 | 0x0256bb04, | ||
| 1492 | 0x75fd50bd, | ||
| 1493 | 0xf550fc04, | ||
| 1494 | 0xb6075621, | ||
| 1495 | 0x11f50464, | ||
| 1496 | 0x57f000ad, | ||
| 1497 | 0x0076bb01, | ||
| 1498 | 0xf90465b6, | ||
| 1499 | 0x04659450, | ||
| 1500 | 0xbd0256bb, | ||
| 1501 | 0x0475fd50, | ||
| 1502 | 0x21f550fc, | ||
| 1503 | 0x64b607b1, | ||
| 1504 | 0x8a11f504, | ||
| 1505 | 0x0076bb00, | ||
| 1506 | 0xf90465b6, | ||
| 1507 | 0x04659450, | ||
| 1508 | 0xbd0256bb, | ||
| 1509 | 0x0475fd50, | ||
| 1510 | 0x21f550fc, | ||
| 1511 | 0x64b60704, | ||
| 1512 | 0x6a11f404, | ||
| 1513 | 0xbbe05bcb, | ||
| 1514 | 0x65b60076, | ||
| 1515 | 0x9450f904, | ||
| 1516 | 0x56bb0465, | ||
| 1517 | 0xfd50bd02, | ||
| 1518 | 0x50fc0475, | ||
| 1519 | 0x064921f5, | ||
| 1520 | 0xb90464b6, | ||
| 1521 | 0x74bd025b, | ||
| 1522 | /* 0x092b: i2c_recv_not_rd08 */ | ||
| 1523 | 0xb0430ef4, | ||
| 1524 | 0x1bf401d6, | ||
| 1525 | 0x0057f03d, | ||
| 1526 | 0x07b121f5, | ||
| 1527 | 0xc73311f4, | ||
| 1528 | 0x21f5e0c5, | ||
| 1529 | 0x11f40756, | ||
| 1530 | 0x0057f029, | ||
| 1531 | 0x07b121f5, | ||
| 1532 | 0xc71f11f4, | ||
| 1533 | 0x21f5e0b5, | ||
| 1534 | 0x11f40756, | ||
| 1535 | 0x4921f515, | ||
| 1536 | 0xc774bd06, | ||
| 1537 | 0x1bf408c5, | ||
| 1538 | 0x0232f409, | ||
| 1539 | /* 0x096b: i2c_recv_not_wr08 */ | ||
| 1540 | /* 0x096b: i2c_recv_done */ | ||
| 1541 | 0xc7030ef4, | ||
| 1542 | 0x21f5f8ce, | ||
| 1543 | 0xe0fc0816, | ||
| 1544 | 0x12f4d0fc, | ||
| 1545 | 0x027cb90a, | ||
| 1546 | 0x02b921f5, | ||
| 1547 | /* 0x0980: i2c_recv_exit */ | ||
| 1548 | /* 0x0982: i2c_init */ | ||
| 1549 | 0x00f800f8, | ||
| 1550 | /* 0x0984: test_recv */ | ||
| 1179 | 0x05d817f1, | 1551 | 0x05d817f1, |
| 1180 | 0xcf0614b6, | 1552 | 0xcf0614b6, |
| 1181 | 0x10b60011, | 1553 | 0x10b60011, |
| @@ -1185,12 +1557,12 @@ uint32_t nva3_pwr_code[] = { | |||
| 1185 | 0x00e7f104, | 1557 | 0x00e7f104, |
| 1186 | 0x4fe3f1d9, | 1558 | 0x4fe3f1d9, |
| 1187 | 0xf521f513, | 1559 | 0xf521f513, |
| 1188 | /* 0x057b: test_init */ | 1560 | /* 0x09ab: test_init */ |
| 1189 | 0xf100f801, | 1561 | 0xf100f801, |
| 1190 | 0xf50800e7, | 1562 | 0xf50800e7, |
| 1191 | 0xf801f521, | 1563 | 0xf801f521, |
| 1192 | /* 0x0585: idle_recv */ | 1564 | /* 0x09b5: idle_recv */ |
| 1193 | /* 0x0587: idle */ | 1565 | /* 0x09b7: idle */ |
| 1194 | 0xf400f800, | 1566 | 0xf400f800, |
| 1195 | 0x17f10031, | 1567 | 0x17f10031, |
| 1196 | 0x14b605d4, | 1568 | 0x14b605d4, |
| @@ -1198,32 +1570,20 @@ uint32_t nva3_pwr_code[] = { | |||
| 1198 | 0xf10110b6, | 1570 | 0xf10110b6, |
| 1199 | 0xb605d407, | 1571 | 0xb605d407, |
| 1200 | 0x01d00604, | 1572 | 0x01d00604, |
| 1201 | /* 0x05a3: idle_loop */ | 1573 | /* 0x09d3: idle_loop */ |
| 1202 | 0xf004bd00, | 1574 | 0xf004bd00, |
| 1203 | 0x32f45817, | 1575 | 0x32f45817, |
| 1204 | /* 0x05a9: idle_proc */ | 1576 | /* 0x09d9: idle_proc */ |
| 1205 | /* 0x05a9: idle_proc_exec */ | 1577 | /* 0x09d9: idle_proc_exec */ |
| 1206 | 0xb910f902, | 1578 | 0xb910f902, |
| 1207 | 0x21f5021e, | 1579 | 0x21f5021e, |
| 1208 | 0x10fc02c2, | 1580 | 0x10fc02c2, |
| 1209 | 0xf40911f4, | 1581 | 0xf40911f4, |
| 1210 | 0x0ef40231, | 1582 | 0x0ef40231, |
| 1211 | /* 0x05bd: idle_proc_next */ | 1583 | /* 0x09ed: idle_proc_next */ |
| 1212 | 0x5810b6ef, | 1584 | 0x5810b6ef, |
| 1213 | 0xf4061fb8, | 1585 | 0xf4061fb8, |
| 1214 | 0x02f4e61b, | 1586 | 0x02f4e61b, |
| 1215 | 0x0028f4dd, | 1587 | 0x0028f4dd, |
| 1216 | 0x00bb0ef4, | 1588 | 0x00bb0ef4, |
| 1217 | 0x00000000, | ||
| 1218 | 0x00000000, | ||
| 1219 | 0x00000000, | ||
| 1220 | 0x00000000, | ||
| 1221 | 0x00000000, | ||
| 1222 | 0x00000000, | ||
| 1223 | 0x00000000, | ||
| 1224 | 0x00000000, | ||
| 1225 | 0x00000000, | ||
| 1226 | 0x00000000, | ||
| 1227 | 0x00000000, | ||
| 1228 | 0x00000000, | ||
| 1229 | }; | 1589 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc index eaa64da68e36..48f79434a449 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | #include "host.fuc" | 37 | #include "host.fuc" |
| 38 | #include "memx.fuc" | 38 | #include "memx.fuc" |
| 39 | #include "perf.fuc" | 39 | #include "perf.fuc" |
| 40 | #include "i2c_.fuc" | ||
| 40 | #include "test.fuc" | 41 | #include "test.fuc" |
| 41 | #include "idle.fuc" | 42 | #include "idle.fuc" |
| 42 | #undef INCLUDE_PROC | 43 | #undef INCLUDE_PROC |
| @@ -46,6 +47,7 @@ | |||
| 46 | #include "host.fuc" | 47 | #include "host.fuc" |
| 47 | #include "memx.fuc" | 48 | #include "memx.fuc" |
| 48 | #include "perf.fuc" | 49 | #include "perf.fuc" |
| 50 | #include "i2c_.fuc" | ||
| 49 | #include "test.fuc" | 51 | #include "test.fuc" |
| 50 | #include "idle.fuc" | 52 | #include "idle.fuc" |
| 51 | #undef INCLUDE_DATA | 53 | #undef INCLUDE_DATA |
| @@ -57,6 +59,7 @@ | |||
| 57 | #include "host.fuc" | 59 | #include "host.fuc" |
| 58 | #include "memx.fuc" | 60 | #include "memx.fuc" |
| 59 | #include "perf.fuc" | 61 | #include "perf.fuc" |
| 62 | #include "i2c_.fuc" | ||
| 60 | #include "test.fuc" | 63 | #include "test.fuc" |
| 61 | #include "idle.fuc" | 64 | #include "idle.fuc" |
| 62 | #undef INCLUDE_CODE | 65 | #undef INCLUDE_CODE |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h index 82c8e8b88917..4dba00d2dd1a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h | |||
| @@ -89,9 +89,31 @@ uint32_t nvc0_pwr_data[] = { | |||
| 89 | 0x00000000, | 89 | 0x00000000, |
| 90 | 0x00000000, | 90 | 0x00000000, |
| 91 | 0x00000000, | 91 | 0x00000000, |
| 92 | 0x5f433249, | ||
| 93 | 0x00000982, | ||
| 94 | 0x00000825, | ||
| 95 | 0x00000000, | ||
| 96 | 0x00000000, | ||
| 97 | 0x00000000, | ||
| 98 | 0x00000000, | ||
| 99 | 0x00000000, | ||
| 100 | 0x00000000, | ||
| 101 | 0x00000000, | ||
| 102 | 0x00000000, | ||
| 103 | 0x00000000, | ||
| 104 | 0x00000000, | ||
| 105 | 0x00000000, | ||
| 106 | 0x00000000, | ||
| 107 | 0x00000000, | ||
| 108 | 0x00000000, | ||
| 109 | 0x00000000, | ||
| 110 | 0x00000000, | ||
| 111 | 0x00000000, | ||
| 112 | 0x00000000, | ||
| 113 | 0x00000000, | ||
| 92 | 0x54534554, | 114 | 0x54534554, |
| 93 | 0x0000057b, | 115 | 0x000009ab, |
| 94 | 0x00000554, | 116 | 0x00000984, |
| 95 | 0x00000000, | 117 | 0x00000000, |
| 96 | 0x00000000, | 118 | 0x00000000, |
| 97 | 0x00000000, | 119 | 0x00000000, |
| @@ -112,8 +134,8 @@ uint32_t nvc0_pwr_data[] = { | |||
| 112 | 0x00000000, | 134 | 0x00000000, |
| 113 | 0x00000000, | 135 | 0x00000000, |
| 114 | 0x454c4449, | 136 | 0x454c4449, |
| 115 | 0x00000587, | 137 | 0x000009b7, |
| 116 | 0x00000585, | 138 | 0x000009b5, |
| 117 | 0x00000000, | 139 | 0x00000000, |
| 118 | 0x00000000, | 140 | 0x00000000, |
| 119 | 0x00000000, | 141 | 0x00000000, |
| @@ -133,12 +155,12 @@ uint32_t nvc0_pwr_data[] = { | |||
| 133 | 0x00000000, | 155 | 0x00000000, |
| 134 | 0x00000000, | 156 | 0x00000000, |
| 135 | 0x00000000, | 157 | 0x00000000, |
| 136 | /* 0x0210: proc_list_tail */ | 158 | /* 0x0268: proc_list_tail */ |
| 137 | /* 0x0210: time_prev */ | 159 | /* 0x0268: time_prev */ |
| 138 | 0x00000000, | 160 | 0x00000000, |
| 139 | /* 0x0214: time_next */ | 161 | /* 0x026c: time_next */ |
| 140 | 0x00000000, | 162 | 0x00000000, |
| 141 | /* 0x0218: fifo_queue */ | 163 | /* 0x0270: fifo_queue */ |
| 142 | 0x00000000, | 164 | 0x00000000, |
| 143 | 0x00000000, | 165 | 0x00000000, |
| 144 | 0x00000000, | 166 | 0x00000000, |
| @@ -171,7 +193,7 @@ uint32_t nvc0_pwr_data[] = { | |||
| 171 | 0x00000000, | 193 | 0x00000000, |
| 172 | 0x00000000, | 194 | 0x00000000, |
| 173 | 0x00000000, | 195 | 0x00000000, |
| 174 | /* 0x0298: rfifo_queue */ | 196 | /* 0x02f0: rfifo_queue */ |
| 175 | 0x00000000, | 197 | 0x00000000, |
| 176 | 0x00000000, | 198 | 0x00000000, |
| 177 | 0x00000000, | 199 | 0x00000000, |
| @@ -204,11 +226,11 @@ uint32_t nvc0_pwr_data[] = { | |||
| 204 | 0x00000000, | 226 | 0x00000000, |
| 205 | 0x00000000, | 227 | 0x00000000, |
| 206 | 0x00000000, | 228 | 0x00000000, |
| 207 | /* 0x0318: memx_func_head */ | 229 | /* 0x0370: memx_func_head */ |
| 208 | 0x00010000, | 230 | 0x00010000, |
| 209 | 0x00000000, | 231 | 0x00000000, |
| 210 | 0x0000046f, | 232 | 0x0000046f, |
| 211 | /* 0x0324: memx_func_next */ | 233 | /* 0x037c: memx_func_next */ |
| 212 | 0x00000001, | 234 | 0x00000001, |
| 213 | 0x00000000, | 235 | 0x00000000, |
| 214 | 0x00000496, | 236 | 0x00000496, |
| @@ -221,8 +243,18 @@ uint32_t nvc0_pwr_data[] = { | |||
| 221 | 0x00010004, | 243 | 0x00010004, |
| 222 | 0x00000000, | 244 | 0x00000000, |
| 223 | 0x000004fc, | 245 | 0x000004fc, |
| 224 | /* 0x0354: memx_func_tail */ | 246 | /* 0x03ac: memx_func_tail */ |
| 225 | /* 0x0354: memx_data_head */ | 247 | /* 0x03ac: memx_data_head */ |
| 248 | 0x00000000, | ||
| 249 | 0x00000000, | ||
| 250 | 0x00000000, | ||
| 251 | 0x00000000, | ||
| 252 | 0x00000000, | ||
| 253 | 0x00000000, | ||
| 254 | 0x00000000, | ||
| 255 | 0x00000000, | ||
| 256 | 0x00000000, | ||
| 257 | 0x00000000, | ||
| 226 | 0x00000000, | 258 | 0x00000000, |
| 227 | 0x00000000, | 259 | 0x00000000, |
| 228 | 0x00000000, | 260 | 0x00000000, |
| @@ -725,6 +757,42 @@ uint32_t nvc0_pwr_data[] = { | |||
| 725 | 0x00000000, | 757 | 0x00000000, |
| 726 | 0x00000000, | 758 | 0x00000000, |
| 727 | 0x00000000, | 759 | 0x00000000, |
| 760 | /* 0x0bac: memx_data_tail */ | ||
| 761 | /* 0x0bac: i2c_scl_map */ | ||
| 762 | 0x00001000, | ||
| 763 | 0x00004000, | ||
| 764 | 0x00010000, | ||
| 765 | 0x00000100, | ||
| 766 | 0x00040000, | ||
| 767 | 0x00100000, | ||
| 768 | 0x00400000, | ||
| 769 | 0x01000000, | ||
| 770 | 0x04000000, | ||
| 771 | 0x10000000, | ||
| 772 | /* 0x0bd4: i2c_sda_map */ | ||
| 773 | 0x00002000, | ||
| 774 | 0x00008000, | ||
| 775 | 0x00020000, | ||
| 776 | 0x00000200, | ||
| 777 | 0x00080000, | ||
| 778 | 0x00200000, | ||
| 779 | 0x00800000, | ||
| 780 | 0x02000000, | ||
| 781 | 0x08000000, | ||
| 782 | 0x20000000, | ||
| 783 | /* 0x0bfc: i2c_ctrl */ | ||
| 784 | 0x0000e138, | ||
| 785 | 0x0000e150, | ||
| 786 | 0x0000e168, | ||
| 787 | 0x0000e180, | ||
| 788 | 0x0000e254, | ||
| 789 | 0x0000e274, | ||
| 790 | 0x0000e764, | ||
| 791 | 0x0000e780, | ||
| 792 | 0x0000e79c, | ||
| 793 | 0x0000e7b8, | ||
| 794 | 0x00000000, | ||
| 795 | 0x00000000, | ||
| 728 | 0x00000000, | 796 | 0x00000000, |
| 729 | 0x00000000, | 797 | 0x00000000, |
| 730 | 0x00000000, | 798 | 0x00000000, |
| @@ -735,7 +803,6 @@ uint32_t nvc0_pwr_data[] = { | |||
| 735 | 0x00000000, | 803 | 0x00000000, |
| 736 | 0x00000000, | 804 | 0x00000000, |
| 737 | 0x00000000, | 805 | 0x00000000, |
| 738 | /* 0x0b54: memx_data_tail */ | ||
| 739 | 0x00000000, | 806 | 0x00000000, |
| 740 | 0x00000000, | 807 | 0x00000000, |
| 741 | 0x00000000, | 808 | 0x00000000, |
| @@ -787,15 +854,15 @@ uint32_t nvc0_pwr_code[] = { | |||
| 787 | 0x07a007f1, | 854 | 0x07a007f1, |
| 788 | 0xd00604b6, | 855 | 0xd00604b6, |
| 789 | 0x04bd000e, | 856 | 0x04bd000e, |
| 790 | 0xf001e7f0, | 857 | 0xf001d7f0, |
| 791 | 0x07f101e3, | 858 | 0x07f101d3, |
| 792 | 0x04b607ac, | 859 | 0x04b607ac, |
| 793 | 0x000ed006, | 860 | 0x000dd006, |
| 794 | /* 0x0022: rd32_wait */ | 861 | /* 0x0022: rd32_wait */ |
| 795 | 0xe7f104bd, | 862 | 0xd7f104bd, |
| 796 | 0xe4b607ac, | 863 | 0xd4b607ac, |
| 797 | 0x00eecf06, | 864 | 0x00ddcf06, |
| 798 | 0x7000e4f1, | 865 | 0x7000d4f1, |
| 799 | 0xf1f21bf4, | 866 | 0xf1f21bf4, |
| 800 | 0xb607a4d7, | 867 | 0xb607a4d7, |
| 801 | 0xddcf06d4, | 868 | 0xddcf06d4, |
| @@ -807,15 +874,15 @@ uint32_t nvc0_pwr_code[] = { | |||
| 807 | 0xb607a407, | 874 | 0xb607a407, |
| 808 | 0x0dd00604, | 875 | 0x0dd00604, |
| 809 | 0xf004bd00, | 876 | 0xf004bd00, |
| 810 | 0xe5f002e7, | 877 | 0xd5f002d7, |
| 811 | 0x01e3f0f0, | 878 | 0x01d3f0f0, |
| 812 | 0x07ac07f1, | 879 | 0x07ac07f1, |
| 813 | 0xd00604b6, | 880 | 0xd00604b6, |
| 814 | 0x04bd000e, | 881 | 0x04bd000d, |
| 815 | /* 0x006c: wr32_wait */ | 882 | /* 0x006c: wr32_wait */ |
| 816 | 0x07ace7f1, | 883 | 0x07acd7f1, |
| 817 | 0xcf06e4b6, | 884 | 0xcf06d4b6, |
| 818 | 0xe4f100ee, | 885 | 0xd4f100dd, |
| 819 | 0x1bf47000, | 886 | 0x1bf47000, |
| 820 | /* 0x007f: nsec */ | 887 | /* 0x007f: nsec */ |
| 821 | 0xf000f8f2, | 888 | 0xf000f8f2, |
| @@ -845,21 +912,21 @@ uint32_t nvc0_pwr_code[] = { | |||
| 845 | 0x9800f8df, | 912 | 0x9800f8df, |
| 846 | 0x96b003e9, | 913 | 0x96b003e9, |
| 847 | 0x2a0bf400, | 914 | 0x2a0bf400, |
| 848 | 0xbb840a98, | 915 | 0xbb9a0a98, |
| 849 | 0x1cf4029a, | 916 | 0x1cf4029a, |
| 850 | 0x01d7f00f, | 917 | 0x01d7f00f, |
| 851 | 0x025421f5, | 918 | 0x025421f5, |
| 852 | 0x0ef494bd, | 919 | 0x0ef494bd, |
| 853 | /* 0x00e9: intr_watchdog_next_time */ | 920 | /* 0x00e9: intr_watchdog_next_time */ |
| 854 | 0x850a9815, | 921 | 0x9b0a9815, |
| 855 | 0xf400a6b0, | 922 | 0xf400a6b0, |
| 856 | 0x9ab8090b, | 923 | 0x9ab8090b, |
| 857 | 0x061cf406, | 924 | 0x061cf406, |
| 858 | /* 0x00f8: intr_watchdog_next_time_set */ | 925 | /* 0x00f8: intr_watchdog_next_time_set */ |
| 859 | /* 0x00fb: intr_watchdog_next_proc */ | 926 | /* 0x00fb: intr_watchdog_next_proc */ |
| 860 | 0x80850980, | 927 | 0x809b0980, |
| 861 | 0xe0b603e9, | 928 | 0xe0b603e9, |
| 862 | 0x10e6b158, | 929 | 0x68e6b158, |
| 863 | 0xc61bf402, | 930 | 0xc61bf402, |
| 864 | /* 0x010a: intr */ | 931 | /* 0x010a: intr */ |
| 865 | 0x00f900f8, | 932 | 0x00f900f8, |
| @@ -880,15 +947,15 @@ uint32_t nvc0_pwr_code[] = { | |||
| 880 | 0x0088cf06, | 947 | 0x0088cf06, |
| 881 | 0xf40289c4, | 948 | 0xf40289c4, |
| 882 | 0x0080230b, | 949 | 0x0080230b, |
| 883 | 0x58e7f085, | 950 | 0x58e7f09b, |
| 884 | 0x98cb21f4, | 951 | 0x98cb21f4, |
| 885 | 0x96b08509, | 952 | 0x96b09b09, |
| 886 | 0x110bf400, | 953 | 0x110bf400, |
| 887 | 0xb63407f0, | 954 | 0xb63407f0, |
| 888 | 0x09d00604, | 955 | 0x09d00604, |
| 889 | 0x8004bd00, | 956 | 0x8004bd00, |
| 890 | /* 0x016e: intr_skip_watchdog */ | 957 | /* 0x016e: intr_skip_watchdog */ |
| 891 | 0x89e48409, | 958 | 0x89e49a09, |
| 892 | 0x0bf40800, | 959 | 0x0bf40800, |
| 893 | 0x8897f148, | 960 | 0x8897f148, |
| 894 | 0x0694b606, | 961 | 0x0694b606, |
| @@ -948,7 +1015,7 @@ uint32_t nvc0_pwr_code[] = { | |||
| 948 | 0x000ed006, | 1015 | 0x000ed006, |
| 949 | 0x0e8004bd, | 1016 | 0x0e8004bd, |
| 950 | /* 0x0241: timer_enable */ | 1017 | /* 0x0241: timer_enable */ |
| 951 | 0x0187f084, | 1018 | 0x0187f09a, |
| 952 | 0xb63807f0, | 1019 | 0xb63807f0, |
| 953 | 0x08d00604, | 1020 | 0x08d00604, |
| 954 | /* 0x024f: timer_done */ | 1021 | /* 0x024f: timer_done */ |
| @@ -979,7 +1046,7 @@ uint32_t nvc0_pwr_code[] = { | |||
| 979 | 0xb8008a98, | 1046 | 0xb8008a98, |
| 980 | 0x0bf406ae, | 1047 | 0x0bf406ae, |
| 981 | 0x5880b610, | 1048 | 0x5880b610, |
| 982 | 0x021086b1, | 1049 | 0x026886b1, |
| 983 | 0xf4f01bf4, | 1050 | 0xf4f01bf4, |
| 984 | /* 0x02b2: find_done */ | 1051 | /* 0x02b2: find_done */ |
| 985 | 0x8eb90132, | 1052 | 0x8eb90132, |
| @@ -1049,7 +1116,7 @@ uint32_t nvc0_pwr_code[] = { | |||
| 1049 | 0x320bf406, | 1116 | 0x320bf406, |
| 1050 | 0x94071ec4, | 1117 | 0x94071ec4, |
| 1051 | 0xe0b704ee, | 1118 | 0xe0b704ee, |
| 1052 | 0xeb980218, | 1119 | 0xeb980270, |
| 1053 | 0x02ec9803, | 1120 | 0x02ec9803, |
| 1054 | 0x9801ed98, | 1121 | 0x9801ed98, |
| 1055 | 0x21f500ee, | 1122 | 0x21f500ee, |
| @@ -1075,7 +1142,7 @@ uint32_t nvc0_pwr_code[] = { | |||
| 1075 | 0xe60bf406, | 1142 | 0xe60bf406, |
| 1076 | 0xb60723c4, | 1143 | 0xb60723c4, |
| 1077 | 0x30b70434, | 1144 | 0x30b70434, |
| 1078 | 0x3b800298, | 1145 | 0x3b8002f0, |
| 1079 | 0x023c8003, | 1146 | 0x023c8003, |
| 1080 | 0x80013d80, | 1147 | 0x80013d80, |
| 1081 | 0x20b6003e, | 1148 | 0x20b6003e, |
| @@ -1090,13 +1157,13 @@ uint32_t nvc0_pwr_code[] = { | |||
| 1090 | /* 0x0430: host_init */ | 1157 | /* 0x0430: host_init */ |
| 1091 | 0x008017f1, | 1158 | 0x008017f1, |
| 1092 | 0xf11014b6, | 1159 | 0xf11014b6, |
| 1093 | 0xf1021815, | 1160 | 0xf1027015, |
| 1094 | 0xb604d007, | 1161 | 0xb604d007, |
| 1095 | 0x01d00604, | 1162 | 0x01d00604, |
| 1096 | 0xf104bd00, | 1163 | 0xf104bd00, |
| 1097 | 0xb6008017, | 1164 | 0xb6008017, |
| 1098 | 0x15f11014, | 1165 | 0x15f11014, |
| 1099 | 0x07f10298, | 1166 | 0x07f102f0, |
| 1100 | 0x04b604dc, | 1167 | 0x04b604dc, |
| 1101 | 0x0001d006, | 1168 | 0x0001d006, |
| 1102 | 0x17f004bd, | 1169 | 0x17f004bd, |
| @@ -1156,14 +1223,14 @@ uint32_t nvc0_pwr_code[] = { | |||
| 1156 | 0x00139802, | 1223 | 0x00139802, |
| 1157 | 0x950410b6, | 1224 | 0x950410b6, |
| 1158 | 0x30f01034, | 1225 | 0x30f01034, |
| 1159 | 0xc835980c, | 1226 | 0xde35980c, |
| 1160 | 0x12b855f9, | 1227 | 0x12b855f9, |
| 1161 | 0xec1ef406, | 1228 | 0xec1ef406, |
| 1162 | 0xe0fcd0fc, | 1229 | 0xe0fcd0fc, |
| 1163 | 0x02b921f5, | 1230 | 0x02b921f5, |
| 1164 | /* 0x0532: memx_info */ | 1231 | /* 0x0532: memx_info */ |
| 1165 | 0xc7f100f8, | 1232 | 0xc7f100f8, |
| 1166 | 0xb7f10354, | 1233 | 0xb7f103ac, |
| 1167 | 0x21f50800, | 1234 | 0x21f50800, |
| 1168 | 0x00f802b9, | 1235 | 0x00f802b9, |
| 1169 | /* 0x0540: memx_recv */ | 1236 | /* 0x0540: memx_recv */ |
| @@ -1175,7 +1242,312 @@ uint32_t nvc0_pwr_code[] = { | |||
| 1175 | /* 0x0550: perf_recv */ | 1242 | /* 0x0550: perf_recv */ |
| 1176 | /* 0x0552: perf_init */ | 1243 | /* 0x0552: perf_init */ |
| 1177 | 0x00f800f8, | 1244 | 0x00f800f8, |
| 1178 | /* 0x0554: test_recv */ | 1245 | /* 0x0554: i2c_drive_scl */ |
| 1246 | 0xf40036b0, | ||
| 1247 | 0x07f1110b, | ||
| 1248 | 0x04b607e0, | ||
| 1249 | 0x0001d006, | ||
| 1250 | 0x00f804bd, | ||
| 1251 | /* 0x0568: i2c_drive_scl_lo */ | ||
| 1252 | 0x07e407f1, | ||
| 1253 | 0xd00604b6, | ||
| 1254 | 0x04bd0001, | ||
| 1255 | /* 0x0576: i2c_drive_sda */ | ||
| 1256 | 0x36b000f8, | ||
| 1257 | 0x110bf400, | ||
| 1258 | 0x07e007f1, | ||
| 1259 | 0xd00604b6, | ||
| 1260 | 0x04bd0002, | ||
| 1261 | /* 0x058a: i2c_drive_sda_lo */ | ||
| 1262 | 0x07f100f8, | ||
| 1263 | 0x04b607e4, | ||
| 1264 | 0x0002d006, | ||
| 1265 | 0x00f804bd, | ||
| 1266 | /* 0x0598: i2c_sense_scl */ | ||
| 1267 | 0xf10132f4, | ||
| 1268 | 0xb607c437, | ||
| 1269 | 0x33cf0634, | ||
| 1270 | 0x0431fd00, | ||
| 1271 | 0xf4060bf4, | ||
| 1272 | /* 0x05ae: i2c_sense_scl_done */ | ||
| 1273 | 0x00f80131, | ||
| 1274 | /* 0x05b0: i2c_sense_sda */ | ||
| 1275 | 0xf10132f4, | ||
| 1276 | 0xb607c437, | ||
| 1277 | 0x33cf0634, | ||
| 1278 | 0x0432fd00, | ||
| 1279 | 0xf4060bf4, | ||
| 1280 | /* 0x05c6: i2c_sense_sda_done */ | ||
| 1281 | 0x00f80131, | ||
| 1282 | /* 0x05c8: i2c_raise_scl */ | ||
| 1283 | 0x47f140f9, | ||
| 1284 | 0x37f00898, | ||
| 1285 | 0x5421f501, | ||
| 1286 | /* 0x05d5: i2c_raise_scl_wait */ | ||
| 1287 | 0xe8e7f105, | ||
| 1288 | 0x7f21f403, | ||
| 1289 | 0x059821f5, | ||
| 1290 | 0xb60901f4, | ||
| 1291 | 0x1bf40142, | ||
| 1292 | /* 0x05e9: i2c_raise_scl_done */ | ||
| 1293 | 0xf840fcef, | ||
| 1294 | /* 0x05ed: i2c_start */ | ||
| 1295 | 0x9821f500, | ||
| 1296 | 0x0d11f405, | ||
| 1297 | 0x05b021f5, | ||
| 1298 | 0xf40611f4, | ||
| 1299 | /* 0x05fe: i2c_start_rep */ | ||
| 1300 | 0x37f0300e, | ||
| 1301 | 0x5421f500, | ||
| 1302 | 0x0137f005, | ||
| 1303 | 0x057621f5, | ||
| 1304 | 0xb60076bb, | ||
| 1305 | 0x50f90465, | ||
| 1306 | 0xbb046594, | ||
| 1307 | 0x50bd0256, | ||
| 1308 | 0xfc0475fd, | ||
| 1309 | 0xc821f550, | ||
| 1310 | 0x0464b605, | ||
| 1311 | /* 0x062b: i2c_start_send */ | ||
| 1312 | 0xf01f11f4, | ||
| 1313 | 0x21f50037, | ||
| 1314 | 0xe7f10576, | ||
| 1315 | 0x21f41388, | ||
| 1316 | 0x0037f07f, | ||
| 1317 | 0x055421f5, | ||
| 1318 | 0x1388e7f1, | ||
| 1319 | /* 0x0647: i2c_start_out */ | ||
| 1320 | 0xf87f21f4, | ||
| 1321 | /* 0x0649: i2c_stop */ | ||
| 1322 | 0x0037f000, | ||
| 1323 | 0x055421f5, | ||
| 1324 | 0xf50037f0, | ||
| 1325 | 0xf1057621, | ||
| 1326 | 0xf403e8e7, | ||
| 1327 | 0x37f07f21, | ||
| 1328 | 0x5421f501, | ||
| 1329 | 0x88e7f105, | ||
| 1330 | 0x7f21f413, | ||
| 1331 | 0xf50137f0, | ||
| 1332 | 0xf1057621, | ||
| 1333 | 0xf41388e7, | ||
| 1334 | 0x00f87f21, | ||
| 1335 | /* 0x067c: i2c_bitw */ | ||
| 1336 | 0x057621f5, | ||
| 1337 | 0x03e8e7f1, | ||
| 1338 | 0xbb7f21f4, | ||
| 1339 | 0x65b60076, | ||
| 1340 | 0x9450f904, | ||
| 1341 | 0x56bb0465, | ||
| 1342 | 0xfd50bd02, | ||
| 1343 | 0x50fc0475, | ||
| 1344 | 0x05c821f5, | ||
| 1345 | 0xf40464b6, | ||
| 1346 | 0xe7f11811, | ||
| 1347 | 0x21f41388, | ||
| 1348 | 0x0037f07f, | ||
| 1349 | 0x055421f5, | ||
| 1350 | 0x1388e7f1, | ||
| 1351 | /* 0x06bb: i2c_bitw_out */ | ||
| 1352 | 0xf87f21f4, | ||
| 1353 | /* 0x06bd: i2c_bitr */ | ||
| 1354 | 0x0137f000, | ||
| 1355 | 0x057621f5, | ||
| 1356 | 0x03e8e7f1, | ||
| 1357 | 0xbb7f21f4, | ||
| 1358 | 0x65b60076, | ||
| 1359 | 0x9450f904, | ||
| 1360 | 0x56bb0465, | ||
| 1361 | 0xfd50bd02, | ||
| 1362 | 0x50fc0475, | ||
| 1363 | 0x05c821f5, | ||
| 1364 | 0xf40464b6, | ||
| 1365 | 0x21f51b11, | ||
| 1366 | 0x37f005b0, | ||
| 1367 | 0x5421f500, | ||
| 1368 | 0x88e7f105, | ||
| 1369 | 0x7f21f413, | ||
| 1370 | 0xf4013cf0, | ||
| 1371 | /* 0x0702: i2c_bitr_done */ | ||
| 1372 | 0x00f80131, | ||
| 1373 | /* 0x0704: i2c_get_byte */ | ||
| 1374 | 0xf00057f0, | ||
| 1375 | /* 0x070a: i2c_get_byte_next */ | ||
| 1376 | 0x54b60847, | ||
| 1377 | 0x0076bb01, | ||
| 1378 | 0xf90465b6, | ||
| 1379 | 0x04659450, | ||
| 1380 | 0xbd0256bb, | ||
| 1381 | 0x0475fd50, | ||
| 1382 | 0x21f550fc, | ||
| 1383 | 0x64b606bd, | ||
| 1384 | 0x2b11f404, | ||
| 1385 | 0xb60553fd, | ||
| 1386 | 0x1bf40142, | ||
| 1387 | 0x0137f0d8, | ||
| 1388 | 0xb60076bb, | ||
| 1389 | 0x50f90465, | ||
| 1390 | 0xbb046594, | ||
| 1391 | 0x50bd0256, | ||
| 1392 | 0xfc0475fd, | ||
| 1393 | 0x7c21f550, | ||
| 1394 | 0x0464b606, | ||
| 1395 | /* 0x0754: i2c_get_byte_done */ | ||
| 1396 | /* 0x0756: i2c_put_byte */ | ||
| 1397 | 0x47f000f8, | ||
| 1398 | /* 0x0759: i2c_put_byte_next */ | ||
| 1399 | 0x0142b608, | ||
| 1400 | 0xbb3854ff, | ||
| 1401 | 0x65b60076, | ||
| 1402 | 0x9450f904, | ||
| 1403 | 0x56bb0465, | ||
| 1404 | 0xfd50bd02, | ||
| 1405 | 0x50fc0475, | ||
| 1406 | 0x067c21f5, | ||
| 1407 | 0xf40464b6, | ||
| 1408 | 0x46b03411, | ||
| 1409 | 0xd81bf400, | ||
| 1410 | 0xb60076bb, | ||
| 1411 | 0x50f90465, | ||
| 1412 | 0xbb046594, | ||
| 1413 | 0x50bd0256, | ||
| 1414 | 0xfc0475fd, | ||
| 1415 | 0xbd21f550, | ||
| 1416 | 0x0464b606, | ||
| 1417 | 0xbb0f11f4, | ||
| 1418 | 0x36b00076, | ||
| 1419 | 0x061bf401, | ||
| 1420 | /* 0x07af: i2c_put_byte_done */ | ||
| 1421 | 0xf80132f4, | ||
| 1422 | /* 0x07b1: i2c_addr */ | ||
| 1423 | 0x0076bb00, | ||
| 1424 | 0xf90465b6, | ||
| 1425 | 0x04659450, | ||
| 1426 | 0xbd0256bb, | ||
| 1427 | 0x0475fd50, | ||
| 1428 | 0x21f550fc, | ||
| 1429 | 0x64b605ed, | ||
| 1430 | 0x2911f404, | ||
| 1431 | 0x012ec3e7, | ||
| 1432 | 0xfd0134b6, | ||
| 1433 | 0x76bb0553, | ||
| 1434 | 0x0465b600, | ||
| 1435 | 0x659450f9, | ||
| 1436 | 0x0256bb04, | ||
| 1437 | 0x75fd50bd, | ||
| 1438 | 0xf550fc04, | ||
| 1439 | 0xb6075621, | ||
| 1440 | /* 0x07f6: i2c_addr_done */ | ||
| 1441 | 0x00f80464, | ||
| 1442 | /* 0x07f8: i2c_acquire_addr */ | ||
| 1443 | 0xb6f8cec7, | ||
| 1444 | 0xe0b702e4, | ||
| 1445 | 0xee980bfc, | ||
| 1446 | /* 0x0807: i2c_acquire */ | ||
| 1447 | 0xf500f800, | ||
| 1448 | 0xf407f821, | ||
| 1449 | 0xd9f00421, | ||
| 1450 | 0x3f21f403, | ||
| 1451 | /* 0x0816: i2c_release */ | ||
| 1452 | 0x21f500f8, | ||
| 1453 | 0x21f407f8, | ||
| 1454 | 0x03daf004, | ||
| 1455 | 0xf83f21f4, | ||
| 1456 | /* 0x0825: i2c_recv */ | ||
| 1457 | 0x0132f400, | ||
| 1458 | 0xb6f8c1c7, | ||
| 1459 | 0x16b00214, | ||
| 1460 | 0x3a1ff528, | ||
| 1461 | 0xd413a001, | ||
| 1462 | 0x0032980b, | ||
| 1463 | 0x0bac13a0, | ||
| 1464 | 0xf4003198, | ||
| 1465 | 0xd0f90231, | ||
| 1466 | 0xd0f9e0f9, | ||
| 1467 | 0x000067f1, | ||
| 1468 | 0x100063f1, | ||
| 1469 | 0xbb016792, | ||
| 1470 | 0x65b60076, | ||
| 1471 | 0x9450f904, | ||
| 1472 | 0x56bb0465, | ||
| 1473 | 0xfd50bd02, | ||
| 1474 | 0x50fc0475, | ||
| 1475 | 0x080721f5, | ||
| 1476 | 0xfc0464b6, | ||
| 1477 | 0x00d6b0d0, | ||
| 1478 | 0x00b31bf5, | ||
| 1479 | 0xbb0057f0, | ||
| 1480 | 0x65b60076, | ||
| 1481 | 0x9450f904, | ||
| 1482 | 0x56bb0465, | ||
| 1483 | 0xfd50bd02, | ||
| 1484 | 0x50fc0475, | ||
| 1485 | 0x07b121f5, | ||
| 1486 | 0xf50464b6, | ||
| 1487 | 0xc700d011, | ||
| 1488 | 0x76bbe0c5, | ||
| 1489 | 0x0465b600, | ||
| 1490 | 0x659450f9, | ||
| 1491 | 0x0256bb04, | ||
| 1492 | 0x75fd50bd, | ||
| 1493 | 0xf550fc04, | ||
| 1494 | 0xb6075621, | ||
| 1495 | 0x11f50464, | ||
| 1496 | 0x57f000ad, | ||
| 1497 | 0x0076bb01, | ||
| 1498 | 0xf90465b6, | ||
| 1499 | 0x04659450, | ||
| 1500 | 0xbd0256bb, | ||
| 1501 | 0x0475fd50, | ||
| 1502 | 0x21f550fc, | ||
| 1503 | 0x64b607b1, | ||
| 1504 | 0x8a11f504, | ||
| 1505 | 0x0076bb00, | ||
| 1506 | 0xf90465b6, | ||
| 1507 | 0x04659450, | ||
| 1508 | 0xbd0256bb, | ||
| 1509 | 0x0475fd50, | ||
| 1510 | 0x21f550fc, | ||
| 1511 | 0x64b60704, | ||
| 1512 | 0x6a11f404, | ||
| 1513 | 0xbbe05bcb, | ||
| 1514 | 0x65b60076, | ||
| 1515 | 0x9450f904, | ||
| 1516 | 0x56bb0465, | ||
| 1517 | 0xfd50bd02, | ||
| 1518 | 0x50fc0475, | ||
| 1519 | 0x064921f5, | ||
| 1520 | 0xb90464b6, | ||
| 1521 | 0x74bd025b, | ||
| 1522 | /* 0x092b: i2c_recv_not_rd08 */ | ||
| 1523 | 0xb0430ef4, | ||
| 1524 | 0x1bf401d6, | ||
| 1525 | 0x0057f03d, | ||
| 1526 | 0x07b121f5, | ||
| 1527 | 0xc73311f4, | ||
| 1528 | 0x21f5e0c5, | ||
| 1529 | 0x11f40756, | ||
| 1530 | 0x0057f029, | ||
| 1531 | 0x07b121f5, | ||
| 1532 | 0xc71f11f4, | ||
| 1533 | 0x21f5e0b5, | ||
| 1534 | 0x11f40756, | ||
| 1535 | 0x4921f515, | ||
| 1536 | 0xc774bd06, | ||
| 1537 | 0x1bf408c5, | ||
| 1538 | 0x0232f409, | ||
| 1539 | /* 0x096b: i2c_recv_not_wr08 */ | ||
| 1540 | /* 0x096b: i2c_recv_done */ | ||
| 1541 | 0xc7030ef4, | ||
| 1542 | 0x21f5f8ce, | ||
| 1543 | 0xe0fc0816, | ||
| 1544 | 0x12f4d0fc, | ||
| 1545 | 0x027cb90a, | ||
| 1546 | 0x02b921f5, | ||
| 1547 | /* 0x0980: i2c_recv_exit */ | ||
| 1548 | /* 0x0982: i2c_init */ | ||
| 1549 | 0x00f800f8, | ||
| 1550 | /* 0x0984: test_recv */ | ||
| 1179 | 0x05d817f1, | 1551 | 0x05d817f1, |
| 1180 | 0xcf0614b6, | 1552 | 0xcf0614b6, |
| 1181 | 0x10b60011, | 1553 | 0x10b60011, |
| @@ -1185,12 +1557,12 @@ uint32_t nvc0_pwr_code[] = { | |||
| 1185 | 0x00e7f104, | 1557 | 0x00e7f104, |
| 1186 | 0x4fe3f1d9, | 1558 | 0x4fe3f1d9, |
| 1187 | 0xf521f513, | 1559 | 0xf521f513, |
| 1188 | /* 0x057b: test_init */ | 1560 | /* 0x09ab: test_init */ |
| 1189 | 0xf100f801, | 1561 | 0xf100f801, |
| 1190 | 0xf50800e7, | 1562 | 0xf50800e7, |
| 1191 | 0xf801f521, | 1563 | 0xf801f521, |
| 1192 | /* 0x0585: idle_recv */ | 1564 | /* 0x09b5: idle_recv */ |
| 1193 | /* 0x0587: idle */ | 1565 | /* 0x09b7: idle */ |
| 1194 | 0xf400f800, | 1566 | 0xf400f800, |
| 1195 | 0x17f10031, | 1567 | 0x17f10031, |
| 1196 | 0x14b605d4, | 1568 | 0x14b605d4, |
| @@ -1198,32 +1570,20 @@ uint32_t nvc0_pwr_code[] = { | |||
| 1198 | 0xf10110b6, | 1570 | 0xf10110b6, |
| 1199 | 0xb605d407, | 1571 | 0xb605d407, |
| 1200 | 0x01d00604, | 1572 | 0x01d00604, |
| 1201 | /* 0x05a3: idle_loop */ | 1573 | /* 0x09d3: idle_loop */ |
| 1202 | 0xf004bd00, | 1574 | 0xf004bd00, |
| 1203 | 0x32f45817, | 1575 | 0x32f45817, |
| 1204 | /* 0x05a9: idle_proc */ | 1576 | /* 0x09d9: idle_proc */ |
| 1205 | /* 0x05a9: idle_proc_exec */ | 1577 | /* 0x09d9: idle_proc_exec */ |
| 1206 | 0xb910f902, | 1578 | 0xb910f902, |
| 1207 | 0x21f5021e, | 1579 | 0x21f5021e, |
| 1208 | 0x10fc02c2, | 1580 | 0x10fc02c2, |
| 1209 | 0xf40911f4, | 1581 | 0xf40911f4, |
| 1210 | 0x0ef40231, | 1582 | 0x0ef40231, |
| 1211 | /* 0x05bd: idle_proc_next */ | 1583 | /* 0x09ed: idle_proc_next */ |
| 1212 | 0x5810b6ef, | 1584 | 0x5810b6ef, |
| 1213 | 0xf4061fb8, | 1585 | 0xf4061fb8, |
| 1214 | 0x02f4e61b, | 1586 | 0x02f4e61b, |
| 1215 | 0x0028f4dd, | 1587 | 0x0028f4dd, |
| 1216 | 0x00bb0ef4, | 1588 | 0x00bb0ef4, |
| 1217 | 0x00000000, | ||
| 1218 | 0x00000000, | ||
| 1219 | 0x00000000, | ||
| 1220 | 0x00000000, | ||
| 1221 | 0x00000000, | ||
| 1222 | 0x00000000, | ||
| 1223 | 0x00000000, | ||
| 1224 | 0x00000000, | ||
| 1225 | 0x00000000, | ||
| 1226 | 0x00000000, | ||
| 1227 | 0x00000000, | ||
| 1228 | 0x00000000, | ||
| 1229 | }; | 1589 | }; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc index 32d65ea254dd..8a89dfe41ce1 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | #include "host.fuc" | 37 | #include "host.fuc" |
| 38 | #include "memx.fuc" | 38 | #include "memx.fuc" |
| 39 | #include "perf.fuc" | 39 | #include "perf.fuc" |
| 40 | #include "i2c_.fuc" | ||
| 40 | #include "test.fuc" | 41 | #include "test.fuc" |
| 41 | #include "idle.fuc" | 42 | #include "idle.fuc" |
| 42 | #undef INCLUDE_PROC | 43 | #undef INCLUDE_PROC |
| @@ -46,6 +47,7 @@ | |||
| 46 | #include "host.fuc" | 47 | #include "host.fuc" |
| 47 | #include "memx.fuc" | 48 | #include "memx.fuc" |
| 48 | #include "perf.fuc" | 49 | #include "perf.fuc" |
| 50 | #include "i2c_.fuc" | ||
| 49 | #include "test.fuc" | 51 | #include "test.fuc" |
| 50 | #include "idle.fuc" | 52 | #include "idle.fuc" |
| 51 | #undef INCLUDE_DATA | 53 | #undef INCLUDE_DATA |
| @@ -57,6 +59,7 @@ | |||
| 57 | #include "host.fuc" | 59 | #include "host.fuc" |
| 58 | #include "memx.fuc" | 60 | #include "memx.fuc" |
| 59 | #include "perf.fuc" | 61 | #include "perf.fuc" |
| 62 | #include "i2c_.fuc" | ||
| 60 | #include "test.fuc" | 63 | #include "test.fuc" |
| 61 | #include "idle.fuc" | 64 | #include "idle.fuc" |
| 62 | #undef INCLUDE_CODE | 65 | #undef INCLUDE_CODE |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h index ce65e2a4b789..5e24c6bc041d 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h | |||
| @@ -89,33 +89,13 @@ uint32_t nvd0_pwr_data[] = { | |||
| 89 | 0x00000000, | 89 | 0x00000000, |
| 90 | 0x00000000, | 90 | 0x00000000, |
| 91 | 0x00000000, | 91 | 0x00000000, |
| 92 | 0x54534554, | 92 | 0x5f433249, |
| 93 | 0x000004eb, | 93 | 0x000008e3, |
| 94 | 0x000004ca, | 94 | 0x00000786, |
| 95 | 0x00000000, | ||
| 96 | 0x00000000, | ||
| 97 | 0x00000000, | ||
| 98 | 0x00000000, | ||
| 99 | 0x00000000, | ||
| 100 | 0x00000000, | ||
| 101 | 0x00000000, | ||
| 102 | 0x00000000, | ||
| 103 | 0x00000000, | ||
| 104 | 0x00000000, | ||
| 105 | 0x00000000, | ||
| 106 | 0x00000000, | ||
| 107 | 0x00000000, | ||
| 108 | 0x00000000, | ||
| 109 | 0x00000000, | ||
| 110 | 0x00000000, | 95 | 0x00000000, |
| 111 | 0x00000000, | 96 | 0x00000000, |
| 112 | 0x00000000, | 97 | 0x00000000, |
| 113 | 0x00000000, | 98 | 0x00000000, |
| 114 | 0x454c4449, | ||
| 115 | 0x000004f7, | ||
| 116 | 0x000004f5, | ||
| 117 | 0x00000000, | ||
| 118 | 0x00000000, | ||
| 119 | 0x00000000, | 99 | 0x00000000, |
| 120 | 0x00000000, | 100 | 0x00000000, |
| 121 | 0x00000000, | 101 | 0x00000000, |
| @@ -131,14 +111,13 @@ uint32_t nvd0_pwr_data[] = { | |||
| 131 | 0x00000000, | 111 | 0x00000000, |
| 132 | 0x00000000, | 112 | 0x00000000, |
| 133 | 0x00000000, | 113 | 0x00000000, |
| 114 | 0x54534554, | ||
| 115 | 0x00000906, | ||
| 116 | 0x000008e5, | ||
| 134 | 0x00000000, | 117 | 0x00000000, |
| 135 | 0x00000000, | 118 | 0x00000000, |
| 136 | /* 0x0210: proc_list_tail */ | ||
| 137 | /* 0x0210: time_prev */ | ||
| 138 | 0x00000000, | 119 | 0x00000000, |
| 139 | /* 0x0214: time_next */ | ||
| 140 | 0x00000000, | 120 | 0x00000000, |
| 141 | /* 0x0218: fifo_queue */ | ||
| 142 | 0x00000000, | 121 | 0x00000000, |
| 143 | 0x00000000, | 122 | 0x00000000, |
| 144 | 0x00000000, | 123 | 0x00000000, |
| @@ -154,6 +133,9 @@ uint32_t nvd0_pwr_data[] = { | |||
| 154 | 0x00000000, | 133 | 0x00000000, |
| 155 | 0x00000000, | 134 | 0x00000000, |
| 156 | 0x00000000, | 135 | 0x00000000, |
| 136 | 0x454c4449, | ||
| 137 | 0x00000912, | ||
| 138 | 0x00000910, | ||
| 157 | 0x00000000, | 139 | 0x00000000, |
| 158 | 0x00000000, | 140 | 0x00000000, |
| 159 | 0x00000000, | 141 | 0x00000000, |
| @@ -171,11 +153,14 @@ uint32_t nvd0_pwr_data[] = { | |||
| 171 | 0x00000000, | 153 | 0x00000000, |
| 172 | 0x00000000, | 154 | 0x00000000, |
| 173 | 0x00000000, | 155 | 0x00000000, |
| 174 | /* 0x0298: rfifo_queue */ | ||
| 175 | 0x00000000, | 156 | 0x00000000, |
| 176 | 0x00000000, | 157 | 0x00000000, |
| 158 | /* 0x0268: proc_list_tail */ | ||
| 159 | /* 0x0268: time_prev */ | ||
| 177 | 0x00000000, | 160 | 0x00000000, |
| 161 | /* 0x026c: time_next */ | ||
| 178 | 0x00000000, | 162 | 0x00000000, |
| 163 | /* 0x0270: fifo_queue */ | ||
| 179 | 0x00000000, | 164 | 0x00000000, |
| 180 | 0x00000000, | 165 | 0x00000000, |
| 181 | 0x00000000, | 166 | 0x00000000, |
| @@ -204,31 +189,11 @@ uint32_t nvd0_pwr_data[] = { | |||
| 204 | 0x00000000, | 189 | 0x00000000, |
| 205 | 0x00000000, | 190 | 0x00000000, |
| 206 | 0x00000000, | 191 | 0x00000000, |
| 207 | /* 0x0318: memx_func_head */ | ||
| 208 | 0x00010000, | ||
| 209 | 0x00000000, | ||
| 210 | 0x000003f4, | ||
| 211 | /* 0x0324: memx_func_next */ | ||
| 212 | 0x00000001, | ||
| 213 | 0x00000000, | ||
| 214 | 0x00000415, | ||
| 215 | 0x00000002, | ||
| 216 | 0x00000002, | ||
| 217 | 0x00000430, | ||
| 218 | 0x00040003, | ||
| 219 | 0x00000000, | ||
| 220 | 0x00000458, | ||
| 221 | 0x00010004, | ||
| 222 | 0x00000000, | ||
| 223 | 0x00000472, | ||
| 224 | /* 0x0354: memx_func_tail */ | ||
| 225 | /* 0x0354: memx_data_head */ | ||
| 226 | 0x00000000, | ||
| 227 | 0x00000000, | ||
| 228 | 0x00000000, | 192 | 0x00000000, |
| 229 | 0x00000000, | 193 | 0x00000000, |
| 230 | 0x00000000, | 194 | 0x00000000, |
| 231 | 0x00000000, | 195 | 0x00000000, |
| 196 | /* 0x02f0: rfifo_queue */ | ||
| 232 | 0x00000000, | 197 | 0x00000000, |
| 233 | 0x00000000, | 198 | 0x00000000, |
| 234 | 0x00000000, | 199 | 0x00000000, |
| @@ -261,10 +226,25 @@ uint32_t nvd0_pwr_data[] = { | |||
| 261 | 0x00000000, | 226 | 0x00000000, |
| 262 | 0x00000000, | 227 | 0x00000000, |
| 263 | 0x00000000, | 228 | 0x00000000, |
| 229 | /* 0x0370: memx_func_head */ | ||
| 230 | 0x00010000, | ||
| 264 | 0x00000000, | 231 | 0x00000000, |
| 232 | 0x000003f4, | ||
| 233 | /* 0x037c: memx_func_next */ | ||
| 234 | 0x00000001, | ||
| 265 | 0x00000000, | 235 | 0x00000000, |
| 236 | 0x00000415, | ||
| 237 | 0x00000002, | ||
| 238 | 0x00000002, | ||
| 239 | 0x00000430, | ||
| 240 | 0x00040003, | ||
| 266 | 0x00000000, | 241 | 0x00000000, |
| 242 | 0x00000458, | ||
| 243 | 0x00010004, | ||
| 267 | 0x00000000, | 244 | 0x00000000, |
| 245 | 0x00000472, | ||
| 246 | /* 0x03ac: memx_func_tail */ | ||
| 247 | /* 0x03ac: memx_data_head */ | ||
| 268 | 0x00000000, | 248 | 0x00000000, |
| 269 | 0x00000000, | 249 | 0x00000000, |
| 270 | 0x00000000, | 250 | 0x00000000, |
| @@ -735,7 +715,6 @@ uint32_t nvd0_pwr_data[] = { | |||
| 735 | 0x00000000, | 715 | 0x00000000, |
| 736 | 0x00000000, | 716 | 0x00000000, |
| 737 | 0x00000000, | 717 | 0x00000000, |
| 738 | /* 0x0b54: memx_data_tail */ | ||
| 739 | 0x00000000, | 718 | 0x00000000, |
| 740 | 0x00000000, | 719 | 0x00000000, |
| 741 | 0x00000000, | 720 | 0x00000000, |
| @@ -778,6 +757,29 @@ uint32_t nvd0_pwr_data[] = { | |||
| 778 | 0x00000000, | 757 | 0x00000000, |
| 779 | 0x00000000, | 758 | 0x00000000, |
| 780 | 0x00000000, | 759 | 0x00000000, |
| 760 | /* 0x0bac: memx_data_tail */ | ||
| 761 | /* 0x0bac: i2c_scl_map */ | ||
| 762 | 0x00000400, | ||
| 763 | 0x00000800, | ||
| 764 | 0x00001000, | ||
| 765 | 0x00002000, | ||
| 766 | 0x00004000, | ||
| 767 | 0x00008000, | ||
| 768 | 0x00010000, | ||
| 769 | 0x00020000, | ||
| 770 | 0x00040000, | ||
| 771 | 0x00080000, | ||
| 772 | /* 0x0bd4: i2c_sda_map */ | ||
| 773 | 0x00100000, | ||
| 774 | 0x00200000, | ||
| 775 | 0x00400000, | ||
| 776 | 0x00800000, | ||
| 777 | 0x01000000, | ||
| 778 | 0x02000000, | ||
| 779 | 0x04000000, | ||
| 780 | 0x08000000, | ||
| 781 | 0x10000000, | ||
| 782 | 0x20000000, | ||
| 781 | 0x00000000, | 783 | 0x00000000, |
| 782 | }; | 784 | }; |
| 783 | 785 | ||
| @@ -786,14 +788,14 @@ uint32_t nvd0_pwr_code[] = { | |||
| 786 | /* 0x0004: rd32 */ | 788 | /* 0x0004: rd32 */ |
| 787 | 0x07a007f1, | 789 | 0x07a007f1, |
| 788 | 0xbd000ed0, | 790 | 0xbd000ed0, |
| 789 | 0x01e7f004, | 791 | 0x01d7f004, |
| 790 | 0xf101e3f0, | 792 | 0xf101d3f0, |
| 791 | 0xd007ac07, | 793 | 0xd007ac07, |
| 792 | 0x04bd000e, | 794 | 0x04bd000d, |
| 793 | /* 0x001c: rd32_wait */ | 795 | /* 0x001c: rd32_wait */ |
| 794 | 0x07ace7f1, | 796 | 0x07acd7f1, |
| 795 | 0xf100eecf, | 797 | 0xf100ddcf, |
| 796 | 0xf47000e4, | 798 | 0xf47000d4, |
| 797 | 0xd7f1f51b, | 799 | 0xd7f1f51b, |
| 798 | 0xddcf07a4, | 800 | 0xddcf07a4, |
| 799 | /* 0x0033: wr32 */ | 801 | /* 0x0033: wr32 */ |
| @@ -802,14 +804,14 @@ uint32_t nvd0_pwr_code[] = { | |||
| 802 | 0x04bd000e, | 804 | 0x04bd000e, |
| 803 | 0x07a407f1, | 805 | 0x07a407f1, |
| 804 | 0xbd000dd0, | 806 | 0xbd000dd0, |
| 805 | 0x02e7f004, | 807 | 0x02d7f004, |
| 806 | 0xf0f0e5f0, | 808 | 0xf0f0d5f0, |
| 807 | 0x07f101e3, | 809 | 0x07f101d3, |
| 808 | 0x0ed007ac, | 810 | 0x0dd007ac, |
| 809 | /* 0x0057: wr32_wait */ | 811 | /* 0x0057: wr32_wait */ |
| 810 | 0xf104bd00, | 812 | 0xf104bd00, |
| 811 | 0xcf07ace7, | 813 | 0xcf07acd7, |
| 812 | 0xe4f100ee, | 814 | 0xd4f100dd, |
| 813 | 0x1bf47000, | 815 | 0x1bf47000, |
| 814 | /* 0x0067: nsec */ | 816 | /* 0x0067: nsec */ |
| 815 | 0xf000f8f5, | 817 | 0xf000f8f5, |
| @@ -836,21 +838,21 @@ uint32_t nvd0_pwr_code[] = { | |||
| 836 | 0x9800f8e2, | 838 | 0x9800f8e2, |
| 837 | 0x96b003e9, | 839 | 0x96b003e9, |
| 838 | 0x2a0bf400, | 840 | 0x2a0bf400, |
| 839 | 0xbb840a98, | 841 | 0xbb9a0a98, |
| 840 | 0x1cf4029a, | 842 | 0x1cf4029a, |
| 841 | 0x01d7f00f, | 843 | 0x01d7f00f, |
| 842 | 0x020621f5, | 844 | 0x020621f5, |
| 843 | 0x0ef494bd, | 845 | 0x0ef494bd, |
| 844 | /* 0x00c5: intr_watchdog_next_time */ | 846 | /* 0x00c5: intr_watchdog_next_time */ |
| 845 | 0x850a9815, | 847 | 0x9b0a9815, |
| 846 | 0xf400a6b0, | 848 | 0xf400a6b0, |
| 847 | 0x9ab8090b, | 849 | 0x9ab8090b, |
| 848 | 0x061cf406, | 850 | 0x061cf406, |
| 849 | /* 0x00d4: intr_watchdog_next_time_set */ | 851 | /* 0x00d4: intr_watchdog_next_time_set */ |
| 850 | /* 0x00d7: intr_watchdog_next_proc */ | 852 | /* 0x00d7: intr_watchdog_next_proc */ |
| 851 | 0x80850980, | 853 | 0x809b0980, |
| 852 | 0xe0b603e9, | 854 | 0xe0b603e9, |
| 853 | 0x10e6b158, | 855 | 0x68e6b158, |
| 854 | 0xc61bf402, | 856 | 0xc61bf402, |
| 855 | /* 0x00e6: intr */ | 857 | /* 0x00e6: intr */ |
| 856 | 0x00f900f8, | 858 | 0x00f900f8, |
| @@ -868,15 +870,15 @@ uint32_t nvd0_pwr_code[] = { | |||
| 868 | 0x0887f004, | 870 | 0x0887f004, |
| 869 | 0xc40088cf, | 871 | 0xc40088cf, |
| 870 | 0x0bf40289, | 872 | 0x0bf40289, |
| 871 | 0x85008020, | 873 | 0x9b008020, |
| 872 | 0xf458e7f0, | 874 | 0xf458e7f0, |
| 873 | 0x0998a721, | 875 | 0x0998a721, |
| 874 | 0x0096b085, | 876 | 0x0096b09b, |
| 875 | 0xf00e0bf4, | 877 | 0xf00e0bf4, |
| 876 | 0x09d03407, | 878 | 0x09d03407, |
| 877 | 0x8004bd00, | 879 | 0x8004bd00, |
| 878 | /* 0x013e: intr_skip_watchdog */ | 880 | /* 0x013e: intr_skip_watchdog */ |
| 879 | 0x89e48409, | 881 | 0x89e49a09, |
| 880 | 0x0bf40800, | 882 | 0x0bf40800, |
| 881 | 0x8897f13c, | 883 | 0x8897f13c, |
| 882 | 0x0099cf06, | 884 | 0x0099cf06, |
| @@ -929,7 +931,7 @@ uint32_t nvd0_pwr_code[] = { | |||
| 929 | 0x0ed03407, | 931 | 0x0ed03407, |
| 930 | 0x8004bd00, | 932 | 0x8004bd00, |
| 931 | /* 0x01f6: timer_enable */ | 933 | /* 0x01f6: timer_enable */ |
| 932 | 0x87f0840e, | 934 | 0x87f09a0e, |
| 933 | 0x3807f001, | 935 | 0x3807f001, |
| 934 | 0xbd0008d0, | 936 | 0xbd0008d0, |
| 935 | /* 0x0201: timer_done */ | 937 | /* 0x0201: timer_done */ |
| @@ -960,7 +962,7 @@ uint32_t nvd0_pwr_code[] = { | |||
| 960 | 0x06aeb800, | 962 | 0x06aeb800, |
| 961 | 0xb6100bf4, | 963 | 0xb6100bf4, |
| 962 | 0x86b15880, | 964 | 0x86b15880, |
| 963 | 0x1bf40210, | 965 | 0x1bf40268, |
| 964 | 0x0132f4f0, | 966 | 0x0132f4f0, |
| 965 | /* 0x0264: find_done */ | 967 | /* 0x0264: find_done */ |
| 966 | 0xfc028eb9, | 968 | 0xfc028eb9, |
| @@ -1024,7 +1026,7 @@ uint32_t nvd0_pwr_code[] = { | |||
| 1024 | 0x0bf40612, | 1026 | 0x0bf40612, |
| 1025 | 0x071ec42f, | 1027 | 0x071ec42f, |
| 1026 | 0xb704ee94, | 1028 | 0xb704ee94, |
| 1027 | 0x980218e0, | 1029 | 0x980270e0, |
| 1028 | 0xec9803eb, | 1030 | 0xec9803eb, |
| 1029 | 0x01ed9802, | 1031 | 0x01ed9802, |
| 1030 | 0xf500ee98, | 1032 | 0xf500ee98, |
| @@ -1048,7 +1050,7 @@ uint32_t nvd0_pwr_code[] = { | |||
| 1048 | 0xec0bf406, | 1050 | 0xec0bf406, |
| 1049 | 0xb60723c4, | 1051 | 0xb60723c4, |
| 1050 | 0x30b70434, | 1052 | 0x30b70434, |
| 1051 | 0x3b800298, | 1053 | 0x3b8002f0, |
| 1052 | 0x023c8003, | 1054 | 0x023c8003, |
| 1053 | 0x80013d80, | 1055 | 0x80013d80, |
| 1054 | 0x20b6003e, | 1056 | 0x20b6003e, |
| @@ -1061,12 +1063,12 @@ uint32_t nvd0_pwr_code[] = { | |||
| 1061 | /* 0x03be: host_init */ | 1063 | /* 0x03be: host_init */ |
| 1062 | 0x17f100f8, | 1064 | 0x17f100f8, |
| 1063 | 0x14b60080, | 1065 | 0x14b60080, |
| 1064 | 0x1815f110, | 1066 | 0x7015f110, |
| 1065 | 0xd007f102, | 1067 | 0xd007f102, |
| 1066 | 0x0001d004, | 1068 | 0x0001d004, |
| 1067 | 0x17f104bd, | 1069 | 0x17f104bd, |
| 1068 | 0x14b60080, | 1070 | 0x14b60080, |
| 1069 | 0x9815f110, | 1071 | 0xf015f110, |
| 1070 | 0xdc07f102, | 1072 | 0xdc07f102, |
| 1071 | 0x0001d004, | 1073 | 0x0001d004, |
| 1072 | 0x17f004bd, | 1074 | 0x17f004bd, |
| @@ -1122,13 +1124,13 @@ uint32_t nvd0_pwr_code[] = { | |||
| 1122 | 0x10b60013, | 1124 | 0x10b60013, |
| 1123 | 0x10349504, | 1125 | 0x10349504, |
| 1124 | 0x980c30f0, | 1126 | 0x980c30f0, |
| 1125 | 0x55f9c835, | 1127 | 0x55f9de35, |
| 1126 | 0xf40612b8, | 1128 | 0xf40612b8, |
| 1127 | 0xd0fcec1e, | 1129 | 0xd0fcec1e, |
| 1128 | 0x21f5e0fc, | 1130 | 0x21f5e0fc, |
| 1129 | 0x00f8026b, | 1131 | 0x00f8026b, |
| 1130 | /* 0x04a8: memx_info */ | 1132 | /* 0x04a8: memx_info */ |
| 1131 | 0x0354c7f1, | 1133 | 0x03acc7f1, |
| 1132 | 0x0800b7f1, | 1134 | 0x0800b7f1, |
| 1133 | 0x026b21f5, | 1135 | 0x026b21f5, |
| 1134 | /* 0x04b6: memx_recv */ | 1136 | /* 0x04b6: memx_recv */ |
| @@ -1140,49 +1142,342 @@ uint32_t nvd0_pwr_code[] = { | |||
| 1140 | /* 0x04c6: perf_recv */ | 1142 | /* 0x04c6: perf_recv */ |
| 1141 | 0x00f800f8, | 1143 | 0x00f800f8, |
| 1142 | /* 0x04c8: perf_init */ | 1144 | /* 0x04c8: perf_init */ |
| 1143 | /* 0x04ca: test_recv */ | 1145 | /* 0x04ca: i2c_drive_scl */ |
| 1144 | 0x17f100f8, | 1146 | 0x36b000f8, |
| 1145 | 0x11cf05d8, | 1147 | 0x0e0bf400, |
| 1146 | 0x0110b600, | 1148 | 0x07e007f1, |
| 1147 | 0x05d807f1, | ||
| 1148 | 0xbd0001d0, | 1149 | 0xbd0001d0, |
| 1149 | 0x00e7f104, | 1150 | /* 0x04db: i2c_drive_scl_lo */ |
| 1150 | 0x4fe3f1d9, | 1151 | 0xf100f804, |
| 1151 | 0xb621f513, | 1152 | 0xd007e407, |
| 1152 | /* 0x04eb: test_init */ | 1153 | 0x04bd0001, |
| 1153 | 0xf100f801, | 1154 | /* 0x04e6: i2c_drive_sda */ |
| 1154 | 0xf50800e7, | 1155 | 0x36b000f8, |
| 1155 | 0xf801b621, | 1156 | 0x0e0bf400, |
| 1156 | /* 0x04f5: idle_recv */ | 1157 | 0x07e007f1, |
| 1157 | /* 0x04f7: idle */ | 1158 | 0xbd0002d0, |
| 1158 | 0xf400f800, | 1159 | /* 0x04f7: i2c_drive_sda_lo */ |
| 1159 | 0x17f10031, | 1160 | 0xf100f804, |
| 1160 | 0x11cf05d4, | 1161 | 0xd007e407, |
| 1161 | 0x0110b600, | 1162 | 0x04bd0002, |
| 1162 | 0x05d407f1, | 1163 | /* 0x0502: i2c_sense_scl */ |
| 1163 | 0xbd0001d0, | 1164 | 0x32f400f8, |
| 1164 | /* 0x050d: idle_loop */ | 1165 | 0xc437f101, |
| 1165 | 0x5817f004, | 1166 | 0x0033cf07, |
| 1166 | /* 0x0513: idle_proc */ | 1167 | 0xf40431fd, |
| 1167 | /* 0x0513: idle_proc_exec */ | 1168 | 0x31f4060b, |
| 1168 | 0xf90232f4, | 1169 | /* 0x0515: i2c_sense_scl_done */ |
| 1169 | 0x021eb910, | 1170 | /* 0x0517: i2c_sense_sda */ |
| 1170 | 0x027421f5, | 1171 | 0xf400f801, |
| 1171 | 0x11f410fc, | 1172 | 0x37f10132, |
| 1172 | 0x0231f409, | 1173 | 0x33cf07c4, |
| 1173 | /* 0x0527: idle_proc_next */ | 1174 | 0x0432fd00, |
| 1174 | 0xb6ef0ef4, | 1175 | 0xf4060bf4, |
| 1175 | 0x1fb85810, | 1176 | /* 0x052a: i2c_sense_sda_done */ |
| 1176 | 0xe61bf406, | 1177 | 0x00f80131, |
| 1177 | 0xf4dd02f4, | 1178 | /* 0x052c: i2c_raise_scl */ |
| 1178 | 0x0ef40028, | 1179 | 0x47f140f9, |
| 1179 | 0x000000c1, | 1180 | 0x37f00898, |
| 1180 | 0x00000000, | 1181 | 0xca21f501, |
| 1181 | 0x00000000, | 1182 | /* 0x0539: i2c_raise_scl_wait */ |
| 1182 | 0x00000000, | 1183 | 0xe8e7f104, |
| 1183 | 0x00000000, | 1184 | 0x6721f403, |
| 1184 | 0x00000000, | 1185 | 0x050221f5, |
| 1185 | 0x00000000, | 1186 | 0xb60901f4, |
| 1187 | 0x1bf40142, | ||
| 1188 | /* 0x054d: i2c_raise_scl_done */ | ||
| 1189 | 0xf840fcef, | ||
| 1190 | /* 0x0551: i2c_start */ | ||
| 1191 | 0x0221f500, | ||
| 1192 | 0x0d11f405, | ||
| 1193 | 0x051721f5, | ||
| 1194 | 0xf40611f4, | ||
| 1195 | /* 0x0562: i2c_start_rep */ | ||
| 1196 | 0x37f0300e, | ||
| 1197 | 0xca21f500, | ||
| 1198 | 0x0137f004, | ||
| 1199 | 0x04e621f5, | ||
| 1200 | 0xb60076bb, | ||
| 1201 | 0x50f90465, | ||
| 1202 | 0xbb046594, | ||
| 1203 | 0x50bd0256, | ||
| 1204 | 0xfc0475fd, | ||
| 1205 | 0x2c21f550, | ||
| 1206 | 0x0464b605, | ||
| 1207 | /* 0x058f: i2c_start_send */ | ||
| 1208 | 0xf01f11f4, | ||
| 1209 | 0x21f50037, | ||
| 1210 | 0xe7f104e6, | ||
| 1211 | 0x21f41388, | ||
| 1212 | 0x0037f067, | ||
| 1213 | 0x04ca21f5, | ||
| 1214 | 0x1388e7f1, | ||
| 1215 | /* 0x05ab: i2c_start_out */ | ||
| 1216 | 0xf86721f4, | ||
| 1217 | /* 0x05ad: i2c_stop */ | ||
| 1218 | 0x0037f000, | ||
| 1219 | 0x04ca21f5, | ||
| 1220 | 0xf50037f0, | ||
| 1221 | 0xf104e621, | ||
| 1222 | 0xf403e8e7, | ||
| 1223 | 0x37f06721, | ||
| 1224 | 0xca21f501, | ||
| 1225 | 0x88e7f104, | ||
| 1226 | 0x6721f413, | ||
| 1227 | 0xf50137f0, | ||
| 1228 | 0xf104e621, | ||
| 1229 | 0xf41388e7, | ||
| 1230 | 0x00f86721, | ||
| 1231 | /* 0x05e0: i2c_bitw */ | ||
| 1232 | 0x04e621f5, | ||
| 1233 | 0x03e8e7f1, | ||
| 1234 | 0xbb6721f4, | ||
| 1235 | 0x65b60076, | ||
| 1236 | 0x9450f904, | ||
| 1237 | 0x56bb0465, | ||
| 1238 | 0xfd50bd02, | ||
| 1239 | 0x50fc0475, | ||
| 1240 | 0x052c21f5, | ||
| 1241 | 0xf40464b6, | ||
| 1242 | 0xe7f11811, | ||
| 1243 | 0x21f41388, | ||
| 1244 | 0x0037f067, | ||
| 1245 | 0x04ca21f5, | ||
| 1246 | 0x1388e7f1, | ||
| 1247 | /* 0x061f: i2c_bitw_out */ | ||
| 1248 | 0xf86721f4, | ||
| 1249 | /* 0x0621: i2c_bitr */ | ||
| 1250 | 0x0137f000, | ||
| 1251 | 0x04e621f5, | ||
| 1252 | 0x03e8e7f1, | ||
| 1253 | 0xbb6721f4, | ||
| 1254 | 0x65b60076, | ||
| 1255 | 0x9450f904, | ||
| 1256 | 0x56bb0465, | ||
| 1257 | 0xfd50bd02, | ||
| 1258 | 0x50fc0475, | ||
| 1259 | 0x052c21f5, | ||
| 1260 | 0xf40464b6, | ||
| 1261 | 0x21f51b11, | ||
| 1262 | 0x37f00517, | ||
| 1263 | 0xca21f500, | ||
| 1264 | 0x88e7f104, | ||
| 1265 | 0x6721f413, | ||
| 1266 | 0xf4013cf0, | ||
| 1267 | /* 0x0666: i2c_bitr_done */ | ||
| 1268 | 0x00f80131, | ||
| 1269 | /* 0x0668: i2c_get_byte */ | ||
| 1270 | 0xf00057f0, | ||
| 1271 | /* 0x066e: i2c_get_byte_next */ | ||
| 1272 | 0x54b60847, | ||
| 1273 | 0x0076bb01, | ||
| 1274 | 0xf90465b6, | ||
| 1275 | 0x04659450, | ||
| 1276 | 0xbd0256bb, | ||
| 1277 | 0x0475fd50, | ||
| 1278 | 0x21f550fc, | ||
| 1279 | 0x64b60621, | ||
| 1280 | 0x2b11f404, | ||
| 1281 | 0xb60553fd, | ||
| 1282 | 0x1bf40142, | ||
| 1283 | 0x0137f0d8, | ||
| 1284 | 0xb60076bb, | ||
| 1285 | 0x50f90465, | ||
| 1286 | 0xbb046594, | ||
| 1287 | 0x50bd0256, | ||
| 1288 | 0xfc0475fd, | ||
| 1289 | 0xe021f550, | ||
| 1290 | 0x0464b605, | ||
| 1291 | /* 0x06b8: i2c_get_byte_done */ | ||
| 1292 | /* 0x06ba: i2c_put_byte */ | ||
| 1293 | 0x47f000f8, | ||
| 1294 | /* 0x06bd: i2c_put_byte_next */ | ||
| 1295 | 0x0142b608, | ||
| 1296 | 0xbb3854ff, | ||
| 1297 | 0x65b60076, | ||
| 1298 | 0x9450f904, | ||
| 1299 | 0x56bb0465, | ||
| 1300 | 0xfd50bd02, | ||
| 1301 | 0x50fc0475, | ||
| 1302 | 0x05e021f5, | ||
| 1303 | 0xf40464b6, | ||
| 1304 | 0x46b03411, | ||
| 1305 | 0xd81bf400, | ||
| 1306 | 0xb60076bb, | ||
| 1307 | 0x50f90465, | ||
| 1308 | 0xbb046594, | ||
| 1309 | 0x50bd0256, | ||
| 1310 | 0xfc0475fd, | ||
| 1311 | 0x2121f550, | ||
| 1312 | 0x0464b606, | ||
| 1313 | 0xbb0f11f4, | ||
| 1314 | 0x36b00076, | ||
| 1315 | 0x061bf401, | ||
| 1316 | /* 0x0713: i2c_put_byte_done */ | ||
| 1317 | 0xf80132f4, | ||
| 1318 | /* 0x0715: i2c_addr */ | ||
| 1319 | 0x0076bb00, | ||
| 1320 | 0xf90465b6, | ||
| 1321 | 0x04659450, | ||
| 1322 | 0xbd0256bb, | ||
| 1323 | 0x0475fd50, | ||
| 1324 | 0x21f550fc, | ||
| 1325 | 0x64b60551, | ||
| 1326 | 0x2911f404, | ||
| 1327 | 0x012ec3e7, | ||
| 1328 | 0xfd0134b6, | ||
| 1329 | 0x76bb0553, | ||
| 1330 | 0x0465b600, | ||
| 1331 | 0x659450f9, | ||
| 1332 | 0x0256bb04, | ||
| 1333 | 0x75fd50bd, | ||
| 1334 | 0xf550fc04, | ||
| 1335 | 0xb606ba21, | ||
| 1336 | /* 0x075a: i2c_addr_done */ | ||
| 1337 | 0x00f80464, | ||
| 1338 | /* 0x075c: i2c_acquire_addr */ | ||
| 1339 | 0xb6f8cec7, | ||
| 1340 | 0xe0b705e4, | ||
| 1341 | 0x00f8d014, | ||
| 1342 | /* 0x0768: i2c_acquire */ | ||
| 1343 | 0x075c21f5, | ||
| 1344 | 0xf00421f4, | ||
| 1345 | 0x21f403d9, | ||
| 1346 | /* 0x0777: i2c_release */ | ||
| 1347 | 0xf500f833, | ||
| 1348 | 0xf4075c21, | ||
| 1349 | 0xdaf00421, | ||
| 1350 | 0x3321f403, | ||
| 1351 | /* 0x0786: i2c_recv */ | ||
| 1352 | 0x32f400f8, | ||
| 1353 | 0xf8c1c701, | ||
| 1354 | 0xb00214b6, | ||
| 1355 | 0x1ff52816, | ||
| 1356 | 0x13a0013a, | ||
| 1357 | 0x32980bd4, | ||
| 1358 | 0xac13a000, | ||
| 1359 | 0x0031980b, | ||
| 1360 | 0xf90231f4, | ||
| 1361 | 0xf9e0f9d0, | ||
| 1362 | 0x0067f1d0, | ||
| 1363 | 0x0063f100, | ||
| 1364 | 0x01679210, | ||
| 1365 | 0xb60076bb, | ||
| 1366 | 0x50f90465, | ||
| 1367 | 0xbb046594, | ||
| 1368 | 0x50bd0256, | ||
| 1369 | 0xfc0475fd, | ||
| 1370 | 0x6821f550, | ||
| 1371 | 0x0464b607, | ||
| 1372 | 0xd6b0d0fc, | ||
| 1373 | 0xb31bf500, | ||
| 1374 | 0x0057f000, | ||
| 1375 | 0xb60076bb, | ||
| 1376 | 0x50f90465, | ||
| 1377 | 0xbb046594, | ||
| 1378 | 0x50bd0256, | ||
| 1379 | 0xfc0475fd, | ||
| 1380 | 0x1521f550, | ||
| 1381 | 0x0464b607, | ||
| 1382 | 0x00d011f5, | ||
| 1383 | 0xbbe0c5c7, | ||
| 1384 | 0x65b60076, | ||
| 1385 | 0x9450f904, | ||
| 1386 | 0x56bb0465, | ||
| 1387 | 0xfd50bd02, | ||
| 1388 | 0x50fc0475, | ||
| 1389 | 0x06ba21f5, | ||
| 1390 | 0xf50464b6, | ||
| 1391 | 0xf000ad11, | ||
| 1392 | 0x76bb0157, | ||
| 1393 | 0x0465b600, | ||
| 1394 | 0x659450f9, | ||
| 1395 | 0x0256bb04, | ||
| 1396 | 0x75fd50bd, | ||
| 1397 | 0xf550fc04, | ||
| 1398 | 0xb6071521, | ||
| 1399 | 0x11f50464, | ||
| 1400 | 0x76bb008a, | ||
| 1401 | 0x0465b600, | ||
| 1402 | 0x659450f9, | ||
| 1403 | 0x0256bb04, | ||
| 1404 | 0x75fd50bd, | ||
| 1405 | 0xf550fc04, | ||
| 1406 | 0xb6066821, | ||
| 1407 | 0x11f40464, | ||
| 1408 | 0xe05bcb6a, | ||
| 1409 | 0xb60076bb, | ||
| 1410 | 0x50f90465, | ||
| 1411 | 0xbb046594, | ||
| 1412 | 0x50bd0256, | ||
| 1413 | 0xfc0475fd, | ||
| 1414 | 0xad21f550, | ||
| 1415 | 0x0464b605, | ||
| 1416 | 0xbd025bb9, | ||
| 1417 | 0x430ef474, | ||
| 1418 | /* 0x088c: i2c_recv_not_rd08 */ | ||
| 1419 | 0xf401d6b0, | ||
| 1420 | 0x57f03d1b, | ||
| 1421 | 0x1521f500, | ||
| 1422 | 0x3311f407, | ||
| 1423 | 0xf5e0c5c7, | ||
| 1424 | 0xf406ba21, | ||
| 1425 | 0x57f02911, | ||
| 1426 | 0x1521f500, | ||
| 1427 | 0x1f11f407, | ||
| 1428 | 0xf5e0b5c7, | ||
| 1429 | 0xf406ba21, | ||
| 1430 | 0x21f51511, | ||
| 1431 | 0x74bd05ad, | ||
| 1432 | 0xf408c5c7, | ||
| 1433 | 0x32f4091b, | ||
| 1434 | 0x030ef402, | ||
| 1435 | /* 0x08cc: i2c_recv_not_wr08 */ | ||
| 1436 | /* 0x08cc: i2c_recv_done */ | ||
| 1437 | 0xf5f8cec7, | ||
| 1438 | 0xfc077721, | ||
| 1439 | 0xf4d0fce0, | ||
| 1440 | 0x7cb90a12, | ||
| 1441 | 0x6b21f502, | ||
| 1442 | /* 0x08e1: i2c_recv_exit */ | ||
| 1443 | /* 0x08e3: i2c_init */ | ||
| 1444 | 0xf800f802, | ||
| 1445 | /* 0x08e5: test_recv */ | ||
| 1446 | 0xd817f100, | ||
| 1447 | 0x0011cf05, | ||
| 1448 | 0xf10110b6, | ||
| 1449 | 0xd005d807, | ||
| 1450 | 0x04bd0001, | ||
| 1451 | 0xd900e7f1, | ||
| 1452 | 0x134fe3f1, | ||
| 1453 | 0x01b621f5, | ||
| 1454 | /* 0x0906: test_init */ | ||
| 1455 | 0xe7f100f8, | ||
| 1456 | 0x21f50800, | ||
| 1457 | 0x00f801b6, | ||
| 1458 | /* 0x0910: idle_recv */ | ||
| 1459 | /* 0x0912: idle */ | ||
| 1460 | 0x31f400f8, | ||
| 1461 | 0xd417f100, | ||
| 1462 | 0x0011cf05, | ||
| 1463 | 0xf10110b6, | ||
| 1464 | 0xd005d407, | ||
| 1465 | 0x04bd0001, | ||
| 1466 | /* 0x0928: idle_loop */ | ||
| 1467 | 0xf45817f0, | ||
| 1468 | /* 0x092e: idle_proc */ | ||
| 1469 | /* 0x092e: idle_proc_exec */ | ||
| 1470 | 0x10f90232, | ||
| 1471 | 0xf5021eb9, | ||
| 1472 | 0xfc027421, | ||
| 1473 | 0x0911f410, | ||
| 1474 | 0xf40231f4, | ||
| 1475 | /* 0x0942: idle_proc_next */ | ||
| 1476 | 0x10b6ef0e, | ||
| 1477 | 0x061fb858, | ||
| 1478 | 0xf4e61bf4, | ||
| 1479 | 0x28f4dd02, | ||
| 1480 | 0xc10ef400, | ||
| 1186 | 0x00000000, | 1481 | 0x00000000, |
| 1187 | 0x00000000, | 1482 | 0x00000000, |
| 1188 | 0x00000000, | 1483 | 0x00000000, |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h index 5fb0cccc6c64..574acfa44c8c 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h +++ b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h | |||
| @@ -7,6 +7,7 @@ | |||
| 7 | #define PROC_HOST 0x54534f48 | 7 | #define PROC_HOST 0x54534f48 |
| 8 | #define PROC_MEMX 0x584d454d | 8 | #define PROC_MEMX 0x584d454d |
| 9 | #define PROC_PERF 0x46524550 | 9 | #define PROC_PERF 0x46524550 |
| 10 | #define PROC_I2C_ 0x5f433249 | ||
| 10 | #define PROC_TEST 0x54534554 | 11 | #define PROC_TEST 0x54534554 |
| 11 | 12 | ||
| 12 | /* KERN: message identifiers */ | 13 | /* KERN: message identifiers */ |
| @@ -24,4 +25,22 @@ | |||
| 24 | #define MEMX_WAIT 3 | 25 | #define MEMX_WAIT 3 |
| 25 | #define MEMX_DELAY 4 | 26 | #define MEMX_DELAY 4 |
| 26 | 27 | ||
| 28 | /* I2C_: message identifiers */ | ||
| 29 | #define I2C__MSG_RD08 0 | ||
| 30 | #define I2C__MSG_WR08 1 | ||
| 31 | |||
| 32 | #define I2C__MSG_DATA0_PORT 24:31 | ||
| 33 | #define I2C__MSG_DATA0_ADDR 14:23 | ||
| 34 | |||
| 35 | #define I2C__MSG_DATA0_RD08_PORT I2C__MSG_DATA0_PORT | ||
| 36 | #define I2C__MSG_DATA0_RD08_ADDR I2C__MSG_DATA0_ADDR | ||
| 37 | #define I2C__MSG_DATA0_RD08_REG 0:7 | ||
| 38 | #define I2C__MSG_DATA1_RD08_VAL 0:7 | ||
| 39 | |||
| 40 | #define I2C__MSG_DATA0_WR08_PORT I2C__MSG_DATA0_PORT | ||
| 41 | #define I2C__MSG_DATA0_WR08_ADDR I2C__MSG_DATA0_ADDR | ||
| 42 | #define I2C__MSG_DATA0_WR08_SYNC 8:8 | ||
| 43 | #define I2C__MSG_DATA0_WR08_REG 0:7 | ||
| 44 | #define I2C__MSG_DATA1_WR08_VAL 0:7 | ||
| 45 | |||
| 27 | #endif | 46 | #endif |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c index ef3133e7575c..7dd680ff2f6f 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c | |||
| @@ -72,13 +72,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) | |||
| 72 | vmm->flush(vm); | 72 | vmm->flush(vm); |
| 73 | } | 73 | } |
| 74 | 74 | ||
| 75 | void | 75 | static void |
| 76 | nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) | ||
| 77 | { | ||
| 78 | nouveau_vm_map_at(vma, 0, node); | ||
| 79 | } | ||
| 80 | |||
| 81 | void | ||
| 82 | nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, | 76 | nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, |
| 83 | struct nouveau_mem *mem) | 77 | struct nouveau_mem *mem) |
| 84 | { | 78 | { |
| @@ -136,7 +130,7 @@ finish: | |||
| 136 | vmm->flush(vm); | 130 | vmm->flush(vm); |
| 137 | } | 131 | } |
| 138 | 132 | ||
| 139 | void | 133 | static void |
| 140 | nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, | 134 | nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, |
| 141 | struct nouveau_mem *mem) | 135 | struct nouveau_mem *mem) |
| 142 | { | 136 | { |
| @@ -175,6 +169,18 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, | |||
| 175 | } | 169 | } |
| 176 | 170 | ||
| 177 | void | 171 | void |
| 172 | nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) | ||
| 173 | { | ||
| 174 | if (node->sg) | ||
| 175 | nouveau_vm_map_sg_table(vma, 0, node->size << 12, node); | ||
| 176 | else | ||
| 177 | if (node->pages) | ||
| 178 | nouveau_vm_map_sg(vma, 0, node->size << 12, node); | ||
| 179 | else | ||
| 180 | nouveau_vm_map_at(vma, 0, node); | ||
| 181 | } | ||
| 182 | |||
| 183 | void | ||
| 178 | nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) | 184 | nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) |
| 179 | { | 185 | { |
| 180 | struct nouveau_vm *vm = vma->vm; | 186 | struct nouveau_vm *vm = vma->vm; |
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index b13ff0fc42de..2f1ed61f7c8c 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c | |||
| @@ -77,11 +77,6 @@ nv04_display_create(struct drm_device *dev) | |||
| 77 | 77 | ||
| 78 | nouveau_hw_save_vga_fonts(dev, 1); | 78 | nouveau_hw_save_vga_fonts(dev, 1); |
| 79 | 79 | ||
| 80 | ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE, 0xd1500000, | ||
| 81 | NV04_DISP_CLASS, NULL, 0, &disp->core); | ||
| 82 | if (ret) | ||
| 83 | return ret; | ||
| 84 | |||
| 85 | nv04_crtc_create(dev, 0); | 80 | nv04_crtc_create(dev, 0); |
| 86 | if (nv_two_heads(dev)) | 81 | if (nv_two_heads(dev)) |
| 87 | nv04_crtc_create(dev, 1); | 82 | nv04_crtc_create(dev, 1); |
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h index 56a28db04000..4245fc3dab70 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h | |||
| @@ -80,7 +80,6 @@ struct nv04_display { | |||
| 80 | struct nv04_mode_state saved_reg; | 80 | struct nv04_mode_state saved_reg; |
| 81 | uint32_t saved_vga_font[4][16384]; | 81 | uint32_t saved_vga_font[4][16384]; |
| 82 | uint32_t dac_users[4]; | 82 | uint32_t dac_users[4]; |
| 83 | struct nouveau_object *core; | ||
| 84 | struct nouveau_bo *image[2]; | 83 | struct nouveau_bo *image[2]; |
| 85 | }; | 84 | }; |
| 86 | 85 | ||
diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index 32e7064b819b..ab03f7719d2d 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c | |||
| @@ -55,9 +55,12 @@ struct nouveau_plane { | |||
| 55 | int hue; | 55 | int hue; |
| 56 | int saturation; | 56 | int saturation; |
| 57 | int iturbt_709; | 57 | int iturbt_709; |
| 58 | |||
| 59 | void (*set_params)(struct nouveau_plane *); | ||
| 58 | }; | 60 | }; |
| 59 | 61 | ||
| 60 | static uint32_t formats[] = { | 62 | static uint32_t formats[] = { |
| 63 | DRM_FORMAT_YUYV, | ||
| 61 | DRM_FORMAT_UYVY, | 64 | DRM_FORMAT_UYVY, |
| 62 | DRM_FORMAT_NV12, | 65 | DRM_FORMAT_NV12, |
| 63 | }; | 66 | }; |
| @@ -140,10 +143,10 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
| 140 | nv_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); | 143 | nv_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); |
| 141 | nv_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); | 144 | nv_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); |
| 142 | 145 | ||
| 143 | if (fb->pixel_format == DRM_FORMAT_NV12) { | 146 | if (fb->pixel_format != DRM_FORMAT_UYVY) |
| 144 | format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; | 147 | format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; |
| 148 | if (fb->pixel_format == DRM_FORMAT_NV12) | ||
| 145 | format |= NV_PVIDEO_FORMAT_PLANAR; | 149 | format |= NV_PVIDEO_FORMAT_PLANAR; |
| 146 | } | ||
| 147 | if (nv_plane->iturbt_709) | 150 | if (nv_plane->iturbt_709) |
| 148 | format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; | 151 | format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; |
| 149 | if (nv_plane->colorkey & (1 << 24)) | 152 | if (nv_plane->colorkey & (1 << 24)) |
| @@ -182,9 +185,9 @@ nv10_disable_plane(struct drm_plane *plane) | |||
| 182 | } | 185 | } |
| 183 | 186 | ||
| 184 | static void | 187 | static void |
| 185 | nv10_destroy_plane(struct drm_plane *plane) | 188 | nv_destroy_plane(struct drm_plane *plane) |
| 186 | { | 189 | { |
| 187 | nv10_disable_plane(plane); | 190 | plane->funcs->disable_plane(plane); |
| 188 | drm_plane_cleanup(plane); | 191 | drm_plane_cleanup(plane); |
| 189 | kfree(plane); | 192 | kfree(plane); |
| 190 | } | 193 | } |
| @@ -217,9 +220,9 @@ nv10_set_params(struct nouveau_plane *plane) | |||
| 217 | } | 220 | } |
| 218 | 221 | ||
| 219 | static int | 222 | static int |
| 220 | nv10_set_property(struct drm_plane *plane, | 223 | nv_set_property(struct drm_plane *plane, |
| 221 | struct drm_property *property, | 224 | struct drm_property *property, |
| 222 | uint64_t value) | 225 | uint64_t value) |
| 223 | { | 226 | { |
| 224 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; | 227 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; |
| 225 | 228 | ||
| @@ -238,15 +241,16 @@ nv10_set_property(struct drm_plane *plane, | |||
| 238 | else | 241 | else |
| 239 | return -EINVAL; | 242 | return -EINVAL; |
| 240 | 243 | ||
| 241 | nv10_set_params(nv_plane); | 244 | if (nv_plane->set_params) |
| 245 | nv_plane->set_params(nv_plane); | ||
| 242 | return 0; | 246 | return 0; |
| 243 | } | 247 | } |
| 244 | 248 | ||
| 245 | static const struct drm_plane_funcs nv10_plane_funcs = { | 249 | static const struct drm_plane_funcs nv10_plane_funcs = { |
| 246 | .update_plane = nv10_update_plane, | 250 | .update_plane = nv10_update_plane, |
| 247 | .disable_plane = nv10_disable_plane, | 251 | .disable_plane = nv10_disable_plane, |
| 248 | .set_property = nv10_set_property, | 252 | .set_property = nv_set_property, |
| 249 | .destroy = nv10_destroy_plane, | 253 | .destroy = nv_destroy_plane, |
| 250 | }; | 254 | }; |
| 251 | 255 | ||
| 252 | static void | 256 | static void |
| @@ -266,7 +270,7 @@ nv10_overlay_init(struct drm_device *device) | |||
| 266 | case 0x15: | 270 | case 0x15: |
| 267 | case 0x1a: | 271 | case 0x1a: |
| 268 | case 0x20: | 272 | case 0x20: |
| 269 | num_formats = 1; | 273 | num_formats = 2; |
| 270 | break; | 274 | break; |
| 271 | } | 275 | } |
| 272 | 276 | ||
| @@ -321,8 +325,159 @@ nv10_overlay_init(struct drm_device *device) | |||
| 321 | drm_object_attach_property(&plane->base.base, | 325 | drm_object_attach_property(&plane->base.base, |
| 322 | plane->props.iturbt_709, plane->iturbt_709); | 326 | plane->props.iturbt_709, plane->iturbt_709); |
| 323 | 327 | ||
| 328 | plane->set_params = nv10_set_params; | ||
| 324 | nv10_set_params(plane); | 329 | nv10_set_params(plane); |
| 325 | nv_wr32(dev, NV_PVIDEO_STOP, 1); | 330 | nv10_disable_plane(&plane->base); |
| 331 | return; | ||
| 332 | cleanup: | ||
| 333 | drm_plane_cleanup(&plane->base); | ||
| 334 | err: | ||
| 335 | kfree(plane); | ||
| 336 | nv_error(dev, "Failed to create plane\n"); | ||
| 337 | } | ||
| 338 | |||
| 339 | static int | ||
| 340 | nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | ||
| 341 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | ||
| 342 | unsigned int crtc_w, unsigned int crtc_h, | ||
| 343 | uint32_t src_x, uint32_t src_y, | ||
| 344 | uint32_t src_w, uint32_t src_h) | ||
| 345 | { | ||
| 346 | struct nouveau_device *dev = nouveau_dev(plane->dev); | ||
| 347 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; | ||
| 348 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | ||
| 349 | struct nouveau_bo *cur = nv_plane->cur; | ||
| 350 | uint32_t overlay = 1; | ||
| 351 | int brightness = (nv_plane->brightness - 512) * 62 / 512; | ||
| 352 | int pitch, ret, i; | ||
| 353 | |||
| 354 | /* Source parameters given in 16.16 fixed point, ignore fractional. */ | ||
| 355 | src_x >>= 16; | ||
| 356 | src_y >>= 16; | ||
| 357 | src_w >>= 16; | ||
| 358 | src_h >>= 16; | ||
| 359 | |||
| 360 | pitch = ALIGN(src_w * 4, 0x100); | ||
| 361 | |||
| 362 | if (pitch > 0xffff) | ||
| 363 | return -ERANGE; | ||
| 364 | |||
| 365 | /* TODO: Compute an offset? Not sure how to do this for YUYV. */ | ||
| 366 | if (src_x != 0 || src_y != 0) | ||
| 367 | return -ERANGE; | ||
| 368 | |||
| 369 | if (crtc_w < src_w || crtc_h < src_h) | ||
| 370 | return -ERANGE; | ||
| 371 | |||
| 372 | ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM); | ||
| 373 | if (ret) | ||
| 374 | return ret; | ||
| 375 | |||
| 376 | nv_plane->cur = nv_fb->nvbo; | ||
| 377 | |||
| 378 | nv_wr32(dev, NV_PVIDEO_OE_STATE, 0); | ||
| 379 | nv_wr32(dev, NV_PVIDEO_SU_STATE, 0); | ||
| 380 | nv_wr32(dev, NV_PVIDEO_RM_STATE, 0); | ||
| 381 | |||
| 382 | for (i = 0; i < 2; i++) { | ||
| 383 | nv_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i, | ||
| 384 | nv_fb->nvbo->bo.offset); | ||
| 385 | nv_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch); | ||
| 386 | nv_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0); | ||
| 387 | } | ||
| 388 | nv_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x); | ||
| 389 | nv_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w); | ||
| 390 | nv_wr32(dev, NV_PVIDEO_STEP_SIZE, | ||
| 391 | (uint32_t)(((src_h - 1) << 11) / (crtc_h - 1)) << 16 | (uint32_t)(((src_w - 1) << 11) / (crtc_w - 1))); | ||
| 392 | |||
| 393 | /* It should be possible to convert hue/contrast to this */ | ||
| 394 | nv_wr32(dev, NV_PVIDEO_RED_CSC_OFFSET, 0x69 - brightness); | ||
| 395 | nv_wr32(dev, NV_PVIDEO_GREEN_CSC_OFFSET, 0x3e + brightness); | ||
| 396 | nv_wr32(dev, NV_PVIDEO_BLUE_CSC_OFFSET, 0x89 - brightness); | ||
| 397 | nv_wr32(dev, NV_PVIDEO_CSC_ADJUST, 0); | ||
| 398 | |||
| 399 | nv_wr32(dev, NV_PVIDEO_CONTROL_Y, 0x001); /* (BLUR_ON, LINE_HALF) */ | ||
| 400 | nv_wr32(dev, NV_PVIDEO_CONTROL_X, 0x111); /* (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | ||
| 401 | |||
| 402 | nv_wr32(dev, NV_PVIDEO_FIFO_BURST_LENGTH, 0x03); | ||
| 403 | nv_wr32(dev, NV_PVIDEO_FIFO_THRES_SIZE, 0x38); | ||
| 404 | |||
| 405 | nv_wr32(dev, NV_PVIDEO_KEY, nv_plane->colorkey); | ||
| 406 | |||
| 407 | if (nv_plane->colorkey & (1 << 24)) | ||
| 408 | overlay |= 0x10; | ||
| 409 | if (fb->pixel_format == DRM_FORMAT_YUYV) | ||
| 410 | overlay |= 0x100; | ||
| 411 | |||
| 412 | nv_wr32(dev, NV_PVIDEO_OVERLAY, overlay); | ||
| 413 | |||
| 414 | nv_wr32(dev, NV_PVIDEO_SU_STATE, nv_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16)); | ||
| 415 | |||
| 416 | if (cur) | ||
| 417 | nouveau_bo_unpin(cur); | ||
| 418 | |||
| 419 | return 0; | ||
| 420 | } | ||
| 421 | |||
| 422 | static int | ||
| 423 | nv04_disable_plane(struct drm_plane *plane) | ||
| 424 | { | ||
| 425 | struct nouveau_device *dev = nouveau_dev(plane->dev); | ||
| 426 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; | ||
| 427 | |||
| 428 | nv_mask(dev, NV_PVIDEO_OVERLAY, 1, 0); | ||
| 429 | nv_wr32(dev, NV_PVIDEO_OE_STATE, 0); | ||
| 430 | nv_wr32(dev, NV_PVIDEO_SU_STATE, 0); | ||
| 431 | nv_wr32(dev, NV_PVIDEO_RM_STATE, 0); | ||
| 432 | if (nv_plane->cur) { | ||
| 433 | nouveau_bo_unpin(nv_plane->cur); | ||
| 434 | nv_plane->cur = NULL; | ||
| 435 | } | ||
| 436 | |||
| 437 | return 0; | ||
| 438 | } | ||
| 439 | |||
| 440 | static const struct drm_plane_funcs nv04_plane_funcs = { | ||
| 441 | .update_plane = nv04_update_plane, | ||
| 442 | .disable_plane = nv04_disable_plane, | ||
| 443 | .set_property = nv_set_property, | ||
| 444 | .destroy = nv_destroy_plane, | ||
| 445 | }; | ||
| 446 | |||
| 447 | static void | ||
| 448 | nv04_overlay_init(struct drm_device *device) | ||
| 449 | { | ||
| 450 | struct nouveau_device *dev = nouveau_dev(device); | ||
| 451 | struct nouveau_plane *plane = kzalloc(sizeof(struct nouveau_plane), GFP_KERNEL); | ||
| 452 | int ret; | ||
| 453 | |||
| 454 | if (!plane) | ||
| 455 | return; | ||
| 456 | |||
| 457 | ret = drm_plane_init(device, &plane->base, 1 /* single crtc */, | ||
| 458 | &nv04_plane_funcs, | ||
| 459 | formats, 2, false); | ||
| 460 | if (ret) | ||
| 461 | goto err; | ||
| 462 | |||
| 463 | /* Set up the plane properties */ | ||
| 464 | plane->props.colorkey = drm_property_create_range( | ||
| 465 | device, 0, "colorkey", 0, 0x01ffffff); | ||
| 466 | plane->props.brightness = drm_property_create_range( | ||
| 467 | device, 0, "brightness", 0, 1024); | ||
| 468 | if (!plane->props.colorkey || | ||
| 469 | !plane->props.brightness) | ||
| 470 | goto cleanup; | ||
| 471 | |||
| 472 | plane->colorkey = 0; | ||
| 473 | drm_object_attach_property(&plane->base.base, | ||
| 474 | plane->props.colorkey, plane->colorkey); | ||
| 475 | |||
| 476 | plane->brightness = 512; | ||
| 477 | drm_object_attach_property(&plane->base.base, | ||
| 478 | plane->props.brightness, plane->brightness); | ||
| 479 | |||
| 480 | nv04_disable_plane(&plane->base); | ||
| 326 | return; | 481 | return; |
| 327 | cleanup: | 482 | cleanup: |
| 328 | drm_plane_cleanup(&plane->base); | 483 | drm_plane_cleanup(&plane->base); |
| @@ -335,6 +490,8 @@ void | |||
| 335 | nouveau_overlay_init(struct drm_device *device) | 490 | nouveau_overlay_init(struct drm_device *device) |
| 336 | { | 491 | { |
| 337 | struct nouveau_device *dev = nouveau_dev(device); | 492 | struct nouveau_device *dev = nouveau_dev(device); |
| 338 | if (dev->chipset >= 0x10 && dev->chipset <= 0x40) | 493 | if (dev->chipset < 0x10) |
| 494 | nv04_overlay_init(device); | ||
| 495 | else if (dev->chipset <= 0x40) | ||
| 339 | nv10_overlay_init(device); | 496 | nv10_overlay_init(device); |
| 340 | } | 497 | } |
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index c0fde6b9393c..488686d490c0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c | |||
| @@ -560,28 +560,6 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |||
| 560 | } | 560 | } |
| 561 | 561 | ||
| 562 | 562 | ||
| 563 | /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access | ||
| 564 | * TTM_PL_{VRAM,TT} directly. | ||
| 565 | */ | ||
| 566 | |||
| 567 | static int | ||
| 568 | nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, | ||
| 569 | struct nouveau_bo *nvbo, bool evict, | ||
| 570 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) | ||
| 571 | { | ||
| 572 | struct nouveau_fence *fence = NULL; | ||
| 573 | int ret; | ||
| 574 | |||
| 575 | ret = nouveau_fence_new(chan, false, &fence); | ||
| 576 | if (ret) | ||
| 577 | return ret; | ||
| 578 | |||
| 579 | ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, evict, | ||
| 580 | no_wait_gpu, new_mem); | ||
| 581 | nouveau_fence_unref(&fence); | ||
| 582 | return ret; | ||
| 583 | } | ||
| 584 | |||
| 585 | static int | 563 | static int |
| 586 | nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) | 564 | nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) |
| 587 | { | 565 | { |
| @@ -798,25 +776,25 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |||
| 798 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | 776 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) |
| 799 | { | 777 | { |
| 800 | struct nouveau_mem *node = old_mem->mm_node; | 778 | struct nouveau_mem *node = old_mem->mm_node; |
| 801 | struct nouveau_bo *nvbo = nouveau_bo(bo); | ||
| 802 | u64 length = (new_mem->num_pages << PAGE_SHIFT); | 779 | u64 length = (new_mem->num_pages << PAGE_SHIFT); |
| 803 | u64 src_offset = node->vma[0].offset; | 780 | u64 src_offset = node->vma[0].offset; |
| 804 | u64 dst_offset = node->vma[1].offset; | 781 | u64 dst_offset = node->vma[1].offset; |
| 782 | int src_tiled = !!node->memtype; | ||
| 783 | int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype; | ||
| 805 | int ret; | 784 | int ret; |
| 806 | 785 | ||
| 807 | while (length) { | 786 | while (length) { |
| 808 | u32 amount, stride, height; | 787 | u32 amount, stride, height; |
| 809 | 788 | ||
| 789 | ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); | ||
| 790 | if (ret) | ||
| 791 | return ret; | ||
| 792 | |||
| 810 | amount = min(length, (u64)(4 * 1024 * 1024)); | 793 | amount = min(length, (u64)(4 * 1024 * 1024)); |
| 811 | stride = 16 * 4; | 794 | stride = 16 * 4; |
| 812 | height = amount / stride; | 795 | height = amount / stride; |
| 813 | 796 | ||
| 814 | if (old_mem->mem_type == TTM_PL_VRAM && | 797 | if (src_tiled) { |
| 815 | nouveau_bo_tile_layout(nvbo)) { | ||
| 816 | ret = RING_SPACE(chan, 8); | ||
| 817 | if (ret) | ||
| 818 | return ret; | ||
| 819 | |||
| 820 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); | 798 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); |
| 821 | OUT_RING (chan, 0); | 799 | OUT_RING (chan, 0); |
| 822 | OUT_RING (chan, 0); | 800 | OUT_RING (chan, 0); |
| @@ -826,19 +804,10 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |||
| 826 | OUT_RING (chan, 0); | 804 | OUT_RING (chan, 0); |
| 827 | OUT_RING (chan, 0); | 805 | OUT_RING (chan, 0); |
| 828 | } else { | 806 | } else { |
| 829 | ret = RING_SPACE(chan, 2); | ||
| 830 | if (ret) | ||
| 831 | return ret; | ||
| 832 | |||
| 833 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); | 807 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); |
| 834 | OUT_RING (chan, 1); | 808 | OUT_RING (chan, 1); |
| 835 | } | 809 | } |
| 836 | if (new_mem->mem_type == TTM_PL_VRAM && | 810 | if (dst_tiled) { |
| 837 | nouveau_bo_tile_layout(nvbo)) { | ||
| 838 | ret = RING_SPACE(chan, 8); | ||
| 839 | if (ret) | ||
| 840 | return ret; | ||
| 841 | |||
| 842 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); | 811 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); |
| 843 | OUT_RING (chan, 0); | 812 | OUT_RING (chan, 0); |
| 844 | OUT_RING (chan, 0); | 813 | OUT_RING (chan, 0); |
| @@ -848,18 +817,10 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |||
| 848 | OUT_RING (chan, 0); | 817 | OUT_RING (chan, 0); |
| 849 | OUT_RING (chan, 0); | 818 | OUT_RING (chan, 0); |
| 850 | } else { | 819 | } else { |
| 851 | ret = RING_SPACE(chan, 2); | ||
| 852 | if (ret) | ||
| 853 | return ret; | ||
| 854 | |||
| 855 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); | 820 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); |
| 856 | OUT_RING (chan, 1); | 821 | OUT_RING (chan, 1); |
| 857 | } | 822 | } |
| 858 | 823 | ||
| 859 | ret = RING_SPACE(chan, 14); | ||
| 860 | if (ret) | ||
| 861 | return ret; | ||
| 862 | |||
| 863 | BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); | 824 | BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); |
| 864 | OUT_RING (chan, upper_32_bits(src_offset)); | 825 | OUT_RING (chan, upper_32_bits(src_offset)); |
| 865 | OUT_RING (chan, upper_32_bits(dst_offset)); | 826 | OUT_RING (chan, upper_32_bits(dst_offset)); |
| @@ -953,23 +914,28 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |||
| 953 | } | 914 | } |
| 954 | 915 | ||
| 955 | static int | 916 | static int |
| 956 | nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo, | 917 | nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, |
| 957 | struct ttm_mem_reg *mem, struct nouveau_vma *vma) | 918 | struct ttm_mem_reg *mem) |
| 958 | { | 919 | { |
| 959 | struct nouveau_mem *node = mem->mm_node; | 920 | struct nouveau_mem *old_node = bo->mem.mm_node; |
| 921 | struct nouveau_mem *new_node = mem->mm_node; | ||
| 922 | u64 size = (u64)mem->num_pages << PAGE_SHIFT; | ||
| 960 | int ret; | 923 | int ret; |
| 961 | 924 | ||
| 962 | ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages << | 925 | ret = nouveau_vm_get(nv_client(drm)->vm, size, old_node->page_shift, |
| 963 | PAGE_SHIFT, node->page_shift, | 926 | NV_MEM_ACCESS_RW, &old_node->vma[0]); |
| 964 | NV_MEM_ACCESS_RW, vma); | ||
| 965 | if (ret) | 927 | if (ret) |
| 966 | return ret; | 928 | return ret; |
| 967 | 929 | ||
| 968 | if (mem->mem_type == TTM_PL_VRAM) | 930 | ret = nouveau_vm_get(nv_client(drm)->vm, size, new_node->page_shift, |
| 969 | nouveau_vm_map(vma, node); | 931 | NV_MEM_ACCESS_RW, &old_node->vma[1]); |
| 970 | else | 932 | if (ret) { |
| 971 | nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node); | 933 | nouveau_vm_put(&old_node->vma[0]); |
| 934 | return ret; | ||
| 935 | } | ||
| 972 | 936 | ||
| 937 | nouveau_vm_map(&old_node->vma[0], old_node); | ||
| 938 | nouveau_vm_map(&old_node->vma[1], new_node); | ||
| 973 | return 0; | 939 | return 0; |
| 974 | } | 940 | } |
| 975 | 941 | ||
| @@ -979,35 +945,34 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, | |||
| 979 | { | 945 | { |
| 980 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); | 946 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
| 981 | struct nouveau_channel *chan = drm->ttm.chan; | 947 | struct nouveau_channel *chan = drm->ttm.chan; |
| 982 | struct nouveau_bo *nvbo = nouveau_bo(bo); | 948 | struct nouveau_fence *fence; |
| 983 | struct ttm_mem_reg *old_mem = &bo->mem; | ||
| 984 | int ret; | 949 | int ret; |
| 985 | 950 | ||
| 986 | mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING); | ||
| 987 | |||
| 988 | /* create temporary vmas for the transfer and attach them to the | 951 | /* create temporary vmas for the transfer and attach them to the |
| 989 | * old nouveau_mem node, these will get cleaned up after ttm has | 952 | * old nouveau_mem node, these will get cleaned up after ttm has |
| 990 | * destroyed the ttm_mem_reg | 953 | * destroyed the ttm_mem_reg |
| 991 | */ | 954 | */ |
| 992 | if (nv_device(drm->device)->card_type >= NV_50) { | 955 | if (nv_device(drm->device)->card_type >= NV_50) { |
| 993 | struct nouveau_mem *node = old_mem->mm_node; | 956 | ret = nouveau_bo_move_prep(drm, bo, new_mem); |
| 994 | |||
| 995 | ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]); | ||
| 996 | if (ret) | ||
| 997 | goto out; | ||
| 998 | |||
| 999 | ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]); | ||
| 1000 | if (ret) | 957 | if (ret) |
| 1001 | goto out; | 958 | return ret; |
| 1002 | } | 959 | } |
| 1003 | 960 | ||
| 1004 | ret = drm->ttm.move(chan, bo, &bo->mem, new_mem); | 961 | mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING); |
| 962 | ret = nouveau_fence_sync(bo->sync_obj, chan); | ||
| 1005 | if (ret == 0) { | 963 | if (ret == 0) { |
| 1006 | ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict, | 964 | ret = drm->ttm.move(chan, bo, &bo->mem, new_mem); |
| 1007 | no_wait_gpu, new_mem); | 965 | if (ret == 0) { |
| 966 | ret = nouveau_fence_new(chan, false, &fence); | ||
| 967 | if (ret == 0) { | ||
| 968 | ret = ttm_bo_move_accel_cleanup(bo, fence, | ||
| 969 | evict, | ||
| 970 | no_wait_gpu, | ||
| 971 | new_mem); | ||
| 972 | nouveau_fence_unref(&fence); | ||
| 973 | } | ||
| 974 | } | ||
| 1008 | } | 975 | } |
| 1009 | |||
| 1010 | out: | ||
| 1011 | mutex_unlock(&chan->cli->mutex); | 976 | mutex_unlock(&chan->cli->mutex); |
| 1012 | return ret; | 977 | return ret; |
| 1013 | } | 978 | } |
| @@ -1147,19 +1112,10 @@ nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) | |||
| 1147 | return; | 1112 | return; |
| 1148 | 1113 | ||
| 1149 | list_for_each_entry(vma, &nvbo->vma_list, head) { | 1114 | list_for_each_entry(vma, &nvbo->vma_list, head) { |
| 1150 | if (new_mem && new_mem->mem_type == TTM_PL_VRAM) { | 1115 | if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM && |
| 1116 | (new_mem->mem_type == TTM_PL_VRAM || | ||
| 1117 | nvbo->page_shift != vma->vm->vmm->lpg_shift)) { | ||
| 1151 | nouveau_vm_map(vma, new_mem->mm_node); | 1118 | nouveau_vm_map(vma, new_mem->mm_node); |
| 1152 | } else | ||
| 1153 | if (new_mem && new_mem->mem_type == TTM_PL_TT && | ||
| 1154 | nvbo->page_shift == vma->vm->vmm->spg_shift) { | ||
| 1155 | if (((struct nouveau_mem *)new_mem->mm_node)->sg) | ||
| 1156 | nouveau_vm_map_sg_table(vma, 0, new_mem-> | ||
| 1157 | num_pages << PAGE_SHIFT, | ||
| 1158 | new_mem->mm_node); | ||
| 1159 | else | ||
| 1160 | nouveau_vm_map_sg(vma, 0, new_mem-> | ||
| 1161 | num_pages << PAGE_SHIFT, | ||
| 1162 | new_mem->mm_node); | ||
| 1163 | } else { | 1119 | } else { |
| 1164 | nouveau_vm_unmap(vma); | 1120 | nouveau_vm_unmap(vma); |
| 1165 | } | 1121 | } |
| @@ -1224,28 +1180,27 @@ nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |||
| 1224 | goto out; | 1180 | goto out; |
| 1225 | } | 1181 | } |
| 1226 | 1182 | ||
| 1227 | /* CPU copy if we have no accelerated method available */ | ||
| 1228 | if (!drm->ttm.move) { | ||
| 1229 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); | ||
| 1230 | goto out; | ||
| 1231 | } | ||
| 1232 | |||
| 1233 | /* Hardware assisted copy. */ | 1183 | /* Hardware assisted copy. */ |
| 1234 | if (new_mem->mem_type == TTM_PL_SYSTEM) | 1184 | if (drm->ttm.move) { |
| 1235 | ret = nouveau_bo_move_flipd(bo, evict, intr, | 1185 | if (new_mem->mem_type == TTM_PL_SYSTEM) |
| 1236 | no_wait_gpu, new_mem); | 1186 | ret = nouveau_bo_move_flipd(bo, evict, intr, |
| 1237 | else if (old_mem->mem_type == TTM_PL_SYSTEM) | 1187 | no_wait_gpu, new_mem); |
| 1238 | ret = nouveau_bo_move_flips(bo, evict, intr, | 1188 | else if (old_mem->mem_type == TTM_PL_SYSTEM) |
| 1239 | no_wait_gpu, new_mem); | 1189 | ret = nouveau_bo_move_flips(bo, evict, intr, |
| 1240 | else | 1190 | no_wait_gpu, new_mem); |
| 1241 | ret = nouveau_bo_move_m2mf(bo, evict, intr, | 1191 | else |
| 1242 | no_wait_gpu, new_mem); | 1192 | ret = nouveau_bo_move_m2mf(bo, evict, intr, |
| 1243 | 1193 | no_wait_gpu, new_mem); | |
| 1244 | if (!ret) | 1194 | if (!ret) |
| 1245 | goto out; | 1195 | goto out; |
| 1196 | } | ||
| 1246 | 1197 | ||
| 1247 | /* Fallback to software copy. */ | 1198 | /* Fallback to software copy. */ |
| 1248 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); | 1199 | spin_lock(&bo->bdev->fence_lock); |
| 1200 | ret = ttm_bo_wait(bo, true, intr, no_wait_gpu); | ||
| 1201 | spin_unlock(&bo->bdev->fence_lock); | ||
| 1202 | if (ret == 0) | ||
| 1203 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); | ||
| 1249 | 1204 | ||
| 1250 | out: | 1205 | out: |
| 1251 | if (nv_device(drm->device)->card_type < NV_50) { | 1206 | if (nv_device(drm->device)->card_type < NV_50) { |
| @@ -1271,6 +1226,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |||
| 1271 | { | 1226 | { |
| 1272 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | 1227 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; |
| 1273 | struct nouveau_drm *drm = nouveau_bdev(bdev); | 1228 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
| 1229 | struct nouveau_mem *node = mem->mm_node; | ||
| 1274 | struct drm_device *dev = drm->dev; | 1230 | struct drm_device *dev = drm->dev; |
| 1275 | int ret; | 1231 | int ret; |
| 1276 | 1232 | ||
| @@ -1293,14 +1249,16 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |||
| 1293 | mem->bus.is_iomem = !dev->agp->cant_use_aperture; | 1249 | mem->bus.is_iomem = !dev->agp->cant_use_aperture; |
| 1294 | } | 1250 | } |
| 1295 | #endif | 1251 | #endif |
| 1296 | break; | 1252 | if (!node->memtype) |
| 1253 | /* untiled */ | ||
| 1254 | break; | ||
| 1255 | /* fallthrough, tiled memory */ | ||
| 1297 | case TTM_PL_VRAM: | 1256 | case TTM_PL_VRAM: |
| 1298 | mem->bus.offset = mem->start << PAGE_SHIFT; | 1257 | mem->bus.offset = mem->start << PAGE_SHIFT; |
| 1299 | mem->bus.base = pci_resource_start(dev->pdev, 1); | 1258 | mem->bus.base = pci_resource_start(dev->pdev, 1); |
| 1300 | mem->bus.is_iomem = true; | 1259 | mem->bus.is_iomem = true; |
| 1301 | if (nv_device(drm->device)->card_type >= NV_50) { | 1260 | if (nv_device(drm->device)->card_type >= NV_50) { |
| 1302 | struct nouveau_bar *bar = nouveau_bar(drm->device); | 1261 | struct nouveau_bar *bar = nouveau_bar(drm->device); |
| 1303 | struct nouveau_mem *node = mem->mm_node; | ||
| 1304 | 1262 | ||
| 1305 | ret = bar->umap(bar, node, NV_MEM_ACCESS_RW, | 1263 | ret = bar->umap(bar, node, NV_MEM_ACCESS_RW, |
| 1306 | &node->bar_vma); | 1264 | &node->bar_vma); |
| @@ -1336,6 +1294,7 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |||
| 1336 | struct nouveau_bo *nvbo = nouveau_bo(bo); | 1294 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
| 1337 | struct nouveau_device *device = nv_device(drm->device); | 1295 | struct nouveau_device *device = nv_device(drm->device); |
| 1338 | u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT; | 1296 | u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT; |
| 1297 | int ret; | ||
| 1339 | 1298 | ||
| 1340 | /* as long as the bo isn't in vram, and isn't tiled, we've got | 1299 | /* as long as the bo isn't in vram, and isn't tiled, we've got |
| 1341 | * nothing to do here. | 1300 | * nothing to do here. |
| @@ -1344,10 +1303,20 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |||
| 1344 | if (nv_device(drm->device)->card_type < NV_50 || | 1303 | if (nv_device(drm->device)->card_type < NV_50 || |
| 1345 | !nouveau_bo_tile_layout(nvbo)) | 1304 | !nouveau_bo_tile_layout(nvbo)) |
| 1346 | return 0; | 1305 | return 0; |
| 1306 | |||
| 1307 | if (bo->mem.mem_type == TTM_PL_SYSTEM) { | ||
| 1308 | nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); | ||
| 1309 | |||
| 1310 | ret = nouveau_bo_validate(nvbo, false, false); | ||
| 1311 | if (ret) | ||
| 1312 | return ret; | ||
| 1313 | } | ||
| 1314 | return 0; | ||
| 1347 | } | 1315 | } |
| 1348 | 1316 | ||
| 1349 | /* make sure bo is in mappable vram */ | 1317 | /* make sure bo is in mappable vram */ |
| 1350 | if (bo->mem.start + bo->mem.num_pages < mappable) | 1318 | if (nv_device(drm->device)->card_type >= NV_50 || |
| 1319 | bo->mem.start + bo->mem.num_pages < mappable) | ||
| 1351 | return 0; | 1320 | return 0; |
| 1352 | 1321 | ||
| 1353 | 1322 | ||
| @@ -1535,7 +1504,6 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, | |||
| 1535 | struct nouveau_vma *vma) | 1504 | struct nouveau_vma *vma) |
| 1536 | { | 1505 | { |
| 1537 | const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT; | 1506 | const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT; |
| 1538 | struct nouveau_mem *node = nvbo->bo.mem.mm_node; | ||
| 1539 | int ret; | 1507 | int ret; |
| 1540 | 1508 | ||
| 1541 | ret = nouveau_vm_get(vm, size, nvbo->page_shift, | 1509 | ret = nouveau_vm_get(vm, size, nvbo->page_shift, |
| @@ -1543,15 +1511,10 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, | |||
| 1543 | if (ret) | 1511 | if (ret) |
| 1544 | return ret; | 1512 | return ret; |
| 1545 | 1513 | ||
| 1546 | if (nvbo->bo.mem.mem_type == TTM_PL_VRAM) | 1514 | if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM && |
| 1515 | (nvbo->bo.mem.mem_type == TTM_PL_VRAM || | ||
| 1516 | nvbo->page_shift != vma->vm->vmm->lpg_shift)) | ||
| 1547 | nouveau_vm_map(vma, nvbo->bo.mem.mm_node); | 1517 | nouveau_vm_map(vma, nvbo->bo.mem.mm_node); |
| 1548 | else if (nvbo->bo.mem.mem_type == TTM_PL_TT && | ||
| 1549 | nvbo->page_shift == vma->vm->vmm->spg_shift) { | ||
| 1550 | if (node->sg) | ||
| 1551 | nouveau_vm_map_sg_table(vma, 0, size, node); | ||
| 1552 | else | ||
| 1553 | nouveau_vm_map_sg(vma, 0, size, node); | ||
| 1554 | } | ||
| 1555 | 1518 | ||
| 1556 | list_add_tail(&vma->head, &nvbo->vma_list); | 1519 | list_add_tail(&vma->head, &nvbo->vma_list); |
| 1557 | vma->refcount = 1; | 1520 | vma->refcount = 1; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 25ea82f8def3..b4262ad66b18 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c | |||
| @@ -74,14 +74,14 @@ nouveau_display_vblank_fini(struct drm_device *dev) | |||
| 74 | struct nouveau_display *disp = nouveau_display(dev); | 74 | struct nouveau_display *disp = nouveau_display(dev); |
| 75 | int i; | 75 | int i; |
| 76 | 76 | ||
| 77 | drm_vblank_cleanup(dev); | ||
| 78 | |||
| 77 | if (disp->vblank) { | 79 | if (disp->vblank) { |
| 78 | for (i = 0; i < dev->mode_config.num_crtc; i++) | 80 | for (i = 0; i < dev->mode_config.num_crtc; i++) |
| 79 | nouveau_event_ref(NULL, &disp->vblank[i]); | 81 | nouveau_event_ref(NULL, &disp->vblank[i]); |
| 80 | kfree(disp->vblank); | 82 | kfree(disp->vblank); |
| 81 | disp->vblank = NULL; | 83 | disp->vblank = NULL; |
| 82 | } | 84 | } |
| 83 | |||
| 84 | drm_vblank_cleanup(dev); | ||
| 85 | } | 85 | } |
| 86 | 86 | ||
| 87 | static int | 87 | static int |
| @@ -407,10 +407,31 @@ nouveau_display_create(struct drm_device *dev) | |||
| 407 | drm_kms_helper_poll_disable(dev); | 407 | drm_kms_helper_poll_disable(dev); |
| 408 | 408 | ||
| 409 | if (drm->vbios.dcb.entries) { | 409 | if (drm->vbios.dcb.entries) { |
| 410 | if (nv_device(drm->device)->card_type < NV_50) | 410 | static const u16 oclass[] = { |
| 411 | ret = nv04_display_create(dev); | 411 | NVF0_DISP_CLASS, |
| 412 | else | 412 | NVE0_DISP_CLASS, |
| 413 | ret = nv50_display_create(dev); | 413 | NVD0_DISP_CLASS, |
| 414 | NVA3_DISP_CLASS, | ||
| 415 | NV94_DISP_CLASS, | ||
| 416 | NVA0_DISP_CLASS, | ||
| 417 | NV84_DISP_CLASS, | ||
| 418 | NV50_DISP_CLASS, | ||
| 419 | NV04_DISP_CLASS, | ||
| 420 | }; | ||
| 421 | int i; | ||
| 422 | |||
| 423 | for (i = 0, ret = -ENODEV; ret && i < ARRAY_SIZE(oclass); i++) { | ||
| 424 | ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE, | ||
| 425 | NVDRM_DISPLAY, oclass[i], | ||
| 426 | NULL, 0, &disp->core); | ||
| 427 | } | ||
| 428 | |||
| 429 | if (ret == 0) { | ||
| 430 | if (nv_mclass(disp->core) < NV50_DISP_CLASS) | ||
| 431 | ret = nv04_display_create(dev); | ||
| 432 | else | ||
| 433 | ret = nv50_display_create(dev); | ||
| 434 | } | ||
| 414 | } else { | 435 | } else { |
| 415 | ret = 0; | 436 | ret = 0; |
| 416 | } | 437 | } |
| @@ -439,6 +460,7 @@ void | |||
| 439 | nouveau_display_destroy(struct drm_device *dev) | 460 | nouveau_display_destroy(struct drm_device *dev) |
| 440 | { | 461 | { |
| 441 | struct nouveau_display *disp = nouveau_display(dev); | 462 | struct nouveau_display *disp = nouveau_display(dev); |
| 463 | struct nouveau_drm *drm = nouveau_drm(dev); | ||
| 442 | 464 | ||
| 443 | nouveau_backlight_exit(dev); | 465 | nouveau_backlight_exit(dev); |
| 444 | nouveau_display_vblank_fini(dev); | 466 | nouveau_display_vblank_fini(dev); |
| @@ -449,6 +471,8 @@ nouveau_display_destroy(struct drm_device *dev) | |||
| 449 | if (disp->dtor) | 471 | if (disp->dtor) |
| 450 | disp->dtor(dev); | 472 | disp->dtor(dev); |
| 451 | 473 | ||
| 474 | nouveau_object_del(nv_object(drm), NVDRM_DEVICE, NVDRM_DISPLAY); | ||
| 475 | |||
| 452 | nouveau_drm(dev)->display = NULL; | 476 | nouveau_drm(dev)->display = NULL; |
| 453 | kfree(disp); | 477 | kfree(disp); |
| 454 | } | 478 | } |
| @@ -603,6 +627,14 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
| 603 | if (!s) | 627 | if (!s) |
| 604 | return -ENOMEM; | 628 | return -ENOMEM; |
| 605 | 629 | ||
| 630 | if (new_bo != old_bo) { | ||
| 631 | ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM); | ||
| 632 | if (ret) | ||
| 633 | goto fail_free; | ||
| 634 | } | ||
| 635 | |||
| 636 | mutex_lock(&chan->cli->mutex); | ||
| 637 | |||
| 606 | /* synchronise rendering channel with the kernel's channel */ | 638 | /* synchronise rendering channel with the kernel's channel */ |
| 607 | spin_lock(&new_bo->bo.bdev->fence_lock); | 639 | spin_lock(&new_bo->bo.bdev->fence_lock); |
| 608 | fence = nouveau_fence_ref(new_bo->bo.sync_obj); | 640 | fence = nouveau_fence_ref(new_bo->bo.sync_obj); |
| @@ -612,13 +644,6 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
| 612 | if (ret) | 644 | if (ret) |
| 613 | goto fail_free; | 645 | goto fail_free; |
| 614 | 646 | ||
| 615 | if (new_bo != old_bo) { | ||
| 616 | ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM); | ||
| 617 | if (ret) | ||
| 618 | goto fail_free; | ||
| 619 | } | ||
| 620 | |||
| 621 | mutex_lock(&chan->cli->mutex); | ||
| 622 | ret = ttm_bo_reserve(&old_bo->bo, true, false, false, NULL); | 647 | ret = ttm_bo_reserve(&old_bo->bo, true, false, false, NULL); |
| 623 | if (ret) | 648 | if (ret) |
| 624 | goto fail_unpin; | 649 | goto fail_unpin; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 8bc8bab90e8d..73aa231130b8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h | |||
| @@ -36,6 +36,7 @@ struct nouveau_display { | |||
| 36 | int (*init)(struct drm_device *); | 36 | int (*init)(struct drm_device *); |
| 37 | void (*fini)(struct drm_device *); | 37 | void (*fini)(struct drm_device *); |
| 38 | 38 | ||
| 39 | struct nouveau_object *core; | ||
| 39 | struct nouveau_eventh **vblank; | 40 | struct nouveau_eventh **vblank; |
| 40 | 41 | ||
| 41 | struct drm_property *dithering_mode; | 42 | struct drm_property *dithering_mode; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h index 4b0fb6c66be9..23ca7a517246 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.h +++ b/drivers/gpu/drm/nouveau/nouveau_drm.h | |||
| @@ -54,6 +54,7 @@ enum nouveau_drm_handle { | |||
| 54 | NVDRM_CLIENT = 0xffffffff, | 54 | NVDRM_CLIENT = 0xffffffff, |
| 55 | NVDRM_DEVICE = 0xdddddddd, | 55 | NVDRM_DEVICE = 0xdddddddd, |
| 56 | NVDRM_CONTROL = 0xdddddddc, | 56 | NVDRM_CONTROL = 0xdddddddc, |
| 57 | NVDRM_DISPLAY = 0xd1500000, | ||
| 57 | NVDRM_PUSH = 0xbbbb0000, /* |= client chid */ | 58 | NVDRM_PUSH = 0xbbbb0000, /* |= client chid */ |
| 58 | NVDRM_CHAN = 0xcccc0000, /* |= client chid */ | 59 | NVDRM_CHAN = 0xcccc0000, /* |= client chid */ |
| 59 | NVDRM_NVSW = 0x55550000, | 60 | NVDRM_NVSW = 0x55550000, |
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 0447163cd2b4..27c3fd89e8ce 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c | |||
| @@ -463,12 +463,6 @@ validate_list(struct nouveau_channel *chan, struct nouveau_cli *cli, | |||
| 463 | list_for_each_entry(nvbo, list, entry) { | 463 | list_for_each_entry(nvbo, list, entry) { |
| 464 | struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index]; | 464 | struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index]; |
| 465 | 465 | ||
| 466 | ret = validate_sync(chan, nvbo); | ||
| 467 | if (unlikely(ret)) { | ||
| 468 | NV_ERROR(cli, "fail pre-validate sync\n"); | ||
| 469 | return ret; | ||
| 470 | } | ||
| 471 | |||
| 472 | ret = nouveau_gem_set_domain(&nvbo->gem, b->read_domains, | 466 | ret = nouveau_gem_set_domain(&nvbo->gem, b->read_domains, |
| 473 | b->write_domains, | 467 | b->write_domains, |
| 474 | b->valid_domains); | 468 | b->valid_domains); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index 0843ebc910d4..a4d22e5eb176 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c | |||
| @@ -31,16 +31,17 @@ nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) | |||
| 31 | { | 31 | { |
| 32 | struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; | 32 | struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; |
| 33 | struct nouveau_mem *node = mem->mm_node; | 33 | struct nouveau_mem *node = mem->mm_node; |
| 34 | u64 size = mem->num_pages << 12; | ||
| 35 | 34 | ||
| 36 | if (ttm->sg) { | 35 | if (ttm->sg) { |
| 37 | node->sg = ttm->sg; | 36 | node->sg = ttm->sg; |
| 38 | nouveau_vm_map_sg_table(&node->vma[0], 0, size, node); | 37 | node->pages = NULL; |
| 39 | } else { | 38 | } else { |
| 39 | node->sg = NULL; | ||
| 40 | node->pages = nvbe->ttm.dma_address; | 40 | node->pages = nvbe->ttm.dma_address; |
| 41 | nouveau_vm_map_sg(&node->vma[0], 0, size, node); | ||
| 42 | } | 41 | } |
| 42 | node->size = (mem->num_pages << PAGE_SHIFT) >> 12; | ||
| 43 | 43 | ||
| 44 | nouveau_vm_map(&node->vma[0], node); | ||
| 44 | nvbe->node = node; | 45 | nvbe->node = node; |
| 45 | return 0; | 46 | return 0; |
| 46 | } | 47 | } |
| @@ -67,9 +68,13 @@ nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) | |||
| 67 | 68 | ||
| 68 | /* noop: bound in move_notify() */ | 69 | /* noop: bound in move_notify() */ |
| 69 | if (ttm->sg) { | 70 | if (ttm->sg) { |
| 70 | node->sg = ttm->sg; | 71 | node->sg = ttm->sg; |
| 71 | } else | 72 | node->pages = NULL; |
| 73 | } else { | ||
| 74 | node->sg = NULL; | ||
| 72 | node->pages = nvbe->ttm.dma_address; | 75 | node->pages = nvbe->ttm.dma_address; |
| 76 | } | ||
| 77 | node->size = (mem->num_pages << PAGE_SHIFT) >> 12; | ||
| 73 | return 0; | 78 | return 0; |
| 74 | } | 79 | } |
| 75 | 80 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 19e3757291fb..d45d50da978f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c | |||
| @@ -171,6 +171,7 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man, | |||
| 171 | node = kzalloc(sizeof(*node), GFP_KERNEL); | 171 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
| 172 | if (!node) | 172 | if (!node) |
| 173 | return -ENOMEM; | 173 | return -ENOMEM; |
| 174 | |||
| 174 | node->page_shift = 12; | 175 | node->page_shift = 12; |
| 175 | 176 | ||
| 176 | switch (nv_device(drm->device)->card_type) { | 177 | switch (nv_device(drm->device)->card_type) { |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 4e384a2f99c3..6ae7a697866e 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
| @@ -2199,16 +2199,6 @@ nv50_display_destroy(struct drm_device *dev) | |||
| 2199 | int | 2199 | int |
| 2200 | nv50_display_create(struct drm_device *dev) | 2200 | nv50_display_create(struct drm_device *dev) |
| 2201 | { | 2201 | { |
| 2202 | static const u16 oclass[] = { | ||
| 2203 | NVF0_DISP_CLASS, | ||
| 2204 | NVE0_DISP_CLASS, | ||
| 2205 | NVD0_DISP_CLASS, | ||
| 2206 | NVA3_DISP_CLASS, | ||
| 2207 | NV94_DISP_CLASS, | ||
| 2208 | NVA0_DISP_CLASS, | ||
| 2209 | NV84_DISP_CLASS, | ||
| 2210 | NV50_DISP_CLASS, | ||
| 2211 | }; | ||
| 2212 | struct nouveau_device *device = nouveau_dev(dev); | 2202 | struct nouveau_device *device = nouveau_dev(dev); |
| 2213 | struct nouveau_drm *drm = nouveau_drm(dev); | 2203 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 2214 | struct dcb_table *dcb = &drm->vbios.dcb; | 2204 | struct dcb_table *dcb = &drm->vbios.dcb; |
| @@ -2225,6 +2215,7 @@ nv50_display_create(struct drm_device *dev) | |||
| 2225 | nouveau_display(dev)->dtor = nv50_display_destroy; | 2215 | nouveau_display(dev)->dtor = nv50_display_destroy; |
| 2226 | nouveau_display(dev)->init = nv50_display_init; | 2216 | nouveau_display(dev)->init = nv50_display_init; |
| 2227 | nouveau_display(dev)->fini = nv50_display_fini; | 2217 | nouveau_display(dev)->fini = nv50_display_fini; |
| 2218 | disp->core = nouveau_display(dev)->core; | ||
| 2228 | 2219 | ||
| 2229 | /* small shared memory area we use for notifiers and semaphores */ | 2220 | /* small shared memory area we use for notifiers and semaphores */ |
| 2230 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | 2221 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
| @@ -2243,17 +2234,6 @@ nv50_display_create(struct drm_device *dev) | |||
| 2243 | if (ret) | 2234 | if (ret) |
| 2244 | goto out; | 2235 | goto out; |
| 2245 | 2236 | ||
| 2246 | /* attempt to allocate a supported evo display class */ | ||
| 2247 | ret = -ENODEV; | ||
| 2248 | for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) { | ||
| 2249 | ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE, | ||
| 2250 | 0xd1500000, oclass[i], NULL, 0, | ||
| 2251 | &disp->core); | ||
| 2252 | } | ||
| 2253 | |||
| 2254 | if (ret) | ||
| 2255 | goto out; | ||
| 2256 | |||
| 2257 | /* allocate master evo channel */ | 2237 | /* allocate master evo channel */ |
| 2258 | ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0, | 2238 | ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0, |
| 2259 | &(struct nv50_display_mast_class) { | 2239 | &(struct nv50_display_mast_class) { |