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authorPeter De Schrijver <pdeschrijver@nvidia.com>2013-09-04 10:04:19 -0400
committerPeter De Schrijver <pdeschrijver@nvidia.com>2013-11-26 11:46:47 -0500
commit76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8 (patch)
treead44079c32a84567ba3d05bed0d9252a06736efe /drivers
parent6609dbe40e199ca8b1e99513d0e4bbc32b0d53b7 (diff)
clk: tegra: move periph clocks to common file
Introduce a new file for peripheral clocks common between several Tegra SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT clocks will be initialized here. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/tegra/Makefile2
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c596
-rw-r--r--drivers/clk/tegra/clk-tegra114.c591
-rw-r--r--drivers/clk/tegra/clk-tegra20.c4
-rw-r--r--drivers/clk/tegra/clk-tegra30.c4
-rw-r--r--drivers/clk/tegra/clk.h11
6 files changed, 627 insertions, 581 deletions
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 796ff9aa3899..304ea5df63eb 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -7,7 +7,7 @@ obj-y += clk-pll.o
7obj-y += clk-pll-out.o 7obj-y += clk-pll-out.o
8obj-y += clk-super.o 8obj-y += clk-super.o
9obj-y += clk-tegra-audio.o 9obj-y += clk-tegra-audio.o
10 10obj-y += clk-tegra-periph.o
11obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o 11obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
12obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 12obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
13obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o 13obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
new file mode 100644
index 000000000000..9b04139f331d
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -0,0 +1,596 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/delay.h>
24#include <linux/export.h>
25#include <linux/clk/tegra.h>
26
27#include "clk.h"
28#include "clk-id.h"
29
30#define CLK_SOURCE_I2S0 0x1d8
31#define CLK_SOURCE_I2S1 0x100
32#define CLK_SOURCE_I2S2 0x104
33#define CLK_SOURCE_NDFLASH 0x160
34#define CLK_SOURCE_I2S3 0x3bc
35#define CLK_SOURCE_I2S4 0x3c0
36#define CLK_SOURCE_SPDIF_OUT 0x108
37#define CLK_SOURCE_SPDIF_IN 0x10c
38#define CLK_SOURCE_PWM 0x110
39#define CLK_SOURCE_ADX 0x638
40#define CLK_SOURCE_AMX 0x63c
41#define CLK_SOURCE_HDA 0x428
42#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
43#define CLK_SOURCE_SBC1 0x134
44#define CLK_SOURCE_SBC2 0x118
45#define CLK_SOURCE_SBC3 0x11c
46#define CLK_SOURCE_SBC4 0x1b4
47#define CLK_SOURCE_SBC5 0x3c8
48#define CLK_SOURCE_SBC6 0x3cc
49#define CLK_SOURCE_SATA_OOB 0x420
50#define CLK_SOURCE_SATA 0x424
51#define CLK_SOURCE_NDSPEED 0x3f8
52#define CLK_SOURCE_VFIR 0x168
53#define CLK_SOURCE_SDMMC1 0x150
54#define CLK_SOURCE_SDMMC2 0x154
55#define CLK_SOURCE_SDMMC3 0x1bc
56#define CLK_SOURCE_SDMMC4 0x164
57#define CLK_SOURCE_CVE 0x140
58#define CLK_SOURCE_TVO 0x188
59#define CLK_SOURCE_TVDAC 0x194
60#define CLK_SOURCE_VDE 0x1c8
61#define CLK_SOURCE_CSITE 0x1d4
62#define CLK_SOURCE_LA 0x1f8
63#define CLK_SOURCE_TRACE 0x634
64#define CLK_SOURCE_OWR 0x1cc
65#define CLK_SOURCE_NOR 0x1d0
66#define CLK_SOURCE_MIPI 0x174
67#define CLK_SOURCE_I2C1 0x124
68#define CLK_SOURCE_I2C2 0x198
69#define CLK_SOURCE_I2C3 0x1b8
70#define CLK_SOURCE_I2C4 0x3c4
71#define CLK_SOURCE_I2C5 0x128
72#define CLK_SOURCE_UARTA 0x178
73#define CLK_SOURCE_UARTB 0x17c
74#define CLK_SOURCE_UARTC 0x1a0
75#define CLK_SOURCE_UARTD 0x1c0
76#define CLK_SOURCE_UARTE 0x1c4
77#define CLK_SOURCE_3D 0x158
78#define CLK_SOURCE_2D 0x15c
79#define CLK_SOURCE_MPE 0x170
80#define CLK_SOURCE_VI_SENSOR 0x1a8
81#define CLK_SOURCE_VI 0x148
82#define CLK_SOURCE_EPP 0x16c
83#define CLK_SOURCE_MSENC 0x1f0
84#define CLK_SOURCE_TSEC 0x1f4
85#define CLK_SOURCE_HOST1X 0x180
86#define CLK_SOURCE_HDMI 0x18c
87#define CLK_SOURCE_DISP1 0x138
88#define CLK_SOURCE_DISP2 0x13c
89#define CLK_SOURCE_CILAB 0x614
90#define CLK_SOURCE_CILCD 0x618
91#define CLK_SOURCE_CILE 0x61c
92#define CLK_SOURCE_DSIALP 0x620
93#define CLK_SOURCE_DSIBLP 0x624
94#define CLK_SOURCE_TSENSOR 0x3b8
95#define CLK_SOURCE_D_AUDIO 0x3d0
96#define CLK_SOURCE_DAM0 0x3d8
97#define CLK_SOURCE_DAM1 0x3dc
98#define CLK_SOURCE_DAM2 0x3e0
99#define CLK_SOURCE_ACTMON 0x3e8
100#define CLK_SOURCE_EXTERN1 0x3ec
101#define CLK_SOURCE_EXTERN2 0x3f0
102#define CLK_SOURCE_EXTERN3 0x3f4
103#define CLK_SOURCE_I2CSLOW 0x3fc
104#define CLK_SOURCE_SE 0x42c
105#define CLK_SOURCE_MSELECT 0x3b4
106#define CLK_SOURCE_DFLL_REF 0x62c
107#define CLK_SOURCE_DFLL_SOC 0x630
108#define CLK_SOURCE_SOC_THERM 0x644
109#define CLK_SOURCE_XUSB_HOST_SRC 0x600
110#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
111#define CLK_SOURCE_XUSB_FS_SRC 0x608
112#define CLK_SOURCE_XUSB_SS_SRC 0x610
113#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
114
115#define MASK(x) (BIT(x) - 1)
116
117#define MUX(_name, _parents, _offset, \
118 _clk_num, _gate_flags, _clk_id) \
119 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
120 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
121 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0)
122
123#define MUX_FLAGS(_name, _parents, _offset,\
124 _clk_num, _gate_flags, _clk_id, flags)\
125 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
126 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
127 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags)
128
129#define MUX8(_name, _parents, _offset, \
130 _clk_num, _gate_flags, _clk_id) \
131 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
132 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
133 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0)
134
135#define INT(_name, _parents, _offset, \
136 _clk_num, _gate_flags, _clk_id) \
137 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
138 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
139 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
140 _clk_id, _parents##_idx, 0)
141
142#define INT_FLAGS(_name, _parents, _offset,\
143 _clk_num, _gate_flags, _clk_id, flags)\
144 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
145 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
146 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
147 _clk_id, _parents##_idx, flags)
148
149#define INT8(_name, _parents, _offset,\
150 _clk_num, _gate_flags, _clk_id) \
151 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
152 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
153 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
154 _clk_id, _parents##_idx, 0)
155
156#define UART(_name, _parents, _offset,\
157 _clk_num, _clk_id) \
158 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
159 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
160 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
161 _parents##_idx, 0)
162
163#define I2C(_name, _parents, _offset,\
164 _clk_num, _clk_id) \
165 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
166 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
167 _clk_num, 0, _clk_id, _parents##_idx, 0)
168
169#define XUSB(_name, _parents, _offset, \
170 _clk_num, _gate_flags, _clk_id) \
171 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
172 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
173 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
174 _clk_id, _parents##_idx, 0)
175
176#define AUDIO(_name, _offset, _clk_num,\
177 _gate_flags, _clk_id) \
178 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
179 _offset, 16, 0xE01F, 0, 0, 8, 1, \
180 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \
181 _clk_id, mux_d_audio_clk_idx, 0)
182
183#define NODIV(_name, _parents, _offset, \
184 _mux_shift, _mux_mask, _clk_num, \
185 _gate_flags, _clk_id) \
186 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
187 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
188 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
189 _clk_id, _parents##_idx, 0)
190
191#define GATE(_name, _parent_name, \
192 _clk_num, _gate_flags, _clk_id, _flags) \
193 { \
194 .name = _name, \
195 .clk_id = _clk_id, \
196 .p.parent_name = _parent_name, \
197 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \
198 _clk_num, _gate_flags, 0), \
199 .flags = _flags \
200 }
201
202#define PLLP_BASE 0xa0
203#define PLLP_MISC 0xac
204#define PLLP_OUTA 0xa4
205#define PLLP_OUTB 0xa8
206
207#define PLL_BASE_LOCK BIT(27)
208#define PLL_MISC_LOCK_ENABLE 18
209
210static DEFINE_SPINLOCK(PLLP_OUTA_lock);
211static DEFINE_SPINLOCK(PLLP_OUTB_lock);
212
213#define MUX_I2S_SPDIF(_id) \
214static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
215 #_id, "pll_p",\
216 "clk_m"};
217MUX_I2S_SPDIF(audio0)
218MUX_I2S_SPDIF(audio1)
219MUX_I2S_SPDIF(audio2)
220MUX_I2S_SPDIF(audio3)
221MUX_I2S_SPDIF(audio4)
222MUX_I2S_SPDIF(audio)
223
224#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
225#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
226#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
227#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
228#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
229#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
230
231static const char *mux_pllp_pllc_pllm_clkm[] = {
232 "pll_p", "pll_c", "pll_m", "clk_m"
233};
234#define mux_pllp_pllc_pllm_clkm_idx NULL
235
236static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
237#define mux_pllp_pllc_pllm_idx NULL
238
239static const char *mux_pllp_pllc_clk32_clkm[] = {
240 "pll_p", "pll_c", "clk_32k", "clk_m"
241};
242#define mux_pllp_pllc_clk32_clkm_idx NULL
243
244static const char *mux_plla_pllc_pllp_clkm[] = {
245 "pll_a_out0", "pll_c", "pll_p", "clk_m"
246};
247#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
248
249static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
250 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
251};
252static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
253 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
254};
255
256static const char *mux_pllp_clkm[] = {
257 "pll_p", "clk_m"
258};
259static u32 mux_pllp_clkm_idx[] = {
260 [0] = 0, [1] = 3,
261};
262
263static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
264 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
265};
266#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
267
268static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
269 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
270 "pll_d2_out0", "clk_m"
271};
272#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
273
274static const char *mux_pllm_pllc_pllp_plla[] = {
275 "pll_m", "pll_c", "pll_p", "pll_a_out0"
276};
277#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
278
279static const char *mux_pllp_pllc_clkm[] = {
280 "pll_p", "pll_c", "pll_m"
281};
282static u32 mux_pllp_pllc_clkm_idx[] = {
283 [0] = 0, [1] = 1, [2] = 3,
284};
285
286static const char *mux_pllp_pllc_clkm_clk32[] = {
287 "pll_p", "pll_c", "clk_m", "clk_32k"
288};
289#define mux_pllp_pllc_clkm_clk32_idx NULL
290
291static const char *mux_plla_clk32_pllp_clkm_plle[] = {
292 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
293};
294#define mux_plla_clk32_pllp_clkm_plle_idx NULL
295
296static const char *mux_clkm_pllp_pllc_pllre[] = {
297 "clk_m", "pll_p", "pll_c", "pll_re_out"
298};
299static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
300 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
301};
302
303static const char *mux_clkm_48M_pllp_480M[] = {
304 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
305};
306#define mux_clkm_48M_pllp_480M_idx NULL
307
308static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
309 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
310};
311static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
312 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
313};
314
315static const char *mux_d_audio_clk[] = {
316 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
317 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
318};
319static u32 mux_d_audio_clk_idx[] = {
320 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
321 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
322};
323
324static const char *mux_pllp_plld_pllc_clkm[] = {
325 "pll_p", "pll_d_out0", "pll_c", "clk_m"
326};
327#define mux_pllp_plld_pllc_clkm_idx NULL
328
329static struct tegra_periph_init_data periph_clks[] = {
330 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
331 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
332 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
333 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
334 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
335 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
336 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
337 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
338 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
339 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
340 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
341 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
342 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
343 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
344 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
345 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
346 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
347 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
348 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
349 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
350 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
351 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
352 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
353 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
354 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
355 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
356 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
357 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
358 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
359 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
360 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
361 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
362 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
363 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
364 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
365 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
366 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
367 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
368 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
369 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1),
370 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2),
371 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3),
372 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, tegra_clk_sdmmc4),
373 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
374 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
375 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
376 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
377 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
378 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
379 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
380 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
381 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
382 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
383 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
384 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
385 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
386 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
387 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
388 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
389 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
390 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
391 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
392 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
393 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
394 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
395 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
396 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
397 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
398 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
399 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
400 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
401 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
402 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
403 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
404 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
405 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
406 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
407 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
408 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
409 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
410 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
411 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
412 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
413 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
414 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
415 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
416 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
417 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1),
418 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2),
419 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
420 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
421 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
422 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
423 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 65, tegra_clk_uarte),
424 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
425 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
426 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
427 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
428 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
429};
430
431static struct tegra_periph_init_data gate_clks[] = {
432 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
433 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0),
434 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
435 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
436 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
437 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
438 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
439 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
440 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
441 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
442 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
443 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
444 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
445 GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0),
446 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
447 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
448 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
449 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
450 GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
451 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
452 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
453 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
454 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
455 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
456 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
457 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
458 GATE("dsia", "dsia_mux", 48, 0, tegra_clk_dsia, 0),
459 GATE("dsib", "dsib_mux", 82, 0, tegra_clk_dsib, 0),
460 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
461 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
462};
463
464struct pll_out_data {
465 char *div_name;
466 char *pll_out_name;
467 u32 offset;
468 int clk_id;
469 u8 div_shift;
470 u8 div_flags;
471 u8 rst_shift;
472 spinlock_t *lock;
473};
474
475#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
476 {\
477 .div_name = "pll_p_out" #_num "_div",\
478 .pll_out_name = "pll_p_out" #_num,\
479 .offset = _offset,\
480 .div_shift = _div_shift,\
481 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
482 TEGRA_DIVIDER_ROUND_UP,\
483 .rst_shift = _rst_shift,\
484 .clk_id = tegra_clk_ ## _id,\
485 .lock = &_offset ##_lock,\
486 }
487
488static struct pll_out_data pllp_out_clks[] = {
489 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
490 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
491 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
492 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
493 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
494};
495
496static void __init periph_clk_init(void __iomem *clk_base,
497 struct tegra_clk *tegra_clks)
498{
499 int i;
500 struct clk *clk;
501 struct clk **dt_clk;
502
503 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
504 struct tegra_clk_periph_regs *bank;
505 struct tegra_periph_init_data *data;
506
507 data = periph_clks + i;
508
509 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
510 if (!dt_clk)
511 continue;
512
513 bank = get_reg_bank(data->periph.gate.clk_num);
514 if (!bank)
515 continue;
516
517 data->periph.gate.regs = bank;
518 clk = tegra_clk_register_periph(data->name,
519 data->p.parent_names, data->num_parents,
520 &data->periph, clk_base, data->offset,
521 data->flags);
522 *dt_clk = clk;
523 }
524}
525
526static void __init gate_clk_init(void __iomem *clk_base,
527 struct tegra_clk *tegra_clks)
528{
529 int i;
530 struct clk *clk;
531 struct clk **dt_clk;
532
533 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
534 struct tegra_periph_init_data *data;
535
536 data = gate_clks + i;
537
538 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
539 if (!dt_clk)
540 continue;
541
542 clk = tegra_clk_register_periph_gate(data->name,
543 data->p.parent_name, data->periph.gate.flags,
544 clk_base, data->flags,
545 data->periph.gate.clk_num,
546 periph_clk_enb_refcnt);
547 *dt_clk = clk;
548 }
549}
550
551static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
552 struct tegra_clk *tegra_clks,
553 struct tegra_clk_pll_params *pll_params)
554{
555 struct clk *clk;
556 struct clk **dt_clk;
557 int i;
558
559 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
560 if (dt_clk) {
561 /* PLLP */
562 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
563 pmc_base, 0, pll_params, NULL);
564 clk_register_clkdev(clk, "pll_p", NULL);
565 *dt_clk = clk;
566 }
567
568 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
569 struct pll_out_data *data;
570
571 data = pllp_out_clks + i;
572
573 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
574 if (!dt_clk)
575 continue;
576
577 clk = tegra_clk_register_divider(data->div_name, "pll_p",
578 clk_base + data->offset, 0, data->div_flags,
579 data->div_shift, 8, 1, data->lock);
580 clk = tegra_clk_register_pll_out(data->pll_out_name,
581 data->div_name, clk_base + data->offset,
582 data->rst_shift + 1, data->rst_shift,
583 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
584 data->lock);
585 *dt_clk = clk;
586 }
587}
588
589void __init tegra_periph_clk_init(void __iomem *clk_base,
590 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
591 struct tegra_clk_pll_params *pll_params)
592{
593 init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
594 periph_clk_init(clk_base, tegra_clks);
595 gate_clk_init(clk_base, tegra_clks);
596}
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 8bb9a226d05c..07098597db53 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -106,8 +106,6 @@
106#define PLLE_AUX 0x48c 106#define PLLE_AUX 0x48c
107#define PLLC_OUT 0x84 107#define PLLC_OUT 0x84
108#define PLLM_OUT 0x94 108#define PLLM_OUT 0x94
109#define PLLP_OUTA 0xa4
110#define PLLP_OUTB 0xa8
111 109
112#define PMC_CLK_OUT_CNTRL 0x1a8 110#define PMC_CLK_OUT_CNTRL 0x1a8
113#define PMC_DPD_PADS_ORIDE 0x1c 111#define PMC_DPD_PADS_ORIDE 0x1c
@@ -153,91 +151,8 @@
153#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 151#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
154#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 152#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
155 153
156#define CLK_SOURCE_I2S0 0x1d8
157#define CLK_SOURCE_I2S1 0x100
158#define CLK_SOURCE_I2S2 0x104
159#define CLK_SOURCE_NDFLASH 0x160
160#define CLK_SOURCE_I2S3 0x3bc
161#define CLK_SOURCE_I2S4 0x3c0
162#define CLK_SOURCE_SPDIF_OUT 0x108
163#define CLK_SOURCE_SPDIF_IN 0x10c
164#define CLK_SOURCE_PWM 0x110
165#define CLK_SOURCE_ADX 0x638
166#define CLK_SOURCE_AMX 0x63c
167#define CLK_SOURCE_HDA 0x428
168#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
169#define CLK_SOURCE_SBC1 0x134
170#define CLK_SOURCE_SBC2 0x118
171#define CLK_SOURCE_SBC3 0x11c
172#define CLK_SOURCE_SBC4 0x1b4
173#define CLK_SOURCE_SBC5 0x3c8
174#define CLK_SOURCE_SBC6 0x3cc
175#define CLK_SOURCE_SATA_OOB 0x420
176#define CLK_SOURCE_SATA 0x424
177#define CLK_SOURCE_NDSPEED 0x3f8
178#define CLK_SOURCE_VFIR 0x168
179#define CLK_SOURCE_SDMMC1 0x150
180#define CLK_SOURCE_SDMMC2 0x154
181#define CLK_SOURCE_SDMMC3 0x1bc
182#define CLK_SOURCE_SDMMC4 0x164
183#define CLK_SOURCE_VDE 0x1c8
184#define CLK_SOURCE_CSITE 0x1d4 154#define CLK_SOURCE_CSITE 0x1d4
185#define CLK_SOURCE_LA 0x1f8
186#define CLK_SOURCE_TRACE 0x634
187#define CLK_SOURCE_OWR 0x1cc
188#define CLK_SOURCE_NOR 0x1d0
189#define CLK_SOURCE_MIPI 0x174
190#define CLK_SOURCE_I2C1 0x124
191#define CLK_SOURCE_I2C2 0x198
192#define CLK_SOURCE_I2C3 0x1b8
193#define CLK_SOURCE_I2C4 0x3c4
194#define CLK_SOURCE_I2C5 0x128
195#define CLK_SOURCE_UARTA 0x178
196#define CLK_SOURCE_UARTB 0x17c
197#define CLK_SOURCE_UARTC 0x1a0
198#define CLK_SOURCE_UARTD 0x1c0
199#define CLK_SOURCE_UARTE 0x1c4
200#define CLK_SOURCE_UARTA_DBG 0x178
201#define CLK_SOURCE_UARTB_DBG 0x17c
202#define CLK_SOURCE_UARTC_DBG 0x1a0
203#define CLK_SOURCE_UARTD_DBG 0x1c0
204#define CLK_SOURCE_UARTE_DBG 0x1c4
205#define CLK_SOURCE_3D 0x158
206#define CLK_SOURCE_2D 0x15c
207#define CLK_SOURCE_VI_SENSOR 0x1a8
208#define CLK_SOURCE_VI 0x148
209#define CLK_SOURCE_EPP 0x16c
210#define CLK_SOURCE_MSENC 0x1f0
211#define CLK_SOURCE_TSEC 0x1f4
212#define CLK_SOURCE_HOST1X 0x180
213#define CLK_SOURCE_HDMI 0x18c
214#define CLK_SOURCE_DISP1 0x138
215#define CLK_SOURCE_DISP2 0x13c
216#define CLK_SOURCE_CILAB 0x614
217#define CLK_SOURCE_CILCD 0x618
218#define CLK_SOURCE_CILE 0x61c
219#define CLK_SOURCE_DSIALP 0x620
220#define CLK_SOURCE_DSIBLP 0x624
221#define CLK_SOURCE_TSENSOR 0x3b8
222#define CLK_SOURCE_D_AUDIO 0x3d0
223#define CLK_SOURCE_DAM0 0x3d8
224#define CLK_SOURCE_DAM1 0x3dc
225#define CLK_SOURCE_DAM2 0x3e0
226#define CLK_SOURCE_ACTMON 0x3e8
227#define CLK_SOURCE_EXTERN1 0x3ec
228#define CLK_SOURCE_EXTERN2 0x3f0
229#define CLK_SOURCE_EXTERN3 0x3f4
230#define CLK_SOURCE_I2CSLOW 0x3fc
231#define CLK_SOURCE_SE 0x42c
232#define CLK_SOURCE_MSELECT 0x3b4
233#define CLK_SOURCE_DFLL_REF 0x62c
234#define CLK_SOURCE_DFLL_SOC 0x630
235#define CLK_SOURCE_SOC_THERM 0x644
236#define CLK_SOURCE_XUSB_HOST_SRC 0x600
237#define CLK_SOURCE_XUSB_FALCON_SRC 0x604
238#define CLK_SOURCE_XUSB_FS_SRC 0x608
239#define CLK_SOURCE_XUSB_SS_SRC 0x610 155#define CLK_SOURCE_XUSB_SS_SRC 0x610
240#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
241#define CLK_SOURCE_EMC 0x19c 156#define CLK_SOURCE_EMC 0x19c
242 157
243/* PLLM override registers */ 158/* PLLM override registers */
@@ -261,7 +176,6 @@ static void __iomem *pmc_base;
261static DEFINE_SPINLOCK(pll_d_lock); 176static DEFINE_SPINLOCK(pll_d_lock);
262static DEFINE_SPINLOCK(pll_d2_lock); 177static DEFINE_SPINLOCK(pll_d2_lock);
263static DEFINE_SPINLOCK(pll_u_lock); 178static DEFINE_SPINLOCK(pll_u_lock);
264static DEFINE_SPINLOCK(pll_div_lock);
265static DEFINE_SPINLOCK(pll_re_lock); 179static DEFINE_SPINLOCK(pll_re_lock);
266static DEFINE_SPINLOCK(clk_out_lock); 180static DEFINE_SPINLOCK(clk_out_lock);
267static DEFINE_SPINLOCK(sysrate_lock); 181static DEFINE_SPINLOCK(sysrate_lock);
@@ -723,73 +637,6 @@ static unsigned long tegra114_input_freq[] = {
723 637
724#define MASK(x) (BIT(x) - 1) 638#define MASK(x) (BIT(x) - 1)
725 639
726#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
727 _clk_num, _gate_flags, _clk_id) \
728 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
729 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
730 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0)
731
732#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _parents, _offset,\
733 _clk_num, _gate_flags, _clk_id, flags)\
734 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
735 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
736 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags)
737
738#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
739 _clk_num, _gate_flags, _clk_id) \
740 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
741 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
742 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0)
743
744#define TEGRA_INIT_DATA_INT_FLAGS(_name, _parents, _offset,\
745 _clk_num, _gate_flags, _clk_id, flags)\
746 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
747 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
748 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
749 _gate_flags, _clk_id, _parents##_idx, flags)
750
751#define TEGRA_INIT_DATA_INT8(_name, _parents, _offset,\
752 _clk_num, _gate_flags, _clk_id) \
753 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
754 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
755 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
756 _gate_flags, _clk_id, _parents##_idx, 0)
757
758#define TEGRA_INIT_DATA_UART(_name, _parents, _offset,\
759 _clk_num, _clk_id) \
760 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
761 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART | \
762 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
763 0, _clk_id, _parents##_idx, 0)
764
765#define TEGRA_INIT_DATA_I2C(_name, _parents, _offset,\
766 _clk_num, _clk_id) \
767 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
768 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
769 _clk_num, 0, _clk_id, _parents##_idx, 0)
770
771#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
772 _mux_shift, _mux_mask, _clk_num, \
773 _gate_flags, _clk_id) \
774 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
775 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
776 _clk_num, _gate_flags, \
777 _clk_id, _parents##_idx, 0)
778
779#define TEGRA_INIT_DATA_XUSB(_name, _parents, _offset, \
780 _clk_num, _gate_flags, _clk_id) \
781 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
782 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
783 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
784 _gate_flags, _clk_id, _parents##_idx, 0)
785
786#define TEGRA_INIT_DATA_AUDIO(_name, _offset, _clk_num,\
787 _gate_flags, _clk_id) \
788 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \
789 _offset, 16, 0xE01F, 0, 0, 8, 1, \
790 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
791 _gate_flags , _clk_id, mux_d_audio_clk_idx, 0)
792
793struct utmi_clk_param { 640struct utmi_clk_param {
794 /* Oscillator Frequency in KHz */ 641 /* Oscillator Frequency in KHz */
795 u32 osc_frequency; 642 u32 osc_frequency;
@@ -823,122 +670,11 @@ static const struct utmi_clk_param utmi_parameters[] = {
823 670
824/* peripheral mux definitions */ 671/* peripheral mux definitions */
825 672
826#define MUX_I2S_SPDIF(_id) \
827static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
828 #_id, "pll_p",\
829 "clk_m"};
830MUX_I2S_SPDIF(audio0)
831MUX_I2S_SPDIF(audio1)
832MUX_I2S_SPDIF(audio2)
833MUX_I2S_SPDIF(audio3)
834MUX_I2S_SPDIF(audio4)
835MUX_I2S_SPDIF(audio)
836
837#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
838#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
839#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
840#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
841#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
842#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
843
844static const char *mux_pllp_pllc_pllm_clkm[] = {
845 "pll_p", "pll_c", "pll_m", "clk_m"
846};
847#define mux_pllp_pllc_pllm_clkm_idx NULL
848
849static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
850#define mux_pllp_pllc_pllm_idx NULL
851
852static const char *mux_pllp_pllc_clk32_clkm[] = {
853 "pll_p", "pll_c", "clk_32k", "clk_m"
854};
855#define mux_pllp_pllc_clk32_clkm_idx NULL
856
857static const char *mux_plla_pllc_pllp_clkm[] = {
858 "pll_a_out0", "pll_c", "pll_p", "clk_m"
859};
860#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
861
862static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
863 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
864};
865static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
866 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
867};
868
869static const char *mux_pllp_clkm[] = {
870 "pll_p", "clk_m"
871};
872static u32 mux_pllp_clkm_idx[] = {
873 [0] = 0, [1] = 3,
874};
875
876static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
877 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
878};
879#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
880
881static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
882 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
883 "pll_d2_out0", "clk_m"
884};
885#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
886
887static const char *mux_pllm_pllc_pllp_plla[] = {
888 "pll_m", "pll_c", "pll_p", "pll_a_out0"
889};
890#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
891
892static const char *mux_pllp_pllc_clkm[] = {
893 "pll_p", "pll_c", "pll_m"
894};
895static u32 mux_pllp_pllc_clkm_idx[] = {
896 [0] = 0, [1] = 1, [2] = 3,
897};
898
899static const char *mux_pllp_pllc_clkm_clk32[] = {
900 "pll_p", "pll_c", "clk_m", "clk_32k"
901};
902#define mux_pllp_pllc_clkm_clk32_idx NULL
903
904static const char *mux_plla_clk32_pllp_clkm_plle[] = {
905 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
906};
907#define mux_plla_clk32_pllp_clkm_plle_idx NULL
908
909static const char *mux_clkm_pllp_pllc_pllre[] = {
910 "clk_m", "pll_p", "pll_c", "pll_re_out"
911};
912static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
913 [0] = 0, [1] = 1, [2] = 3, [3] = 5,
914};
915
916static const char *mux_clkm_48M_pllp_480M[] = {
917 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
918};
919#define mux_clkm_48M_pllp_480M_idx NULL
920
921static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
922 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
923};
924static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
925 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
926};
927
928static const char *mux_plld_out0_plld2_out0[] = { 673static const char *mux_plld_out0_plld2_out0[] = {
929 "pll_d_out0", "pll_d2_out0", 674 "pll_d_out0", "pll_d2_out0",
930}; 675};
931#define mux_plld_out0_plld2_out0_idx NULL 676#define mux_plld_out0_plld2_out0_idx NULL
932 677
933static const char *mux_d_audio_clk[] = {
934 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
935 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
936};
937static u32 mux_d_audio_clk_idx[] = {
938 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
939 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
940};
941
942static const char *mux_pllmcp_clkm[] = { 678static const char *mux_pllmcp_clkm[] = {
943 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 679 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
944}; 680};
@@ -1366,53 +1102,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1366 &pll_c3_params, NULL); 1102 &pll_c3_params, NULL);
1367 clks[TEGRA114_CLK_PLL_C3] = clk; 1103 clks[TEGRA114_CLK_PLL_C3] = clk;
1368 1104
1369 /* PLLP */
1370 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0,
1371 &pll_p_params, NULL);
1372 clks[TEGRA114_CLK_PLL_P] = clk;
1373
1374 /* PLLP_OUT1 */
1375 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p",
1376 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1377 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1378 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div",
1379 clk_base + PLLP_OUTA, 1, 0,
1380 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1381 &pll_div_lock);
1382 clks[TEGRA114_CLK_PLL_P_OUT1] = clk;
1383
1384 /* PLLP_OUT2 */
1385 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p",
1386 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED |
1387 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24,
1388 8, 1, &pll_div_lock);
1389 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div",
1390 clk_base + PLLP_OUTA, 17, 16,
1391 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1392 &pll_div_lock);
1393 clks[TEGRA114_CLK_PLL_P_OUT2] = clk;
1394
1395 /* PLLP_OUT3 */
1396 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p",
1397 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1398 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock);
1399 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div",
1400 clk_base + PLLP_OUTB, 1, 0,
1401 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1402 &pll_div_lock);
1403 clks[TEGRA114_CLK_PLL_P_OUT3] = clk;
1404
1405 /* PLLP_OUT4 */
1406 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p",
1407 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED |
1408 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1,
1409 &pll_div_lock);
1410 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div",
1411 clk_base + PLLP_OUTB, 17, 16,
1412 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
1413 &pll_div_lock);
1414 clks[TEGRA114_CLK_PLL_P_OUT4] = clk;
1415
1416 /* PLLM */ 1105 /* PLLM */
1417 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1106 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1418 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 1107 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
@@ -1634,290 +1323,44 @@ static void __init tegra114_super_clk_init(void __iomem *clk_base)
1634 clks[TEGRA114_CLK_PCLK] = clk; 1323 clks[TEGRA114_CLK_PCLK] = clk;
1635} 1324}
1636 1325
1637static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1326static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1638 TEGRA_INIT_DATA_MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S0), 1327 void __iomem *pmc_base)
1639 TEGRA_INIT_DATA_MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S1),
1640 TEGRA_INIT_DATA_MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S2),
1641 TEGRA_INIT_DATA_MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S3),
1642 TEGRA_INIT_DATA_MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S4),
1643 TEGRA_INIT_DATA_MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_OUT),
1644 TEGRA_INIT_DATA_MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_IN),
1645 TEGRA_INIT_DATA_MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_PWM),
1646 TEGRA_INIT_DATA_MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_ADX),
1647 TEGRA_INIT_DATA_MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_AMX),
1648 TEGRA_INIT_DATA_MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA),
1649 TEGRA_INIT_DATA_MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA2CODEC_2X),
1650 TEGRA_INIT_DATA_MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC1),
1651 TEGRA_INIT_DATA_MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC2),
1652 TEGRA_INIT_DATA_MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC3),
1653 TEGRA_INIT_DATA_MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC4),
1654 TEGRA_INIT_DATA_MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC5),
1655 TEGRA_INIT_DATA_MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC6),
1656 TEGRA_INIT_DATA_MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED),
1657 TEGRA_INIT_DATA_MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED),
1658 TEGRA_INIT_DATA_MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_VFIR),
1659 TEGRA_INIT_DATA_MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, TEGRA114_CLK_SDMMC1),
1660 TEGRA_INIT_DATA_MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, TEGRA114_CLK_SDMMC2),
1661 TEGRA_INIT_DATA_MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, TEGRA114_CLK_SDMMC3),
1662 TEGRA_INIT_DATA_MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, 0, TEGRA114_CLK_SDMMC4),
1663 TEGRA_INIT_DATA_INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, TEGRA114_CLK_VDE),
1664 TEGRA_INIT_DATA_MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_CSITE, CLK_IGNORE_UNUSED),
1665 TEGRA_INIT_DATA_MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_LA),
1666 TEGRA_INIT_DATA_MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TRACE),
1667 TEGRA_INIT_DATA_MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_OWR),
1668 TEGRA_INIT_DATA_MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, TEGRA114_CLK_NOR),
1669 TEGRA_INIT_DATA_MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_MIPI),
1670 TEGRA_INIT_DATA_I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, TEGRA114_CLK_I2C1),
1671 TEGRA_INIT_DATA_I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, TEGRA114_CLK_I2C2),
1672 TEGRA_INIT_DATA_I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, TEGRA114_CLK_I2C3),
1673 TEGRA_INIT_DATA_I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, TEGRA114_CLK_I2C4),
1674 TEGRA_INIT_DATA_I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, TEGRA114_CLK_I2C5),
1675 TEGRA_INIT_DATA_UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, TEGRA114_CLK_UARTA),
1676 TEGRA_INIT_DATA_UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, TEGRA114_CLK_UARTB),
1677 TEGRA_INIT_DATA_UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, TEGRA114_CLK_UARTC),
1678 TEGRA_INIT_DATA_UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, TEGRA114_CLK_UARTD),
1679 TEGRA_INIT_DATA_INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, TEGRA114_CLK_GR3D),
1680 TEGRA_INIT_DATA_INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, TEGRA114_CLK_GR2D),
1681 TEGRA_INIT_DATA_MUX("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1682 TEGRA_INIT_DATA_INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, TEGRA114_CLK_VI),
1683 TEGRA_INIT_DATA_INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, TEGRA114_CLK_EPP),
1684 TEGRA_INIT_DATA_INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, TEGRA114_CLK_MSENC),
1685 TEGRA_INIT_DATA_INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, TEGRA114_CLK_TSEC),
1686 TEGRA_INIT_DATA_INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, TEGRA114_CLK_HOST1X),
1687 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA114_CLK_HDMI),
1688 TEGRA_INIT_DATA_MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, TEGRA114_CLK_CILAB),
1689 TEGRA_INIT_DATA_MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, TEGRA114_CLK_CILCD),
1690 TEGRA_INIT_DATA_MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, TEGRA114_CLK_CILE),
1691 TEGRA_INIT_DATA_MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, TEGRA114_CLK_DSIALP),
1692 TEGRA_INIT_DATA_MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, TEGRA114_CLK_DSIBLP),
1693 TEGRA_INIT_DATA_MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TSENSOR),
1694 TEGRA_INIT_DATA_MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, TEGRA114_CLK_ACTMON),
1695 TEGRA_INIT_DATA_MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, TEGRA114_CLK_EXTERN1),
1696 TEGRA_INIT_DATA_MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, TEGRA114_CLK_EXTERN2),
1697 TEGRA_INIT_DATA_MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, TEGRA114_CLK_EXTERN3),
1698 TEGRA_INIT_DATA_MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2CSLOW),
1699 TEGRA_INIT_DATA_INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SE),
1700 TEGRA_INIT_DATA_INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, TEGRA114_CLK_MSELECT, CLK_IGNORE_UNUSED),
1701 TEGRA_INIT_DATA_MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_REF),
1702 TEGRA_INIT_DATA_MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_SOC),
1703 TEGRA_INIT_DATA_MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SOC_THERM),
1704 TEGRA_INIT_DATA_XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_HOST_SRC),
1705 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FALCON_SRC),
1706 TEGRA_INIT_DATA_XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FS_SRC),
1707 TEGRA_INIT_DATA_XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_SS_SRC),
1708 TEGRA_INIT_DATA_XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_DEV_SRC),
1709 TEGRA_INIT_DATA_AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_D_AUDIO),
1710 TEGRA_INIT_DATA_AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM0),
1711 TEGRA_INIT_DATA_AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM1),
1712 TEGRA_INIT_DATA_AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM2),
1713};
1714
1715static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1716 TEGRA_INIT_DATA_NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, TEGRA114_CLK_DISP1),
1717 TEGRA_INIT_DATA_NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, TEGRA114_CLK_DISP2),
1718};
1719
1720static __init void tegra114_periph_clk_init(void __iomem *clk_base)
1721{ 1328{
1722 struct tegra_periph_init_data *data;
1723 struct clk *clk; 1329 struct clk *clk;
1724 int i;
1725 u32 val; 1330 u32 val;
1726 1331
1727 /* apbdma */ 1332 /* xusb_hs_src */
1728 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 1333 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1729 0, 34, periph_clk_enb_refcnt); 1334 val |= BIT(25); /* always select PLLU_60M */
1730 clks[TEGRA114_CLK_APBDMA] = clk; 1335 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1731 1336
1732 /* rtc */ 1337 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1733 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1338 1, 1);
1734 TEGRA_PERIPH_ON_APB | 1339 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk;
1735 TEGRA_PERIPH_NO_RESET, clk_base, 1340
1736 0, 4, periph_clk_enb_refcnt); 1341 /* dsia mux */
1737 clks[TEGRA114_CLK_RTC] = clk;
1738
1739 /* kbc */
1740 clk = tegra_clk_register_periph_gate("kbc", "clk_32k",
1741 TEGRA_PERIPH_ON_APB |
1742 TEGRA_PERIPH_NO_RESET, clk_base,
1743 0, 36, periph_clk_enb_refcnt);
1744 clks[TEGRA114_CLK_KBC] = clk;
1745
1746 /* timer */
1747 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base,
1748 0, 5, periph_clk_enb_refcnt);
1749 clks[TEGRA114_CLK_TIMER] = clk;
1750
1751 /* kfuse */
1752 clk = tegra_clk_register_periph_gate("kfuse", "clk_m",
1753 TEGRA_PERIPH_ON_APB, clk_base, 0, 40,
1754 periph_clk_enb_refcnt);
1755 clks[TEGRA114_CLK_KFUSE] = clk;
1756
1757 /* fuse */
1758 clk = tegra_clk_register_periph_gate("fuse", "clk_m",
1759 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1760 periph_clk_enb_refcnt);
1761 clks[TEGRA114_CLK_FUSE] = clk;
1762
1763 /* fuse_burn */
1764 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m",
1765 TEGRA_PERIPH_ON_APB, clk_base, 0, 39,
1766 periph_clk_enb_refcnt);
1767 clks[TEGRA114_CLK_FUSE_BURN] = clk;
1768
1769 /* apbif */
1770 clk = tegra_clk_register_periph_gate("apbif", "clk_m",
1771 TEGRA_PERIPH_ON_APB, clk_base, 0, 107,
1772 periph_clk_enb_refcnt);
1773 clks[TEGRA114_CLK_APBIF] = clk;
1774
1775 /* hda2hdmi */
1776 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m",
1777 TEGRA_PERIPH_ON_APB, clk_base, 0, 128,
1778 periph_clk_enb_refcnt);
1779 clks[TEGRA114_CLK_HDA2HDMI] = clk;
1780
1781 /* vcp */
1782 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0,
1783 29, periph_clk_enb_refcnt);
1784 clks[TEGRA114_CLK_VCP] = clk;
1785
1786 /* bsea */
1787 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base,
1788 0, 62, periph_clk_enb_refcnt);
1789 clks[TEGRA114_CLK_BSEA] = clk;
1790
1791 /* bsev */
1792 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base,
1793 0, 63, periph_clk_enb_refcnt);
1794 clks[TEGRA114_CLK_BSEV] = clk;
1795
1796 /* mipi-cal */
1797 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1798 0, 56, periph_clk_enb_refcnt);
1799 clks[TEGRA114_CLK_MIPI_CAL] = clk;
1800
1801 /* usbd */
1802 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base,
1803 0, 22, periph_clk_enb_refcnt);
1804 clks[TEGRA114_CLK_USBD] = clk;
1805
1806 /* usb2 */
1807 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base,
1808 0, 58, periph_clk_enb_refcnt);
1809 clks[TEGRA114_CLK_USB2] = clk;
1810
1811 /* usb3 */
1812 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base,
1813 0, 59, periph_clk_enb_refcnt);
1814 clks[TEGRA114_CLK_USB3] = clk;
1815
1816 /* csi */
1817 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base,
1818 0, 52, periph_clk_enb_refcnt);
1819 clks[TEGRA114_CLK_CSI] = clk;
1820
1821 /* isp */
1822 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0,
1823 23, periph_clk_enb_refcnt);
1824 clks[TEGRA114_CLK_ISP] = clk;
1825
1826 /* csus */
1827 clk = tegra_clk_register_periph_gate("csus", "clk_m",
1828 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92,
1829 periph_clk_enb_refcnt);
1830 clks[TEGRA114_CLK_CSUS] = clk;
1831
1832 /* dds */
1833 clk = tegra_clk_register_periph_gate("dds", "clk_m",
1834 TEGRA_PERIPH_ON_APB, clk_base, 0, 150,
1835 periph_clk_enb_refcnt);
1836 clks[TEGRA114_CLK_DDS] = clk;
1837
1838 /* dp2 */
1839 clk = tegra_clk_register_periph_gate("dp2", "clk_m",
1840 TEGRA_PERIPH_ON_APB, clk_base, 0, 152,
1841 periph_clk_enb_refcnt);
1842 clks[TEGRA114_CLK_DP2] = clk;
1843
1844 /* dtv */
1845 clk = tegra_clk_register_periph_gate("dtv", "clk_m",
1846 TEGRA_PERIPH_ON_APB, clk_base, 0, 79,
1847 periph_clk_enb_refcnt);
1848 clks[TEGRA114_CLK_DTV] = clk;
1849
1850 /* dsia */
1851 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1342 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1852 ARRAY_SIZE(mux_plld_out0_plld2_out0), 1343 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1853 CLK_SET_RATE_NO_REPARENT, 1344 CLK_SET_RATE_NO_REPARENT,
1854 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1345 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1855 clks[TEGRA114_CLK_DSIA_MUX] = clk; 1346 clks[TEGRA114_CLK_DSIA_MUX] = clk;
1856 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1857 0, 48, periph_clk_enb_refcnt);
1858 clks[TEGRA114_CLK_DSIA] = clk;
1859 1347
1860 /* dsib */ 1348 /* dsib mux */
1861 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1349 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1862 ARRAY_SIZE(mux_plld_out0_plld2_out0), 1350 ARRAY_SIZE(mux_plld_out0_plld2_out0),
1863 CLK_SET_RATE_NO_REPARENT, 1351 CLK_SET_RATE_NO_REPARENT,
1864 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1352 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1865 clks[TEGRA114_CLK_DSIB_MUX] = clk; 1353 clks[TEGRA114_CLK_DSIB_MUX] = clk;
1866 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1867 0, 82, periph_clk_enb_refcnt);
1868 clks[TEGRA114_CLK_DSIB] = clk;
1869 1354
1870 /* xusb_hs_src */ 1355 /* emc mux */
1871 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
1872 val |= BIT(25); /* always select PLLU_60M */
1873 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
1874
1875 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
1876 1, 1);
1877 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk;
1878
1879 /* xusb_host */
1880 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0,
1881 clk_base, 0, 89, periph_clk_enb_refcnt);
1882 clks[TEGRA114_CLK_XUSB_HOST] = clk;
1883
1884 /* xusb_ss */
1885 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0,
1886 clk_base, 0, 156, periph_clk_enb_refcnt);
1887 clks[TEGRA114_CLK_XUSB_HOST] = clk;
1888
1889 /* xusb_dev */
1890 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0,
1891 clk_base, 0, 95, periph_clk_enb_refcnt);
1892 clks[TEGRA114_CLK_XUSB_DEV] = clk;
1893
1894 /* emc */
1895 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1356 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1896 ARRAY_SIZE(mux_pllmcp_clkm), 1357 ARRAY_SIZE(mux_pllmcp_clkm),
1897 CLK_SET_RATE_NO_REPARENT, 1358 CLK_SET_RATE_NO_REPARENT,
1898 clk_base + CLK_SOURCE_EMC, 1359 clk_base + CLK_SOURCE_EMC,
1899 29, 3, 0, NULL); 1360 29, 3, 0, NULL);
1900 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
1901 CLK_IGNORE_UNUSED, 57, periph_clk_enb_refcnt);
1902 clks[TEGRA114_CLK_EMC] = clk;
1903
1904 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1905 data = &tegra_periph_clk_list[i];
1906 1361
1907 clk = tegra_clk_register_periph(data->name, 1362 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1908 data->parent_names, data->num_parents, &data->periph, 1363 &pll_p_params);
1909 clk_base, data->offset, data->flags);
1910 clks[data->clk_id] = clk;
1911 }
1912
1913 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1914 data = &tegra_periph_nodiv_clk_list[i];
1915
1916 clk = tegra_clk_register_periph_nodiv(data->name,
1917 data->parent_names, data->num_parents,
1918 &data->periph, clk_base, data->offset);
1919 clks[data->clk_id] = clk;
1920 }
1921} 1364}
1922 1365
1923/* Tegra114 CPU clock and reset control functions */ 1366/* Tegra114 CPU clock and reset control functions */
@@ -2167,7 +1610,7 @@ static void __init tegra114_clock_init(struct device_node *np)
2167 1610
2168 tegra114_fixed_clk_init(clk_base); 1611 tegra114_fixed_clk_init(clk_base);
2169 tegra114_pll_init(clk_base, pmc_base); 1612 tegra114_pll_init(clk_base, pmc_base);
2170 tegra114_periph_clk_init(clk_base); 1613 tegra114_periph_clk_init(clk_base, pmc_base);
2171 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params); 1614 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
2172 tegra114_pmc_clk_init(pmc_base); 1615 tegra114_pmc_clk_init(pmc_base);
2173 tegra114_super_clk_init(clk_base); 1616 tegra114_super_clk_init(clk_base);
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 31547fde92e4..7c9af8e2c33b 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -973,7 +973,7 @@ static void __init tegra20_periph_clk_init(void)
973 973
974 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 974 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
975 data = &tegra_periph_clk_list[i]; 975 data = &tegra_periph_clk_list[i];
976 clk = tegra_clk_register_periph(data->name, data->parent_names, 976 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
977 data->num_parents, &data->periph, 977 data->num_parents, &data->periph,
978 clk_base, data->offset, data->flags); 978 clk_base, data->offset, data->flags);
979 clk_register_clkdev(clk, data->con_id, data->dev_id); 979 clk_register_clkdev(clk, data->con_id, data->dev_id);
@@ -983,7 +983,7 @@ static void __init tegra20_periph_clk_init(void)
983 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 983 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
984 data = &tegra_periph_nodiv_clk_list[i]; 984 data = &tegra_periph_nodiv_clk_list[i];
985 clk = tegra_clk_register_periph_nodiv(data->name, 985 clk = tegra_clk_register_periph_nodiv(data->name,
986 data->parent_names, 986 data->p.parent_names,
987 data->num_parents, &data->periph, 987 data->num_parents, &data->periph,
988 clk_base, data->offset); 988 clk_base, data->offset);
989 clk_register_clkdev(clk, data->con_id, data->dev_id); 989 clk_register_clkdev(clk, data->con_id, data->dev_id);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index da540f6dc9c9..c75db196728c 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1616,7 +1616,7 @@ static void __init tegra30_periph_clk_init(void)
1616 1616
1617 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1617 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1618 data = &tegra_periph_clk_list[i]; 1618 data = &tegra_periph_clk_list[i];
1619 clk = tegra_clk_register_periph(data->name, data->parent_names, 1619 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1620 data->num_parents, &data->periph, 1620 data->num_parents, &data->periph,
1621 clk_base, data->offset, data->flags); 1621 clk_base, data->offset, data->flags);
1622 clk_register_clkdev(clk, data->con_id, data->dev_id); 1622 clk_register_clkdev(clk, data->con_id, data->dev_id);
@@ -1626,7 +1626,7 @@ static void __init tegra30_periph_clk_init(void)
1626 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1626 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1627 data = &tegra_periph_nodiv_clk_list[i]; 1627 data = &tegra_periph_nodiv_clk_list[i];
1628 clk = tegra_clk_register_periph_nodiv(data->name, 1628 clk = tegra_clk_register_periph_nodiv(data->name,
1629 data->parent_names, 1629 data->p.parent_names,
1630 data->num_parents, &data->periph, 1630 data->num_parents, &data->periph,
1631 clk_base, data->offset); 1631 clk_base, data->offset);
1632 clk_register_clkdev(clk, data->con_id, data->dev_id); 1632 clk_register_clkdev(clk, data->con_id, data->dev_id);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 3306e41e6270..9ec6118e9b99 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -460,7 +460,10 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
460struct tegra_periph_init_data { 460struct tegra_periph_init_data {
461 const char *name; 461 const char *name;
462 int clk_id; 462 int clk_id;
463 const char **parent_names; 463 union {
464 const char **parent_names;
465 const char *parent_name;
466 } p;
464 int num_parents; 467 int num_parents;
465 struct tegra_clk_periph periph; 468 struct tegra_clk_periph periph;
466 u32 offset; 469 u32 offset;
@@ -477,7 +480,7 @@ struct tegra_periph_init_data {
477 { \ 480 { \
478 .name = _name, \ 481 .name = _name, \
479 .clk_id = _clk_id, \ 482 .clk_id = _clk_id, \
480 .parent_names = _parent_names, \ 483 .p.parent_names = _parent_names, \
481 .num_parents = ARRAY_SIZE(_parent_names), \ 484 .num_parents = ARRAY_SIZE(_parent_names), \
482 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 485 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
483 _mux_flags, _div_shift, \ 486 _mux_flags, _div_shift, \
@@ -597,6 +600,10 @@ void tegra_audio_clk_init(void __iomem *clk_base,
597 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 600 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
598 struct tegra_clk_pll_params *pll_params); 601 struct tegra_clk_pll_params *pll_params);
599 602
603void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
604 struct tegra_clk *tegra_clks,
605 struct tegra_clk_pll_params *pll_params);
606
600void tegra114_clock_tune_cpu_trimmers_high(void); 607void tegra114_clock_tune_cpu_trimmers_high(void);
601void tegra114_clock_tune_cpu_trimmers_low(void); 608void tegra114_clock_tune_cpu_trimmers_low(void);
602void tegra114_clock_tune_cpu_trimmers_init(void); 609void tegra114_clock_tune_cpu_trimmers_init(void);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-13 22:41:04 -0400