diff options
author | Emil Velikov <emil.l.velikov@gmail.com> | 2011-03-19 19:31:51 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2011-05-15 20:47:10 -0400 |
commit | 71298e2f0b6fb6dce9f2b2e999652edf1f643d9e (patch) | |
tree | 30be179378f92fd78a548538870d4bc7676d1020 /drivers | |
parent | 01e542c65de11a47e726ebef63f5e59b4a74568d (diff) |
drm/nouveau: Fix indentation-related checkpatch.pl error messages.
Fix 'ERROR: code indent should use tabs where possible'
Fix 'ERROR: space required before the open parenthesis ('
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_grctx.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_graph.c | 18 |
4 files changed, 21 insertions, 21 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index a76514a209b3..6b362d5a6d6f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -887,13 +887,13 @@ extern void nouveau_channel_idle(struct nouveau_channel *chan); | |||
887 | int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ | 887 | int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ |
888 | if (ret) \ | 888 | if (ret) \ |
889 | return ret; \ | 889 | return ret; \ |
890 | } while(0) | 890 | } while (0) |
891 | 891 | ||
892 | #define NVOBJ_MTHD(d,c,m,e) do { \ | 892 | #define NVOBJ_MTHD(d,c,m,e) do { \ |
893 | int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ | 893 | int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ |
894 | if (ret) \ | 894 | if (ret) \ |
895 | return ret; \ | 895 | return ret; \ |
896 | } while(0) | 896 | } while (0) |
897 | 897 | ||
898 | extern int nouveau_gpuobj_early_init(struct drm_device *); | 898 | extern int nouveau_gpuobj_early_init(struct drm_device *); |
899 | extern int nouveau_gpuobj_init(struct drm_device *); | 899 | extern int nouveau_gpuobj_init(struct drm_device *); |
@@ -903,7 +903,7 @@ extern void nouveau_gpuobj_resume(struct drm_device *dev); | |||
903 | extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); | 903 | extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); |
904 | extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, | 904 | extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, |
905 | int (*exec)(struct nouveau_channel *, | 905 | int (*exec)(struct nouveau_channel *, |
906 | u32 class, u32 mthd, u32 data)); | 906 | u32 class, u32 mthd, u32 data)); |
907 | extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); | 907 | extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); |
908 | extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); | 908 | extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); |
909 | extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, | 909 | extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 5045f8b921d6..be07a4bc4aae 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c | |||
@@ -599,7 +599,7 @@ nouveau_mem_timing_init(struct drm_device *dev) | |||
599 | 599 | ||
600 | /* Get "some number" from the timing reg for NV_40 | 600 | /* Get "some number" from the timing reg for NV_40 |
601 | * Used in calculations later */ | 601 | * Used in calculations later */ |
602 | if(dev_priv->card_type == NV_40) { | 602 | if (dev_priv->card_type == NV_40) { |
603 | magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24; | 603 | magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24; |
604 | } | 604 | } |
605 | 605 | ||
@@ -645,22 +645,22 @@ nouveau_mem_timing_init(struct drm_device *dev) | |||
645 | timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 | | 645 | timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 | |
646 | tUNK_18 << 16 | | 646 | tUNK_18 << 16 | |
647 | (tUNK_1 + tUNK_19 + 1 + magic_number) << 8; | 647 | (tUNK_1 + tUNK_19 + 1 + magic_number) << 8; |
648 | if(dev_priv->chipset == 0xa8) { | 648 | if (dev_priv->chipset == 0xa8) { |
649 | timing->reg_100224 |= (tUNK_2 - 1); | 649 | timing->reg_100224 |= (tUNK_2 - 1); |
650 | } else { | 650 | } else { |
651 | timing->reg_100224 |= (tUNK_2 + 2 - magic_number); | 651 | timing->reg_100224 |= (tUNK_2 + 2 - magic_number); |
652 | } | 652 | } |
653 | 653 | ||
654 | timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10); | 654 | timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10); |
655 | if(dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) { | 655 | if (dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) { |
656 | timing->reg_100228 |= (tUNK_19 - 1) << 24; | 656 | timing->reg_100228 |= (tUNK_19 - 1) << 24; |
657 | } | 657 | } |
658 | 658 | ||
659 | if(dev_priv->card_type == NV_40) { | 659 | if (dev_priv->card_type == NV_40) { |
660 | /* NV40: don't know what the rest of the regs are.. | 660 | /* NV40: don't know what the rest of the regs are.. |
661 | * And don't need to know either */ | 661 | * And don't need to know either */ |
662 | timing->reg_100228 |= 0x20200000 | magic_number << 24; | 662 | timing->reg_100228 |= 0x20200000 | magic_number << 24; |
663 | } else if(dev_priv->card_type >= NV_50) { | 663 | } else if (dev_priv->card_type >= NV_50) { |
664 | /* XXX: reg_10022c */ | 664 | /* XXX: reg_10022c */ |
665 | timing->reg_10022c = tUNK_2 - 1; | 665 | timing->reg_10022c = tUNK_2 - 1; |
666 | 666 | ||
@@ -670,7 +670,7 @@ nouveau_mem_timing_init(struct drm_device *dev) | |||
670 | timing->reg_100234 = (tRAS << 24 | tRC); | 670 | timing->reg_100234 = (tRAS << 24 | tRC); |
671 | timing->reg_100234 += max(tUNK_10,tUNK_11) << 16; | 671 | timing->reg_100234 += max(tUNK_10,tUNK_11) << 16; |
672 | 672 | ||
673 | if(dev_priv->chipset < 0xa3) { | 673 | if (dev_priv->chipset < 0xa3) { |
674 | timing->reg_100234 |= (tUNK_2 + 2) << 8; | 674 | timing->reg_100234 |= (tUNK_2 + 2) << 8; |
675 | } else { | 675 | } else { |
676 | /* XXX: +6? */ | 676 | /* XXX: +6? */ |
@@ -681,7 +681,7 @@ nouveau_mem_timing_init(struct drm_device *dev) | |||
681 | * reg_100238: 0x00?????? | 681 | * reg_100238: 0x00?????? |
682 | * reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */ | 682 | * reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */ |
683 | timing->reg_10023c = 0x202; | 683 | timing->reg_10023c = 0x202; |
684 | if(dev_priv->chipset < 0xa3) { | 684 | if (dev_priv->chipset < 0xa3) { |
685 | timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16; | 685 | timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16; |
686 | } else { | 686 | } else { |
687 | /* currently unknown | 687 | /* currently unknown |
diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c index 336aab2a24a6..a1e98d143785 100644 --- a/drivers/gpu/drm/nouveau/nv50_grctx.c +++ b/drivers/gpu/drm/nouveau/nv50_grctx.c | |||
@@ -747,7 +747,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx) | |||
747 | gr_def(ctx, offset + 0x64, 0x0000001f); | 747 | gr_def(ctx, offset + 0x64, 0x0000001f); |
748 | gr_def(ctx, offset + 0x68, 0x0000000f); | 748 | gr_def(ctx, offset + 0x68, 0x0000000f); |
749 | gr_def(ctx, offset + 0x6c, 0x0000000f); | 749 | gr_def(ctx, offset + 0x6c, 0x0000000f); |
750 | } else if(dev_priv->chipset < 0xa0) { | 750 | } else if (dev_priv->chipset < 0xa0) { |
751 | cp_ctx(ctx, offset + 0x50, 1); | 751 | cp_ctx(ctx, offset + 0x50, 1); |
752 | cp_ctx(ctx, offset + 0x70, 1); | 752 | cp_ctx(ctx, offset + 0x70, 1); |
753 | } else { | 753 | } else { |
@@ -2836,7 +2836,7 @@ nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx) | |||
2836 | xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ | 2836 | xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ |
2837 | if (IS_NVA3F(dev_priv->chipset)) | 2837 | if (IS_NVA3F(dev_priv->chipset)) |
2838 | xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ | 2838 | xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ |
2839 | if(dev_priv->chipset == 0x50) | 2839 | if (dev_priv->chipset == 0x50) |
2840 | xf_emit(ctx, 1, 0); /* ff */ | 2840 | xf_emit(ctx, 1, 0); /* ff */ |
2841 | else | 2841 | else |
2842 | xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ | 2842 | xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ |
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c index 3de9b721d8db..c19ff3042093 100644 --- a/drivers/gpu/drm/nouveau/nvc0_graph.c +++ b/drivers/gpu/drm/nouveau/nvc0_graph.c | |||
@@ -200,15 +200,15 @@ nvc0_graph_create_context(struct nouveau_channel *chan) | |||
200 | for (i = 0; i < priv->grctx_size; i += 4) | 200 | for (i = 0; i < priv->grctx_size; i += 4) |
201 | nv_wo32(grctx, i, priv->grctx_vals[i / 4]); | 201 | nv_wo32(grctx, i, priv->grctx_vals[i / 4]); |
202 | 202 | ||
203 | nv_wo32(grctx, 0xf4, 0); | 203 | nv_wo32(grctx, 0xf4, 0); |
204 | nv_wo32(grctx, 0xf8, 0); | 204 | nv_wo32(grctx, 0xf8, 0); |
205 | nv_wo32(grctx, 0x10, grch->mmio_nr); | 205 | nv_wo32(grctx, 0x10, grch->mmio_nr); |
206 | nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst)); | 206 | nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst)); |
207 | nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst)); | 207 | nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst)); |
208 | nv_wo32(grctx, 0x1c, 1); | 208 | nv_wo32(grctx, 0x1c, 1); |
209 | nv_wo32(grctx, 0x20, 0); | 209 | nv_wo32(grctx, 0x20, 0); |
210 | nv_wo32(grctx, 0x28, 0); | 210 | nv_wo32(grctx, 0x28, 0); |
211 | nv_wo32(grctx, 0x2c, 0); | 211 | nv_wo32(grctx, 0x2c, 0); |
212 | pinstmem->flush(dev); | 212 | pinstmem->flush(dev); |
213 | return 0; | 213 | return 0; |
214 | 214 | ||